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[mirror_ubuntu-artful-kernel.git] / drivers / nvme / host / core.c
CommitLineData
21d34711
CH		 1/*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/blkdev.h>
16#include <linux/blk-mq.h>
5fd4ce1b 17#include <linux/delay.h>
21d34711 18#include <linux/errno.h>
1673f1f0 19#include <linux/hdreg.h>
21d34711 20#include <linux/kernel.h>
5bae7f73
CH		 21#include <linux/module.h>
22#include <linux/list_sort.h>
21d34711
CH		 23#include <linux/slab.h>
24#include <linux/types.h>
1673f1f0
CH		 25#include <linux/pr.h>
26#include <linux/ptrace.h>
27#include <linux/nvme_ioctl.h>
28#include <linux/t10-pi.h>
c5552fde 29#include <linux/pm_qos.h>
1673f1f0 30#include <asm/unaligned.h>
21d34711
CH		 31
32#include "nvme.h"
038bd4cb 33#include "fabrics.h"
21d34711 34
f3ca80fc
CH		 35#define NVME_MINORS (1U << MINORBITS)
36
ba0ba7d3
ML		 37unsigned char admin_timeout = 60;
38module_param(admin_timeout, byte, 0644);
39MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 40EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3
ML		 41
42unsigned char nvme_io_timeout = 30;
43module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
44MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 45EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3 46
b3b1b0b0 47static unsigned char shutdown_timeout = 5;
ba0ba7d3
ML		 48module_param(shutdown_timeout, byte, 0644);
49MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
50
44e44b29
CH		 51static u8 nvme_max_retries = 5;
52module_param_named(max_retries, nvme_max_retries, byte, 0644);
f80ec966 53MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
5bae7f73 54
f3ca80fc
CH		 55static int nvme_char_major;
56module_param(nvme_char_major, int, 0);
57
9947d6a0 58static unsigned long default_ps_max_latency_us = 100000;
c5552fde
AL		 59module_param(default_ps_max_latency_us, ulong, 0644);
60MODULE_PARM_DESC(default_ps_max_latency_us,
61 "max power saving latency for new devices; use PM QOS to change per device");
62
c35e30b4
AL		 63static bool force_apst;
64module_param(force_apst, bool, 0644);
65MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off");
66
f5d11840
JA		 67static bool streams;
68module_param(streams, bool, 0644);
69MODULE_PARM_DESC(streams, "turn on support for Streams write directives");
70
9a6327d2
SG		 71struct workqueue_struct *nvme_wq;
72EXPORT_SYMBOL_GPL(nvme_wq);
73
f3ca80fc 74static LIST_HEAD(nvme_ctrl_list);
9f2482b9 75static DEFINE_SPINLOCK(dev_list_lock);
1673f1f0 76
f3ca80fc
CH		 77static struct class *nvme_class;
78
d86c4d8e
CH		 79int nvme_reset_ctrl(struct nvme_ctrl *ctrl)
80{
81 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
82 return -EBUSY;
83 if (!queue_work(nvme_wq, &ctrl->reset_work))
84 return -EBUSY;
85 return 0;
86}
87EXPORT_SYMBOL_GPL(nvme_reset_ctrl);
88
89static int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
90{
91 int ret;
92
93 ret = nvme_reset_ctrl(ctrl);
94 if (!ret)
95 flush_work(&ctrl->reset_work);
96 return ret;
97}
98
2a842aca 99static blk_status_t nvme_error_status(struct request *req)
27fa9bc5
CH		 100{
101 switch (nvme_req(req)->status & 0x7ff) {
102 case NVME_SC_SUCCESS:
2a842aca 103 return BLK_STS_OK;
27fa9bc5 104 case NVME_SC_CAP_EXCEEDED:
2a842aca 105 return BLK_STS_NOSPC;
e02ab023 106 case NVME_SC_ONCS_NOT_SUPPORTED:
2a842aca 107 return BLK_STS_NOTSUPP;
e02ab023
JG		 108 case NVME_SC_WRITE_FAULT:
109 case NVME_SC_READ_ERROR:
110 case NVME_SC_UNWRITTEN_BLOCK:
2a842aca
CH		 111 return BLK_STS_MEDIUM;
112 default:
113 return BLK_STS_IOERR;
27fa9bc5
CH		 114 }
115}
27fa9bc5 116
f6324b1b 117static inline bool nvme_req_needs_retry(struct request *req)
77f02a7a 118{
f6324b1b
CH		 119 if (blk_noretry_request(req))
120 return false;
27fa9bc5 121 if (nvme_req(req)->status & NVME_SC_DNR)
f6324b1b
CH		 122 return false;
123 if (jiffies - req->start_time >= req->timeout)
124 return false;
44e44b29 125 if (nvme_req(req)->retries >= nvme_max_retries)
f6324b1b
CH		 126 return false;
127 return true;
77f02a7a
CH		 128}
129
130void nvme_complete_rq(struct request *req)
131{
27fa9bc5
CH		 132 if (unlikely(nvme_req(req)->status && nvme_req_needs_retry(req))) {
133 nvme_req(req)->retries++;
8d7b8faf 134 blk_mq_requeue_request(req, true);
27fa9bc5 135 return;
77f02a7a
CH		 136 }
137
27fa9bc5 138 blk_mq_end_request(req, nvme_error_status(req));
77f02a7a
CH		 139}
140EXPORT_SYMBOL_GPL(nvme_complete_rq);
141
c55a2fd4
ML		 142void nvme_cancel_request(struct request *req, void *data, bool reserved)
143{
144 int status;
145
146 if (!blk_mq_request_started(req))
147 return;
148
149 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
150 "Cancelling I/O %d", req->tag);
151
152 status = NVME_SC_ABORT_REQ;
153 if (blk_queue_dying(req->q))
154 status |= NVME_SC_DNR;
27fa9bc5 155 nvme_req(req)->status = status;
08e0029a 156 blk_mq_complete_request(req);
27fa9bc5 157
c55a2fd4
ML		 158}
159EXPORT_SYMBOL_GPL(nvme_cancel_request);
160
bb8d261e
CH		 161bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
162 enum nvme_ctrl_state new_state)
163{
f6b6a28e 164 enum nvme_ctrl_state old_state;
bb8d261e
CH		 165 bool changed = false;
166
167 spin_lock_irq(&ctrl->lock);
f6b6a28e
GKB		 168
169 old_state = ctrl->state;
bb8d261e
CH		 170 switch (new_state) {
171 case NVME_CTRL_LIVE:
172 switch (old_state) {
7d2e8008 173 case NVME_CTRL_NEW:
bb8d261e 174 case NVME_CTRL_RESETTING:
def61eca 175 case NVME_CTRL_RECONNECTING:
bb8d261e
CH		 176 changed = true;
177 /* FALLTHRU */
178 default:
179 break;
180 }
181 break;
182 case NVME_CTRL_RESETTING:
183 switch (old_state) {
184 case NVME_CTRL_NEW:
def61eca 185 case NVME_CTRL_LIVE:
def61eca
CH		 186 changed = true;
187 /* FALLTHRU */
188 default:
189 break;
190 }
191 break;
192 case NVME_CTRL_RECONNECTING:
193 switch (old_state) {
bb8d261e
CH		 194 case NVME_CTRL_LIVE:
195 changed = true;
196 /* FALLTHRU */
197 default:
198 break;
199 }
200 break;
201 case NVME_CTRL_DELETING:
202 switch (old_state) {
203 case NVME_CTRL_LIVE:
204 case NVME_CTRL_RESETTING:
def61eca 205 case NVME_CTRL_RECONNECTING:
bb8d261e
CH		 206 changed = true;
207 /* FALLTHRU */
208 default:
209 break;
210 }
211 break;
0ff9d4e1
KB		 212 case NVME_CTRL_DEAD:
213 switch (old_state) {
214 case NVME_CTRL_DELETING:
215 changed = true;
216 /* FALLTHRU */
217 default:
218 break;
219 }
220 break;
bb8d261e
CH		 221 default:
222 break;
223 }
bb8d261e
CH		 224
225 if (changed)
226 ctrl->state = new_state;
227
f6b6a28e
GKB		 228 spin_unlock_irq(&ctrl->lock);
229
bb8d261e
CH		 230 return changed;
231}
232EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
233
1673f1f0
CH		 234static void nvme_free_ns(struct kref *kref)
235{
236 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
237
b0b4e09c
MB		 238 if (ns->ndev)
239 nvme_nvm_unregister(ns);
1673f1f0 240
b0b4e09c
MB		 241 if (ns->disk) {
242 spin_lock(&dev_list_lock);
243 ns->disk->private_data = NULL;
244 spin_unlock(&dev_list_lock);
245 }
1673f1f0 246
1673f1f0 247 put_disk(ns->disk);
075790eb
KB		 248 ida_simple_remove(&ns->ctrl->ns_ida, ns->instance);
249 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH		 250 kfree(ns);
251}
252
5bae7f73 253static void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH		 254{
255 kref_put(&ns->kref, nvme_free_ns);
256}
257
258static struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk)
259{
260 struct nvme_ns *ns;
261
262 spin_lock(&dev_list_lock);
263 ns = disk->private_data;
e439bb12
SG		 264 if (ns) {
265 if (!kref_get_unless_zero(&ns->kref))
266 goto fail;
267 if (!try_module_get(ns->ctrl->ops->module))
268 goto fail_put_ns;
269 }
1673f1f0
CH		 270 spin_unlock(&dev_list_lock);
271
272 return ns;
e439bb12
SG		 273
274fail_put_ns:
275 kref_put(&ns->kref, nvme_free_ns);
276fail:
277 spin_unlock(&dev_list_lock);
278 return NULL;
1673f1f0
CH		 279}
280
4160982e 281struct request *nvme_alloc_request(struct request_queue *q,
eb71f435 282 struct nvme_command *cmd, unsigned int flags, int qid)
21d34711 283{
aebf526b 284 unsigned op = nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN;
21d34711 285 struct request *req;
21d34711 286
eb71f435 287 if (qid == NVME_QID_ANY) {
aebf526b 288 req = blk_mq_alloc_request(q, op, flags);
eb71f435 289 } else {
aebf526b 290 req = blk_mq_alloc_request_hctx(q, op, flags,
eb71f435
CH		 291 qid ? qid - 1 : 0);
292 }
21d34711 293 if (IS_ERR(req))
4160982e 294 return req;
21d34711 295
21d34711 296 req->cmd_flags |= REQ_FAILFAST_DRIVER;
d49187e9 297 nvme_req(req)->cmd = cmd;
21d34711 298
4160982e
CH		 299 return req;
300}
576d55d6 301EXPORT_SYMBOL_GPL(nvme_alloc_request);
4160982e 302
f5d11840
JA		 303static int nvme_toggle_streams(struct nvme_ctrl *ctrl, bool enable)
304{
305 struct nvme_command c;
306
307 memset(&c, 0, sizeof(c));
308
309 c.directive.opcode = nvme_admin_directive_send;
310 c.directive.nsid = cpu_to_le32(0xffffffff);
311 c.directive.doper = NVME_DIR_SND_ID_OP_ENABLE;
312 c.directive.dtype = NVME_DIR_IDENTIFY;
313 c.directive.tdtype = NVME_DIR_STREAMS;
314 c.directive.endir = enable ? NVME_DIR_ENDIR : 0;
315
316 return nvme_submit_sync_cmd(ctrl->admin_q, &c, NULL, 0);
317}
318
319static int nvme_disable_streams(struct nvme_ctrl *ctrl)
320{
321 return nvme_toggle_streams(ctrl, false);
322}
323
324static int nvme_enable_streams(struct nvme_ctrl *ctrl)
325{
326 return nvme_toggle_streams(ctrl, true);
327}
328
329static int nvme_get_stream_params(struct nvme_ctrl *ctrl,
330 struct streams_directive_params *s, u32 nsid)
331{
332 struct nvme_command c;
333
334 memset(&c, 0, sizeof(c));
335 memset(s, 0, sizeof(*s));
336
337 c.directive.opcode = nvme_admin_directive_recv;
338 c.directive.nsid = cpu_to_le32(nsid);
dc1a0afb 339 c.directive.numd = cpu_to_le32(sizeof(*s));
f5d11840
JA		 340 c.directive.doper = NVME_DIR_RCV_ST_OP_PARAM;
341 c.directive.dtype = NVME_DIR_STREAMS;
342
343 return nvme_submit_sync_cmd(ctrl->admin_q, &c, s, sizeof(*s));
344}
345
346static int nvme_configure_directives(struct nvme_ctrl *ctrl)
347{
348 struct streams_directive_params s;
349 int ret;
350
351 if (!(ctrl->oacs & NVME_CTRL_OACS_DIRECTIVES))
352 return 0;
353 if (!streams)
354 return 0;
355
356 ret = nvme_enable_streams(ctrl);
357 if (ret)
358 return ret;
359
360 ret = nvme_get_stream_params(ctrl, &s, 0xffffffff);
361 if (ret)
362 return ret;
363
364 ctrl->nssa = le16_to_cpu(s.nssa);
365 if (ctrl->nssa < BLK_MAX_WRITE_HINTS - 1) {
366 dev_info(ctrl->device, "too few streams (%u) available\n",
367 ctrl->nssa);
368 nvme_disable_streams(ctrl);
369 return 0;
370 }
371
372 ctrl->nr_streams = min_t(unsigned, ctrl->nssa, BLK_MAX_WRITE_HINTS - 1);
373 dev_info(ctrl->device, "Using %u streams\n", ctrl->nr_streams);
374 return 0;
375}
376
377/*
378 * Check if 'req' has a write hint associated with it. If it does, assign
379 * a valid namespace stream to the write.
380 */
381static void nvme_assign_write_stream(struct nvme_ctrl *ctrl,
382 struct request *req, u16 *control,
383 u32 *dsmgmt)
384{
385 enum rw_hint streamid = req->write_hint;
386
387 if (streamid == WRITE_LIFE_NOT_SET || streamid == WRITE_LIFE_NONE)
388 streamid = 0;
389 else {
390 streamid--;
391 if (WARN_ON_ONCE(streamid > ctrl->nr_streams))
392 return;
393
394 *control |= NVME_RW_DTYPE_STREAMS;
395 *dsmgmt |= streamid << 16;
396 }
397
398 if (streamid < ARRAY_SIZE(req->q->write_hints))
399 req->q->write_hints[streamid] += blk_rq_bytes(req) >> 9;
400}
401
8093f7ca
ML		 402static inline void nvme_setup_flush(struct nvme_ns *ns,
403 struct nvme_command *cmnd)
404{
405 memset(cmnd, 0, sizeof(*cmnd));
406 cmnd->common.opcode = nvme_cmd_flush;
407 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
408}
409
fc17b653 410static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 411 struct nvme_command *cmnd)
412{
b35ba01e 413 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
8093f7ca 414 struct nvme_dsm_range *range;
b35ba01e 415 struct bio *bio;
8093f7ca 416
b35ba01e 417 range = kmalloc_array(segments, sizeof(*range), GFP_ATOMIC);
8093f7ca 418 if (!range)
fc17b653 419 return BLK_STS_RESOURCE;
8093f7ca 420
b35ba01e
CH		 421 __rq_for_each_bio(bio, req) {
422 u64 slba = nvme_block_nr(ns, bio->bi_iter.bi_sector);
423 u32 nlb = bio->bi_iter.bi_size >> ns->lba_shift;
424
425 range[n].cattr = cpu_to_le32(0);
426 range[n].nlb = cpu_to_le32(nlb);
427 range[n].slba = cpu_to_le64(slba);
428 n++;
429 }
430
431 if (WARN_ON_ONCE(n != segments)) {
432 kfree(range);
fc17b653 433 return BLK_STS_IOERR;
b35ba01e 434 }
8093f7ca
ML		 435
436 memset(cmnd, 0, sizeof(*cmnd));
437 cmnd->dsm.opcode = nvme_cmd_dsm;
438 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
f1dd03a8 439 cmnd->dsm.nr = cpu_to_le32(segments - 1);
8093f7ca
ML		 440 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
441
f9d03f96
CH		 442 req->special_vec.bv_page = virt_to_page(range);
443 req->special_vec.bv_offset = offset_in_page(range);
b35ba01e 444 req->special_vec.bv_len = sizeof(*range) * segments;
f9d03f96 445 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 446
fc17b653 447 return BLK_STS_OK;
8093f7ca 448}
8093f7ca 449
ebe6d874
CH		 450static inline blk_status_t nvme_setup_rw(struct nvme_ns *ns,
451 struct request *req, struct nvme_command *cmnd)
8093f7ca 452{
f5d11840 453 struct nvme_ctrl *ctrl = ns->ctrl;
8093f7ca
ML		 454 u16 control = 0;
455 u32 dsmgmt = 0;
456
ebe6d874
CH		 457 /*
458 * If formated with metadata, require the block layer provide a buffer
459 * unless this namespace is formated such that the metadata can be
460 * stripped/generated by the controller with PRACT=1.
461 */
8fa61121
SG		 462 if (ns && ns->ms &&
463 (!ns->pi_type || ns->ms != sizeof(struct t10_pi_tuple)) &&
ebe6d874
CH		 464 !blk_integrity_rq(req) && !blk_rq_is_passthrough(req))
465 return BLK_STS_NOTSUPP;
466
8093f7ca
ML		 467 if (req->cmd_flags & REQ_FUA)
468 control |= NVME_RW_FUA;
469 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
470 control |= NVME_RW_LR;
471
472 if (req->cmd_flags & REQ_RAHEAD)
473 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
474
475 memset(cmnd, 0, sizeof(*cmnd));
476 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
8093f7ca
ML		 477 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
478 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
479 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
480
f5d11840
JA		 481 if (req_op(req) == REQ_OP_WRITE && ctrl->nr_streams)
482 nvme_assign_write_stream(ctrl, req, &control, &dsmgmt);
483
8093f7ca
ML		 484 if (ns->ms) {
485 switch (ns->pi_type) {
486 case NVME_NS_DPS_PI_TYPE3:
487 control |= NVME_RW_PRINFO_PRCHK_GUARD;
488 break;
489 case NVME_NS_DPS_PI_TYPE1:
490 case NVME_NS_DPS_PI_TYPE2:
491 control |= NVME_RW_PRINFO_PRCHK_GUARD |
492 NVME_RW_PRINFO_PRCHK_REF;
493 cmnd->rw.reftag = cpu_to_le32(
494 nvme_block_nr(ns, blk_rq_pos(req)));
495 break;
496 }
497 if (!blk_integrity_rq(req))
498 control |= NVME_RW_PRINFO_PRACT;
499 }
500
501 cmnd->rw.control = cpu_to_le16(control);
502 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
ebe6d874 503 return 0;
8093f7ca
ML		 504}
505
fc17b653 506blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 507 struct nvme_command *cmd)
508{
fc17b653 509 blk_status_t ret = BLK_STS_OK;
8093f7ca 510
987f699a 511 if (!(req->rq_flags & RQF_DONTPREP)) {
44e44b29 512 nvme_req(req)->retries = 0;
27fa9bc5 513 nvme_req(req)->flags = 0;
987f699a
CH		 514 req->rq_flags |= RQF_DONTPREP;
515 }
516
aebf526b
CH		 517 switch (req_op(req)) {
518 case REQ_OP_DRV_IN:
519 case REQ_OP_DRV_OUT:
d49187e9 520 memcpy(cmd, nvme_req(req)->cmd, sizeof(*cmd));
aebf526b
CH		 521 break;
522 case REQ_OP_FLUSH:
8093f7ca 523 nvme_setup_flush(ns, cmd);
aebf526b 524 break;
e850fd16
CH		 525 case REQ_OP_WRITE_ZEROES:
526 /* currently only aliased to deallocate for a few ctrls: */
aebf526b 527 case REQ_OP_DISCARD:
8093f7ca 528 ret = nvme_setup_discard(ns, req, cmd);
aebf526b
CH		 529 break;
530 case REQ_OP_READ:
531 case REQ_OP_WRITE:
ebe6d874 532 ret = nvme_setup_rw(ns, req, cmd);
aebf526b
CH		 533 break;
534 default:
535 WARN_ON_ONCE(1);
fc17b653 536 return BLK_STS_IOERR;
aebf526b 537 }
8093f7ca 538
721b3917 539 cmd->common.command_id = req->tag;
8093f7ca
ML		 540 return ret;
541}
542EXPORT_SYMBOL_GPL(nvme_setup_cmd);
543
4160982e
CH		 544/*
545 * Returns 0 on success. If the result is negative, it's a Linux error code;
546 * if the result is positive, it's an NVM Express status code
547 */
548int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 549 union nvme_result *result, void *buffer, unsigned bufflen,
eb71f435 550 unsigned timeout, int qid, int at_head, int flags)
4160982e
CH		 551{
552 struct request *req;
553 int ret;
554
eb71f435 555 req = nvme_alloc_request(q, cmd, flags, qid);
4160982e
CH		 556 if (IS_ERR(req))
557 return PTR_ERR(req);
558
559 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
560
21d34711
CH		 561 if (buffer && bufflen) {
562 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
563 if (ret)
564 goto out;
4160982e
CH		 565 }
566
eb71f435 567 blk_execute_rq(req->q, NULL, req, at_head);
d49187e9
CH		 568 if (result)
569 *result = nvme_req(req)->result;
27fa9bc5
CH		 570 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
571 ret = -EINTR;
572 else
573 ret = nvme_req(req)->status;
4160982e
CH		 574 out:
575 blk_mq_free_request(req);
576 return ret;
577}
eb71f435 578EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH		 579
580int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
581 void *buffer, unsigned bufflen)
582{
eb71f435
CH		 583 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 0,
584 NVME_QID_ANY, 0, 0);
4160982e 585}
576d55d6 586EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 587
0b7f1f26
KB		 588int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
589 void __user *ubuffer, unsigned bufflen,
590 void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
591 u32 *result, unsigned timeout)
4160982e 592{
7a5abb4b 593 bool write = nvme_is_write(cmd);
0b7f1f26
KB		 594 struct nvme_ns *ns = q->queuedata;
595 struct gendisk *disk = ns ? ns->disk : NULL;
4160982e 596 struct request *req;
0b7f1f26
KB		 597 struct bio *bio = NULL;
598 void *meta = NULL;
4160982e
CH		 599 int ret;
600
eb71f435 601 req = nvme_alloc_request(q, cmd, 0, NVME_QID_ANY);
4160982e
CH		 602 if (IS_ERR(req))
603 return PTR_ERR(req);
604
605 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
606
607 if (ubuffer && bufflen) {
21d34711
CH		 608 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
609 GFP_KERNEL);
610 if (ret)
611 goto out;
612 bio = req->bio;
21d34711 613
0b7f1f26
KB		 614 if (!disk)
615 goto submit;
616 bio->bi_bdev = bdget_disk(disk, 0);
617 if (!bio->bi_bdev) {
618 ret = -ENODEV;
619 goto out_unmap;
620 }
621
e9fc63d6 622 if (meta_buffer && meta_len) {
0b7f1f26
KB		 623 struct bio_integrity_payload *bip;
624
625 meta = kmalloc(meta_len, GFP_KERNEL);
626 if (!meta) {
627 ret = -ENOMEM;
628 goto out_unmap;
629 }
630
631 if (write) {
632 if (copy_from_user(meta, meta_buffer,
633 meta_len)) {
634 ret = -EFAULT;
635 goto out_free_meta;
636 }
637 }
638
639 bip = bio_integrity_alloc(bio, GFP_KERNEL, 1);
06c1e390
KB		 640 if (IS_ERR(bip)) {
641 ret = PTR_ERR(bip);
0b7f1f26
KB		 642 goto out_free_meta;
643 }
644
645 bip->bip_iter.bi_size = meta_len;
646 bip->bip_iter.bi_sector = meta_seed;
647
648 ret = bio_integrity_add_page(bio, virt_to_page(meta),
649 meta_len, offset_in_page(meta));
650 if (ret != meta_len) {
651 ret = -ENOMEM;
652 goto out_free_meta;
653 }
654 }
655 }
656 submit:
657 blk_execute_rq(req->q, disk, req, 0);
27fa9bc5
CH		 658 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
659 ret = -EINTR;
660 else
661 ret = nvme_req(req)->status;
21d34711 662 if (result)
d49187e9 663 *result = le32_to_cpu(nvme_req(req)->result.u32);
0b7f1f26
KB		 664 if (meta && !ret && !write) {
665 if (copy_to_user(meta_buffer, meta, meta_len))
666 ret = -EFAULT;
667 }
668 out_free_meta:
669 kfree(meta);
670 out_unmap:
671 if (bio) {
672 if (disk && bio->bi_bdev)
673 bdput(bio->bi_bdev);
674 blk_rq_unmap_user(bio);
675 }
21d34711
CH		 676 out:
677 blk_mq_free_request(req);
678 return ret;
679}
680
0b7f1f26
KB		 681int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
682 void __user *ubuffer, unsigned bufflen, u32 *result,
683 unsigned timeout)
684{
685 return __nvme_submit_user_cmd(q, cmd, ubuffer, bufflen, NULL, 0, 0,
686 result, timeout);
687}
688
2a842aca 689static void nvme_keep_alive_end_io(struct request *rq, blk_status_t status)
038bd4cb
SG		 690{
691 struct nvme_ctrl *ctrl = rq->end_io_data;
692
693 blk_mq_free_request(rq);
694
2a842aca 695 if (status) {
038bd4cb 696 dev_err(ctrl->device,
2a842aca
CH		 697 "failed nvme_keep_alive_end_io error=%d\n",
698 status);
038bd4cb
SG		 699 return;
700 }
701
702 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
703}
704
705static int nvme_keep_alive(struct nvme_ctrl *ctrl)
706{
707 struct nvme_command c;
708 struct request *rq;
709
710 memset(&c, 0, sizeof(c));
711 c.common.opcode = nvme_admin_keep_alive;
712
713 rq = nvme_alloc_request(ctrl->admin_q, &c, BLK_MQ_REQ_RESERVED,
714 NVME_QID_ANY);
715 if (IS_ERR(rq))
716 return PTR_ERR(rq);
717
718 rq->timeout = ctrl->kato * HZ;
719 rq->end_io_data = ctrl;
720
721 blk_execute_rq_nowait(rq->q, NULL, rq, 0, nvme_keep_alive_end_io);
722
723 return 0;
724}
725
726static void nvme_keep_alive_work(struct work_struct *work)
727{
728 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
729 struct nvme_ctrl, ka_work);
730
731 if (nvme_keep_alive(ctrl)) {
732 /* allocation failure, reset the controller */
733 dev_err(ctrl->device, "keep-alive failed\n");
39bdc590 734 nvme_reset_ctrl(ctrl);
038bd4cb
SG		 735 return;
736 }
737}
738
739void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
740{
741 if (unlikely(ctrl->kato == 0))
742 return;
743
744 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
745 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
746}
747EXPORT_SYMBOL_GPL(nvme_start_keep_alive);
748
749void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
750{
751 if (unlikely(ctrl->kato == 0))
752 return;
753
754 cancel_delayed_work_sync(&ctrl->ka_work);
755}
756EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
757
3f7f25a9 758static int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH		 759{
760 struct nvme_command c = { };
761 int error;
762
763 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
764 c.identify.opcode = nvme_admin_identify;
986994a2 765 c.identify.cns = NVME_ID_CNS_CTRL;
21d34711
CH		 766
767 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
768 if (!*id)
769 return -ENOMEM;
770
771 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
772 sizeof(struct nvme_id_ctrl));
773 if (error)
774 kfree(*id);
775 return error;
776}
777
3b22ba26
JT		 778static int nvme_identify_ns_descs(struct nvme_ns *ns, unsigned nsid)
779{
780 struct nvme_command c = { };
781 int status;
782 void *data;
783 int pos;
784 int len;
785
786 c.identify.opcode = nvme_admin_identify;
787 c.identify.nsid = cpu_to_le32(nsid);
788 c.identify.cns = NVME_ID_CNS_NS_DESC_LIST;
789
790 data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
791 if (!data)
792 return -ENOMEM;
793
794 status = nvme_submit_sync_cmd(ns->ctrl->admin_q, &c, data,
795 NVME_IDENTIFY_DATA_SIZE);
796 if (status)
797 goto free_data;
798
799 for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) {
800 struct nvme_ns_id_desc *cur = data + pos;
801
802 if (cur->nidl == 0)
803 break;
804
805 switch (cur->nidt) {
806 case NVME_NIDT_EUI64:
807 if (cur->nidl != NVME_NIDT_EUI64_LEN) {
808 dev_warn(ns->ctrl->device,
809 "ctrl returned bogus length: %d for NVME_NIDT_EUI64\n",
810 cur->nidl);
811 goto free_data;
812 }
813 len = NVME_NIDT_EUI64_LEN;
814 memcpy(ns->eui, data + pos + sizeof(*cur), len);
815 break;
816 case NVME_NIDT_NGUID:
817 if (cur->nidl != NVME_NIDT_NGUID_LEN) {
818 dev_warn(ns->ctrl->device,
819 "ctrl returned bogus length: %d for NVME_NIDT_NGUID\n",
820 cur->nidl);
821 goto free_data;
822 }
823 len = NVME_NIDT_NGUID_LEN;
824 memcpy(ns->nguid, data + pos + sizeof(*cur), len);
825 break;
826 case NVME_NIDT_UUID:
827 if (cur->nidl != NVME_NIDT_UUID_LEN) {
828 dev_warn(ns->ctrl->device,
829 "ctrl returned bogus length: %d for NVME_NIDT_UUID\n",
830 cur->nidl);
831 goto free_data;
832 }
833 len = NVME_NIDT_UUID_LEN;
834 uuid_copy(&ns->uuid, data + pos + sizeof(*cur));
835 break;
836 default:
837 /* Skip unnkown types */
838 len = cur->nidl;
839 break;
840 }
841
842 len += sizeof(*cur);
843 }
844free_data:
845 kfree(data);
846 return status;
847}
848
540c801c
KB		 849static int nvme_identify_ns_list(struct nvme_ctrl *dev, unsigned nsid, __le32 *ns_list)
850{
851 struct nvme_command c = { };
852
853 c.identify.opcode = nvme_admin_identify;
986994a2 854 c.identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST;
540c801c
KB		 855 c.identify.nsid = cpu_to_le32(nsid);
856 return nvme_submit_sync_cmd(dev->admin_q, &c, ns_list, 0x1000);
857}
858
3f7f25a9 859static int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
21d34711
CH		 860 struct nvme_id_ns **id)
861{
862 struct nvme_command c = { };
863 int error;
864
865 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
778f067c
MG		 866 c.identify.opcode = nvme_admin_identify;
867 c.identify.nsid = cpu_to_le32(nsid);
986994a2 868 c.identify.cns = NVME_ID_CNS_NS;
21d34711
CH		 869
870 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
871 if (!*id)
872 return -ENOMEM;
873
874 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
875 sizeof(struct nvme_id_ns));
876 if (error)
877 kfree(*id);
878 return error;
879}
880
3f7f25a9 881static int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
1a6fe74d 882 void *buffer, size_t buflen, u32 *result)
21d34711
CH		 883{
884 struct nvme_command c;
d49187e9 885 union nvme_result res;
1cb3cce5 886 int ret;
21d34711
CH		 887
888 memset(&c, 0, sizeof(c));
889 c.features.opcode = nvme_admin_set_features;
21d34711
CH		 890 c.features.fid = cpu_to_le32(fid);
891 c.features.dword11 = cpu_to_le32(dword11);
892
d49187e9 893 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
1a6fe74d 894 buffer, buflen, 0, NVME_QID_ANY, 0, 0);
9b47f77a 895 if (ret >= 0 && result)
d49187e9 896 *result = le32_to_cpu(res.u32);
1cb3cce5 897 return ret;
21d34711
CH		 898}
899
9a0be7ab
CH		 900int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
901{
902 u32 q_count = (*count - 1) | ((*count - 1) << 16);
903 u32 result;
904 int status, nr_io_queues;
905
1a6fe74d 906 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 907 &result);
f5fa90dc 908 if (status < 0)
9a0be7ab
CH		 909 return status;
910
f5fa90dc
CH		 911 /*
912 * Degraded controllers might return an error when setting the queue
913 * count. We still want to be able to bring them online and offer
914 * access to the admin queue, as that might be only way to fix them up.
915 */
916 if (status > 0) {
f0425db0 917 dev_err(ctrl->device, "Could not set queue count (%d)\n", status);
f5fa90dc
CH		 918 *count = 0;
919 } else {
920 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
921 *count = min(*count, nr_io_queues);
922 }
923
9a0be7ab
CH		 924 return 0;
925}
576d55d6 926EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 927
1673f1f0
CH		 928static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
929{
930 struct nvme_user_io io;
931 struct nvme_command c;
932 unsigned length, meta_len;
933 void __user *metadata;
934
935 if (copy_from_user(&io, uio, sizeof(io)))
936 return -EFAULT;
63088ec7
KB		 937 if (io.flags)
938 return -EINVAL;
1673f1f0
CH		 939
940 switch (io.opcode) {
941 case nvme_cmd_write:
942 case nvme_cmd_read:
943 case nvme_cmd_compare:
944 break;
945 default:
946 return -EINVAL;
947 }
948
949 length = (io.nblocks + 1) << ns->lba_shift;
950 meta_len = (io.nblocks + 1) * ns->ms;
951 metadata = (void __user *)(uintptr_t)io.metadata;
952
953 if (ns->ext) {
954 length += meta_len;
955 meta_len = 0;
956 } else if (meta_len) {
957 if ((io.metadata & 3) || !io.metadata)
958 return -EINVAL;
959 }
960
961 memset(&c, 0, sizeof(c));
962 c.rw.opcode = io.opcode;
963 c.rw.flags = io.flags;
964 c.rw.nsid = cpu_to_le32(ns->ns_id);
965 c.rw.slba = cpu_to_le64(io.slba);
966 c.rw.length = cpu_to_le16(io.nblocks);
967 c.rw.control = cpu_to_le16(io.control);
968 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
969 c.rw.reftag = cpu_to_le32(io.reftag);
970 c.rw.apptag = cpu_to_le16(io.apptag);
971 c.rw.appmask = cpu_to_le16(io.appmask);
972
973 return __nvme_submit_user_cmd(ns->queue, &c,
974 (void __user *)(uintptr_t)io.addr, length,
975 metadata, meta_len, io.slba, NULL, 0);
976}
977
f3ca80fc 978static int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1673f1f0
CH		 979 struct nvme_passthru_cmd __user *ucmd)
980{
981 struct nvme_passthru_cmd cmd;
982 struct nvme_command c;
983 unsigned timeout = 0;
984 int status;
985
986 if (!capable(CAP_SYS_ADMIN))
987 return -EACCES;
988 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
989 return -EFAULT;
63088ec7
KB		 990 if (cmd.flags)
991 return -EINVAL;
1673f1f0
CH		 992
993 memset(&c, 0, sizeof(c));
994 c.common.opcode = cmd.opcode;
995 c.common.flags = cmd.flags;
996 c.common.nsid = cpu_to_le32(cmd.nsid);
997 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
998 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
999 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1000 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1001 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1002 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1003 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1004 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1005
1006 if (cmd.timeout_ms)
1007 timeout = msecs_to_jiffies(cmd.timeout_ms);
1008
1009 status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c,
d1ea7be5 1010 (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
1673f1f0
CH		 1011 &cmd.result, timeout);
1012 if (status >= 0) {
1013 if (put_user(cmd.result, &ucmd->result))
1014 return -EFAULT;
1015 }
1016
1017 return status;
1018}
1019
1020static int nvme_ioctl(struct block_device *bdev, fmode_t mode,
1021 unsigned int cmd, unsigned long arg)
1022{
1023 struct nvme_ns *ns = bdev->bd_disk->private_data;
1024
1025 switch (cmd) {
1026 case NVME_IOCTL_ID:
1027 force_successful_syscall_return();
1028 return ns->ns_id;
1029 case NVME_IOCTL_ADMIN_CMD:
1030 return nvme_user_cmd(ns->ctrl, NULL, (void __user *)arg);
1031 case NVME_IOCTL_IO_CMD:
1032 return nvme_user_cmd(ns->ctrl, ns, (void __user *)arg);
1033 case NVME_IOCTL_SUBMIT_IO:
1034 return nvme_submit_io(ns, (void __user *)arg);
1673f1f0 1035 default:
84d4add7
MB		 1036#ifdef CONFIG_NVM
1037 if (ns->ndev)
1038 return nvme_nvm_ioctl(ns, cmd, arg);
1039#endif
a98e58e5 1040 if (is_sed_ioctl(cmd))
4f1244c8 1041 return sed_ioctl(ns->ctrl->opal_dev, cmd,
e225c20e 1042 (void __user *) arg);
1673f1f0
CH		 1043 return -ENOTTY;
1044 }
1045}
1046
1047#ifdef CONFIG_COMPAT
1048static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1049 unsigned int cmd, unsigned long arg)
1050{
1673f1f0
CH		 1051 return nvme_ioctl(bdev, mode, cmd, arg);
1052}
1053#else
1054#define nvme_compat_ioctl NULL
1055#endif
1056
1057static int nvme_open(struct block_device *bdev, fmode_t mode)
1058{
1059 return nvme_get_ns_from_disk(bdev->bd_disk) ? 0 : -ENXIO;
1060}
1061
1062static void nvme_release(struct gendisk *disk, fmode_t mode)
1063{
e439bb12
SG		 1064 struct nvme_ns *ns = disk->private_data;
1065
1066 module_put(ns->ctrl->ops->module);
1067 nvme_put_ns(ns);
1673f1f0
CH		 1068}
1069
1070static int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1071{
1072 /* some standard values */
1073 geo->heads = 1 << 6;
1074 geo->sectors = 1 << 5;
1075 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
1076 return 0;
1077}
1078
1079#ifdef CONFIG_BLK_DEV_INTEGRITY
c81bfba9
CH		 1080static void nvme_prep_integrity(struct gendisk *disk, struct nvme_id_ns *id,
1081 u16 bs)
1082{
1083 struct nvme_ns *ns = disk->private_data;
1084 u16 old_ms = ns->ms;
1085 u8 pi_type = 0;
1086
1087 ns->ms = le16_to_cpu(id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ms);
1088 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
1089
1090 /* PI implementation requires metadata equal t10 pi tuple size */
1091 if (ns->ms == sizeof(struct t10_pi_tuple))
1092 pi_type = id->dps & NVME_NS_DPS_PI_MASK;
1093
1094 if (blk_get_integrity(disk) &&
1095 (ns->pi_type != pi_type || ns->ms != old_ms ||
1096 bs != queue_logical_block_size(disk->queue) ||
1097 (ns->ms && ns->ext)))
1098 blk_integrity_unregister(disk);
1099
1100 ns->pi_type = pi_type;
1101}
1102
1673f1f0
CH		 1103static void nvme_init_integrity(struct nvme_ns *ns)
1104{
1105 struct blk_integrity integrity;
1106
fa9a89fc 1107 memset(&integrity, 0, sizeof(integrity));
1673f1f0
CH		 1108 switch (ns->pi_type) {
1109 case NVME_NS_DPS_PI_TYPE3:
1110 integrity.profile = &t10_pi_type3_crc;
ba36c21b
NB		 1111 integrity.tag_size = sizeof(u16) + sizeof(u32);
1112 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1113 break;
1114 case NVME_NS_DPS_PI_TYPE1:
1115 case NVME_NS_DPS_PI_TYPE2:
1116 integrity.profile = &t10_pi_type1_crc;
ba36c21b
NB		 1117 integrity.tag_size = sizeof(u16);
1118 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1119 break;
1120 default:
1121 integrity.profile = NULL;
1122 break;
1123 }
1124 integrity.tuple_size = ns->ms;
1125 blk_integrity_register(ns->disk, &integrity);
1126 blk_queue_max_integrity_segments(ns->queue, 1);
1127}
1128#else
c81bfba9
CH		 1129static void nvme_prep_integrity(struct gendisk *disk, struct nvme_id_ns *id,
1130 u16 bs)
1131{
1132}
1673f1f0
CH		 1133static void nvme_init_integrity(struct nvme_ns *ns)
1134{
1135}
1136#endif /* CONFIG_BLK_DEV_INTEGRITY */
1137
6b8190d6
SB		 1138static void nvme_set_chunk_size(struct nvme_ns *ns)
1139{
1140 u32 chunk_size = (((u32)ns->noiob) << (ns->lba_shift - 9));
1141 blk_queue_chunk_sectors(ns->queue, rounddown_pow_of_two(chunk_size));
1142}
1143
1673f1f0
CH		 1144static void nvme_config_discard(struct nvme_ns *ns)
1145{
08095e70 1146 struct nvme_ctrl *ctrl = ns->ctrl;
1673f1f0 1147 u32 logical_block_size = queue_logical_block_size(ns->queue);
08095e70 1148
b35ba01e
CH		 1149 BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) <
1150 NVME_DSM_MAX_RANGES);
1151
f5d11840
JA		 1152 if (ctrl->nr_streams && ns->sws && ns->sgs) {
1153 unsigned int sz = logical_block_size * ns->sws * ns->sgs;
1154
1155 ns->queue->limits.discard_alignment = sz;
1156 ns->queue->limits.discard_granularity = sz;
1157 } else {
1158 ns->queue->limits.discard_alignment = logical_block_size;
1159 ns->queue->limits.discard_granularity = logical_block_size;
1160 }
bd0fc288 1161 blk_queue_max_discard_sectors(ns->queue, UINT_MAX);
b35ba01e 1162 blk_queue_max_discard_segments(ns->queue, NVME_DSM_MAX_RANGES);
1673f1f0 1163 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
e850fd16
CH		 1164
1165 if (ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
1166 blk_queue_max_write_zeroes_sectors(ns->queue, UINT_MAX);
1673f1f0
CH		 1167}
1168
ac81bfa9 1169static int nvme_revalidate_ns(struct nvme_ns *ns, struct nvme_id_ns **id)
1673f1f0 1170{
ac81bfa9 1171 if (nvme_identify_ns(ns->ctrl, ns->ns_id, id)) {
b0b4e09c 1172 dev_warn(ns->ctrl->dev, "%s: Identify failure\n", __func__);
1673f1f0
CH		 1173 return -ENODEV;
1174 }
1673f1f0 1175
ac81bfa9
MB		 1176 if ((*id)->ncap == 0) {
1177 kfree(*id);
1178 return -ENODEV;
1673f1f0
CH		 1179 }
1180
8ef2074d 1181 if (ns->ctrl->vs >= NVME_VS(1, 1, 0))
ac81bfa9 1182 memcpy(ns->eui, (*id)->eui64, sizeof(ns->eui));
8ef2074d 1183 if (ns->ctrl->vs >= NVME_VS(1, 2, 0))
90985b84 1184 memcpy(ns->nguid, (*id)->nguid, sizeof(ns->nguid));
3b22ba26
JT		 1185 if (ns->ctrl->vs >= NVME_VS(1, 3, 0)) {
1186 /* Don't treat error as fatal we potentially
1187 * already have a NGUID or EUI-64
1188 */
1189 if (nvme_identify_ns_descs(ns, ns->ns_id))
1190 dev_warn(ns->ctrl->device,
1191 "%s: Identify Descriptors failed\n", __func__);
1192 }
ac81bfa9
MB		 1193
1194 return 0;
1195}
1196
1197static void __nvme_revalidate_disk(struct gendisk *disk, struct nvme_id_ns *id)
1198{
1199 struct nvme_ns *ns = disk->private_data;
f5d11840 1200 struct nvme_ctrl *ctrl = ns->ctrl;
c81bfba9 1201 u16 bs;
1673f1f0
CH		 1202
1203 /*
1204 * If identify namespace failed, use default 512 byte block size so
1205 * block layer can use before failing read/write for 0 capacity.
1206 */
c81bfba9 1207 ns->lba_shift = id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ds;
1673f1f0
CH		 1208 if (ns->lba_shift == 0)
1209 ns->lba_shift = 9;
1210 bs = 1 << ns->lba_shift;
6b8190d6 1211 ns->noiob = le16_to_cpu(id->noiob);
1673f1f0
CH		 1212
1213 blk_mq_freeze_queue(disk->queue);
1673f1f0 1214
f5d11840 1215 if (ctrl->ops->flags & NVME_F_METADATA_SUPPORTED)
c81bfba9 1216 nvme_prep_integrity(disk, id, bs);
1673f1f0 1217 blk_queue_logical_block_size(ns->queue, bs);
6b8190d6
SB		 1218 if (ns->noiob)
1219 nvme_set_chunk_size(ns);
4b9d5b15 1220 if (ns->ms && !blk_get_integrity(disk) && !ns->ext)
1673f1f0 1221 nvme_init_integrity(ns);
1673f1f0
CH		 1222 if (ns->ms && !(ns->ms == 8 && ns->pi_type) && !blk_get_integrity(disk))
1223 set_capacity(disk, 0);
1224 else
1225 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1226
f5d11840 1227 if (ctrl->oncs & NVME_CTRL_ONCS_DSM)
1673f1f0
CH		 1228 nvme_config_discard(ns);
1229 blk_mq_unfreeze_queue(disk->queue);
ac81bfa9 1230}
1673f1f0 1231
ac81bfa9
MB		 1232static int nvme_revalidate_disk(struct gendisk *disk)
1233{
1234 struct nvme_ns *ns = disk->private_data;
1235 struct nvme_id_ns *id = NULL;
1236 int ret;
1237
1238 if (test_bit(NVME_NS_DEAD, &ns->flags)) {
1239 set_capacity(disk, 0);
1240 return -ENODEV;
1241 }
1242
1243 ret = nvme_revalidate_ns(ns, &id);
1244 if (ret)
1245 return ret;
1246
1247 __nvme_revalidate_disk(disk, id);
1673f1f0 1248 kfree(id);
ac81bfa9 1249
1673f1f0
CH		 1250 return 0;
1251}
1252
1253static char nvme_pr_type(enum pr_type type)
1254{
1255 switch (type) {
1256 case PR_WRITE_EXCLUSIVE:
1257 return 1;
1258 case PR_EXCLUSIVE_ACCESS:
1259 return 2;
1260 case PR_WRITE_EXCLUSIVE_REG_ONLY:
1261 return 3;
1262 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
1263 return 4;
1264 case PR_WRITE_EXCLUSIVE_ALL_REGS:
1265 return 5;
1266 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
1267 return 6;
1268 default:
1269 return 0;
1270 }
1271};
1272
1273static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
1274 u64 key, u64 sa_key, u8 op)
1275{
1276 struct nvme_ns *ns = bdev->bd_disk->private_data;
1277 struct nvme_command c;
1278 u8 data[16] = { 0, };
1279
1280 put_unaligned_le64(key, &data[0]);
1281 put_unaligned_le64(sa_key, &data[8]);
1282
1283 memset(&c, 0, sizeof(c));
1284 c.common.opcode = op;
1285 c.common.nsid = cpu_to_le32(ns->ns_id);
1286 c.common.cdw10[0] = cpu_to_le32(cdw10);
1287
1288 return nvme_submit_sync_cmd(ns->queue, &c, data, 16);
1289}
1290
1291static int nvme_pr_register(struct block_device *bdev, u64 old,
1292 u64 new, unsigned flags)
1293{
1294 u32 cdw10;
1295
1296 if (flags & ~PR_FL_IGNORE_KEY)
1297 return -EOPNOTSUPP;
1298
1299 cdw10 = old ? 2 : 0;
1300 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
1301 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
1302 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
1303}
1304
1305static int nvme_pr_reserve(struct block_device *bdev, u64 key,
1306 enum pr_type type, unsigned flags)
1307{
1308 u32 cdw10;
1309
1310 if (flags & ~PR_FL_IGNORE_KEY)
1311 return -EOPNOTSUPP;
1312
1313 cdw10 = nvme_pr_type(type) << 8;
1314 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
1315 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
1316}
1317
1318static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
1319 enum pr_type type, bool abort)
1320{
1321 u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
1322 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
1323}
1324
1325static int nvme_pr_clear(struct block_device *bdev, u64 key)
1326{
8c0b3915 1327 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
1673f1f0
CH		 1328 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
1329}
1330
1331static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
1332{
1333 u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
1334 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
1335}
1336
1337static const struct pr_ops nvme_pr_ops = {
1338 .pr_register = nvme_pr_register,
1339 .pr_reserve = nvme_pr_reserve,
1340 .pr_release = nvme_pr_release,
1341 .pr_preempt = nvme_pr_preempt,
1342 .pr_clear = nvme_pr_clear,
1343};
1344
a98e58e5 1345#ifdef CONFIG_BLK_SED_OPAL
4f1244c8
CH		 1346int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
1347 bool send)
a98e58e5 1348{
4f1244c8 1349 struct nvme_ctrl *ctrl = data;
a98e58e5 1350 struct nvme_command cmd;
a98e58e5
SB		 1351
1352 memset(&cmd, 0, sizeof(cmd));
1353 if (send)
1354 cmd.common.opcode = nvme_admin_security_send;
1355 else
1356 cmd.common.opcode = nvme_admin_security_recv;
a98e58e5
SB		 1357 cmd.common.nsid = 0;
1358 cmd.common.cdw10[0] = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
1359 cmd.common.cdw10[1] = cpu_to_le32(len);
1360
1361 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len,
1362 ADMIN_TIMEOUT, NVME_QID_ANY, 1, 0);
1363}
1364EXPORT_SYMBOL_GPL(nvme_sec_submit);
1365#endif /* CONFIG_BLK_SED_OPAL */
1366
5bae7f73 1367static const struct block_device_operations nvme_fops = {
1673f1f0
CH		 1368 .owner = THIS_MODULE,
1369 .ioctl = nvme_ioctl,
1370 .compat_ioctl = nvme_compat_ioctl,
1371 .open = nvme_open,
1372 .release = nvme_release,
1373 .getgeo = nvme_getgeo,
1374 .revalidate_disk= nvme_revalidate_disk,
1375 .pr_ops = &nvme_pr_ops,
1376};
1377
5fd4ce1b
CH		 1378static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
1379{
1380 unsigned long timeout =
1381 ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1382 u32 csts, bit = enabled ? NVME_CSTS_RDY : 0;
1383 int ret;
1384
1385 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB		 1386 if (csts == ~0)
1387 return -ENODEV;
5fd4ce1b
CH		 1388 if ((csts & NVME_CSTS_RDY) == bit)
1389 break;
1390
1391 msleep(100);
1392 if (fatal_signal_pending(current))
1393 return -EINTR;
1394 if (time_after(jiffies, timeout)) {
1b3c47c1 1395 dev_err(ctrl->device,
5fd4ce1b
CH		 1396 "Device not ready; aborting %s\n", enabled ?
1397 "initialisation" : "reset");
1398 return -ENODEV;
1399 }
1400 }
1401
1402 return ret;
1403}
1404
1405/*
1406 * If the device has been passed off to us in an enabled state, just clear
1407 * the enabled bit. The spec says we should set the 'shutdown notification
1408 * bits', but doing so may cause the device to complete commands to the
1409 * admin queue ... and we don't know what memory that might be pointing at!
1410 */
1411int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1412{
1413 int ret;
1414
1415 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1416 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
1417
1418 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1419 if (ret)
1420 return ret;
54adc010 1421
b5a10c5f 1422 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010
GP		 1423 msleep(NVME_QUIRK_DELAY_AMOUNT);
1424
5fd4ce1b
CH		 1425 return nvme_wait_ready(ctrl, cap, false);
1426}
576d55d6 1427EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b
CH		 1428
1429int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1430{
1431 /*
1432 * Default to a 4K page size, with the intention to update this
1433 * path in the future to accomodate architectures with differing
1434 * kernel and IO page sizes.
1435 */
1436 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12, page_shift = 12;
1437 int ret;
1438
1439 if (page_shift < dev_page_min) {
1b3c47c1 1440 dev_err(ctrl->device,
5fd4ce1b
CH		 1441 "Minimum device page size %u too large for host (%u)\n",
1442 1 << dev_page_min, 1 << page_shift);
1443 return -ENODEV;
1444 }
1445
1446 ctrl->page_size = 1 << page_shift;
1447
1448 ctrl->ctrl_config = NVME_CC_CSS_NVM;
1449 ctrl->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1450 ctrl->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1451 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1452 ctrl->ctrl_config |= NVME_CC_ENABLE;
1453
1454 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1455 if (ret)
1456 return ret;
1457 return nvme_wait_ready(ctrl, cap, true);
1458}
576d55d6 1459EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b
CH		 1460
1461int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl)
1462{
b3b1b0b0 1463 unsigned long timeout = jiffies + (shutdown_timeout * HZ);
5fd4ce1b
CH		 1464 u32 csts;
1465 int ret;
1466
1467 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1468 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
1469
1470 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1471 if (ret)
1472 return ret;
1473
1474 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
1475 if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_CMPLT)
1476 break;
1477
1478 msleep(100);
1479 if (fatal_signal_pending(current))
1480 return -EINTR;
1481 if (time_after(jiffies, timeout)) {
1b3c47c1 1482 dev_err(ctrl->device,
5fd4ce1b
CH		 1483 "Device shutdown incomplete; abort shutdown\n");
1484 return -ENODEV;
1485 }
1486 }
1487
1488 return ret;
1489}
576d55d6 1490EXPORT_SYMBOL_GPL(nvme_shutdown_ctrl);
5fd4ce1b 1491
da35825d
CH		 1492static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
1493 struct request_queue *q)
1494{
7c88cb00
JA		 1495 bool vwc = false;
1496
da35825d 1497 if (ctrl->max_hw_sectors) {
45686b61
CH		 1498 u32 max_segments =
1499 (ctrl->max_hw_sectors / (ctrl->page_size >> 9)) + 1;
1500
da35825d 1501 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
45686b61 1502 blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
da35825d 1503 }
e6282aef
KB		 1504 if (ctrl->quirks & NVME_QUIRK_STRIPE_SIZE)
1505 blk_queue_chunk_sectors(q, ctrl->max_hw_sectors);
da35825d 1506 blk_queue_virt_boundary(q, ctrl->page_size - 1);
7c88cb00
JA		 1507 if (ctrl->vwc & NVME_CTRL_VWC_PRESENT)
1508 vwc = true;
1509 blk_queue_write_cache(q, vwc, vwc);
da35825d
CH		 1510}
1511
c5552fde
AL		 1512static void nvme_configure_apst(struct nvme_ctrl *ctrl)
1513{
1514 /*
1515 * APST (Autonomous Power State Transition) lets us program a
1516 * table of power state transitions that the controller will
1517 * perform automatically. We configure it with a simple
1518 * heuristic: we are willing to spend at most 2% of the time
1519 * transitioning between power states. Therefore, when running
1520 * in any given state, we will enter the next lower-power
76e4ad09 1521 * non-operational state after waiting 50 * (enlat + exlat)
da87591b 1522 * microseconds, as long as that state's exit latency is under
c5552fde
AL		 1523 * the requested maximum latency.
1524 *
1525 * We will not autonomously enter any non-operational state for
1526 * which the total latency exceeds ps_max_latency_us. Users
1527 * can set ps_max_latency_us to zero to turn off APST.
1528 */
1529
1530 unsigned apste;
1531 struct nvme_feat_auto_pst *table;
fb0dc399
AL		 1532 u64 max_lat_us = 0;
1533 int max_ps = -1;
c5552fde
AL		 1534 int ret;
1535
1536 /*
1537 * If APST isn't supported or if we haven't been initialized yet,
1538 * then don't do anything.
1539 */
1540 if (!ctrl->apsta)
1541 return;
1542
1543 if (ctrl->npss > 31) {
1544 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
1545 return;
1546 }
1547
1548 table = kzalloc(sizeof(*table), GFP_KERNEL);
1549 if (!table)
1550 return;
1551
76a5af84 1552 if (!ctrl->apst_enabled || ctrl->ps_max_latency_us == 0) {
c5552fde
AL		 1553 /* Turn off APST. */
1554 apste = 0;
fb0dc399 1555 dev_dbg(ctrl->device, "APST disabled\n");
c5552fde
AL		 1556 } else {
1557 __le64 target = cpu_to_le64(0);
1558 int state;
1559
1560 /*
1561 * Walk through all states from lowest- to highest-power.
1562 * According to the spec, lower-numbered states use more
1563 * power. NPSS, despite the name, is the index of the
1564 * lowest-power state, not the number of states.
1565 */
1566 for (state = (int)ctrl->npss; state >= 0; state--) {
da87591b 1567 u64 total_latency_us, exit_latency_us, transition_ms;
c5552fde
AL		 1568
1569 if (target)
1570 table->entries[state] = target;
1571
ff5350a8
AL		 1572 /*
1573 * Don't allow transitions to the deepest state
1574 * if it's quirked off.
1575 */
1576 if (state == ctrl->npss &&
1577 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
1578 continue;
1579
c5552fde
AL		 1580 /*
1581 * Is this state a useful non-operational state for
1582 * higher-power states to autonomously transition to?
1583 */
1584 if (!(ctrl->psd[state].flags &
1585 NVME_PS_FLAGS_NON_OP_STATE))
1586 continue;
1587
da87591b
KHF		 1588 exit_latency_us =
1589 (u64)le32_to_cpu(ctrl->psd[state].exit_lat);
1590 if (exit_latency_us > ctrl->ps_max_latency_us)
c5552fde
AL		 1591 continue;
1592
da87591b
KHF		 1593 total_latency_us =
1594 exit_latency_us +
1595 le32_to_cpu(ctrl->psd[state].entry_lat);
1596
c5552fde
AL		 1597 /*
1598 * This state is good. Use it as the APST idle
1599 * target for higher power states.
1600 */
1601 transition_ms = total_latency_us + 19;
1602 do_div(transition_ms, 20);
1603 if (transition_ms > (1 << 24) - 1)
1604 transition_ms = (1 << 24) - 1;
1605
1606 target = cpu_to_le64((state << 3) |
1607 (transition_ms << 8));
fb0dc399
AL		 1608
1609 if (max_ps == -1)
1610 max_ps = state;
1611
1612 if (total_latency_us > max_lat_us)
1613 max_lat_us = total_latency_us;
c5552fde
AL		 1614 }
1615
1616 apste = 1;
fb0dc399
AL		 1617
1618 if (max_ps == -1) {
1619 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n");
1620 } else {
1621 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n",
1622 max_ps, max_lat_us, (int)sizeof(*table), table);
1623 }
c5552fde
AL		 1624 }
1625
1626 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
1627 table, sizeof(*table), NULL);
1628 if (ret)
1629 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
1630
1631 kfree(table);
1632}
1633
1634static void nvme_set_latency_tolerance(struct device *dev, s32 val)
1635{
1636 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1637 u64 latency;
1638
1639 switch (val) {
1640 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
1641 case PM_QOS_LATENCY_ANY:
1642 latency = U64_MAX;
1643 break;
1644
1645 default:
1646 latency = val;
1647 }
1648
1649 if (ctrl->ps_max_latency_us != latency) {
1650 ctrl->ps_max_latency_us = latency;
1651 nvme_configure_apst(ctrl);
1652 }
1653}
1654
bd4da3ab
AL		 1655struct nvme_core_quirk_entry {
1656 /*
1657 * NVMe model and firmware strings are padded with spaces. For
1658 * simplicity, strings in the quirk table are padded with NULLs
1659 * instead.
1660 */
1661 u16 vid;
1662 const char *mn;
1663 const char *fr;
1664 unsigned long quirks;
1665};
1666
1667static const struct nvme_core_quirk_entry core_quirks[] = {
c5552fde 1668 {
be56945c
AL		 1669 /*
1670 * This Toshiba device seems to die using any APST states. See:
1671 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
1672 */
1673 .vid = 0x1179,
1674 .mn = "THNSF5256GPUK TOSHIBA",
c5552fde 1675 .quirks = NVME_QUIRK_NO_APST,
be56945c 1676 }
bd4da3ab
AL		 1677};
1678
1679/* match is null-terminated but idstr is space-padded. */
1680static bool string_matches(const char *idstr, const char *match, size_t len)
1681{
1682 size_t matchlen;
1683
1684 if (!match)
1685 return true;
1686
1687 matchlen = strlen(match);
1688 WARN_ON_ONCE(matchlen > len);
1689
1690 if (memcmp(idstr, match, matchlen))
1691 return false;
1692
1693 for (; matchlen < len; matchlen++)
1694 if (idstr[matchlen] != ' ')
1695 return false;
1696
1697 return true;
1698}
1699
1700static bool quirk_matches(const struct nvme_id_ctrl *id,
1701 const struct nvme_core_quirk_entry *q)
1702{
1703 return q->vid == le16_to_cpu(id->vid) &&
1704 string_matches(id->mn, q->mn, sizeof(id->mn)) &&
1705 string_matches(id->fr, q->fr, sizeof(id->fr));
1706}
1707
180de007
CH		 1708static void nvme_init_subnqn(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
1709{
1710 size_t nqnlen;
1711 int off;
1712
1713 nqnlen = strnlen(id->subnqn, NVMF_NQN_SIZE);
1714 if (nqnlen > 0 && nqnlen < NVMF_NQN_SIZE) {
1715 strcpy(ctrl->subnqn, id->subnqn);
1716 return;
1717 }
1718
1719 if (ctrl->vs >= NVME_VS(1, 2, 1))
1720 dev_warn(ctrl->device, "missing or invalid SUBNQN field.\n");
1721
1722 /* Generate a "fake" NQN per Figure 254 in NVMe 1.3 + ECN 001 */
1723 off = snprintf(ctrl->subnqn, NVMF_NQN_SIZE,
1724 "nqn.2014.08.org.nvmexpress:%4x%4x",
1725 le16_to_cpu(id->vid), le16_to_cpu(id->ssvid));
1726 memcpy(ctrl->subnqn + off, id->sn, sizeof(id->sn));
1727 off += sizeof(id->sn);
1728 memcpy(ctrl->subnqn + off, id->mn, sizeof(id->mn));
1729 off += sizeof(id->mn);
1730 memset(ctrl->subnqn + off, 0, sizeof(ctrl->subnqn) - off);
1731}
1732
7fd8930f
CH		 1733/*
1734 * Initialize the cached copies of the Identify data and various controller
1735 * register in our nvme_ctrl structure. This should be called as soon as
1736 * the admin queue is fully up and running.
1737 */
1738int nvme_init_identify(struct nvme_ctrl *ctrl)
1739{
1740 struct nvme_id_ctrl *id;
1741 u64 cap;
1742 int ret, page_shift;
a229dbf6 1743 u32 max_hw_sectors;
76a5af84 1744 bool prev_apst_enabled;
7fd8930f 1745
f3ca80fc
CH		 1746 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
1747 if (ret) {
1b3c47c1 1748 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
f3ca80fc
CH		 1749 return ret;
1750 }
1751
7fd8930f
CH		 1752 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &cap);
1753 if (ret) {
1b3c47c1 1754 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
7fd8930f
CH		 1755 return ret;
1756 }
1757 page_shift = NVME_CAP_MPSMIN(cap) + 12;
1758
8ef2074d 1759 if (ctrl->vs >= NVME_VS(1, 1, 0))
f3ca80fc
CH		 1760 ctrl->subsystem = NVME_CAP_NSSRC(cap);
1761
7fd8930f
CH		 1762 ret = nvme_identify_ctrl(ctrl, &id);
1763 if (ret) {
1b3c47c1 1764 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH		 1765 return -EIO;
1766 }
1767
180de007
CH		 1768 nvme_init_subnqn(ctrl, id);
1769
bd4da3ab
AL		 1770 if (!ctrl->identified) {
1771 /*
1772 * Check for quirks. Quirk can depend on firmware version,
1773 * so, in principle, the set of quirks present can change
1774 * across a reset. As a possible future enhancement, we
1775 * could re-scan for quirks every time we reinitialize
1776 * the device, but we'd have to make sure that the driver
1777 * behaves intelligently if the quirks change.
1778 */
1779
1780 int i;
1781
1782 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
1783 if (quirk_matches(id, &core_quirks[i]))
1784 ctrl->quirks |= core_quirks[i].quirks;
1785 }
1786 }
1787
c35e30b4 1788 if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) {
f0425db0 1789 dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n");
c35e30b4
AL		 1790 ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS;
1791 }
1792
8a9ae523 1793 ctrl->oacs = le16_to_cpu(id->oacs);
118472ab 1794 ctrl->vid = le16_to_cpu(id->vid);
7fd8930f 1795 ctrl->oncs = le16_to_cpup(&id->oncs);
6bf25d16 1796 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 1797 ctrl->vwc = id->vwc;
931e1c22 1798 ctrl->cntlid = le16_to_cpup(&id->cntlid);
7fd8930f
CH		 1799 memcpy(ctrl->serial, id->sn, sizeof(id->sn));
1800 memcpy(ctrl->model, id->mn, sizeof(id->mn));
1801 memcpy(ctrl->firmware_rev, id->fr, sizeof(id->fr));
1802 if (id->mdts)
a229dbf6 1803 max_hw_sectors = 1 << (id->mdts + page_shift - 9);
7fd8930f 1804 else
a229dbf6
CH		 1805 max_hw_sectors = UINT_MAX;
1806 ctrl->max_hw_sectors =
1807 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 1808
da35825d 1809 nvme_set_queue_limits(ctrl, ctrl->admin_q);
07bfcd09 1810 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 1811 ctrl->kas = le16_to_cpu(id->kas);
07bfcd09 1812
c5552fde 1813 ctrl->npss = id->npss;
76a5af84
KHF		 1814 ctrl->apsta = id->apsta;
1815 prev_apst_enabled = ctrl->apst_enabled;
c35e30b4
AL		 1816 if (ctrl->quirks & NVME_QUIRK_NO_APST) {
1817 if (force_apst && id->apsta) {
f0425db0 1818 dev_warn(ctrl->device, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n");
76a5af84 1819 ctrl->apst_enabled = true;
c35e30b4 1820 } else {
76a5af84 1821 ctrl->apst_enabled = false;
c35e30b4
AL		 1822 }
1823 } else {
76a5af84 1824 ctrl->apst_enabled = id->apsta;
c35e30b4 1825 }
c5552fde
AL		 1826 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
1827
d3d5b87d 1828 if (ctrl->ops->flags & NVME_F_FABRICS) {
07bfcd09
CH		 1829 ctrl->icdoff = le16_to_cpu(id->icdoff);
1830 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
1831 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
1832 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
1833
1834 /*
1835 * In fabrics we need to verify the cntlid matches the
1836 * admin connect
1837 */
1838 if (ctrl->cntlid != le16_to_cpu(id->cntlid))
1839 ret = -EINVAL;
038bd4cb
SG		 1840
1841 if (!ctrl->opts->discovery_nqn && !ctrl->kas) {
f0425db0 1842 dev_err(ctrl->device,
038bd4cb
SG		 1843 "keep-alive support is mandatory for fabrics\n");
1844 ret = -EINVAL;
1845 }
07bfcd09
CH		 1846 } else {
1847 ctrl->cntlid = le16_to_cpu(id->cntlid);
fe6d53c9
CH		 1848 ctrl->hmpre = le32_to_cpu(id->hmpre);
1849 ctrl->hmmin = le32_to_cpu(id->hmmin);
07bfcd09 1850 }
da35825d 1851
7fd8930f 1852 kfree(id);
bd4da3ab 1853
76a5af84 1854 if (ctrl->apst_enabled && !prev_apst_enabled)
c5552fde 1855 dev_pm_qos_expose_latency_tolerance(ctrl->device);
76a5af84 1856 else if (!ctrl->apst_enabled && prev_apst_enabled)
c5552fde
AL		 1857 dev_pm_qos_hide_latency_tolerance(ctrl->device);
1858
1859 nvme_configure_apst(ctrl);
f5d11840 1860 nvme_configure_directives(ctrl);
c5552fde 1861
bd4da3ab 1862 ctrl->identified = true;
c5552fde 1863
07bfcd09 1864 return ret;
7fd8930f 1865}
576d55d6 1866EXPORT_SYMBOL_GPL(nvme_init_identify);
7fd8930f 1867
f3ca80fc 1868static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 1869{
f3ca80fc
CH		 1870 struct nvme_ctrl *ctrl;
1871 int instance = iminor(inode);
1872 int ret = -ENODEV;
1673f1f0 1873
f3ca80fc
CH		 1874 spin_lock(&dev_list_lock);
1875 list_for_each_entry(ctrl, &nvme_ctrl_list, node) {
1876 if (ctrl->instance != instance)
1877 continue;
1878
1879 if (!ctrl->admin_q) {
1880 ret = -EWOULDBLOCK;
1881 break;
1882 }
1883 if (!kref_get_unless_zero(&ctrl->kref))
1884 break;
1885 file->private_data = ctrl;
1886 ret = 0;
1887 break;
1888 }
1889 spin_unlock(&dev_list_lock);
1890
1891 return ret;
1673f1f0
CH		 1892}
1893
f3ca80fc 1894static int nvme_dev_release(struct inode *inode, struct file *file)
1673f1f0 1895{
f3ca80fc
CH		 1896 nvme_put_ctrl(file->private_data);
1897 return 0;
1898}
1899
bfd89471
CH		 1900static int nvme_dev_user_cmd(struct nvme_ctrl *ctrl, void __user *argp)
1901{
1902 struct nvme_ns *ns;
1903 int ret;
1904
1905 mutex_lock(&ctrl->namespaces_mutex);
1906 if (list_empty(&ctrl->namespaces)) {
1907 ret = -ENOTTY;
1908 goto out_unlock;
1909 }
1910
1911 ns = list_first_entry(&ctrl->namespaces, struct nvme_ns, list);
1912 if (ns != list_last_entry(&ctrl->namespaces, struct nvme_ns, list)) {
1b3c47c1 1913 dev_warn(ctrl->device,
bfd89471
CH		 1914 "NVME_IOCTL_IO_CMD not supported when multiple namespaces present!\n");
1915 ret = -EINVAL;
1916 goto out_unlock;
1917 }
1918
1b3c47c1 1919 dev_warn(ctrl->device,
bfd89471
CH		 1920 "using deprecated NVME_IOCTL_IO_CMD ioctl on the char device!\n");
1921 kref_get(&ns->kref);
1922 mutex_unlock(&ctrl->namespaces_mutex);
1923
1924 ret = nvme_user_cmd(ctrl, ns, argp);
1925 nvme_put_ns(ns);
1926 return ret;
1927
1928out_unlock:
1929 mutex_unlock(&ctrl->namespaces_mutex);
1930 return ret;
1931}
1932
f3ca80fc
CH		 1933static long nvme_dev_ioctl(struct file *file, unsigned int cmd,
1934 unsigned long arg)
1935{
1936 struct nvme_ctrl *ctrl = file->private_data;
1937 void __user *argp = (void __user *)arg;
f3ca80fc
CH		 1938
1939 switch (cmd) {
1940 case NVME_IOCTL_ADMIN_CMD:
1941 return nvme_user_cmd(ctrl, NULL, argp);
1942 case NVME_IOCTL_IO_CMD:
bfd89471 1943 return nvme_dev_user_cmd(ctrl, argp);
f3ca80fc 1944 case NVME_IOCTL_RESET:
1b3c47c1 1945 dev_warn(ctrl->device, "resetting controller\n");
d86c4d8e 1946 return nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 1947 case NVME_IOCTL_SUBSYS_RESET:
1948 return nvme_reset_subsystem(ctrl);
9ec3bb2f
KB		 1949 case NVME_IOCTL_RESCAN:
1950 nvme_queue_scan(ctrl);
1951 return 0;
f3ca80fc
CH		 1952 default:
1953 return -ENOTTY;
1954 }
1955}
1956
1957static const struct file_operations nvme_dev_fops = {
1958 .owner = THIS_MODULE,
1959 .open = nvme_dev_open,
1960 .release = nvme_dev_release,
1961 .unlocked_ioctl = nvme_dev_ioctl,
1962 .compat_ioctl = nvme_dev_ioctl,
1963};
1964
1965static ssize_t nvme_sysfs_reset(struct device *dev,
1966 struct device_attribute *attr, const char *buf,
1967 size_t count)
1968{
1969 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1970 int ret;
1971
d86c4d8e 1972 ret = nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 1973 if (ret < 0)
1974 return ret;
1975 return count;
1673f1f0 1976}
f3ca80fc 1977static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
1673f1f0 1978
9ec3bb2f
KB		 1979static ssize_t nvme_sysfs_rescan(struct device *dev,
1980 struct device_attribute *attr, const char *buf,
1981 size_t count)
1982{
1983 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1984
1985 nvme_queue_scan(ctrl);
1986 return count;
1987}
1988static DEVICE_ATTR(rescan_controller, S_IWUSR, NULL, nvme_sysfs_rescan);
1989
118472ab
KB		 1990static ssize_t wwid_show(struct device *dev, struct device_attribute *attr,
1991 char *buf)
1992{
40267efd 1993 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
118472ab
KB		 1994 struct nvme_ctrl *ctrl = ns->ctrl;
1995 int serial_len = sizeof(ctrl->serial);
1996 int model_len = sizeof(ctrl->model);
1997
6484f5d1
JT		 1998 if (!uuid_is_null(&ns->uuid))
1999 return sprintf(buf, "uuid.%pU\n", &ns->uuid);
2000
90985b84
JT		 2001 if (memchr_inv(ns->nguid, 0, sizeof(ns->nguid)))
2002 return sprintf(buf, "eui.%16phN\n", ns->nguid);
118472ab
KB		 2003
2004 if (memchr_inv(ns->eui, 0, sizeof(ns->eui)))
2005 return sprintf(buf, "eui.%8phN\n", ns->eui);
2006
2007 while (ctrl->serial[serial_len - 1] == ' ')
2008 serial_len--;
2009 while (ctrl->model[model_len - 1] == ' ')
2010 model_len--;
2011
2012 return sprintf(buf, "nvme.%04x-%*phN-%*phN-%08x\n", ctrl->vid,
2013 serial_len, ctrl->serial, model_len, ctrl->model, ns->ns_id);
2014}
2015static DEVICE_ATTR(wwid, S_IRUGO, wwid_show, NULL);
2016
d934f984
JT		 2017static ssize_t nguid_show(struct device *dev, struct device_attribute *attr,
2018 char *buf)
2019{
2020 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2021 return sprintf(buf, "%pU\n", ns->nguid);
2022}
2023static DEVICE_ATTR(nguid, S_IRUGO, nguid_show, NULL);
2024
2b9b6e86
KB		 2025static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,
2026 char *buf)
2027{
40267efd 2028 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
d934f984
JT		 2029
2030 /* For backward compatibility expose the NGUID to userspace if
2031 * we have no UUID set
2032 */
2033 if (uuid_is_null(&ns->uuid)) {
2034 printk_ratelimited(KERN_WARNING
2035 "No UUID available providing old NGUID\n");
2036 return sprintf(buf, "%pU\n", ns->nguid);
2037 }
2038 return sprintf(buf, "%pU\n", &ns->uuid);
2b9b6e86
KB		 2039}
2040static DEVICE_ATTR(uuid, S_IRUGO, uuid_show, NULL);
2041
2042static ssize_t eui_show(struct device *dev, struct device_attribute *attr,
2043 char *buf)
2044{
40267efd 2045 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 2046 return sprintf(buf, "%8phd\n", ns->eui);
2047}
2048static DEVICE_ATTR(eui, S_IRUGO, eui_show, NULL);
2049
2050static ssize_t nsid_show(struct device *dev, struct device_attribute *attr,
2051 char *buf)
2052{
40267efd 2053 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 2054 return sprintf(buf, "%d\n", ns->ns_id);
2055}
2056static DEVICE_ATTR(nsid, S_IRUGO, nsid_show, NULL);
2057
2058static struct attribute *nvme_ns_attrs[] = {
118472ab 2059 &dev_attr_wwid.attr,
2b9b6e86 2060 &dev_attr_uuid.attr,
d934f984 2061 &dev_attr_nguid.attr,
2b9b6e86
KB		 2062 &dev_attr_eui.attr,
2063 &dev_attr_nsid.attr,
2064 NULL,
2065};
2066
1a353d85 2067static umode_t nvme_ns_attrs_are_visible(struct kobject *kobj,
2b9b6e86
KB		 2068 struct attribute *a, int n)
2069{
2070 struct device *dev = container_of(kobj, struct device, kobj);
40267efd 2071 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 2072
2073 if (a == &dev_attr_uuid.attr) {
d934f984
JT		 2074 if (uuid_is_null(&ns->uuid) ||
2075 !memchr_inv(ns->nguid, 0, sizeof(ns->nguid)))
2076 return 0;
2077 }
2078 if (a == &dev_attr_nguid.attr) {
90985b84 2079 if (!memchr_inv(ns->nguid, 0, sizeof(ns->nguid)))
2b9b6e86
KB		 2080 return 0;
2081 }
2082 if (a == &dev_attr_eui.attr) {
2083 if (!memchr_inv(ns->eui, 0, sizeof(ns->eui)))
2084 return 0;
2085 }
2086 return a->mode;
2087}
2088
2089static const struct attribute_group nvme_ns_attr_group = {
2090 .attrs = nvme_ns_attrs,
1a353d85 2091 .is_visible = nvme_ns_attrs_are_visible,
2b9b6e86
KB		 2092};
2093
931e1c22 2094#define nvme_show_str_function(field) \
779ff756
KB		 2095static ssize_t field##_show(struct device *dev, \
2096 struct device_attribute *attr, char *buf) \
2097{ \
2098 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
2099 return sprintf(buf, "%.*s\n", (int)sizeof(ctrl->field), ctrl->field); \
2100} \
2101static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
2102
931e1c22
ML		 2103#define nvme_show_int_function(field) \
2104static ssize_t field##_show(struct device *dev, \
2105 struct device_attribute *attr, char *buf) \
2106{ \
2107 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
2108 return sprintf(buf, "%d\n", ctrl->field); \
2109} \
2110static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
2111
2112nvme_show_str_function(model);
2113nvme_show_str_function(serial);
2114nvme_show_str_function(firmware_rev);
2115nvme_show_int_function(cntlid);
779ff756 2116
1a353d85
ML		 2117static ssize_t nvme_sysfs_delete(struct device *dev,
2118 struct device_attribute *attr, const char *buf,
2119 size_t count)
2120{
2121 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2122
2123 if (device_remove_file_self(dev, attr))
2124 ctrl->ops->delete_ctrl(ctrl);
2125 return count;
2126}
2127static DEVICE_ATTR(delete_controller, S_IWUSR, NULL, nvme_sysfs_delete);
2128
2129static ssize_t nvme_sysfs_show_transport(struct device *dev,
2130 struct device_attribute *attr,
2131 char *buf)
2132{
2133 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2134
2135 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->ops->name);
2136}
2137static DEVICE_ATTR(transport, S_IRUGO, nvme_sysfs_show_transport, NULL);
2138
8432bdb2
SG		 2139static ssize_t nvme_sysfs_show_state(struct device *dev,
2140 struct device_attribute *attr,
2141 char *buf)
2142{
2143 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2144 static const char *const state_name[] = {
2145 [NVME_CTRL_NEW] = "new",
2146 [NVME_CTRL_LIVE] = "live",
2147 [NVME_CTRL_RESETTING] = "resetting",
2148 [NVME_CTRL_RECONNECTING]= "reconnecting",
2149 [NVME_CTRL_DELETING] = "deleting",
2150 [NVME_CTRL_DEAD] = "dead",
2151 };
2152
2153 if ((unsigned)ctrl->state < ARRAY_SIZE(state_name) &&
2154 state_name[ctrl->state])
2155 return sprintf(buf, "%s\n", state_name[ctrl->state]);
2156
2157 return sprintf(buf, "unknown state\n");
2158}
2159
2160static DEVICE_ATTR(state, S_IRUGO, nvme_sysfs_show_state, NULL);
2161
1a353d85
ML		 2162static ssize_t nvme_sysfs_show_subsysnqn(struct device *dev,
2163 struct device_attribute *attr,
2164 char *buf)
2165{
2166 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2167
180de007 2168 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->subnqn);
1a353d85
ML		 2169}
2170static DEVICE_ATTR(subsysnqn, S_IRUGO, nvme_sysfs_show_subsysnqn, NULL);
2171
2172static ssize_t nvme_sysfs_show_address(struct device *dev,
2173 struct device_attribute *attr,
2174 char *buf)
2175{
2176 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2177
2178 return ctrl->ops->get_address(ctrl, buf, PAGE_SIZE);
2179}
2180static DEVICE_ATTR(address, S_IRUGO, nvme_sysfs_show_address, NULL);
2181
779ff756
KB		 2182static struct attribute *nvme_dev_attrs[] = {
2183 &dev_attr_reset_controller.attr,
9ec3bb2f 2184 &dev_attr_rescan_controller.attr,
779ff756
KB		 2185 &dev_attr_model.attr,
2186 &dev_attr_serial.attr,
2187 &dev_attr_firmware_rev.attr,
931e1c22 2188 &dev_attr_cntlid.attr,
1a353d85
ML		 2189 &dev_attr_delete_controller.attr,
2190 &dev_attr_transport.attr,
2191 &dev_attr_subsysnqn.attr,
2192 &dev_attr_address.attr,
8432bdb2 2193 &dev_attr_state.attr,
779ff756
KB		 2194 NULL
2195};
2196
1a353d85
ML		 2197static umode_t nvme_dev_attrs_are_visible(struct kobject *kobj,
2198 struct attribute *a, int n)
2199{
2200 struct device *dev = container_of(kobj, struct device, kobj);
2201 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2202
49d3d50b
CH		 2203 if (a == &dev_attr_delete_controller.attr && !ctrl->ops->delete_ctrl)
2204 return 0;
2205 if (a == &dev_attr_address.attr && !ctrl->ops->get_address)
2206 return 0;
1a353d85
ML		 2207
2208 return a->mode;
2209}
2210
779ff756 2211static struct attribute_group nvme_dev_attrs_group = {
1a353d85
ML		 2212 .attrs = nvme_dev_attrs,
2213 .is_visible = nvme_dev_attrs_are_visible,
779ff756
KB		 2214};
2215
2216static const struct attribute_group *nvme_dev_attr_groups[] = {
2217 &nvme_dev_attrs_group,
2218 NULL,
2219};
2220
5bae7f73
CH		 2221static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2222{
2223 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2224 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2225
2226 return nsa->ns_id - nsb->ns_id;
2227}
2228
32f0c4af 2229static struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 2230{
32f0c4af 2231 struct nvme_ns *ns, *ret = NULL;
69d3b8ac 2232
32f0c4af 2233 mutex_lock(&ctrl->namespaces_mutex);
5bae7f73 2234 list_for_each_entry(ns, &ctrl->namespaces, list) {
32f0c4af
KB		 2235 if (ns->ns_id == nsid) {
2236 kref_get(&ns->kref);
2237 ret = ns;
2238 break;
2239 }
5bae7f73
CH		 2240 if (ns->ns_id > nsid)
2241 break;
2242 }
32f0c4af
KB		 2243 mutex_unlock(&ctrl->namespaces_mutex);
2244 return ret;
5bae7f73
CH		 2245}
2246
f5d11840
JA		 2247static int nvme_setup_streams_ns(struct nvme_ctrl *ctrl, struct nvme_ns *ns)
2248{
2249 struct streams_directive_params s;
2250 int ret;
2251
2252 if (!ctrl->nr_streams)
2253 return 0;
2254
2255 ret = nvme_get_stream_params(ctrl, &s, ns->ns_id);
2256 if (ret)
2257 return ret;
2258
2259 ns->sws = le32_to_cpu(s.sws);
2260 ns->sgs = le16_to_cpu(s.sgs);
2261
2262 if (ns->sws) {
2263 unsigned int bs = 1 << ns->lba_shift;
2264
2265 blk_queue_io_min(ns->queue, bs * ns->sws);
2266 if (ns->sgs)
2267 blk_queue_io_opt(ns->queue, bs * ns->sws * ns->sgs);
2268 }
2269
2270 return 0;
2271}
2272
5bae7f73
CH		 2273static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
2274{
2275 struct nvme_ns *ns;
2276 struct gendisk *disk;
ac81bfa9
MB		 2277 struct nvme_id_ns *id;
2278 char disk_name[DISK_NAME_LEN];
5bae7f73
CH		 2279 int node = dev_to_node(ctrl->dev);
2280
2281 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
2282 if (!ns)
2283 return;
2284
075790eb
KB		 2285 ns->instance = ida_simple_get(&ctrl->ns_ida, 1, 0, GFP_KERNEL);
2286 if (ns->instance < 0)
2287 goto out_free_ns;
2288
5bae7f73
CH		 2289 ns->queue = blk_mq_init_queue(ctrl->tagset);
2290 if (IS_ERR(ns->queue))
075790eb 2291 goto out_release_instance;
5bae7f73
CH		 2292 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
2293 ns->queue->queuedata = ns;
2294 ns->ctrl = ctrl;
2295
5bae7f73
CH		 2296 kref_init(&ns->kref);
2297 ns->ns_id = nsid;
5bae7f73 2298 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
5bae7f73
CH		 2299
2300 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
da35825d 2301 nvme_set_queue_limits(ctrl, ns->queue);
f5d11840 2302 nvme_setup_streams_ns(ctrl, ns);
5bae7f73 2303
ac81bfa9 2304 sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->instance);
5bae7f73 2305
ac81bfa9
MB		 2306 if (nvme_revalidate_ns(ns, &id))
2307 goto out_free_queue;
2308
3dc87dd0
MB		 2309 if (nvme_nvm_ns_supported(ns, id) &&
2310 nvme_nvm_register(ns, disk_name, node)) {
f0425db0 2311 dev_warn(ctrl->device, "%s: LightNVM init failure\n", __func__);
3dc87dd0
MB		 2312 goto out_free_id;
2313 }
ac81bfa9 2314
3dc87dd0
MB		 2315 disk = alloc_disk_node(0, node);
2316 if (!disk)
2317 goto out_free_id;
ac81bfa9 2318
3dc87dd0
MB		 2319 disk->fops = &nvme_fops;
2320 disk->private_data = ns;
2321 disk->queue = ns->queue;
2322 disk->flags = GENHD_FL_EXT_DEVT;
2323 memcpy(disk->disk_name, disk_name, DISK_NAME_LEN);
2324 ns->disk = disk;
2325
2326 __nvme_revalidate_disk(disk, id);
5bae7f73 2327
32f0c4af
KB		 2328 mutex_lock(&ctrl->namespaces_mutex);
2329 list_add_tail(&ns->list, &ctrl->namespaces);
2330 mutex_unlock(&ctrl->namespaces_mutex);
2331
5bae7f73 2332 kref_get(&ctrl->kref);
ac81bfa9
MB		 2333
2334 kfree(id);
2335
0d52c756 2336 device_add_disk(ctrl->device, ns->disk);
2b9b6e86
KB		 2337 if (sysfs_create_group(&disk_to_dev(ns->disk)->kobj,
2338 &nvme_ns_attr_group))
2339 pr_warn("%s: failed to create sysfs group for identification\n",
2340 ns->disk->disk_name);
3dc87dd0
MB		 2341 if (ns->ndev && nvme_nvm_register_sysfs(ns))
2342 pr_warn("%s: failed to register lightnvm sysfs group for identification\n",
2343 ns->disk->disk_name);
5bae7f73 2344 return;
ac81bfa9
MB		 2345 out_free_id:
2346 kfree(id);
5bae7f73
CH		 2347 out_free_queue:
2348 blk_cleanup_queue(ns->queue);
075790eb
KB		 2349 out_release_instance:
2350 ida_simple_remove(&ctrl->ns_ida, ns->instance);
5bae7f73
CH		 2351 out_free_ns:
2352 kfree(ns);
2353}
2354
2355static void nvme_ns_remove(struct nvme_ns *ns)
2356{
646017a6
KB		 2357 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
2358 return;
69d3b8ac 2359
b0b4e09c 2360 if (ns->disk && ns->disk->flags & GENHD_FL_UP) {
5bae7f73
CH		 2361 if (blk_get_integrity(ns->disk))
2362 blk_integrity_unregister(ns->disk);
2b9b6e86
KB		 2363 sysfs_remove_group(&disk_to_dev(ns->disk)->kobj,
2364 &nvme_ns_attr_group);
3dc87dd0
MB		 2365 if (ns->ndev)
2366 nvme_nvm_unregister_sysfs(ns);
5bae7f73 2367 del_gendisk(ns->disk);
5bae7f73
CH		 2368 blk_cleanup_queue(ns->queue);
2369 }
32f0c4af
KB		 2370
2371 mutex_lock(&ns->ctrl->namespaces_mutex);
5bae7f73 2372 list_del_init(&ns->list);
32f0c4af
KB		 2373 mutex_unlock(&ns->ctrl->namespaces_mutex);
2374
5bae7f73
CH		 2375 nvme_put_ns(ns);
2376}
2377
540c801c
KB		 2378static void nvme_validate_ns(struct nvme_ctrl *ctrl, unsigned nsid)
2379{
2380 struct nvme_ns *ns;
2381
32f0c4af 2382 ns = nvme_find_get_ns(ctrl, nsid);
540c801c 2383 if (ns) {
b0b4e09c 2384 if (ns->disk && revalidate_disk(ns->disk))
540c801c 2385 nvme_ns_remove(ns);
32f0c4af 2386 nvme_put_ns(ns);
540c801c
KB		 2387 } else
2388 nvme_alloc_ns(ctrl, nsid);
2389}
2390
47b0e50a
SB		 2391static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
2392 unsigned nsid)
2393{
2394 struct nvme_ns *ns, *next;
2395
2396 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
2397 if (ns->ns_id > nsid)
2398 nvme_ns_remove(ns);
2399 }
2400}
2401
540c801c
KB		 2402static int nvme_scan_ns_list(struct nvme_ctrl *ctrl, unsigned nn)
2403{
2404 struct nvme_ns *ns;
2405 __le32 *ns_list;
2406 unsigned i, j, nsid, prev = 0, num_lists = DIV_ROUND_UP(nn, 1024);
2407 int ret = 0;
2408
2409 ns_list = kzalloc(0x1000, GFP_KERNEL);
2410 if (!ns_list)
2411 return -ENOMEM;
2412
2413 for (i = 0; i < num_lists; i++) {
2414 ret = nvme_identify_ns_list(ctrl, prev, ns_list);
2415 if (ret)
47b0e50a 2416 goto free;
540c801c
KB		 2417
2418 for (j = 0; j < min(nn, 1024U); j++) {
2419 nsid = le32_to_cpu(ns_list[j]);
2420 if (!nsid)
2421 goto out;
2422
2423 nvme_validate_ns(ctrl, nsid);
2424
2425 while (++prev < nsid) {
32f0c4af
KB		 2426 ns = nvme_find_get_ns(ctrl, prev);
2427 if (ns) {
540c801c 2428 nvme_ns_remove(ns);
32f0c4af
KB		 2429 nvme_put_ns(ns);
2430 }
540c801c
KB		 2431 }
2432 }
2433 nn -= j;
2434 }
2435 out:
47b0e50a
SB		 2436 nvme_remove_invalid_namespaces(ctrl, prev);
2437 free:
540c801c
KB		 2438 kfree(ns_list);
2439 return ret;
2440}
2441
5955be21 2442static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl, unsigned nn)
5bae7f73 2443{
5bae7f73
CH		 2444 unsigned i;
2445
540c801c
KB		 2446 for (i = 1; i <= nn; i++)
2447 nvme_validate_ns(ctrl, i);
2448
47b0e50a 2449 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH		 2450}
2451
5955be21 2452static void nvme_scan_work(struct work_struct *work)
5bae7f73 2453{
5955be21
CH		 2454 struct nvme_ctrl *ctrl =
2455 container_of(work, struct nvme_ctrl, scan_work);
5bae7f73 2456 struct nvme_id_ctrl *id;
540c801c 2457 unsigned nn;
5bae7f73 2458
5955be21
CH		 2459 if (ctrl->state != NVME_CTRL_LIVE)
2460 return;
2461
5bae7f73
CH		 2462 if (nvme_identify_ctrl(ctrl, &id))
2463 return;
540c801c
KB		 2464
2465 nn = le32_to_cpu(id->nn);
8ef2074d 2466 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
540c801c
KB		 2467 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
2468 if (!nvme_scan_ns_list(ctrl, nn))
2469 goto done;
2470 }
5955be21 2471 nvme_scan_ns_sequential(ctrl, nn);
540c801c 2472 done:
32f0c4af 2473 mutex_lock(&ctrl->namespaces_mutex);
540c801c 2474 list_sort(NULL, &ctrl->namespaces, ns_cmp);
69d3b8ac 2475 mutex_unlock(&ctrl->namespaces_mutex);
5bae7f73
CH		 2476 kfree(id);
2477}
5955be21
CH		 2478
2479void nvme_queue_scan(struct nvme_ctrl *ctrl)
2480{
2481 /*
2482 * Do not queue new scan work when a controller is reset during
2483 * removal.
2484 */
2485 if (ctrl->state == NVME_CTRL_LIVE)
c669ccdc 2486 queue_work(nvme_wq, &ctrl->scan_work);
5955be21
CH		 2487}
2488EXPORT_SYMBOL_GPL(nvme_queue_scan);
5bae7f73 2489
32f0c4af
KB		 2490/*
2491 * This function iterates the namespace list unlocked to allow recovery from
2492 * controller failure. It is up to the caller to ensure the namespace list is
2493 * not modified by scan work while this function is executing.
2494 */
5bae7f73
CH		 2495void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
2496{
2497 struct nvme_ns *ns, *next;
2498
0ff9d4e1
KB		 2499 /*
2500 * The dead states indicates the controller was not gracefully
2501 * disconnected. In that case, we won't be able to flush any data while
2502 * removing the namespaces' disks; fail all the queues now to avoid
2503 * potentially having to clean up the failed sync later.
2504 */
2505 if (ctrl->state == NVME_CTRL_DEAD)
2506 nvme_kill_queues(ctrl);
2507
5bae7f73
CH		 2508 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list)
2509 nvme_ns_remove(ns);
2510}
576d55d6 2511EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 2512
f866fc42
CH		 2513static void nvme_async_event_work(struct work_struct *work)
2514{
2515 struct nvme_ctrl *ctrl =
2516 container_of(work, struct nvme_ctrl, async_event_work);
2517
2518 spin_lock_irq(&ctrl->lock);
2519 while (ctrl->event_limit > 0) {
2520 int aer_idx = --ctrl->event_limit;
2521
2522 spin_unlock_irq(&ctrl->lock);
2523 ctrl->ops->submit_async_event(ctrl, aer_idx);
2524 spin_lock_irq(&ctrl->lock);
2525 }
2526 spin_unlock_irq(&ctrl->lock);
2527}
2528
7bf58533
CH		 2529void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
2530 union nvme_result *res)
f866fc42 2531{
7bf58533
CH		 2532 u32 result = le32_to_cpu(res->u32);
2533 bool done = true;
f866fc42 2534
7bf58533
CH		 2535 switch (le16_to_cpu(status) >> 1) {
2536 case NVME_SC_SUCCESS:
2537 done = false;
2538 /*FALLTHRU*/
2539 case NVME_SC_ABORT_REQ:
f866fc42 2540 ++ctrl->event_limit;
c669ccdc 2541 queue_work(nvme_wq, &ctrl->async_event_work);
7bf58533
CH		 2542 break;
2543 default:
2544 break;
f866fc42
CH		 2545 }
2546
7bf58533 2547 if (done)
f866fc42
CH		 2548 return;
2549
2550 switch (result & 0xff07) {
2551 case NVME_AER_NOTICE_NS_CHANGED:
2552 dev_info(ctrl->device, "rescanning\n");
2553 nvme_queue_scan(ctrl);
2554 break;
2555 default:
2556 dev_warn(ctrl->device, "async event result %08x\n", result);
2557 }
2558}
2559EXPORT_SYMBOL_GPL(nvme_complete_async_event);
2560
2561void nvme_queue_async_events(struct nvme_ctrl *ctrl)
2562{
2563 ctrl->event_limit = NVME_NR_AERS;
c669ccdc 2564 queue_work(nvme_wq, &ctrl->async_event_work);
f866fc42
CH		 2565}
2566EXPORT_SYMBOL_GPL(nvme_queue_async_events);
2567
f3ca80fc
CH		 2568static DEFINE_IDA(nvme_instance_ida);
2569
2570static int nvme_set_instance(struct nvme_ctrl *ctrl)
2571{
2572 int instance, error;
2573
2574 do {
2575 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2576 return -ENODEV;
2577
2578 spin_lock(&dev_list_lock);
2579 error = ida_get_new(&nvme_instance_ida, &instance);
2580 spin_unlock(&dev_list_lock);
2581 } while (error == -EAGAIN);
2582
2583 if (error)
2584 return -ENODEV;
2585
2586 ctrl->instance = instance;
2587 return 0;
2588}
2589
2590static void nvme_release_instance(struct nvme_ctrl *ctrl)
2591{
2592 spin_lock(&dev_list_lock);
2593 ida_remove(&nvme_instance_ida, ctrl->instance);
2594 spin_unlock(&dev_list_lock);
2595}
2596
d09f2b45 2597void nvme_stop_ctrl(struct nvme_ctrl *ctrl)
576d55d6 2598{
d09f2b45 2599 nvme_stop_keep_alive(ctrl);
f866fc42 2600 flush_work(&ctrl->async_event_work);
5955be21 2601 flush_work(&ctrl->scan_work);
d09f2b45
SG		 2602}
2603EXPORT_SYMBOL_GPL(nvme_stop_ctrl);
2604
2605void nvme_start_ctrl(struct nvme_ctrl *ctrl)
2606{
2607 if (ctrl->kato)
2608 nvme_start_keep_alive(ctrl);
2609
2610 if (ctrl->queue_count > 1) {
2611 nvme_queue_scan(ctrl);
2612 nvme_queue_async_events(ctrl);
2613 nvme_start_queues(ctrl);
2614 }
2615}
2616EXPORT_SYMBOL_GPL(nvme_start_ctrl);
5955be21 2617
d09f2b45
SG		 2618void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
2619{
53029b04 2620 device_destroy(nvme_class, MKDEV(nvme_char_major, ctrl->instance));
f3ca80fc
CH		 2621
2622 spin_lock(&dev_list_lock);
2623 list_del(&ctrl->node);
2624 spin_unlock(&dev_list_lock);
53029b04 2625}
576d55d6 2626EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04
KB		 2627
2628static void nvme_free_ctrl(struct kref *kref)
2629{
2630 struct nvme_ctrl *ctrl = container_of(kref, struct nvme_ctrl, kref);
f3ca80fc
CH		 2631
2632 put_device(ctrl->device);
2633 nvme_release_instance(ctrl);
075790eb 2634 ida_destroy(&ctrl->ns_ida);
f3ca80fc
CH		 2635
2636 ctrl->ops->free_ctrl(ctrl);
2637}
2638
2639void nvme_put_ctrl(struct nvme_ctrl *ctrl)
2640{
2641 kref_put(&ctrl->kref, nvme_free_ctrl);
2642}
576d55d6 2643EXPORT_SYMBOL_GPL(nvme_put_ctrl);
f3ca80fc
CH		 2644
2645/*
2646 * Initialize a NVMe controller structures. This needs to be called during
2647 * earliest initialization so that we have the initialized structured around
2648 * during probing.
2649 */
2650int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
2651 const struct nvme_ctrl_ops *ops, unsigned long quirks)
2652{
2653 int ret;
2654
bb8d261e
CH		 2655 ctrl->state = NVME_CTRL_NEW;
2656 spin_lock_init(&ctrl->lock);
f3ca80fc 2657 INIT_LIST_HEAD(&ctrl->namespaces);
69d3b8ac 2658 mutex_init(&ctrl->namespaces_mutex);
f3ca80fc
CH		 2659 kref_init(&ctrl->kref);
2660 ctrl->dev = dev;
2661 ctrl->ops = ops;
2662 ctrl->quirks = quirks;
5955be21 2663 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 2664 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
f3ca80fc
CH		 2665
2666 ret = nvme_set_instance(ctrl);
2667 if (ret)
2668 goto out;
2669
779ff756 2670 ctrl->device = device_create_with_groups(nvme_class, ctrl->dev,
f3ca80fc 2671 MKDEV(nvme_char_major, ctrl->instance),
f4f0f63e 2672 ctrl, nvme_dev_attr_groups,
779ff756 2673 "nvme%d", ctrl->instance);
f3ca80fc
CH		 2674 if (IS_ERR(ctrl->device)) {
2675 ret = PTR_ERR(ctrl->device);
2676 goto out_release_instance;
2677 }
2678 get_device(ctrl->device);
075790eb 2679 ida_init(&ctrl->ns_ida);
f3ca80fc 2680
f3ca80fc
CH		 2681 spin_lock(&dev_list_lock);
2682 list_add_tail(&ctrl->node, &nvme_ctrl_list);
2683 spin_unlock(&dev_list_lock);
2684
c5552fde
AL		 2685 /*
2686 * Initialize latency tolerance controls. The sysfs files won't
2687 * be visible to userspace unless the device actually supports APST.
2688 */
2689 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
2690 dev_pm_qos_update_user_latency_tolerance(ctrl->device,
2691 min(default_ps_max_latency_us, (unsigned long)S32_MAX));
2692
f3ca80fc 2693 return 0;
f3ca80fc
CH		 2694out_release_instance:
2695 nvme_release_instance(ctrl);
2696out:
2697 return ret;
2698}
576d55d6 2699EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 2700
69d9a99c
KB		 2701/**
2702 * nvme_kill_queues(): Ends all namespace queues
2703 * @ctrl: the dead controller that needs to end
2704 *
2705 * Call this function when the driver determines it is unable to get the
2706 * controller in a state capable of servicing IO.
2707 */
2708void nvme_kill_queues(struct nvme_ctrl *ctrl)
2709{
2710 struct nvme_ns *ns;
2711
32f0c4af 2712 mutex_lock(&ctrl->namespaces_mutex);
82654b6b 2713
443bd90f 2714 /* Forcibly unquiesce queues to avoid blocking dispatch */
7dd1ab16
SB		 2715 if (ctrl->admin_q)
2716 blk_mq_unquiesce_queue(ctrl->admin_q);
443bd90f 2717
32f0c4af 2718 list_for_each_entry(ns, &ctrl->namespaces, list) {
69d9a99c
KB		 2719 /*
2720 * Revalidating a dead namespace sets capacity to 0. This will
2721 * end buffered writers dirtying pages that can't be synced.
2722 */
f33447b9
KB		 2723 if (!ns->disk || test_and_set_bit(NVME_NS_DEAD, &ns->flags))
2724 continue;
2725 revalidate_disk(ns->disk);
69d9a99c 2726 blk_set_queue_dying(ns->queue);
806f026f 2727
443bd90f
ML		 2728 /* Forcibly unquiesce queues to avoid blocking dispatch */
2729 blk_mq_unquiesce_queue(ns->queue);
69d9a99c 2730 }
32f0c4af 2731 mutex_unlock(&ctrl->namespaces_mutex);
69d9a99c 2732}
237045fc 2733EXPORT_SYMBOL_GPL(nvme_kill_queues);
69d9a99c 2734
302ad8cc
KB		 2735void nvme_unfreeze(struct nvme_ctrl *ctrl)
2736{
2737 struct nvme_ns *ns;
2738
2739 mutex_lock(&ctrl->namespaces_mutex);
2740 list_for_each_entry(ns, &ctrl->namespaces, list)
2741 blk_mq_unfreeze_queue(ns->queue);
2742 mutex_unlock(&ctrl->namespaces_mutex);
2743}
2744EXPORT_SYMBOL_GPL(nvme_unfreeze);
2745
2746void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout)
2747{
2748 struct nvme_ns *ns;
2749
2750 mutex_lock(&ctrl->namespaces_mutex);
2751 list_for_each_entry(ns, &ctrl->namespaces, list) {
2752 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout);
2753 if (timeout <= 0)
2754 break;
2755 }
2756 mutex_unlock(&ctrl->namespaces_mutex);
2757}
2758EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout);
2759
2760void nvme_wait_freeze(struct nvme_ctrl *ctrl)
2761{
2762 struct nvme_ns *ns;
2763
2764 mutex_lock(&ctrl->namespaces_mutex);
2765 list_for_each_entry(ns, &ctrl->namespaces, list)
2766 blk_mq_freeze_queue_wait(ns->queue);
2767 mutex_unlock(&ctrl->namespaces_mutex);
2768}
2769EXPORT_SYMBOL_GPL(nvme_wait_freeze);
2770
2771void nvme_start_freeze(struct nvme_ctrl *ctrl)
2772{
2773 struct nvme_ns *ns;
2774
2775 mutex_lock(&ctrl->namespaces_mutex);
2776 list_for_each_entry(ns, &ctrl->namespaces, list)
1671d522 2777 blk_freeze_queue_start(ns->queue);
302ad8cc
KB		 2778 mutex_unlock(&ctrl->namespaces_mutex);
2779}
2780EXPORT_SYMBOL_GPL(nvme_start_freeze);
2781
25646264 2782void nvme_stop_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 2783{
2784 struct nvme_ns *ns;
2785
32f0c4af 2786 mutex_lock(&ctrl->namespaces_mutex);
a6eaa884 2787 list_for_each_entry(ns, &ctrl->namespaces, list)
3174dd33 2788 blk_mq_quiesce_queue(ns->queue);
32f0c4af 2789 mutex_unlock(&ctrl->namespaces_mutex);
363c9aac 2790}
576d55d6 2791EXPORT_SYMBOL_GPL(nvme_stop_queues);
363c9aac 2792
25646264 2793void nvme_start_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 2794{
2795 struct nvme_ns *ns;
2796
32f0c4af 2797 mutex_lock(&ctrl->namespaces_mutex);
8d7b8faf 2798 list_for_each_entry(ns, &ctrl->namespaces, list)
f660174e 2799 blk_mq_unquiesce_queue(ns->queue);
32f0c4af 2800 mutex_unlock(&ctrl->namespaces_mutex);
363c9aac 2801}
576d55d6 2802EXPORT_SYMBOL_GPL(nvme_start_queues);
363c9aac 2803
5bae7f73
CH		 2804int __init nvme_core_init(void)
2805{
2806 int result;
2807
9a6327d2
SG		 2808 nvme_wq = alloc_workqueue("nvme-wq",
2809 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
2810 if (!nvme_wq)
2811 return -ENOMEM;
2812
f3ca80fc
CH		 2813 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
2814 &nvme_dev_fops);
2815 if (result < 0)
9a6327d2 2816 goto destroy_wq;
f3ca80fc
CH		 2817 else if (result > 0)
2818 nvme_char_major = result;
2819
2820 nvme_class = class_create(THIS_MODULE, "nvme");
2821 if (IS_ERR(nvme_class)) {
2822 result = PTR_ERR(nvme_class);
2823 goto unregister_chrdev;
2824 }
2825
5bae7f73 2826 return 0;
f3ca80fc 2827
9a6327d2 2828unregister_chrdev:
f3ca80fc 2829 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
9a6327d2
SG		 2830destroy_wq:
2831 destroy_workqueue(nvme_wq);
f3ca80fc 2832 return result;
5bae7f73
CH		 2833}
2834
2835void nvme_core_exit(void)
2836{
f3ca80fc
CH		 2837 class_destroy(nvme_class);
2838 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
9a6327d2 2839 destroy_workqueue(nvme_wq);
5bae7f73 2840}
576d55d6
ML		 2841
2842MODULE_LICENSE("GPL");
2843MODULE_VERSION("1.0");
2844module_init(nvme_core_init);
2845module_exit(nvme_core_exit);
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