]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/nvme/host/core.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
nvme: Make nvme user functions static
[mirror_ubuntu-bionic-kernel.git] / drivers / nvme / host / core.c
CommitLineData
21d34711
CH		 1/*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/blkdev.h>
16#include <linux/blk-mq.h>
5fd4ce1b 17#include <linux/delay.h>
21d34711 18#include <linux/errno.h>
1673f1f0 19#include <linux/hdreg.h>
21d34711 20#include <linux/kernel.h>
5bae7f73
CH		 21#include <linux/module.h>
22#include <linux/list_sort.h>
21d34711
CH		 23#include <linux/slab.h>
24#include <linux/types.h>
1673f1f0
CH		 25#include <linux/pr.h>
26#include <linux/ptrace.h>
27#include <linux/nvme_ioctl.h>
28#include <linux/t10-pi.h>
c5552fde 29#include <linux/pm_qos.h>
1673f1f0 30#include <asm/unaligned.h>
21d34711
CH		 31
32#include "nvme.h"
038bd4cb 33#include "fabrics.h"
21d34711 34
f3ca80fc
CH		 35#define NVME_MINORS (1U << MINORBITS)
36
ba0ba7d3
ML		 37unsigned char admin_timeout = 60;
38module_param(admin_timeout, byte, 0644);
39MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 40EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3
ML		 41
42unsigned char nvme_io_timeout = 30;
43module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
44MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 45EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3 46
b3b1b0b0 47static unsigned char shutdown_timeout = 5;
ba0ba7d3
ML		 48module_param(shutdown_timeout, byte, 0644);
49MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
50
44e44b29
CH		 51static u8 nvme_max_retries = 5;
52module_param_named(max_retries, nvme_max_retries, byte, 0644);
f80ec966 53MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
5bae7f73 54
f3ca80fc
CH		 55static int nvme_char_major;
56module_param(nvme_char_major, int, 0);
57
9947d6a0 58static unsigned long default_ps_max_latency_us = 100000;
c5552fde
AL		 59module_param(default_ps_max_latency_us, ulong, 0644);
60MODULE_PARM_DESC(default_ps_max_latency_us,
61 "max power saving latency for new devices; use PM QOS to change per device");
62
c35e30b4
AL		 63static bool force_apst;
64module_param(force_apst, bool, 0644);
65MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off");
66
f5d11840
JA		 67static bool streams;
68module_param(streams, bool, 0644);
69MODULE_PARM_DESC(streams, "turn on support for Streams write directives");
70
9a6327d2
SG		 71struct workqueue_struct *nvme_wq;
72EXPORT_SYMBOL_GPL(nvme_wq);
73
f3ca80fc 74static LIST_HEAD(nvme_ctrl_list);
9f2482b9 75static DEFINE_SPINLOCK(dev_list_lock);
1673f1f0 76
f3ca80fc
CH		 77static struct class *nvme_class;
78
b6dccf7f
AD		 79static __le32 nvme_get_log_dw10(u8 lid, size_t size)
80{
81 return cpu_to_le32((((size / 4) - 1) << 16) | lid);
82}
83
d86c4d8e
CH		 84int nvme_reset_ctrl(struct nvme_ctrl *ctrl)
85{
86 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
87 return -EBUSY;
88 if (!queue_work(nvme_wq, &ctrl->reset_work))
89 return -EBUSY;
90 return 0;
91}
92EXPORT_SYMBOL_GPL(nvme_reset_ctrl);
93
94static int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
95{
96 int ret;
97
98 ret = nvme_reset_ctrl(ctrl);
99 if (!ret)
100 flush_work(&ctrl->reset_work);
101 return ret;
102}
103
2a842aca 104static blk_status_t nvme_error_status(struct request *req)
27fa9bc5
CH		 105{
106 switch (nvme_req(req)->status & 0x7ff) {
107 case NVME_SC_SUCCESS:
2a842aca 108 return BLK_STS_OK;
27fa9bc5 109 case NVME_SC_CAP_EXCEEDED:
2a842aca 110 return BLK_STS_NOSPC;
e02ab023 111 case NVME_SC_ONCS_NOT_SUPPORTED:
2a842aca 112 return BLK_STS_NOTSUPP;
e02ab023
JG		 113 case NVME_SC_WRITE_FAULT:
114 case NVME_SC_READ_ERROR:
115 case NVME_SC_UNWRITTEN_BLOCK:
a751da33
CH		 116 case NVME_SC_ACCESS_DENIED:
117 case NVME_SC_READ_ONLY:
2a842aca 118 return BLK_STS_MEDIUM;
a751da33
CH		 119 case NVME_SC_GUARD_CHECK:
120 case NVME_SC_APPTAG_CHECK:
121 case NVME_SC_REFTAG_CHECK:
122 case NVME_SC_INVALID_PI:
123 return BLK_STS_PROTECTION;
124 case NVME_SC_RESERVATION_CONFLICT:
125 return BLK_STS_NEXUS;
2a842aca
CH		 126 default:
127 return BLK_STS_IOERR;
27fa9bc5
CH		 128 }
129}
27fa9bc5 130
f6324b1b 131static inline bool nvme_req_needs_retry(struct request *req)
77f02a7a 132{
f6324b1b
CH		 133 if (blk_noretry_request(req))
134 return false;
27fa9bc5 135 if (nvme_req(req)->status & NVME_SC_DNR)
f6324b1b
CH		 136 return false;
137 if (jiffies - req->start_time >= req->timeout)
138 return false;
44e44b29 139 if (nvme_req(req)->retries >= nvme_max_retries)
f6324b1b
CH		 140 return false;
141 return true;
77f02a7a
CH		 142}
143
144void nvme_complete_rq(struct request *req)
145{
27fa9bc5
CH		 146 if (unlikely(nvme_req(req)->status && nvme_req_needs_retry(req))) {
147 nvme_req(req)->retries++;
8d7b8faf 148 blk_mq_requeue_request(req, true);
27fa9bc5 149 return;
77f02a7a
CH		 150 }
151
27fa9bc5 152 blk_mq_end_request(req, nvme_error_status(req));
77f02a7a
CH		 153}
154EXPORT_SYMBOL_GPL(nvme_complete_rq);
155
c55a2fd4
ML		 156void nvme_cancel_request(struct request *req, void *data, bool reserved)
157{
158 int status;
159
160 if (!blk_mq_request_started(req))
161 return;
162
163 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
164 "Cancelling I/O %d", req->tag);
165
166 status = NVME_SC_ABORT_REQ;
167 if (blk_queue_dying(req->q))
168 status |= NVME_SC_DNR;
27fa9bc5 169 nvme_req(req)->status = status;
08e0029a 170 blk_mq_complete_request(req);
27fa9bc5 171
c55a2fd4
ML		 172}
173EXPORT_SYMBOL_GPL(nvme_cancel_request);
174
bb8d261e
CH		 175bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
176 enum nvme_ctrl_state new_state)
177{
f6b6a28e 178 enum nvme_ctrl_state old_state;
0a72bbba 179 unsigned long flags;
bb8d261e
CH		 180 bool changed = false;
181
0a72bbba 182 spin_lock_irqsave(&ctrl->lock, flags);
f6b6a28e
GKB		 183
184 old_state = ctrl->state;
bb8d261e
CH		 185 switch (new_state) {
186 case NVME_CTRL_LIVE:
187 switch (old_state) {
7d2e8008 188 case NVME_CTRL_NEW:
bb8d261e 189 case NVME_CTRL_RESETTING:
def61eca 190 case NVME_CTRL_RECONNECTING:
bb8d261e
CH		 191 changed = true;
192 /* FALLTHRU */
193 default:
194 break;
195 }
196 break;
197 case NVME_CTRL_RESETTING:
198 switch (old_state) {
199 case NVME_CTRL_NEW:
def61eca 200 case NVME_CTRL_LIVE:
def61eca
CH		 201 changed = true;
202 /* FALLTHRU */
203 default:
204 break;
205 }
206 break;
207 case NVME_CTRL_RECONNECTING:
208 switch (old_state) {
bb8d261e
CH		 209 case NVME_CTRL_LIVE:
210 changed = true;
211 /* FALLTHRU */
212 default:
213 break;
214 }
215 break;
216 case NVME_CTRL_DELETING:
217 switch (old_state) {
218 case NVME_CTRL_LIVE:
219 case NVME_CTRL_RESETTING:
def61eca 220 case NVME_CTRL_RECONNECTING:
bb8d261e
CH		 221 changed = true;
222 /* FALLTHRU */
223 default:
224 break;
225 }
226 break;
0ff9d4e1
KB		 227 case NVME_CTRL_DEAD:
228 switch (old_state) {
229 case NVME_CTRL_DELETING:
230 changed = true;
231 /* FALLTHRU */
232 default:
233 break;
234 }
235 break;
bb8d261e
CH		 236 default:
237 break;
238 }
bb8d261e
CH		 239
240 if (changed)
241 ctrl->state = new_state;
242
0a72bbba 243 spin_unlock_irqrestore(&ctrl->lock, flags);
f6b6a28e 244
bb8d261e
CH		 245 return changed;
246}
247EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
248
1673f1f0
CH		 249static void nvme_free_ns(struct kref *kref)
250{
251 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
252
b0b4e09c
MB		 253 if (ns->ndev)
254 nvme_nvm_unregister(ns);
1673f1f0 255
b0b4e09c
MB		 256 if (ns->disk) {
257 spin_lock(&dev_list_lock);
258 ns->disk->private_data = NULL;
259 spin_unlock(&dev_list_lock);
260 }
1673f1f0 261
1673f1f0 262 put_disk(ns->disk);
075790eb
KB		 263 ida_simple_remove(&ns->ctrl->ns_ida, ns->instance);
264 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH		 265 kfree(ns);
266}
267
5bae7f73 268static void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH		 269{
270 kref_put(&ns->kref, nvme_free_ns);
271}
272
273static struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk)
274{
275 struct nvme_ns *ns;
276
277 spin_lock(&dev_list_lock);
278 ns = disk->private_data;
e439bb12
SG		 279 if (ns) {
280 if (!kref_get_unless_zero(&ns->kref))
281 goto fail;
282 if (!try_module_get(ns->ctrl->ops->module))
283 goto fail_put_ns;
284 }
1673f1f0
CH		 285 spin_unlock(&dev_list_lock);
286
287 return ns;
e439bb12
SG		 288
289fail_put_ns:
290 kref_put(&ns->kref, nvme_free_ns);
291fail:
292 spin_unlock(&dev_list_lock);
293 return NULL;
1673f1f0
CH		 294}
295
4160982e 296struct request *nvme_alloc_request(struct request_queue *q,
eb71f435 297 struct nvme_command *cmd, unsigned int flags, int qid)
21d34711 298{
aebf526b 299 unsigned op = nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN;
21d34711 300 struct request *req;
21d34711 301
eb71f435 302 if (qid == NVME_QID_ANY) {
aebf526b 303 req = blk_mq_alloc_request(q, op, flags);
eb71f435 304 } else {
aebf526b 305 req = blk_mq_alloc_request_hctx(q, op, flags,
eb71f435
CH		 306 qid ? qid - 1 : 0);
307 }
21d34711 308 if (IS_ERR(req))
4160982e 309 return req;
21d34711 310
21d34711 311 req->cmd_flags |= REQ_FAILFAST_DRIVER;
d49187e9 312 nvme_req(req)->cmd = cmd;
21d34711 313
4160982e
CH		 314 return req;
315}
576d55d6 316EXPORT_SYMBOL_GPL(nvme_alloc_request);
4160982e 317
f5d11840
JA		 318static int nvme_toggle_streams(struct nvme_ctrl *ctrl, bool enable)
319{
320 struct nvme_command c;
321
322 memset(&c, 0, sizeof(c));
323
324 c.directive.opcode = nvme_admin_directive_send;
62346eae 325 c.directive.nsid = cpu_to_le32(NVME_NSID_ALL);
f5d11840
JA		 326 c.directive.doper = NVME_DIR_SND_ID_OP_ENABLE;
327 c.directive.dtype = NVME_DIR_IDENTIFY;
328 c.directive.tdtype = NVME_DIR_STREAMS;
329 c.directive.endir = enable ? NVME_DIR_ENDIR : 0;
330
331 return nvme_submit_sync_cmd(ctrl->admin_q, &c, NULL, 0);
332}
333
334static int nvme_disable_streams(struct nvme_ctrl *ctrl)
335{
336 return nvme_toggle_streams(ctrl, false);
337}
338
339static int nvme_enable_streams(struct nvme_ctrl *ctrl)
340{
341 return nvme_toggle_streams(ctrl, true);
342}
343
344static int nvme_get_stream_params(struct nvme_ctrl *ctrl,
345 struct streams_directive_params *s, u32 nsid)
346{
347 struct nvme_command c;
348
349 memset(&c, 0, sizeof(c));
350 memset(s, 0, sizeof(*s));
351
352 c.directive.opcode = nvme_admin_directive_recv;
353 c.directive.nsid = cpu_to_le32(nsid);
a082b426 354 c.directive.numd = cpu_to_le32((sizeof(*s) >> 2) - 1);
f5d11840
JA		 355 c.directive.doper = NVME_DIR_RCV_ST_OP_PARAM;
356 c.directive.dtype = NVME_DIR_STREAMS;
357
358 return nvme_submit_sync_cmd(ctrl->admin_q, &c, s, sizeof(*s));
359}
360
361static int nvme_configure_directives(struct nvme_ctrl *ctrl)
362{
363 struct streams_directive_params s;
364 int ret;
365
366 if (!(ctrl->oacs & NVME_CTRL_OACS_DIRECTIVES))
367 return 0;
368 if (!streams)
369 return 0;
370
371 ret = nvme_enable_streams(ctrl);
372 if (ret)
373 return ret;
374
62346eae 375 ret = nvme_get_stream_params(ctrl, &s, NVME_NSID_ALL);
f5d11840
JA		 376 if (ret)
377 return ret;
378
379 ctrl->nssa = le16_to_cpu(s.nssa);
380 if (ctrl->nssa < BLK_MAX_WRITE_HINTS - 1) {
381 dev_info(ctrl->device, "too few streams (%u) available\n",
382 ctrl->nssa);
383 nvme_disable_streams(ctrl);
384 return 0;
385 }
386
387 ctrl->nr_streams = min_t(unsigned, ctrl->nssa, BLK_MAX_WRITE_HINTS - 1);
388 dev_info(ctrl->device, "Using %u streams\n", ctrl->nr_streams);
389 return 0;
390}
391
392/*
393 * Check if 'req' has a write hint associated with it. If it does, assign
394 * a valid namespace stream to the write.
395 */
396static void nvme_assign_write_stream(struct nvme_ctrl *ctrl,
397 struct request *req, u16 *control,
398 u32 *dsmgmt)
399{
400 enum rw_hint streamid = req->write_hint;
401
402 if (streamid == WRITE_LIFE_NOT_SET || streamid == WRITE_LIFE_NONE)
403 streamid = 0;
404 else {
405 streamid--;
406 if (WARN_ON_ONCE(streamid > ctrl->nr_streams))
407 return;
408
409 *control |= NVME_RW_DTYPE_STREAMS;
410 *dsmgmt |= streamid << 16;
411 }
412
413 if (streamid < ARRAY_SIZE(req->q->write_hints))
414 req->q->write_hints[streamid] += blk_rq_bytes(req) >> 9;
415}
416
8093f7ca
ML		 417static inline void nvme_setup_flush(struct nvme_ns *ns,
418 struct nvme_command *cmnd)
419{
420 memset(cmnd, 0, sizeof(*cmnd));
421 cmnd->common.opcode = nvme_cmd_flush;
422 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
423}
424
fc17b653 425static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 426 struct nvme_command *cmnd)
427{
b35ba01e 428 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
8093f7ca 429 struct nvme_dsm_range *range;
b35ba01e 430 struct bio *bio;
8093f7ca 431
b35ba01e 432 range = kmalloc_array(segments, sizeof(*range), GFP_ATOMIC);
8093f7ca 433 if (!range)
fc17b653 434 return BLK_STS_RESOURCE;
8093f7ca 435
b35ba01e
CH		 436 __rq_for_each_bio(bio, req) {
437 u64 slba = nvme_block_nr(ns, bio->bi_iter.bi_sector);
438 u32 nlb = bio->bi_iter.bi_size >> ns->lba_shift;
439
440 range[n].cattr = cpu_to_le32(0);
441 range[n].nlb = cpu_to_le32(nlb);
442 range[n].slba = cpu_to_le64(slba);
443 n++;
444 }
445
446 if (WARN_ON_ONCE(n != segments)) {
447 kfree(range);
fc17b653 448 return BLK_STS_IOERR;
b35ba01e 449 }
8093f7ca
ML		 450
451 memset(cmnd, 0, sizeof(*cmnd));
452 cmnd->dsm.opcode = nvme_cmd_dsm;
453 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
f1dd03a8 454 cmnd->dsm.nr = cpu_to_le32(segments - 1);
8093f7ca
ML		 455 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
456
f9d03f96
CH		 457 req->special_vec.bv_page = virt_to_page(range);
458 req->special_vec.bv_offset = offset_in_page(range);
b35ba01e 459 req->special_vec.bv_len = sizeof(*range) * segments;
f9d03f96 460 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 461
fc17b653 462 return BLK_STS_OK;
8093f7ca 463}
8093f7ca 464
ebe6d874
CH		 465static inline blk_status_t nvme_setup_rw(struct nvme_ns *ns,
466 struct request *req, struct nvme_command *cmnd)
8093f7ca 467{
f5d11840 468 struct nvme_ctrl *ctrl = ns->ctrl;
8093f7ca
ML		 469 u16 control = 0;
470 u32 dsmgmt = 0;
471
ebe6d874
CH		 472 /*
473 * If formated with metadata, require the block layer provide a buffer
474 * unless this namespace is formated such that the metadata can be
475 * stripped/generated by the controller with PRACT=1.
476 */
8fa61121
SG		 477 if (ns && ns->ms &&
478 (!ns->pi_type || ns->ms != sizeof(struct t10_pi_tuple)) &&
ebe6d874
CH		 479 !blk_integrity_rq(req) && !blk_rq_is_passthrough(req))
480 return BLK_STS_NOTSUPP;
481
8093f7ca
ML		 482 if (req->cmd_flags & REQ_FUA)
483 control |= NVME_RW_FUA;
484 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
485 control |= NVME_RW_LR;
486
487 if (req->cmd_flags & REQ_RAHEAD)
488 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
489
490 memset(cmnd, 0, sizeof(*cmnd));
491 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
8093f7ca
ML		 492 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
493 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
494 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
495
f5d11840
JA		 496 if (req_op(req) == REQ_OP_WRITE && ctrl->nr_streams)
497 nvme_assign_write_stream(ctrl, req, &control, &dsmgmt);
498
8093f7ca
ML		 499 if (ns->ms) {
500 switch (ns->pi_type) {
501 case NVME_NS_DPS_PI_TYPE3:
502 control |= NVME_RW_PRINFO_PRCHK_GUARD;
503 break;
504 case NVME_NS_DPS_PI_TYPE1:
505 case NVME_NS_DPS_PI_TYPE2:
506 control |= NVME_RW_PRINFO_PRCHK_GUARD |
507 NVME_RW_PRINFO_PRCHK_REF;
508 cmnd->rw.reftag = cpu_to_le32(
509 nvme_block_nr(ns, blk_rq_pos(req)));
510 break;
511 }
512 if (!blk_integrity_rq(req))
513 control |= NVME_RW_PRINFO_PRACT;
514 }
515
516 cmnd->rw.control = cpu_to_le16(control);
517 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
ebe6d874 518 return 0;
8093f7ca
ML		 519}
520
fc17b653 521blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 522 struct nvme_command *cmd)
523{
fc17b653 524 blk_status_t ret = BLK_STS_OK;
8093f7ca 525
987f699a 526 if (!(req->rq_flags & RQF_DONTPREP)) {
44e44b29 527 nvme_req(req)->retries = 0;
27fa9bc5 528 nvme_req(req)->flags = 0;
987f699a
CH		 529 req->rq_flags |= RQF_DONTPREP;
530 }
531
aebf526b
CH		 532 switch (req_op(req)) {
533 case REQ_OP_DRV_IN:
534 case REQ_OP_DRV_OUT:
d49187e9 535 memcpy(cmd, nvme_req(req)->cmd, sizeof(*cmd));
aebf526b
CH		 536 break;
537 case REQ_OP_FLUSH:
8093f7ca 538 nvme_setup_flush(ns, cmd);
aebf526b 539 break;
e850fd16
CH		 540 case REQ_OP_WRITE_ZEROES:
541 /* currently only aliased to deallocate for a few ctrls: */
aebf526b 542 case REQ_OP_DISCARD:
8093f7ca 543 ret = nvme_setup_discard(ns, req, cmd);
aebf526b
CH		 544 break;
545 case REQ_OP_READ:
546 case REQ_OP_WRITE:
ebe6d874 547 ret = nvme_setup_rw(ns, req, cmd);
aebf526b
CH		 548 break;
549 default:
550 WARN_ON_ONCE(1);
fc17b653 551 return BLK_STS_IOERR;
aebf526b 552 }
8093f7ca 553
721b3917 554 cmd->common.command_id = req->tag;
8093f7ca
ML		 555 return ret;
556}
557EXPORT_SYMBOL_GPL(nvme_setup_cmd);
558
4160982e
CH		 559/*
560 * Returns 0 on success. If the result is negative, it's a Linux error code;
561 * if the result is positive, it's an NVM Express status code
562 */
563int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 564 union nvme_result *result, void *buffer, unsigned bufflen,
eb71f435 565 unsigned timeout, int qid, int at_head, int flags)
4160982e
CH		 566{
567 struct request *req;
568 int ret;
569
eb71f435 570 req = nvme_alloc_request(q, cmd, flags, qid);
4160982e
CH		 571 if (IS_ERR(req))
572 return PTR_ERR(req);
573
574 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
575
21d34711
CH		 576 if (buffer && bufflen) {
577 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
578 if (ret)
579 goto out;
4160982e
CH		 580 }
581
eb71f435 582 blk_execute_rq(req->q, NULL, req, at_head);
d49187e9
CH		 583 if (result)
584 *result = nvme_req(req)->result;
27fa9bc5
CH		 585 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
586 ret = -EINTR;
587 else
588 ret = nvme_req(req)->status;
4160982e
CH		 589 out:
590 blk_mq_free_request(req);
591 return ret;
592}
eb71f435 593EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH		 594
595int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
596 void *buffer, unsigned bufflen)
597{
eb71f435
CH		 598 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 0,
599 NVME_QID_ANY, 0, 0);
4160982e 600}
576d55d6 601EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 602
1cad6562
CH		 603static void *nvme_add_user_metadata(struct bio *bio, void __user *ubuf,
604 unsigned len, u32 seed, bool write)
605{
606 struct bio_integrity_payload *bip;
607 int ret = -ENOMEM;
608 void *buf;
609
610 buf = kmalloc(len, GFP_KERNEL);
611 if (!buf)
612 goto out;
613
614 ret = -EFAULT;
615 if (write && copy_from_user(buf, ubuf, len))
616 goto out_free_meta;
617
618 bip = bio_integrity_alloc(bio, GFP_KERNEL, 1);
619 if (IS_ERR(bip)) {
620 ret = PTR_ERR(bip);
621 goto out_free_meta;
622 }
623
624 bip->bip_iter.bi_size = len;
625 bip->bip_iter.bi_sector = seed;
626 ret = bio_integrity_add_page(bio, virt_to_page(buf), len,
627 offset_in_page(buf));
628 if (ret == len)
629 return buf;
630 ret = -ENOMEM;
631out_free_meta:
632 kfree(buf);
633out:
634 return ERR_PTR(ret);
635}
636
485783ca
KB		 637static int __nvme_submit_user_cmd(struct request_queue *q,
638 struct nvme_command *cmd, void __user *ubuffer,
639 unsigned bufflen, void __user *meta_buffer, unsigned meta_len,
640 u32 meta_seed, u32 *result, unsigned timeout)
4160982e 641{
7a5abb4b 642 bool write = nvme_is_write(cmd);
0b7f1f26
KB		 643 struct nvme_ns *ns = q->queuedata;
644 struct gendisk *disk = ns ? ns->disk : NULL;
4160982e 645 struct request *req;
0b7f1f26
KB		 646 struct bio *bio = NULL;
647 void *meta = NULL;
4160982e
CH		 648 int ret;
649
eb71f435 650 req = nvme_alloc_request(q, cmd, 0, NVME_QID_ANY);
4160982e
CH		 651 if (IS_ERR(req))
652 return PTR_ERR(req);
653
654 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
655
656 if (ubuffer && bufflen) {
21d34711
CH		 657 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
658 GFP_KERNEL);
659 if (ret)
660 goto out;
661 bio = req->bio;
74d46992 662 bio->bi_disk = disk;
1cad6562
CH		 663 if (disk && meta_buffer && meta_len) {
664 meta = nvme_add_user_metadata(bio, meta_buffer, meta_len,
665 meta_seed, write);
666 if (IS_ERR(meta)) {
667 ret = PTR_ERR(meta);
0b7f1f26
KB		 668 goto out_unmap;
669 }
0b7f1f26
KB		 670 }
671 }
1cad6562 672
0b7f1f26 673 blk_execute_rq(req->q, disk, req, 0);
27fa9bc5
CH		 674 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
675 ret = -EINTR;
676 else
677 ret = nvme_req(req)->status;
21d34711 678 if (result)
d49187e9 679 *result = le32_to_cpu(nvme_req(req)->result.u32);
0b7f1f26
KB		 680 if (meta && !ret && !write) {
681 if (copy_to_user(meta_buffer, meta, meta_len))
682 ret = -EFAULT;
683 }
0b7f1f26
KB		 684 kfree(meta);
685 out_unmap:
74d46992 686 if (bio)
0b7f1f26 687 blk_rq_unmap_user(bio);
21d34711
CH		 688 out:
689 blk_mq_free_request(req);
690 return ret;
691}
692
485783ca 693static int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
0b7f1f26
KB		 694 void __user *ubuffer, unsigned bufflen, u32 *result,
695 unsigned timeout)
696{
697 return __nvme_submit_user_cmd(q, cmd, ubuffer, bufflen, NULL, 0, 0,
698 result, timeout);
699}
700
2a842aca 701static void nvme_keep_alive_end_io(struct request *rq, blk_status_t status)
038bd4cb
SG		 702{
703 struct nvme_ctrl *ctrl = rq->end_io_data;
704
705 blk_mq_free_request(rq);
706
2a842aca 707 if (status) {
038bd4cb 708 dev_err(ctrl->device,
2a842aca
CH		 709 "failed nvme_keep_alive_end_io error=%d\n",
710 status);
038bd4cb
SG		 711 return;
712 }
713
714 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
715}
716
717static int nvme_keep_alive(struct nvme_ctrl *ctrl)
718{
719 struct nvme_command c;
720 struct request *rq;
721
722 memset(&c, 0, sizeof(c));
723 c.common.opcode = nvme_admin_keep_alive;
724
725 rq = nvme_alloc_request(ctrl->admin_q, &c, BLK_MQ_REQ_RESERVED,
726 NVME_QID_ANY);
727 if (IS_ERR(rq))
728 return PTR_ERR(rq);
729
730 rq->timeout = ctrl->kato * HZ;
731 rq->end_io_data = ctrl;
732
733 blk_execute_rq_nowait(rq->q, NULL, rq, 0, nvme_keep_alive_end_io);
734
735 return 0;
736}
737
738static void nvme_keep_alive_work(struct work_struct *work)
739{
740 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
741 struct nvme_ctrl, ka_work);
742
743 if (nvme_keep_alive(ctrl)) {
744 /* allocation failure, reset the controller */
745 dev_err(ctrl->device, "keep-alive failed\n");
39bdc590 746 nvme_reset_ctrl(ctrl);
038bd4cb
SG		 747 return;
748 }
749}
750
751void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
752{
753 if (unlikely(ctrl->kato == 0))
754 return;
755
756 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
757 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
758}
759EXPORT_SYMBOL_GPL(nvme_start_keep_alive);
760
761void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
762{
763 if (unlikely(ctrl->kato == 0))
764 return;
765
766 cancel_delayed_work_sync(&ctrl->ka_work);
767}
768EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
769
3f7f25a9 770static int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH		 771{
772 struct nvme_command c = { };
773 int error;
774
775 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
776 c.identify.opcode = nvme_admin_identify;
986994a2 777 c.identify.cns = NVME_ID_CNS_CTRL;
21d34711
CH		 778
779 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
780 if (!*id)
781 return -ENOMEM;
782
783 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
784 sizeof(struct nvme_id_ctrl));
785 if (error)
786 kfree(*id);
787 return error;
788}
789
cdbff4f2
CH		 790static int nvme_identify_ns_descs(struct nvme_ctrl *ctrl, unsigned nsid,
791 u8 *eui64, u8 *nguid, uuid_t *uuid)
3b22ba26
JT		 792{
793 struct nvme_command c = { };
794 int status;
795 void *data;
796 int pos;
797 int len;
798
799 c.identify.opcode = nvme_admin_identify;
800 c.identify.nsid = cpu_to_le32(nsid);
801 c.identify.cns = NVME_ID_CNS_NS_DESC_LIST;
802
803 data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
804 if (!data)
805 return -ENOMEM;
806
cdbff4f2 807 status = nvme_submit_sync_cmd(ctrl->admin_q, &c, data,
3b22ba26
JT		 808 NVME_IDENTIFY_DATA_SIZE);
809 if (status)
810 goto free_data;
811
812 for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) {
813 struct nvme_ns_id_desc *cur = data + pos;
814
815 if (cur->nidl == 0)
816 break;
817
818 switch (cur->nidt) {
819 case NVME_NIDT_EUI64:
820 if (cur->nidl != NVME_NIDT_EUI64_LEN) {
cdbff4f2 821 dev_warn(ctrl->device,
3b22ba26
JT		 822 "ctrl returned bogus length: %d for NVME_NIDT_EUI64\n",
823 cur->nidl);
824 goto free_data;
825 }
826 len = NVME_NIDT_EUI64_LEN;
cdbff4f2 827 memcpy(eui64, data + pos + sizeof(*cur), len);
3b22ba26
JT		 828 break;
829 case NVME_NIDT_NGUID:
830 if (cur->nidl != NVME_NIDT_NGUID_LEN) {
cdbff4f2 831 dev_warn(ctrl->device,
3b22ba26
JT		 832 "ctrl returned bogus length: %d for NVME_NIDT_NGUID\n",
833 cur->nidl);
834 goto free_data;
835 }
836 len = NVME_NIDT_NGUID_LEN;
cdbff4f2 837 memcpy(nguid, data + pos + sizeof(*cur), len);
3b22ba26
JT		 838 break;
839 case NVME_NIDT_UUID:
840 if (cur->nidl != NVME_NIDT_UUID_LEN) {
cdbff4f2 841 dev_warn(ctrl->device,
3b22ba26
JT		 842 "ctrl returned bogus length: %d for NVME_NIDT_UUID\n",
843 cur->nidl);
844 goto free_data;
845 }
846 len = NVME_NIDT_UUID_LEN;
cdbff4f2 847 uuid_copy(uuid, data + pos + sizeof(*cur));
3b22ba26
JT		 848 break;
849 default:
850 /* Skip unnkown types */
851 len = cur->nidl;
852 break;
853 }
854
855 len += sizeof(*cur);
856 }
857free_data:
858 kfree(data);
859 return status;
860}
861
540c801c
KB		 862static int nvme_identify_ns_list(struct nvme_ctrl *dev, unsigned nsid, __le32 *ns_list)
863{
864 struct nvme_command c = { };
865
866 c.identify.opcode = nvme_admin_identify;
986994a2 867 c.identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST;
540c801c
KB		 868 c.identify.nsid = cpu_to_le32(nsid);
869 return nvme_submit_sync_cmd(dev->admin_q, &c, ns_list, 0x1000);
870}
871
cdbff4f2
CH		 872static struct nvme_id_ns *nvme_identify_ns(struct nvme_ctrl *ctrl,
873 unsigned nsid)
21d34711 874{
cdbff4f2 875 struct nvme_id_ns *id;
21d34711
CH		 876 struct nvme_command c = { };
877 int error;
878
879 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
778f067c
MG		 880 c.identify.opcode = nvme_admin_identify;
881 c.identify.nsid = cpu_to_le32(nsid);
986994a2 882 c.identify.cns = NVME_ID_CNS_NS;
21d34711 883
cdbff4f2
CH		 884 id = kmalloc(sizeof(*id), GFP_KERNEL);
885 if (!id)
886 return NULL;
21d34711 887
cdbff4f2
CH		 888 error = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id));
889 if (error) {
890 dev_warn(ctrl->device, "Identify namespace failed\n");
891 kfree(id);
892 return NULL;
893 }
894
895 return id;
21d34711
CH		 896}
897
3f7f25a9 898static int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
1a6fe74d 899 void *buffer, size_t buflen, u32 *result)
21d34711
CH		 900{
901 struct nvme_command c;
d49187e9 902 union nvme_result res;
1cb3cce5 903 int ret;
21d34711
CH		 904
905 memset(&c, 0, sizeof(c));
906 c.features.opcode = nvme_admin_set_features;
21d34711
CH		 907 c.features.fid = cpu_to_le32(fid);
908 c.features.dword11 = cpu_to_le32(dword11);
909
d49187e9 910 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
1a6fe74d 911 buffer, buflen, 0, NVME_QID_ANY, 0, 0);
9b47f77a 912 if (ret >= 0 && result)
d49187e9 913 *result = le32_to_cpu(res.u32);
1cb3cce5 914 return ret;
21d34711
CH		 915}
916
9a0be7ab
CH		 917int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
918{
919 u32 q_count = (*count - 1) | ((*count - 1) << 16);
920 u32 result;
921 int status, nr_io_queues;
922
1a6fe74d 923 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 924 &result);
f5fa90dc 925 if (status < 0)
9a0be7ab
CH		 926 return status;
927
f5fa90dc
CH		 928 /*
929 * Degraded controllers might return an error when setting the queue
930 * count. We still want to be able to bring them online and offer
931 * access to the admin queue, as that might be only way to fix them up.
932 */
933 if (status > 0) {
f0425db0 934 dev_err(ctrl->device, "Could not set queue count (%d)\n", status);
f5fa90dc
CH		 935 *count = 0;
936 } else {
937 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
938 *count = min(*count, nr_io_queues);
939 }
940
9a0be7ab
CH		 941 return 0;
942}
576d55d6 943EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 944
1673f1f0
CH		 945static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
946{
947 struct nvme_user_io io;
948 struct nvme_command c;
949 unsigned length, meta_len;
950 void __user *metadata;
951
952 if (copy_from_user(&io, uio, sizeof(io)))
953 return -EFAULT;
63088ec7
KB		 954 if (io.flags)
955 return -EINVAL;
1673f1f0
CH		 956
957 switch (io.opcode) {
958 case nvme_cmd_write:
959 case nvme_cmd_read:
960 case nvme_cmd_compare:
961 break;
962 default:
963 return -EINVAL;
964 }
965
966 length = (io.nblocks + 1) << ns->lba_shift;
967 meta_len = (io.nblocks + 1) * ns->ms;
968 metadata = (void __user *)(uintptr_t)io.metadata;
969
970 if (ns->ext) {
971 length += meta_len;
972 meta_len = 0;
973 } else if (meta_len) {
974 if ((io.metadata & 3) || !io.metadata)
975 return -EINVAL;
976 }
977
978 memset(&c, 0, sizeof(c));
979 c.rw.opcode = io.opcode;
980 c.rw.flags = io.flags;
981 c.rw.nsid = cpu_to_le32(ns->ns_id);
982 c.rw.slba = cpu_to_le64(io.slba);
983 c.rw.length = cpu_to_le16(io.nblocks);
984 c.rw.control = cpu_to_le16(io.control);
985 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
986 c.rw.reftag = cpu_to_le32(io.reftag);
987 c.rw.apptag = cpu_to_le16(io.apptag);
988 c.rw.appmask = cpu_to_le16(io.appmask);
989
990 return __nvme_submit_user_cmd(ns->queue, &c,
991 (void __user *)(uintptr_t)io.addr, length,
992 metadata, meta_len, io.slba, NULL, 0);
993}
994
f3ca80fc 995static int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1673f1f0
CH		 996 struct nvme_passthru_cmd __user *ucmd)
997{
998 struct nvme_passthru_cmd cmd;
999 struct nvme_command c;
1000 unsigned timeout = 0;
1001 int status;
1002
1003 if (!capable(CAP_SYS_ADMIN))
1004 return -EACCES;
1005 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1006 return -EFAULT;
63088ec7
KB		 1007 if (cmd.flags)
1008 return -EINVAL;
1673f1f0
CH		 1009
1010 memset(&c, 0, sizeof(c));
1011 c.common.opcode = cmd.opcode;
1012 c.common.flags = cmd.flags;
1013 c.common.nsid = cpu_to_le32(cmd.nsid);
1014 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1015 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1016 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1017 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1018 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1019 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1020 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1021 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1022
1023 if (cmd.timeout_ms)
1024 timeout = msecs_to_jiffies(cmd.timeout_ms);
1025
1026 status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c,
d1ea7be5 1027 (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
1673f1f0
CH		 1028 &cmd.result, timeout);
1029 if (status >= 0) {
1030 if (put_user(cmd.result, &ucmd->result))
1031 return -EFAULT;
1032 }
1033
1034 return status;
1035}
1036
1037static int nvme_ioctl(struct block_device *bdev, fmode_t mode,
1038 unsigned int cmd, unsigned long arg)
1039{
1040 struct nvme_ns *ns = bdev->bd_disk->private_data;
1041
1042 switch (cmd) {
1043 case NVME_IOCTL_ID:
1044 force_successful_syscall_return();
1045 return ns->ns_id;
1046 case NVME_IOCTL_ADMIN_CMD:
1047 return nvme_user_cmd(ns->ctrl, NULL, (void __user *)arg);
1048 case NVME_IOCTL_IO_CMD:
1049 return nvme_user_cmd(ns->ctrl, ns, (void __user *)arg);
1050 case NVME_IOCTL_SUBMIT_IO:
1051 return nvme_submit_io(ns, (void __user *)arg);
1673f1f0 1052 default:
84d4add7
MB		 1053#ifdef CONFIG_NVM
1054 if (ns->ndev)
1055 return nvme_nvm_ioctl(ns, cmd, arg);
1056#endif
a98e58e5 1057 if (is_sed_ioctl(cmd))
4f1244c8 1058 return sed_ioctl(ns->ctrl->opal_dev, cmd,
e225c20e 1059 (void __user *) arg);
1673f1f0
CH		 1060 return -ENOTTY;
1061 }
1062}
1063
1064#ifdef CONFIG_COMPAT
1065static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1066 unsigned int cmd, unsigned long arg)
1067{
1673f1f0
CH		 1068 return nvme_ioctl(bdev, mode, cmd, arg);
1069}
1070#else
1071#define nvme_compat_ioctl NULL
1072#endif
1073
1074static int nvme_open(struct block_device *bdev, fmode_t mode)
1075{
1076 return nvme_get_ns_from_disk(bdev->bd_disk) ? 0 : -ENXIO;
1077}
1078
1079static void nvme_release(struct gendisk *disk, fmode_t mode)
1080{
e439bb12
SG		 1081 struct nvme_ns *ns = disk->private_data;
1082
1083 module_put(ns->ctrl->ops->module);
1084 nvme_put_ns(ns);
1673f1f0
CH		 1085}
1086
1087static int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1088{
1089 /* some standard values */
1090 geo->heads = 1 << 6;
1091 geo->sectors = 1 << 5;
1092 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
1093 return 0;
1094}
1095
1096#ifdef CONFIG_BLK_DEV_INTEGRITY
c81bfba9
CH		 1097static void nvme_prep_integrity(struct gendisk *disk, struct nvme_id_ns *id,
1098 u16 bs)
1099{
1100 struct nvme_ns *ns = disk->private_data;
1101 u16 old_ms = ns->ms;
1102 u8 pi_type = 0;
1103
1104 ns->ms = le16_to_cpu(id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ms);
1105 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
1106
1107 /* PI implementation requires metadata equal t10 pi tuple size */
1108 if (ns->ms == sizeof(struct t10_pi_tuple))
1109 pi_type = id->dps & NVME_NS_DPS_PI_MASK;
1110
1111 if (blk_get_integrity(disk) &&
1112 (ns->pi_type != pi_type || ns->ms != old_ms ||
1113 bs != queue_logical_block_size(disk->queue) ||
1114 (ns->ms && ns->ext)))
1115 blk_integrity_unregister(disk);
1116
1117 ns->pi_type = pi_type;
1118}
1119
1673f1f0
CH		 1120static void nvme_init_integrity(struct nvme_ns *ns)
1121{
1122 struct blk_integrity integrity;
1123
fa9a89fc 1124 memset(&integrity, 0, sizeof(integrity));
1673f1f0
CH		 1125 switch (ns->pi_type) {
1126 case NVME_NS_DPS_PI_TYPE3:
1127 integrity.profile = &t10_pi_type3_crc;
ba36c21b
NB		 1128 integrity.tag_size = sizeof(u16) + sizeof(u32);
1129 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1130 break;
1131 case NVME_NS_DPS_PI_TYPE1:
1132 case NVME_NS_DPS_PI_TYPE2:
1133 integrity.profile = &t10_pi_type1_crc;
ba36c21b
NB		 1134 integrity.tag_size = sizeof(u16);
1135 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1136 break;
1137 default:
1138 integrity.profile = NULL;
1139 break;
1140 }
1141 integrity.tuple_size = ns->ms;
1142 blk_integrity_register(ns->disk, &integrity);
1143 blk_queue_max_integrity_segments(ns->queue, 1);
1144}
1145#else
c81bfba9
CH		 1146static void nvme_prep_integrity(struct gendisk *disk, struct nvme_id_ns *id,
1147 u16 bs)
1148{
1149}
1673f1f0
CH		 1150static void nvme_init_integrity(struct nvme_ns *ns)
1151{
1152}
1153#endif /* CONFIG_BLK_DEV_INTEGRITY */
1154
6b8190d6
SB		 1155static void nvme_set_chunk_size(struct nvme_ns *ns)
1156{
1157 u32 chunk_size = (((u32)ns->noiob) << (ns->lba_shift - 9));
1158 blk_queue_chunk_sectors(ns->queue, rounddown_pow_of_two(chunk_size));
1159}
1160
1673f1f0
CH		 1161static void nvme_config_discard(struct nvme_ns *ns)
1162{
08095e70 1163 struct nvme_ctrl *ctrl = ns->ctrl;
1673f1f0 1164 u32 logical_block_size = queue_logical_block_size(ns->queue);
08095e70 1165
b35ba01e
CH		 1166 BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) <
1167 NVME_DSM_MAX_RANGES);
1168
f5d11840
JA		 1169 if (ctrl->nr_streams && ns->sws && ns->sgs) {
1170 unsigned int sz = logical_block_size * ns->sws * ns->sgs;
1171
1172 ns->queue->limits.discard_alignment = sz;
1173 ns->queue->limits.discard_granularity = sz;
1174 } else {
1175 ns->queue->limits.discard_alignment = logical_block_size;
1176 ns->queue->limits.discard_granularity = logical_block_size;
1177 }
bd0fc288 1178 blk_queue_max_discard_sectors(ns->queue, UINT_MAX);
b35ba01e 1179 blk_queue_max_discard_segments(ns->queue, NVME_DSM_MAX_RANGES);
1673f1f0 1180 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
e850fd16
CH		 1181
1182 if (ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
1183 blk_queue_max_write_zeroes_sectors(ns->queue, UINT_MAX);
1673f1f0
CH		 1184}
1185
cdbff4f2
CH		 1186static void nvme_report_ns_ids(struct nvme_ctrl *ctrl, unsigned int nsid,
1187 struct nvme_id_ns *id, u8 *eui64, u8 *nguid, uuid_t *uuid)
1673f1f0 1188{
cdbff4f2
CH		 1189 if (ctrl->vs >= NVME_VS(1, 1, 0))
1190 memcpy(eui64, id->eui64, sizeof(id->eui64));
1191 if (ctrl->vs >= NVME_VS(1, 2, 0))
1192 memcpy(nguid, id->nguid, sizeof(id->nguid));
1193 if (ctrl->vs >= NVME_VS(1, 3, 0)) {
3b22ba26
JT		 1194 /* Don't treat error as fatal we potentially
1195 * already have a NGUID or EUI-64
1196 */
cdbff4f2
CH		 1197 if (nvme_identify_ns_descs(ctrl, nsid, eui64, nguid, uuid))
1198 dev_warn(ctrl->device,
3b22ba26
JT		 1199 "%s: Identify Descriptors failed\n", __func__);
1200 }
ac81bfa9
MB		 1201}
1202
1203static void __nvme_revalidate_disk(struct gendisk *disk, struct nvme_id_ns *id)
1204{
1205 struct nvme_ns *ns = disk->private_data;
f5d11840 1206 struct nvme_ctrl *ctrl = ns->ctrl;
c81bfba9 1207 u16 bs;
1673f1f0
CH		 1208
1209 /*
1210 * If identify namespace failed, use default 512 byte block size so
1211 * block layer can use before failing read/write for 0 capacity.
1212 */
c81bfba9 1213 ns->lba_shift = id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ds;
1673f1f0
CH		 1214 if (ns->lba_shift == 0)
1215 ns->lba_shift = 9;
1216 bs = 1 << ns->lba_shift;
6b8190d6 1217 ns->noiob = le16_to_cpu(id->noiob);
1673f1f0
CH		 1218
1219 blk_mq_freeze_queue(disk->queue);
1673f1f0 1220
f5d11840 1221 if (ctrl->ops->flags & NVME_F_METADATA_SUPPORTED)
c81bfba9 1222 nvme_prep_integrity(disk, id, bs);
1673f1f0 1223 blk_queue_logical_block_size(ns->queue, bs);
6b8190d6
SB		 1224 if (ns->noiob)
1225 nvme_set_chunk_size(ns);
4b9d5b15 1226 if (ns->ms && !blk_get_integrity(disk) && !ns->ext)
1673f1f0 1227 nvme_init_integrity(ns);
1673f1f0
CH		 1228 if (ns->ms && !(ns->ms == 8 && ns->pi_type) && !blk_get_integrity(disk))
1229 set_capacity(disk, 0);
1230 else
1231 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1232
f5d11840 1233 if (ctrl->oncs & NVME_CTRL_ONCS_DSM)
1673f1f0
CH		 1234 nvme_config_discard(ns);
1235 blk_mq_unfreeze_queue(disk->queue);
ac81bfa9 1236}
1673f1f0 1237
ac81bfa9
MB		 1238static int nvme_revalidate_disk(struct gendisk *disk)
1239{
1240 struct nvme_ns *ns = disk->private_data;
cdbff4f2
CH		 1241 struct nvme_ctrl *ctrl = ns->ctrl;
1242 struct nvme_id_ns *id;
1d5df6af
CH		 1243 u8 eui64[8] = { 0 }, nguid[16] = { 0 };
1244 uuid_t uuid = uuid_null;
cdbff4f2 1245 int ret = 0;
ac81bfa9
MB		 1246
1247 if (test_bit(NVME_NS_DEAD, &ns->flags)) {
1248 set_capacity(disk, 0);
1249 return -ENODEV;
1250 }
1251
cdbff4f2
CH		 1252 id = nvme_identify_ns(ctrl, ns->ns_id);
1253 if (!id)
1254 return -ENODEV;
ac81bfa9 1255
cdbff4f2
CH		 1256 if (id->ncap == 0) {
1257 ret = -ENODEV;
1258 goto out;
1259 }
ac81bfa9 1260
1d5df6af
CH		 1261 nvme_report_ns_ids(ctrl, ns->ns_id, id, eui64, nguid, &uuid);
1262 if (!uuid_equal(&ns->uuid, &uuid) ||
1263 memcmp(&ns->nguid, &nguid, sizeof(ns->nguid)) ||
1264 memcmp(&ns->eui, &eui64, sizeof(ns->eui))) {
1265 dev_err(ctrl->device,
1266 "identifiers changed for nsid %d\n", ns->ns_id);
1267 ret = -ENODEV;
1268 }
1269
cdbff4f2
CH		 1270out:
1271 kfree(id);
1272 return ret;
1673f1f0
CH		 1273}
1274
1275static char nvme_pr_type(enum pr_type type)
1276{
1277 switch (type) {
1278 case PR_WRITE_EXCLUSIVE:
1279 return 1;
1280 case PR_EXCLUSIVE_ACCESS:
1281 return 2;
1282 case PR_WRITE_EXCLUSIVE_REG_ONLY:
1283 return 3;
1284 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
1285 return 4;
1286 case PR_WRITE_EXCLUSIVE_ALL_REGS:
1287 return 5;
1288 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
1289 return 6;
1290 default:
1291 return 0;
1292 }
1293};
1294
1295static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
1296 u64 key, u64 sa_key, u8 op)
1297{
1298 struct nvme_ns *ns = bdev->bd_disk->private_data;
1299 struct nvme_command c;
1300 u8 data[16] = { 0, };
1301
1302 put_unaligned_le64(key, &data[0]);
1303 put_unaligned_le64(sa_key, &data[8]);
1304
1305 memset(&c, 0, sizeof(c));
1306 c.common.opcode = op;
1307 c.common.nsid = cpu_to_le32(ns->ns_id);
1308 c.common.cdw10[0] = cpu_to_le32(cdw10);
1309
1310 return nvme_submit_sync_cmd(ns->queue, &c, data, 16);
1311}
1312
1313static int nvme_pr_register(struct block_device *bdev, u64 old,
1314 u64 new, unsigned flags)
1315{
1316 u32 cdw10;
1317
1318 if (flags & ~PR_FL_IGNORE_KEY)
1319 return -EOPNOTSUPP;
1320
1321 cdw10 = old ? 2 : 0;
1322 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
1323 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
1324 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
1325}
1326
1327static int nvme_pr_reserve(struct block_device *bdev, u64 key,
1328 enum pr_type type, unsigned flags)
1329{
1330 u32 cdw10;
1331
1332 if (flags & ~PR_FL_IGNORE_KEY)
1333 return -EOPNOTSUPP;
1334
1335 cdw10 = nvme_pr_type(type) << 8;
1336 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
1337 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
1338}
1339
1340static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
1341 enum pr_type type, bool abort)
1342{
1343 u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
1344 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
1345}
1346
1347static int nvme_pr_clear(struct block_device *bdev, u64 key)
1348{
8c0b3915 1349 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
1673f1f0
CH		 1350 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
1351}
1352
1353static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
1354{
1355 u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
1356 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
1357}
1358
1359static const struct pr_ops nvme_pr_ops = {
1360 .pr_register = nvme_pr_register,
1361 .pr_reserve = nvme_pr_reserve,
1362 .pr_release = nvme_pr_release,
1363 .pr_preempt = nvme_pr_preempt,
1364 .pr_clear = nvme_pr_clear,
1365};
1366
a98e58e5 1367#ifdef CONFIG_BLK_SED_OPAL
4f1244c8
CH		 1368int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
1369 bool send)
a98e58e5 1370{
4f1244c8 1371 struct nvme_ctrl *ctrl = data;
a98e58e5 1372 struct nvme_command cmd;
a98e58e5
SB		 1373
1374 memset(&cmd, 0, sizeof(cmd));
1375 if (send)
1376 cmd.common.opcode = nvme_admin_security_send;
1377 else
1378 cmd.common.opcode = nvme_admin_security_recv;
a98e58e5
SB		 1379 cmd.common.nsid = 0;
1380 cmd.common.cdw10[0] = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
1381 cmd.common.cdw10[1] = cpu_to_le32(len);
1382
1383 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len,
1384 ADMIN_TIMEOUT, NVME_QID_ANY, 1, 0);
1385}
1386EXPORT_SYMBOL_GPL(nvme_sec_submit);
1387#endif /* CONFIG_BLK_SED_OPAL */
1388
5bae7f73 1389static const struct block_device_operations nvme_fops = {
1673f1f0
CH		 1390 .owner = THIS_MODULE,
1391 .ioctl = nvme_ioctl,
1392 .compat_ioctl = nvme_compat_ioctl,
1393 .open = nvme_open,
1394 .release = nvme_release,
1395 .getgeo = nvme_getgeo,
1396 .revalidate_disk= nvme_revalidate_disk,
1397 .pr_ops = &nvme_pr_ops,
1398};
1399
5fd4ce1b
CH		 1400static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
1401{
1402 unsigned long timeout =
1403 ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1404 u32 csts, bit = enabled ? NVME_CSTS_RDY : 0;
1405 int ret;
1406
1407 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB		 1408 if (csts == ~0)
1409 return -ENODEV;
5fd4ce1b
CH		 1410 if ((csts & NVME_CSTS_RDY) == bit)
1411 break;
1412
1413 msleep(100);
1414 if (fatal_signal_pending(current))
1415 return -EINTR;
1416 if (time_after(jiffies, timeout)) {
1b3c47c1 1417 dev_err(ctrl->device,
5fd4ce1b
CH		 1418 "Device not ready; aborting %s\n", enabled ?
1419 "initialisation" : "reset");
1420 return -ENODEV;
1421 }
1422 }
1423
1424 return ret;
1425}
1426
1427/*
1428 * If the device has been passed off to us in an enabled state, just clear
1429 * the enabled bit. The spec says we should set the 'shutdown notification
1430 * bits', but doing so may cause the device to complete commands to the
1431 * admin queue ... and we don't know what memory that might be pointing at!
1432 */
1433int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1434{
1435 int ret;
1436
1437 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1438 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
1439
1440 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1441 if (ret)
1442 return ret;
54adc010 1443
b5a10c5f 1444 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010
GP		 1445 msleep(NVME_QUIRK_DELAY_AMOUNT);
1446
5fd4ce1b
CH		 1447 return nvme_wait_ready(ctrl, cap, false);
1448}
576d55d6 1449EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b
CH		 1450
1451int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1452{
1453 /*
1454 * Default to a 4K page size, with the intention to update this
1455 * path in the future to accomodate architectures with differing
1456 * kernel and IO page sizes.
1457 */
1458 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12, page_shift = 12;
1459 int ret;
1460
1461 if (page_shift < dev_page_min) {
1b3c47c1 1462 dev_err(ctrl->device,
5fd4ce1b
CH		 1463 "Minimum device page size %u too large for host (%u)\n",
1464 1 << dev_page_min, 1 << page_shift);
1465 return -ENODEV;
1466 }
1467
1468 ctrl->page_size = 1 << page_shift;
1469
1470 ctrl->ctrl_config = NVME_CC_CSS_NVM;
1471 ctrl->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
60b43f62 1472 ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;
5fd4ce1b
CH		 1473 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1474 ctrl->ctrl_config |= NVME_CC_ENABLE;
1475
1476 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1477 if (ret)
1478 return ret;
1479 return nvme_wait_ready(ctrl, cap, true);
1480}
576d55d6 1481EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b
CH		 1482
1483int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl)
1484{
07fbd32a 1485 unsigned long timeout = jiffies + (ctrl->shutdown_timeout * HZ);
5fd4ce1b
CH		 1486 u32 csts;
1487 int ret;
1488
1489 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1490 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
1491
1492 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1493 if (ret)
1494 return ret;
1495
1496 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
1497 if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_CMPLT)
1498 break;
1499
1500 msleep(100);
1501 if (fatal_signal_pending(current))
1502 return -EINTR;
1503 if (time_after(jiffies, timeout)) {
1b3c47c1 1504 dev_err(ctrl->device,
5fd4ce1b
CH		 1505 "Device shutdown incomplete; abort shutdown\n");
1506 return -ENODEV;
1507 }
1508 }
1509
1510 return ret;
1511}
576d55d6 1512EXPORT_SYMBOL_GPL(nvme_shutdown_ctrl);
5fd4ce1b 1513
da35825d
CH		 1514static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
1515 struct request_queue *q)
1516{
7c88cb00
JA		 1517 bool vwc = false;
1518
da35825d 1519 if (ctrl->max_hw_sectors) {
45686b61
CH		 1520 u32 max_segments =
1521 (ctrl->max_hw_sectors / (ctrl->page_size >> 9)) + 1;
1522
da35825d 1523 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
45686b61 1524 blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
da35825d 1525 }
e6282aef
KB		 1526 if (ctrl->quirks & NVME_QUIRK_STRIPE_SIZE)
1527 blk_queue_chunk_sectors(q, ctrl->max_hw_sectors);
da35825d 1528 blk_queue_virt_boundary(q, ctrl->page_size - 1);
7c88cb00
JA		 1529 if (ctrl->vwc & NVME_CTRL_VWC_PRESENT)
1530 vwc = true;
1531 blk_queue_write_cache(q, vwc, vwc);
da35825d
CH		 1532}
1533
dbf86b39
JD		 1534static int nvme_configure_timestamp(struct nvme_ctrl *ctrl)
1535{
1536 __le64 ts;
1537 int ret;
1538
1539 if (!(ctrl->oncs & NVME_CTRL_ONCS_TIMESTAMP))
1540 return 0;
1541
1542 ts = cpu_to_le64(ktime_to_ms(ktime_get_real()));
1543 ret = nvme_set_features(ctrl, NVME_FEAT_TIMESTAMP, 0, &ts, sizeof(ts),
1544 NULL);
1545 if (ret)
1546 dev_warn_once(ctrl->device,
1547 "could not set timestamp (%d)\n", ret);
1548 return ret;
1549}
1550
634b8325 1551static int nvme_configure_apst(struct nvme_ctrl *ctrl)
c5552fde
AL		 1552{
1553 /*
1554 * APST (Autonomous Power State Transition) lets us program a
1555 * table of power state transitions that the controller will
1556 * perform automatically. We configure it with a simple
1557 * heuristic: we are willing to spend at most 2% of the time
1558 * transitioning between power states. Therefore, when running
1559 * in any given state, we will enter the next lower-power
76e4ad09 1560 * non-operational state after waiting 50 * (enlat + exlat)
da87591b 1561 * microseconds, as long as that state's exit latency is under
c5552fde
AL		 1562 * the requested maximum latency.
1563 *
1564 * We will not autonomously enter any non-operational state for
1565 * which the total latency exceeds ps_max_latency_us. Users
1566 * can set ps_max_latency_us to zero to turn off APST.
1567 */
1568
1569 unsigned apste;
1570 struct nvme_feat_auto_pst *table;
fb0dc399
AL		 1571 u64 max_lat_us = 0;
1572 int max_ps = -1;
c5552fde
AL		 1573 int ret;
1574
1575 /*
1576 * If APST isn't supported or if we haven't been initialized yet,
1577 * then don't do anything.
1578 */
1579 if (!ctrl->apsta)
634b8325 1580 return 0;
c5552fde
AL		 1581
1582 if (ctrl->npss > 31) {
1583 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
634b8325 1584 return 0;
c5552fde
AL		 1585 }
1586
1587 table = kzalloc(sizeof(*table), GFP_KERNEL);
1588 if (!table)
634b8325 1589 return 0;
c5552fde 1590
76a5af84 1591 if (!ctrl->apst_enabled || ctrl->ps_max_latency_us == 0) {
c5552fde
AL		 1592 /* Turn off APST. */
1593 apste = 0;
fb0dc399 1594 dev_dbg(ctrl->device, "APST disabled\n");
c5552fde
AL		 1595 } else {
1596 __le64 target = cpu_to_le64(0);
1597 int state;
1598
1599 /*
1600 * Walk through all states from lowest- to highest-power.
1601 * According to the spec, lower-numbered states use more
1602 * power. NPSS, despite the name, is the index of the
1603 * lowest-power state, not the number of states.
1604 */
1605 for (state = (int)ctrl->npss; state >= 0; state--) {
da87591b 1606 u64 total_latency_us, exit_latency_us, transition_ms;
c5552fde
AL		 1607
1608 if (target)
1609 table->entries[state] = target;
1610
ff5350a8
AL		 1611 /*
1612 * Don't allow transitions to the deepest state
1613 * if it's quirked off.
1614 */
1615 if (state == ctrl->npss &&
1616 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
1617 continue;
1618
c5552fde
AL		 1619 /*
1620 * Is this state a useful non-operational state for
1621 * higher-power states to autonomously transition to?
1622 */
1623 if (!(ctrl->psd[state].flags &
1624 NVME_PS_FLAGS_NON_OP_STATE))
1625 continue;
1626
da87591b
KHF		 1627 exit_latency_us =
1628 (u64)le32_to_cpu(ctrl->psd[state].exit_lat);
1629 if (exit_latency_us > ctrl->ps_max_latency_us)
c5552fde
AL		 1630 continue;
1631
da87591b
KHF		 1632 total_latency_us =
1633 exit_latency_us +
1634 le32_to_cpu(ctrl->psd[state].entry_lat);
1635
c5552fde
AL		 1636 /*
1637 * This state is good. Use it as the APST idle
1638 * target for higher power states.
1639 */
1640 transition_ms = total_latency_us + 19;
1641 do_div(transition_ms, 20);
1642 if (transition_ms > (1 << 24) - 1)
1643 transition_ms = (1 << 24) - 1;
1644
1645 target = cpu_to_le64((state << 3) |
1646 (transition_ms << 8));
fb0dc399
AL		 1647
1648 if (max_ps == -1)
1649 max_ps = state;
1650
1651 if (total_latency_us > max_lat_us)
1652 max_lat_us = total_latency_us;
c5552fde
AL		 1653 }
1654
1655 apste = 1;
fb0dc399
AL		 1656
1657 if (max_ps == -1) {
1658 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n");
1659 } else {
1660 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n",
1661 max_ps, max_lat_us, (int)sizeof(*table), table);
1662 }
c5552fde
AL		 1663 }
1664
1665 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
1666 table, sizeof(*table), NULL);
1667 if (ret)
1668 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
1669
1670 kfree(table);
634b8325 1671 return ret;
c5552fde
AL		 1672}
1673
1674static void nvme_set_latency_tolerance(struct device *dev, s32 val)
1675{
1676 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1677 u64 latency;
1678
1679 switch (val) {
1680 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
1681 case PM_QOS_LATENCY_ANY:
1682 latency = U64_MAX;
1683 break;
1684
1685 default:
1686 latency = val;
1687 }
1688
1689 if (ctrl->ps_max_latency_us != latency) {
1690 ctrl->ps_max_latency_us = latency;
1691 nvme_configure_apst(ctrl);
1692 }
1693}
1694
bd4da3ab
AL		 1695struct nvme_core_quirk_entry {
1696 /*
1697 * NVMe model and firmware strings are padded with spaces. For
1698 * simplicity, strings in the quirk table are padded with NULLs
1699 * instead.
1700 */
1701 u16 vid;
1702 const char *mn;
1703 const char *fr;
1704 unsigned long quirks;
1705};
1706
1707static const struct nvme_core_quirk_entry core_quirks[] = {
c5552fde 1708 {
be56945c
AL		 1709 /*
1710 * This Toshiba device seems to die using any APST states. See:
1711 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
1712 */
1713 .vid = 0x1179,
1714 .mn = "THNSF5256GPUK TOSHIBA",
c5552fde 1715 .quirks = NVME_QUIRK_NO_APST,
be56945c 1716 }
bd4da3ab
AL		 1717};
1718
1719/* match is null-terminated but idstr is space-padded. */
1720static bool string_matches(const char *idstr, const char *match, size_t len)
1721{
1722 size_t matchlen;
1723
1724 if (!match)
1725 return true;
1726
1727 matchlen = strlen(match);
1728 WARN_ON_ONCE(matchlen > len);
1729
1730 if (memcmp(idstr, match, matchlen))
1731 return false;
1732
1733 for (; matchlen < len; matchlen++)
1734 if (idstr[matchlen] != ' ')
1735 return false;
1736
1737 return true;
1738}
1739
1740static bool quirk_matches(const struct nvme_id_ctrl *id,
1741 const struct nvme_core_quirk_entry *q)
1742{
1743 return q->vid == le16_to_cpu(id->vid) &&
1744 string_matches(id->mn, q->mn, sizeof(id->mn)) &&
1745 string_matches(id->fr, q->fr, sizeof(id->fr));
1746}
1747
180de007
CH		 1748static void nvme_init_subnqn(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
1749{
1750 size_t nqnlen;
1751 int off;
1752
1753 nqnlen = strnlen(id->subnqn, NVMF_NQN_SIZE);
1754 if (nqnlen > 0 && nqnlen < NVMF_NQN_SIZE) {
1755 strcpy(ctrl->subnqn, id->subnqn);
1756 return;
1757 }
1758
1759 if (ctrl->vs >= NVME_VS(1, 2, 1))
1760 dev_warn(ctrl->device, "missing or invalid SUBNQN field.\n");
1761
1762 /* Generate a "fake" NQN per Figure 254 in NVMe 1.3 + ECN 001 */
1763 off = snprintf(ctrl->subnqn, NVMF_NQN_SIZE,
1764 "nqn.2014.08.org.nvmexpress:%4x%4x",
1765 le16_to_cpu(id->vid), le16_to_cpu(id->ssvid));
1766 memcpy(ctrl->subnqn + off, id->sn, sizeof(id->sn));
1767 off += sizeof(id->sn);
1768 memcpy(ctrl->subnqn + off, id->mn, sizeof(id->mn));
1769 off += sizeof(id->mn);
1770 memset(ctrl->subnqn + off, 0, sizeof(ctrl->subnqn) - off);
1771}
1772
7fd8930f
CH		 1773/*
1774 * Initialize the cached copies of the Identify data and various controller
1775 * register in our nvme_ctrl structure. This should be called as soon as
1776 * the admin queue is fully up and running.
1777 */
1778int nvme_init_identify(struct nvme_ctrl *ctrl)
1779{
1780 struct nvme_id_ctrl *id;
1781 u64 cap;
1782 int ret, page_shift;
a229dbf6 1783 u32 max_hw_sectors;
76a5af84 1784 bool prev_apst_enabled;
7fd8930f 1785
f3ca80fc
CH		 1786 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
1787 if (ret) {
1b3c47c1 1788 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
f3ca80fc
CH		 1789 return ret;
1790 }
1791
7fd8930f
CH		 1792 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &cap);
1793 if (ret) {
1b3c47c1 1794 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
7fd8930f
CH		 1795 return ret;
1796 }
1797 page_shift = NVME_CAP_MPSMIN(cap) + 12;
1798
8ef2074d 1799 if (ctrl->vs >= NVME_VS(1, 1, 0))
f3ca80fc
CH		 1800 ctrl->subsystem = NVME_CAP_NSSRC(cap);
1801
7fd8930f
CH		 1802 ret = nvme_identify_ctrl(ctrl, &id);
1803 if (ret) {
1b3c47c1 1804 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH		 1805 return -EIO;
1806 }
1807
180de007
CH		 1808 nvme_init_subnqn(ctrl, id);
1809
bd4da3ab
AL		 1810 if (!ctrl->identified) {
1811 /*
1812 * Check for quirks. Quirk can depend on firmware version,
1813 * so, in principle, the set of quirks present can change
1814 * across a reset. As a possible future enhancement, we
1815 * could re-scan for quirks every time we reinitialize
1816 * the device, but we'd have to make sure that the driver
1817 * behaves intelligently if the quirks change.
1818 */
1819
1820 int i;
1821
1822 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
1823 if (quirk_matches(id, &core_quirks[i]))
1824 ctrl->quirks |= core_quirks[i].quirks;
1825 }
1826 }
1827
c35e30b4 1828 if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) {
f0425db0 1829 dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n");
c35e30b4
AL		 1830 ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS;
1831 }
1832
8a9ae523 1833 ctrl->oacs = le16_to_cpu(id->oacs);
118472ab 1834 ctrl->vid = le16_to_cpu(id->vid);
7fd8930f 1835 ctrl->oncs = le16_to_cpup(&id->oncs);
6bf25d16 1836 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 1837 ctrl->vwc = id->vwc;
931e1c22 1838 ctrl->cntlid = le16_to_cpup(&id->cntlid);
7fd8930f
CH		 1839 memcpy(ctrl->serial, id->sn, sizeof(id->sn));
1840 memcpy(ctrl->model, id->mn, sizeof(id->mn));
1841 memcpy(ctrl->firmware_rev, id->fr, sizeof(id->fr));
1842 if (id->mdts)
a229dbf6 1843 max_hw_sectors = 1 << (id->mdts + page_shift - 9);
7fd8930f 1844 else
a229dbf6
CH		 1845 max_hw_sectors = UINT_MAX;
1846 ctrl->max_hw_sectors =
1847 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 1848
da35825d 1849 nvme_set_queue_limits(ctrl, ctrl->admin_q);
07bfcd09 1850 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 1851 ctrl->kas = le16_to_cpu(id->kas);
07bfcd09 1852
07fbd32a
MP		 1853 if (id->rtd3e) {
1854 /* us -> s */
1855 u32 transition_time = le32_to_cpu(id->rtd3e) / 1000000;
1856
1857 ctrl->shutdown_timeout = clamp_t(unsigned int, transition_time,
1858 shutdown_timeout, 60);
1859
1860 if (ctrl->shutdown_timeout != shutdown_timeout)
1861 dev_warn(ctrl->device,
1862 "Shutdown timeout set to %u seconds\n",
1863 ctrl->shutdown_timeout);
1864 } else
1865 ctrl->shutdown_timeout = shutdown_timeout;
1866
c5552fde 1867 ctrl->npss = id->npss;
76a5af84
KHF		 1868 ctrl->apsta = id->apsta;
1869 prev_apst_enabled = ctrl->apst_enabled;
c35e30b4
AL		 1870 if (ctrl->quirks & NVME_QUIRK_NO_APST) {
1871 if (force_apst && id->apsta) {
f0425db0 1872 dev_warn(ctrl->device, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n");
76a5af84 1873 ctrl->apst_enabled = true;
c35e30b4 1874 } else {
76a5af84 1875 ctrl->apst_enabled = false;
c35e30b4
AL		 1876 }
1877 } else {
76a5af84 1878 ctrl->apst_enabled = id->apsta;
c35e30b4 1879 }
c5552fde
AL		 1880 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
1881
d3d5b87d 1882 if (ctrl->ops->flags & NVME_F_FABRICS) {
07bfcd09
CH		 1883 ctrl->icdoff = le16_to_cpu(id->icdoff);
1884 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
1885 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
1886 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
1887
1888 /*
1889 * In fabrics we need to verify the cntlid matches the
1890 * admin connect
1891 */
634b8325 1892 if (ctrl->cntlid != le16_to_cpu(id->cntlid)) {
07bfcd09 1893 ret = -EINVAL;
634b8325
KB		 1894 goto out_free;
1895 }
038bd4cb
SG		 1896
1897 if (!ctrl->opts->discovery_nqn && !ctrl->kas) {
f0425db0 1898 dev_err(ctrl->device,
038bd4cb
SG		 1899 "keep-alive support is mandatory for fabrics\n");
1900 ret = -EINVAL;
634b8325 1901 goto out_free;
038bd4cb 1902 }
07bfcd09
CH		 1903 } else {
1904 ctrl->cntlid = le16_to_cpu(id->cntlid);
fe6d53c9
CH		 1905 ctrl->hmpre = le32_to_cpu(id->hmpre);
1906 ctrl->hmmin = le32_to_cpu(id->hmmin);
07bfcd09 1907 }
da35825d 1908
7fd8930f 1909 kfree(id);
bd4da3ab 1910
76a5af84 1911 if (ctrl->apst_enabled && !prev_apst_enabled)
c5552fde 1912 dev_pm_qos_expose_latency_tolerance(ctrl->device);
76a5af84 1913 else if (!ctrl->apst_enabled && prev_apst_enabled)
c5552fde
AL		 1914 dev_pm_qos_hide_latency_tolerance(ctrl->device);
1915
634b8325
KB		 1916 ret = nvme_configure_apst(ctrl);
1917 if (ret < 0)
1918 return ret;
dbf86b39
JD		 1919
1920 ret = nvme_configure_timestamp(ctrl);
1921 if (ret < 0)
1922 return ret;
634b8325
KB		 1923
1924 ret = nvme_configure_directives(ctrl);
1925 if (ret < 0)
1926 return ret;
c5552fde 1927
bd4da3ab 1928 ctrl->identified = true;
c5552fde 1929
634b8325
KB		 1930 return 0;
1931
1932out_free:
1933 kfree(id);
07bfcd09 1934 return ret;
7fd8930f 1935}
576d55d6 1936EXPORT_SYMBOL_GPL(nvme_init_identify);
7fd8930f 1937
f3ca80fc 1938static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 1939{
f3ca80fc
CH		 1940 struct nvme_ctrl *ctrl;
1941 int instance = iminor(inode);
1942 int ret = -ENODEV;
1673f1f0 1943
f3ca80fc
CH		 1944 spin_lock(&dev_list_lock);
1945 list_for_each_entry(ctrl, &nvme_ctrl_list, node) {
1946 if (ctrl->instance != instance)
1947 continue;
1948
1949 if (!ctrl->admin_q) {
1950 ret = -EWOULDBLOCK;
1951 break;
1952 }
1953 if (!kref_get_unless_zero(&ctrl->kref))
1954 break;
1955 file->private_data = ctrl;
1956 ret = 0;
1957 break;
1958 }
1959 spin_unlock(&dev_list_lock);
1960
1961 return ret;
1673f1f0
CH		 1962}
1963
f3ca80fc 1964static int nvme_dev_release(struct inode *inode, struct file *file)
1673f1f0 1965{
f3ca80fc
CH		 1966 nvme_put_ctrl(file->private_data);
1967 return 0;
1968}
1969
bfd89471
CH		 1970static int nvme_dev_user_cmd(struct nvme_ctrl *ctrl, void __user *argp)
1971{
1972 struct nvme_ns *ns;
1973 int ret;
1974
1975 mutex_lock(&ctrl->namespaces_mutex);
1976 if (list_empty(&ctrl->namespaces)) {
1977 ret = -ENOTTY;
1978 goto out_unlock;
1979 }
1980
1981 ns = list_first_entry(&ctrl->namespaces, struct nvme_ns, list);
1982 if (ns != list_last_entry(&ctrl->namespaces, struct nvme_ns, list)) {
1b3c47c1 1983 dev_warn(ctrl->device,
bfd89471
CH		 1984 "NVME_IOCTL_IO_CMD not supported when multiple namespaces present!\n");
1985 ret = -EINVAL;
1986 goto out_unlock;
1987 }
1988
1b3c47c1 1989 dev_warn(ctrl->device,
bfd89471
CH		 1990 "using deprecated NVME_IOCTL_IO_CMD ioctl on the char device!\n");
1991 kref_get(&ns->kref);
1992 mutex_unlock(&ctrl->namespaces_mutex);
1993
1994 ret = nvme_user_cmd(ctrl, ns, argp);
1995 nvme_put_ns(ns);
1996 return ret;
1997
1998out_unlock:
1999 mutex_unlock(&ctrl->namespaces_mutex);
2000 return ret;
2001}
2002
f3ca80fc
CH		 2003static long nvme_dev_ioctl(struct file *file, unsigned int cmd,
2004 unsigned long arg)
2005{
2006 struct nvme_ctrl *ctrl = file->private_data;
2007 void __user *argp = (void __user *)arg;
f3ca80fc
CH		 2008
2009 switch (cmd) {
2010 case NVME_IOCTL_ADMIN_CMD:
2011 return nvme_user_cmd(ctrl, NULL, argp);
2012 case NVME_IOCTL_IO_CMD:
bfd89471 2013 return nvme_dev_user_cmd(ctrl, argp);
f3ca80fc 2014 case NVME_IOCTL_RESET:
1b3c47c1 2015 dev_warn(ctrl->device, "resetting controller\n");
d86c4d8e 2016 return nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 2017 case NVME_IOCTL_SUBSYS_RESET:
2018 return nvme_reset_subsystem(ctrl);
9ec3bb2f
KB		 2019 case NVME_IOCTL_RESCAN:
2020 nvme_queue_scan(ctrl);
2021 return 0;
f3ca80fc
CH		 2022 default:
2023 return -ENOTTY;
2024 }
2025}
2026
2027static const struct file_operations nvme_dev_fops = {
2028 .owner = THIS_MODULE,
2029 .open = nvme_dev_open,
2030 .release = nvme_dev_release,
2031 .unlocked_ioctl = nvme_dev_ioctl,
2032 .compat_ioctl = nvme_dev_ioctl,
2033};
2034
2035static ssize_t nvme_sysfs_reset(struct device *dev,
2036 struct device_attribute *attr, const char *buf,
2037 size_t count)
2038{
2039 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2040 int ret;
2041
d86c4d8e 2042 ret = nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 2043 if (ret < 0)
2044 return ret;
2045 return count;
1673f1f0 2046}
f3ca80fc 2047static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
1673f1f0 2048
9ec3bb2f
KB		 2049static ssize_t nvme_sysfs_rescan(struct device *dev,
2050 struct device_attribute *attr, const char *buf,
2051 size_t count)
2052{
2053 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2054
2055 nvme_queue_scan(ctrl);
2056 return count;
2057}
2058static DEVICE_ATTR(rescan_controller, S_IWUSR, NULL, nvme_sysfs_rescan);
2059
118472ab
KB		 2060static ssize_t wwid_show(struct device *dev, struct device_attribute *attr,
2061 char *buf)
2062{
40267efd 2063 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
118472ab
KB		 2064 struct nvme_ctrl *ctrl = ns->ctrl;
2065 int serial_len = sizeof(ctrl->serial);
2066 int model_len = sizeof(ctrl->model);
2067
6484f5d1
JT		 2068 if (!uuid_is_null(&ns->uuid))
2069 return sprintf(buf, "uuid.%pU\n", &ns->uuid);
2070
90985b84
JT		 2071 if (memchr_inv(ns->nguid, 0, sizeof(ns->nguid)))
2072 return sprintf(buf, "eui.%16phN\n", ns->nguid);
118472ab
KB		 2073
2074 if (memchr_inv(ns->eui, 0, sizeof(ns->eui)))
2075 return sprintf(buf, "eui.%8phN\n", ns->eui);
2076
758f3735
MW		 2077 while (serial_len > 0 && (ctrl->serial[serial_len - 1] == ' ' ||
2078 ctrl->serial[serial_len - 1] == '\0'))
118472ab 2079 serial_len--;
758f3735
MW		 2080 while (model_len > 0 && (ctrl->model[model_len - 1] == ' ' ||
2081 ctrl->model[model_len - 1] == '\0'))
118472ab
KB		 2082 model_len--;
2083
2084 return sprintf(buf, "nvme.%04x-%*phN-%*phN-%08x\n", ctrl->vid,
2085 serial_len, ctrl->serial, model_len, ctrl->model, ns->ns_id);
2086}
2087static DEVICE_ATTR(wwid, S_IRUGO, wwid_show, NULL);
2088
d934f984
JT		 2089static ssize_t nguid_show(struct device *dev, struct device_attribute *attr,
2090 char *buf)
2091{
2092 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2093 return sprintf(buf, "%pU\n", ns->nguid);
2094}
2095static DEVICE_ATTR(nguid, S_IRUGO, nguid_show, NULL);
2096
2b9b6e86
KB		 2097static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,
2098 char *buf)
2099{
40267efd 2100 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
d934f984
JT		 2101
2102 /* For backward compatibility expose the NGUID to userspace if
2103 * we have no UUID set
2104 */
2105 if (uuid_is_null(&ns->uuid)) {
2106 printk_ratelimited(KERN_WARNING
2107 "No UUID available providing old NGUID\n");
2108 return sprintf(buf, "%pU\n", ns->nguid);
2109 }
2110 return sprintf(buf, "%pU\n", &ns->uuid);
2b9b6e86
KB		 2111}
2112static DEVICE_ATTR(uuid, S_IRUGO, uuid_show, NULL);
2113
2114static ssize_t eui_show(struct device *dev, struct device_attribute *attr,
2115 char *buf)
2116{
40267efd 2117 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 2118 return sprintf(buf, "%8phd\n", ns->eui);
2119}
2120static DEVICE_ATTR(eui, S_IRUGO, eui_show, NULL);
2121
2122static ssize_t nsid_show(struct device *dev, struct device_attribute *attr,
2123 char *buf)
2124{
40267efd 2125 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 2126 return sprintf(buf, "%d\n", ns->ns_id);
2127}
2128static DEVICE_ATTR(nsid, S_IRUGO, nsid_show, NULL);
2129
2130static struct attribute *nvme_ns_attrs[] = {
118472ab 2131 &dev_attr_wwid.attr,
2b9b6e86 2132 &dev_attr_uuid.attr,
d934f984 2133 &dev_attr_nguid.attr,
2b9b6e86
KB		 2134 &dev_attr_eui.attr,
2135 &dev_attr_nsid.attr,
2136 NULL,
2137};
2138
1a353d85 2139static umode_t nvme_ns_attrs_are_visible(struct kobject *kobj,
2b9b6e86
KB		 2140 struct attribute *a, int n)
2141{
2142 struct device *dev = container_of(kobj, struct device, kobj);
40267efd 2143 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 2144
2145 if (a == &dev_attr_uuid.attr) {
d934f984
JT		 2146 if (uuid_is_null(&ns->uuid) ||
2147 !memchr_inv(ns->nguid, 0, sizeof(ns->nguid)))
2148 return 0;
2149 }
2150 if (a == &dev_attr_nguid.attr) {
90985b84 2151 if (!memchr_inv(ns->nguid, 0, sizeof(ns->nguid)))
2b9b6e86
KB		 2152 return 0;
2153 }
2154 if (a == &dev_attr_eui.attr) {
2155 if (!memchr_inv(ns->eui, 0, sizeof(ns->eui)))
2156 return 0;
2157 }
2158 return a->mode;
2159}
2160
2161static const struct attribute_group nvme_ns_attr_group = {
2162 .attrs = nvme_ns_attrs,
1a353d85 2163 .is_visible = nvme_ns_attrs_are_visible,
2b9b6e86
KB		 2164};
2165
931e1c22 2166#define nvme_show_str_function(field) \
779ff756
KB		 2167static ssize_t field##_show(struct device *dev, \
2168 struct device_attribute *attr, char *buf) \
2169{ \
2170 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
2171 return sprintf(buf, "%.*s\n", (int)sizeof(ctrl->field), ctrl->field); \
2172} \
2173static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
2174
931e1c22
ML		 2175#define nvme_show_int_function(field) \
2176static ssize_t field##_show(struct device *dev, \
2177 struct device_attribute *attr, char *buf) \
2178{ \
2179 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
2180 return sprintf(buf, "%d\n", ctrl->field); \
2181} \
2182static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
2183
2184nvme_show_str_function(model);
2185nvme_show_str_function(serial);
2186nvme_show_str_function(firmware_rev);
2187nvme_show_int_function(cntlid);
779ff756 2188
1a353d85
ML		 2189static ssize_t nvme_sysfs_delete(struct device *dev,
2190 struct device_attribute *attr, const char *buf,
2191 size_t count)
2192{
2193 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2194
2195 if (device_remove_file_self(dev, attr))
2196 ctrl->ops->delete_ctrl(ctrl);
2197 return count;
2198}
2199static DEVICE_ATTR(delete_controller, S_IWUSR, NULL, nvme_sysfs_delete);
2200
2201static ssize_t nvme_sysfs_show_transport(struct device *dev,
2202 struct device_attribute *attr,
2203 char *buf)
2204{
2205 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2206
2207 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->ops->name);
2208}
2209static DEVICE_ATTR(transport, S_IRUGO, nvme_sysfs_show_transport, NULL);
2210
8432bdb2
SG		 2211static ssize_t nvme_sysfs_show_state(struct device *dev,
2212 struct device_attribute *attr,
2213 char *buf)
2214{
2215 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2216 static const char *const state_name[] = {
2217 [NVME_CTRL_NEW] = "new",
2218 [NVME_CTRL_LIVE] = "live",
2219 [NVME_CTRL_RESETTING] = "resetting",
2220 [NVME_CTRL_RECONNECTING]= "reconnecting",
2221 [NVME_CTRL_DELETING] = "deleting",
2222 [NVME_CTRL_DEAD] = "dead",
2223 };
2224
2225 if ((unsigned)ctrl->state < ARRAY_SIZE(state_name) &&
2226 state_name[ctrl->state])
2227 return sprintf(buf, "%s\n", state_name[ctrl->state]);
2228
2229 return sprintf(buf, "unknown state\n");
2230}
2231
2232static DEVICE_ATTR(state, S_IRUGO, nvme_sysfs_show_state, NULL);
2233
1a353d85
ML		 2234static ssize_t nvme_sysfs_show_subsysnqn(struct device *dev,
2235 struct device_attribute *attr,
2236 char *buf)
2237{
2238 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2239
180de007 2240 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->subnqn);
1a353d85
ML		 2241}
2242static DEVICE_ATTR(subsysnqn, S_IRUGO, nvme_sysfs_show_subsysnqn, NULL);
2243
2244static ssize_t nvme_sysfs_show_address(struct device *dev,
2245 struct device_attribute *attr,
2246 char *buf)
2247{
2248 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2249
2250 return ctrl->ops->get_address(ctrl, buf, PAGE_SIZE);
2251}
2252static DEVICE_ATTR(address, S_IRUGO, nvme_sysfs_show_address, NULL);
2253
779ff756
KB		 2254static struct attribute *nvme_dev_attrs[] = {
2255 &dev_attr_reset_controller.attr,
9ec3bb2f 2256 &dev_attr_rescan_controller.attr,
779ff756
KB		 2257 &dev_attr_model.attr,
2258 &dev_attr_serial.attr,
2259 &dev_attr_firmware_rev.attr,
931e1c22 2260 &dev_attr_cntlid.attr,
1a353d85
ML		 2261 &dev_attr_delete_controller.attr,
2262 &dev_attr_transport.attr,
2263 &dev_attr_subsysnqn.attr,
2264 &dev_attr_address.attr,
8432bdb2 2265 &dev_attr_state.attr,
779ff756
KB		 2266 NULL
2267};
2268
1a353d85
ML		 2269static umode_t nvme_dev_attrs_are_visible(struct kobject *kobj,
2270 struct attribute *a, int n)
2271{
2272 struct device *dev = container_of(kobj, struct device, kobj);
2273 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2274
49d3d50b
CH		 2275 if (a == &dev_attr_delete_controller.attr && !ctrl->ops->delete_ctrl)
2276 return 0;
2277 if (a == &dev_attr_address.attr && !ctrl->ops->get_address)
2278 return 0;
1a353d85
ML		 2279
2280 return a->mode;
2281}
2282
779ff756 2283static struct attribute_group nvme_dev_attrs_group = {
1a353d85
ML		 2284 .attrs = nvme_dev_attrs,
2285 .is_visible = nvme_dev_attrs_are_visible,
779ff756
KB		 2286};
2287
2288static const struct attribute_group *nvme_dev_attr_groups[] = {
2289 &nvme_dev_attrs_group,
2290 NULL,
2291};
2292
5bae7f73
CH		 2293static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2294{
2295 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2296 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2297
2298 return nsa->ns_id - nsb->ns_id;
2299}
2300
32f0c4af 2301static struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 2302{
32f0c4af 2303 struct nvme_ns *ns, *ret = NULL;
69d3b8ac 2304
32f0c4af 2305 mutex_lock(&ctrl->namespaces_mutex);
5bae7f73 2306 list_for_each_entry(ns, &ctrl->namespaces, list) {
32f0c4af
KB		 2307 if (ns->ns_id == nsid) {
2308 kref_get(&ns->kref);
2309 ret = ns;
2310 break;
2311 }
5bae7f73
CH		 2312 if (ns->ns_id > nsid)
2313 break;
2314 }
32f0c4af
KB		 2315 mutex_unlock(&ctrl->namespaces_mutex);
2316 return ret;
5bae7f73
CH		 2317}
2318
f5d11840
JA		 2319static int nvme_setup_streams_ns(struct nvme_ctrl *ctrl, struct nvme_ns *ns)
2320{
2321 struct streams_directive_params s;
2322 int ret;
2323
2324 if (!ctrl->nr_streams)
2325 return 0;
2326
2327 ret = nvme_get_stream_params(ctrl, &s, ns->ns_id);
2328 if (ret)
2329 return ret;
2330
2331 ns->sws = le32_to_cpu(s.sws);
2332 ns->sgs = le16_to_cpu(s.sgs);
2333
2334 if (ns->sws) {
2335 unsigned int bs = 1 << ns->lba_shift;
2336
2337 blk_queue_io_min(ns->queue, bs * ns->sws);
2338 if (ns->sgs)
2339 blk_queue_io_opt(ns->queue, bs * ns->sws * ns->sgs);
2340 }
2341
2342 return 0;
2343}
2344
5bae7f73
CH		 2345static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
2346{
2347 struct nvme_ns *ns;
2348 struct gendisk *disk;
ac81bfa9
MB		 2349 struct nvme_id_ns *id;
2350 char disk_name[DISK_NAME_LEN];
5bae7f73
CH		 2351 int node = dev_to_node(ctrl->dev);
2352
2353 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
2354 if (!ns)
2355 return;
2356
075790eb
KB		 2357 ns->instance = ida_simple_get(&ctrl->ns_ida, 1, 0, GFP_KERNEL);
2358 if (ns->instance < 0)
2359 goto out_free_ns;
2360
5bae7f73
CH		 2361 ns->queue = blk_mq_init_queue(ctrl->tagset);
2362 if (IS_ERR(ns->queue))
075790eb 2363 goto out_release_instance;
5bae7f73
CH		 2364 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
2365 ns->queue->queuedata = ns;
2366 ns->ctrl = ctrl;
2367
5bae7f73
CH		 2368 kref_init(&ns->kref);
2369 ns->ns_id = nsid;
5bae7f73 2370 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
5bae7f73
CH		 2371
2372 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
da35825d 2373 nvme_set_queue_limits(ctrl, ns->queue);
f5d11840 2374 nvme_setup_streams_ns(ctrl, ns);
5bae7f73 2375
ac81bfa9 2376 sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->instance);
5bae7f73 2377
cdbff4f2
CH		 2378 id = nvme_identify_ns(ctrl, nsid);
2379 if (!id)
ac81bfa9
MB		 2380 goto out_free_queue;
2381
cdbff4f2
CH		 2382 if (id->ncap == 0)
2383 goto out_free_id;
2384
2385 nvme_report_ns_ids(ctrl, ns->ns_id, id, ns->eui, ns->nguid, &ns->uuid);
2386
3dc87dd0
MB		 2387 if (nvme_nvm_ns_supported(ns, id) &&
2388 nvme_nvm_register(ns, disk_name, node)) {
f0425db0 2389 dev_warn(ctrl->device, "%s: LightNVM init failure\n", __func__);
3dc87dd0
MB		 2390 goto out_free_id;
2391 }
ac81bfa9 2392
3dc87dd0
MB		 2393 disk = alloc_disk_node(0, node);
2394 if (!disk)
2395 goto out_free_id;
ac81bfa9 2396
3dc87dd0
MB		 2397 disk->fops = &nvme_fops;
2398 disk->private_data = ns;
2399 disk->queue = ns->queue;
2400 disk->flags = GENHD_FL_EXT_DEVT;
2401 memcpy(disk->disk_name, disk_name, DISK_NAME_LEN);
2402 ns->disk = disk;
2403
2404 __nvme_revalidate_disk(disk, id);
5bae7f73 2405
32f0c4af
KB		 2406 mutex_lock(&ctrl->namespaces_mutex);
2407 list_add_tail(&ns->list, &ctrl->namespaces);
2408 mutex_unlock(&ctrl->namespaces_mutex);
2409
5bae7f73 2410 kref_get(&ctrl->kref);
ac81bfa9
MB		 2411
2412 kfree(id);
2413
0d52c756 2414 device_add_disk(ctrl->device, ns->disk);
2b9b6e86
KB		 2415 if (sysfs_create_group(&disk_to_dev(ns->disk)->kobj,
2416 &nvme_ns_attr_group))
2417 pr_warn("%s: failed to create sysfs group for identification\n",
2418 ns->disk->disk_name);
3dc87dd0
MB		 2419 if (ns->ndev && nvme_nvm_register_sysfs(ns))
2420 pr_warn("%s: failed to register lightnvm sysfs group for identification\n",
2421 ns->disk->disk_name);
5bae7f73 2422 return;
ac81bfa9
MB		 2423 out_free_id:
2424 kfree(id);
5bae7f73
CH		 2425 out_free_queue:
2426 blk_cleanup_queue(ns->queue);
075790eb
KB		 2427 out_release_instance:
2428 ida_simple_remove(&ctrl->ns_ida, ns->instance);
5bae7f73
CH		 2429 out_free_ns:
2430 kfree(ns);
2431}
2432
2433static void nvme_ns_remove(struct nvme_ns *ns)
2434{
646017a6
KB		 2435 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
2436 return;
69d3b8ac 2437
b0b4e09c 2438 if (ns->disk && ns->disk->flags & GENHD_FL_UP) {
5bae7f73
CH		 2439 if (blk_get_integrity(ns->disk))
2440 blk_integrity_unregister(ns->disk);
2b9b6e86
KB		 2441 sysfs_remove_group(&disk_to_dev(ns->disk)->kobj,
2442 &nvme_ns_attr_group);
3dc87dd0
MB		 2443 if (ns->ndev)
2444 nvme_nvm_unregister_sysfs(ns);
5bae7f73 2445 del_gendisk(ns->disk);
5bae7f73
CH		 2446 blk_cleanup_queue(ns->queue);
2447 }
32f0c4af
KB		 2448
2449 mutex_lock(&ns->ctrl->namespaces_mutex);
5bae7f73 2450 list_del_init(&ns->list);
32f0c4af
KB		 2451 mutex_unlock(&ns->ctrl->namespaces_mutex);
2452
5bae7f73
CH		 2453 nvme_put_ns(ns);
2454}
2455
540c801c
KB		 2456static void nvme_validate_ns(struct nvme_ctrl *ctrl, unsigned nsid)
2457{
2458 struct nvme_ns *ns;
2459
32f0c4af 2460 ns = nvme_find_get_ns(ctrl, nsid);
540c801c 2461 if (ns) {
b0b4e09c 2462 if (ns->disk && revalidate_disk(ns->disk))
540c801c 2463 nvme_ns_remove(ns);
32f0c4af 2464 nvme_put_ns(ns);
540c801c
KB		 2465 } else
2466 nvme_alloc_ns(ctrl, nsid);
2467}
2468
47b0e50a
SB		 2469static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
2470 unsigned nsid)
2471{
2472 struct nvme_ns *ns, *next;
2473
2474 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
2475 if (ns->ns_id > nsid)
2476 nvme_ns_remove(ns);
2477 }
2478}
2479
540c801c
KB		 2480static int nvme_scan_ns_list(struct nvme_ctrl *ctrl, unsigned nn)
2481{
2482 struct nvme_ns *ns;
2483 __le32 *ns_list;
2484 unsigned i, j, nsid, prev = 0, num_lists = DIV_ROUND_UP(nn, 1024);
2485 int ret = 0;
2486
2487 ns_list = kzalloc(0x1000, GFP_KERNEL);
2488 if (!ns_list)
2489 return -ENOMEM;
2490
2491 for (i = 0; i < num_lists; i++) {
2492 ret = nvme_identify_ns_list(ctrl, prev, ns_list);
2493 if (ret)
47b0e50a 2494 goto free;
540c801c
KB		 2495
2496 for (j = 0; j < min(nn, 1024U); j++) {
2497 nsid = le32_to_cpu(ns_list[j]);
2498 if (!nsid)
2499 goto out;
2500
2501 nvme_validate_ns(ctrl, nsid);
2502
2503 while (++prev < nsid) {
32f0c4af
KB		 2504 ns = nvme_find_get_ns(ctrl, prev);
2505 if (ns) {
540c801c 2506 nvme_ns_remove(ns);
32f0c4af
KB		 2507 nvme_put_ns(ns);
2508 }
540c801c
KB		 2509 }
2510 }
2511 nn -= j;
2512 }
2513 out:
47b0e50a
SB		 2514 nvme_remove_invalid_namespaces(ctrl, prev);
2515 free:
540c801c
KB		 2516 kfree(ns_list);
2517 return ret;
2518}
2519
5955be21 2520static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl, unsigned nn)
5bae7f73 2521{
5bae7f73
CH		 2522 unsigned i;
2523
540c801c
KB		 2524 for (i = 1; i <= nn; i++)
2525 nvme_validate_ns(ctrl, i);
2526
47b0e50a 2527 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH		 2528}
2529
5955be21 2530static void nvme_scan_work(struct work_struct *work)
5bae7f73 2531{
5955be21
CH		 2532 struct nvme_ctrl *ctrl =
2533 container_of(work, struct nvme_ctrl, scan_work);
5bae7f73 2534 struct nvme_id_ctrl *id;
540c801c 2535 unsigned nn;
5bae7f73 2536
5955be21
CH		 2537 if (ctrl->state != NVME_CTRL_LIVE)
2538 return;
2539
5bae7f73
CH		 2540 if (nvme_identify_ctrl(ctrl, &id))
2541 return;
540c801c
KB		 2542
2543 nn = le32_to_cpu(id->nn);
8ef2074d 2544 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
540c801c
KB		 2545 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
2546 if (!nvme_scan_ns_list(ctrl, nn))
2547 goto done;
2548 }
5955be21 2549 nvme_scan_ns_sequential(ctrl, nn);
540c801c 2550 done:
32f0c4af 2551 mutex_lock(&ctrl->namespaces_mutex);
540c801c 2552 list_sort(NULL, &ctrl->namespaces, ns_cmp);
69d3b8ac 2553 mutex_unlock(&ctrl->namespaces_mutex);
5bae7f73
CH		 2554 kfree(id);
2555}
5955be21
CH		 2556
2557void nvme_queue_scan(struct nvme_ctrl *ctrl)
2558{
2559 /*
2560 * Do not queue new scan work when a controller is reset during
2561 * removal.
2562 */
2563 if (ctrl->state == NVME_CTRL_LIVE)
c669ccdc 2564 queue_work(nvme_wq, &ctrl->scan_work);
5955be21
CH		 2565}
2566EXPORT_SYMBOL_GPL(nvme_queue_scan);
5bae7f73 2567
32f0c4af
KB		 2568/*
2569 * This function iterates the namespace list unlocked to allow recovery from
2570 * controller failure. It is up to the caller to ensure the namespace list is
2571 * not modified by scan work while this function is executing.
2572 */
5bae7f73
CH		 2573void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
2574{
2575 struct nvme_ns *ns, *next;
2576
0ff9d4e1
KB		 2577 /*
2578 * The dead states indicates the controller was not gracefully
2579 * disconnected. In that case, we won't be able to flush any data while
2580 * removing the namespaces' disks; fail all the queues now to avoid
2581 * potentially having to clean up the failed sync later.
2582 */
2583 if (ctrl->state == NVME_CTRL_DEAD)
2584 nvme_kill_queues(ctrl);
2585
5bae7f73
CH		 2586 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list)
2587 nvme_ns_remove(ns);
2588}
576d55d6 2589EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 2590
f866fc42
CH		 2591static void nvme_async_event_work(struct work_struct *work)
2592{
2593 struct nvme_ctrl *ctrl =
2594 container_of(work, struct nvme_ctrl, async_event_work);
2595
2596 spin_lock_irq(&ctrl->lock);
2597 while (ctrl->event_limit > 0) {
2598 int aer_idx = --ctrl->event_limit;
2599
2600 spin_unlock_irq(&ctrl->lock);
2601 ctrl->ops->submit_async_event(ctrl, aer_idx);
2602 spin_lock_irq(&ctrl->lock);
2603 }
2604 spin_unlock_irq(&ctrl->lock);
2605}
2606
b6dccf7f
AD		 2607static bool nvme_ctrl_pp_status(struct nvme_ctrl *ctrl)
2608{
2609
2610 u32 csts;
2611
2612 if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts))
2613 return false;
2614
2615 if (csts == ~0)
2616 return false;
2617
2618 return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP));
2619}
2620
2621static void nvme_get_fw_slot_info(struct nvme_ctrl *ctrl)
2622{
2623 struct nvme_command c = { };
2624 struct nvme_fw_slot_info_log *log;
2625
2626 log = kmalloc(sizeof(*log), GFP_KERNEL);
2627 if (!log)
2628 return;
2629
2630 c.common.opcode = nvme_admin_get_log_page;
62346eae 2631 c.common.nsid = cpu_to_le32(NVME_NSID_ALL);
b6dccf7f
AD		 2632 c.common.cdw10[0] = nvme_get_log_dw10(NVME_LOG_FW_SLOT, sizeof(*log));
2633
2634 if (!nvme_submit_sync_cmd(ctrl->admin_q, &c, log, sizeof(*log)))
2635 dev_warn(ctrl->device,
2636 "Get FW SLOT INFO log error\n");
2637 kfree(log);
2638}
2639
2640static void nvme_fw_act_work(struct work_struct *work)
2641{
2642 struct nvme_ctrl *ctrl = container_of(work,
2643 struct nvme_ctrl, fw_act_work);
2644 unsigned long fw_act_timeout;
2645
2646 if (ctrl->mtfa)
2647 fw_act_timeout = jiffies +
2648 msecs_to_jiffies(ctrl->mtfa * 100);
2649 else
2650 fw_act_timeout = jiffies +
2651 msecs_to_jiffies(admin_timeout * 1000);
2652
2653 nvme_stop_queues(ctrl);
2654 while (nvme_ctrl_pp_status(ctrl)) {
2655 if (time_after(jiffies, fw_act_timeout)) {
2656 dev_warn(ctrl->device,
2657 "Fw activation timeout, reset controller\n");
2658 nvme_reset_ctrl(ctrl);
2659 break;
2660 }
2661 msleep(100);
2662 }
2663
2664 if (ctrl->state != NVME_CTRL_LIVE)
2665 return;
2666
2667 nvme_start_queues(ctrl);
2668 /* read FW slot informationi to clear the AER*/
2669 nvme_get_fw_slot_info(ctrl);
2670}
2671
7bf58533
CH		 2672void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
2673 union nvme_result *res)
f866fc42 2674{
7bf58533
CH		 2675 u32 result = le32_to_cpu(res->u32);
2676 bool done = true;
f866fc42 2677
7bf58533
CH		 2678 switch (le16_to_cpu(status) >> 1) {
2679 case NVME_SC_SUCCESS:
2680 done = false;
2681 /*FALLTHRU*/
2682 case NVME_SC_ABORT_REQ:
f866fc42 2683 ++ctrl->event_limit;
c669ccdc 2684 queue_work(nvme_wq, &ctrl->async_event_work);
7bf58533
CH		 2685 break;
2686 default:
2687 break;
f866fc42
CH		 2688 }
2689
7bf58533 2690 if (done)
f866fc42
CH		 2691 return;
2692
2693 switch (result & 0xff07) {
2694 case NVME_AER_NOTICE_NS_CHANGED:
2695 dev_info(ctrl->device, "rescanning\n");
2696 nvme_queue_scan(ctrl);
2697 break;
b6dccf7f
AD		 2698 case NVME_AER_NOTICE_FW_ACT_STARTING:
2699 schedule_work(&ctrl->fw_act_work);
2700 break;
f866fc42
CH		 2701 default:
2702 dev_warn(ctrl->device, "async event result %08x\n", result);
2703 }
2704}
2705EXPORT_SYMBOL_GPL(nvme_complete_async_event);
2706
2707void nvme_queue_async_events(struct nvme_ctrl *ctrl)
2708{
2709 ctrl->event_limit = NVME_NR_AERS;
c669ccdc 2710 queue_work(nvme_wq, &ctrl->async_event_work);
f866fc42
CH		 2711}
2712EXPORT_SYMBOL_GPL(nvme_queue_async_events);
2713
f3ca80fc
CH		 2714static DEFINE_IDA(nvme_instance_ida);
2715
2716static int nvme_set_instance(struct nvme_ctrl *ctrl)
2717{
2718 int instance, error;
2719
2720 do {
2721 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2722 return -ENODEV;
2723
2724 spin_lock(&dev_list_lock);
2725 error = ida_get_new(&nvme_instance_ida, &instance);
2726 spin_unlock(&dev_list_lock);
2727 } while (error == -EAGAIN);
2728
2729 if (error)
2730 return -ENODEV;
2731
2732 ctrl->instance = instance;
2733 return 0;
2734}
2735
2736static void nvme_release_instance(struct nvme_ctrl *ctrl)
2737{
2738 spin_lock(&dev_list_lock);
2739 ida_remove(&nvme_instance_ida, ctrl->instance);
2740 spin_unlock(&dev_list_lock);
2741}
2742
d09f2b45 2743void nvme_stop_ctrl(struct nvme_ctrl *ctrl)
576d55d6 2744{
d09f2b45 2745 nvme_stop_keep_alive(ctrl);
f866fc42 2746 flush_work(&ctrl->async_event_work);
5955be21 2747 flush_work(&ctrl->scan_work);
b6dccf7f 2748 cancel_work_sync(&ctrl->fw_act_work);
d09f2b45
SG		 2749}
2750EXPORT_SYMBOL_GPL(nvme_stop_ctrl);
2751
2752void nvme_start_ctrl(struct nvme_ctrl *ctrl)
2753{
2754 if (ctrl->kato)
2755 nvme_start_keep_alive(ctrl);
2756
2757 if (ctrl->queue_count > 1) {
2758 nvme_queue_scan(ctrl);
2759 nvme_queue_async_events(ctrl);
2760 nvme_start_queues(ctrl);
2761 }
2762}
2763EXPORT_SYMBOL_GPL(nvme_start_ctrl);
5955be21 2764
d09f2b45
SG		 2765void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
2766{
53029b04 2767 device_destroy(nvme_class, MKDEV(nvme_char_major, ctrl->instance));
f3ca80fc
CH		 2768
2769 spin_lock(&dev_list_lock);
2770 list_del(&ctrl->node);
2771 spin_unlock(&dev_list_lock);
53029b04 2772}
576d55d6 2773EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04
KB		 2774
2775static void nvme_free_ctrl(struct kref *kref)
2776{
2777 struct nvme_ctrl *ctrl = container_of(kref, struct nvme_ctrl, kref);
f3ca80fc
CH		 2778
2779 put_device(ctrl->device);
2780 nvme_release_instance(ctrl);
075790eb 2781 ida_destroy(&ctrl->ns_ida);
f3ca80fc
CH		 2782
2783 ctrl->ops->free_ctrl(ctrl);
2784}
2785
2786void nvme_put_ctrl(struct nvme_ctrl *ctrl)
2787{
2788 kref_put(&ctrl->kref, nvme_free_ctrl);
2789}
576d55d6 2790EXPORT_SYMBOL_GPL(nvme_put_ctrl);
f3ca80fc
CH		 2791
2792/*
2793 * Initialize a NVMe controller structures. This needs to be called during
2794 * earliest initialization so that we have the initialized structured around
2795 * during probing.
2796 */
2797int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
2798 const struct nvme_ctrl_ops *ops, unsigned long quirks)
2799{
2800 int ret;
2801
bb8d261e
CH		 2802 ctrl->state = NVME_CTRL_NEW;
2803 spin_lock_init(&ctrl->lock);
f3ca80fc 2804 INIT_LIST_HEAD(&ctrl->namespaces);
69d3b8ac 2805 mutex_init(&ctrl->namespaces_mutex);
f3ca80fc
CH		 2806 kref_init(&ctrl->kref);
2807 ctrl->dev = dev;
2808 ctrl->ops = ops;
2809 ctrl->quirks = quirks;
5955be21 2810 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 2811 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
b6dccf7f 2812 INIT_WORK(&ctrl->fw_act_work, nvme_fw_act_work);
f3ca80fc
CH		 2813
2814 ret = nvme_set_instance(ctrl);
2815 if (ret)
2816 goto out;
2817
779ff756 2818 ctrl->device = device_create_with_groups(nvme_class, ctrl->dev,
f3ca80fc 2819 MKDEV(nvme_char_major, ctrl->instance),
f4f0f63e 2820 ctrl, nvme_dev_attr_groups,
779ff756 2821 "nvme%d", ctrl->instance);
f3ca80fc
CH		 2822 if (IS_ERR(ctrl->device)) {
2823 ret = PTR_ERR(ctrl->device);
2824 goto out_release_instance;
2825 }
2826 get_device(ctrl->device);
075790eb 2827 ida_init(&ctrl->ns_ida);
f3ca80fc 2828
f3ca80fc
CH		 2829 spin_lock(&dev_list_lock);
2830 list_add_tail(&ctrl->node, &nvme_ctrl_list);
2831 spin_unlock(&dev_list_lock);
2832
c5552fde
AL		 2833 /*
2834 * Initialize latency tolerance controls. The sysfs files won't
2835 * be visible to userspace unless the device actually supports APST.
2836 */
2837 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
2838 dev_pm_qos_update_user_latency_tolerance(ctrl->device,
2839 min(default_ps_max_latency_us, (unsigned long)S32_MAX));
2840
f3ca80fc 2841 return 0;
f3ca80fc
CH		 2842out_release_instance:
2843 nvme_release_instance(ctrl);
2844out:
2845 return ret;
2846}
576d55d6 2847EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 2848
69d9a99c
KB		 2849/**
2850 * nvme_kill_queues(): Ends all namespace queues
2851 * @ctrl: the dead controller that needs to end
2852 *
2853 * Call this function when the driver determines it is unable to get the
2854 * controller in a state capable of servicing IO.
2855 */
2856void nvme_kill_queues(struct nvme_ctrl *ctrl)
2857{
2858 struct nvme_ns *ns;
2859
32f0c4af 2860 mutex_lock(&ctrl->namespaces_mutex);
82654b6b 2861
443bd90f 2862 /* Forcibly unquiesce queues to avoid blocking dispatch */
7dd1ab16
SB		 2863 if (ctrl->admin_q)
2864 blk_mq_unquiesce_queue(ctrl->admin_q);
443bd90f 2865
32f0c4af 2866 list_for_each_entry(ns, &ctrl->namespaces, list) {
69d9a99c
KB		 2867 /*
2868 * Revalidating a dead namespace sets capacity to 0. This will
2869 * end buffered writers dirtying pages that can't be synced.
2870 */
f33447b9
KB		 2871 if (!ns->disk || test_and_set_bit(NVME_NS_DEAD, &ns->flags))
2872 continue;
2873 revalidate_disk(ns->disk);
69d9a99c 2874 blk_set_queue_dying(ns->queue);
806f026f 2875
443bd90f
ML		 2876 /* Forcibly unquiesce queues to avoid blocking dispatch */
2877 blk_mq_unquiesce_queue(ns->queue);
69d9a99c 2878 }
32f0c4af 2879 mutex_unlock(&ctrl->namespaces_mutex);
69d9a99c 2880}
237045fc 2881EXPORT_SYMBOL_GPL(nvme_kill_queues);
69d9a99c 2882
302ad8cc
KB		 2883void nvme_unfreeze(struct nvme_ctrl *ctrl)
2884{
2885 struct nvme_ns *ns;
2886
2887 mutex_lock(&ctrl->namespaces_mutex);
2888 list_for_each_entry(ns, &ctrl->namespaces, list)
2889 blk_mq_unfreeze_queue(ns->queue);
2890 mutex_unlock(&ctrl->namespaces_mutex);
2891}
2892EXPORT_SYMBOL_GPL(nvme_unfreeze);
2893
2894void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout)
2895{
2896 struct nvme_ns *ns;
2897
2898 mutex_lock(&ctrl->namespaces_mutex);
2899 list_for_each_entry(ns, &ctrl->namespaces, list) {
2900 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout);
2901 if (timeout <= 0)
2902 break;
2903 }
2904 mutex_unlock(&ctrl->namespaces_mutex);
2905}
2906EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout);
2907
2908void nvme_wait_freeze(struct nvme_ctrl *ctrl)
2909{
2910 struct nvme_ns *ns;
2911
2912 mutex_lock(&ctrl->namespaces_mutex);
2913 list_for_each_entry(ns, &ctrl->namespaces, list)
2914 blk_mq_freeze_queue_wait(ns->queue);
2915 mutex_unlock(&ctrl->namespaces_mutex);
2916}
2917EXPORT_SYMBOL_GPL(nvme_wait_freeze);
2918
2919void nvme_start_freeze(struct nvme_ctrl *ctrl)
2920{
2921 struct nvme_ns *ns;
2922
2923 mutex_lock(&ctrl->namespaces_mutex);
2924 list_for_each_entry(ns, &ctrl->namespaces, list)
1671d522 2925 blk_freeze_queue_start(ns->queue);
302ad8cc
KB		 2926 mutex_unlock(&ctrl->namespaces_mutex);
2927}
2928EXPORT_SYMBOL_GPL(nvme_start_freeze);
2929
25646264 2930void nvme_stop_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 2931{
2932 struct nvme_ns *ns;
2933
32f0c4af 2934 mutex_lock(&ctrl->namespaces_mutex);
a6eaa884 2935 list_for_each_entry(ns, &ctrl->namespaces, list)
3174dd33 2936 blk_mq_quiesce_queue(ns->queue);
32f0c4af 2937 mutex_unlock(&ctrl->namespaces_mutex);
363c9aac 2938}
576d55d6 2939EXPORT_SYMBOL_GPL(nvme_stop_queues);
363c9aac 2940
25646264 2941void nvme_start_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 2942{
2943 struct nvme_ns *ns;
2944
32f0c4af 2945 mutex_lock(&ctrl->namespaces_mutex);
8d7b8faf 2946 list_for_each_entry(ns, &ctrl->namespaces, list)
f660174e 2947 blk_mq_unquiesce_queue(ns->queue);
32f0c4af 2948 mutex_unlock(&ctrl->namespaces_mutex);
363c9aac 2949}
576d55d6 2950EXPORT_SYMBOL_GPL(nvme_start_queues);
363c9aac 2951
5bae7f73
CH		 2952int __init nvme_core_init(void)
2953{
2954 int result;
2955
9a6327d2
SG		 2956 nvme_wq = alloc_workqueue("nvme-wq",
2957 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
2958 if (!nvme_wq)
2959 return -ENOMEM;
2960
f3ca80fc
CH		 2961 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
2962 &nvme_dev_fops);
2963 if (result < 0)
9a6327d2 2964 goto destroy_wq;
f3ca80fc
CH		 2965 else if (result > 0)
2966 nvme_char_major = result;
2967
2968 nvme_class = class_create(THIS_MODULE, "nvme");
2969 if (IS_ERR(nvme_class)) {
2970 result = PTR_ERR(nvme_class);
2971 goto unregister_chrdev;
2972 }
2973
5bae7f73 2974 return 0;
f3ca80fc 2975
9a6327d2 2976unregister_chrdev:
f3ca80fc 2977 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
9a6327d2
SG		 2978destroy_wq:
2979 destroy_workqueue(nvme_wq);
f3ca80fc 2980 return result;
5bae7f73
CH		 2981}
2982
2983void nvme_core_exit(void)
2984{
f3ca80fc
CH		 2985 class_destroy(nvme_class);
2986 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
9a6327d2 2987 destroy_workqueue(nvme_wq);
5bae7f73 2988}
576d55d6
ML		 2989
2990MODULE_LICENSE("GPL");
2991MODULE_VERSION("1.0");
2992module_init(nvme_core_init);
2993module_exit(nvme_core_exit);
ubuntu-bionic-kernel mirror