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Merge tag 'at91-ab-4.13-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/abellon...
[mirror_ubuntu-bionic-kernel.git] / drivers / nvme / host / core.c
CommitLineData
21d34711
CH		 1/*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/blkdev.h>
16#include <linux/blk-mq.h>
5fd4ce1b 17#include <linux/delay.h>
21d34711 18#include <linux/errno.h>
1673f1f0 19#include <linux/hdreg.h>
21d34711 20#include <linux/kernel.h>
5bae7f73
CH		 21#include <linux/module.h>
22#include <linux/list_sort.h>
21d34711
CH		 23#include <linux/slab.h>
24#include <linux/types.h>
1673f1f0
CH		 25#include <linux/pr.h>
26#include <linux/ptrace.h>
27#include <linux/nvme_ioctl.h>
28#include <linux/t10-pi.h>
c5552fde 29#include <linux/pm_qos.h>
1673f1f0
CH		 30#include <scsi/sg.h>
31#include <asm/unaligned.h>
21d34711
CH		 32
33#include "nvme.h"
038bd4cb 34#include "fabrics.h"
21d34711 35
f3ca80fc
CH		 36#define NVME_MINORS (1U << MINORBITS)
37
ba0ba7d3
ML		 38unsigned char admin_timeout = 60;
39module_param(admin_timeout, byte, 0644);
40MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 41EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3
ML		 42
43unsigned char nvme_io_timeout = 30;
44module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
45MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 46EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3
ML		 47
48unsigned char shutdown_timeout = 5;
49module_param(shutdown_timeout, byte, 0644);
50MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
51
44e44b29
CH		 52static u8 nvme_max_retries = 5;
53module_param_named(max_retries, nvme_max_retries, byte, 0644);
f80ec966 54MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
5bae7f73 55
f3ca80fc
CH		 56static int nvme_char_major;
57module_param(nvme_char_major, int, 0);
58
c5552fde
AL		 59static unsigned long default_ps_max_latency_us = 25000;
60module_param(default_ps_max_latency_us, ulong, 0644);
61MODULE_PARM_DESC(default_ps_max_latency_us,
62 "max power saving latency for new devices; use PM QOS to change per device");
63
c35e30b4
AL		 64static bool force_apst;
65module_param(force_apst, bool, 0644);
66MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off");
67
f3ca80fc 68static LIST_HEAD(nvme_ctrl_list);
9f2482b9 69static DEFINE_SPINLOCK(dev_list_lock);
1673f1f0 70
f3ca80fc
CH		 71static struct class *nvme_class;
72
65ba6b54 73static int nvme_error_status(struct request *req)
27fa9bc5
CH		 74{
75 switch (nvme_req(req)->status & 0x7ff) {
76 case NVME_SC_SUCCESS:
77 return 0;
78 case NVME_SC_CAP_EXCEEDED:
79 return -ENOSPC;
80 default:
81 return -EIO;
e02ab023
JG		 82
83 /*
84 * XXX: these errors are a nasty side-band protocol to
85 * drivers/md/dm-mpath.c:noretry_error() that aren't documented
86 * anywhere..
87 */
88 case NVME_SC_CMD_SEQ_ERROR:
89 return -EILSEQ;
90 case NVME_SC_ONCS_NOT_SUPPORTED:
91 return -EOPNOTSUPP;
92 case NVME_SC_WRITE_FAULT:
93 case NVME_SC_READ_ERROR:
94 case NVME_SC_UNWRITTEN_BLOCK:
95 return -ENODATA;
27fa9bc5
CH		 96 }
97}
27fa9bc5 98
f6324b1b 99static inline bool nvme_req_needs_retry(struct request *req)
77f02a7a 100{
f6324b1b
CH		 101 if (blk_noretry_request(req))
102 return false;
27fa9bc5 103 if (nvme_req(req)->status & NVME_SC_DNR)
f6324b1b
CH		 104 return false;
105 if (jiffies - req->start_time >= req->timeout)
106 return false;
44e44b29 107 if (nvme_req(req)->retries >= nvme_max_retries)
f6324b1b
CH		 108 return false;
109 return true;
77f02a7a
CH		 110}
111
112void nvme_complete_rq(struct request *req)
113{
27fa9bc5
CH		 114 if (unlikely(nvme_req(req)->status && nvme_req_needs_retry(req))) {
115 nvme_req(req)->retries++;
116 blk_mq_requeue_request(req, !blk_mq_queue_stopped(req->q));
117 return;
77f02a7a
CH		 118 }
119
27fa9bc5 120 blk_mq_end_request(req, nvme_error_status(req));
77f02a7a
CH		 121}
122EXPORT_SYMBOL_GPL(nvme_complete_rq);
123
c55a2fd4
ML		 124void nvme_cancel_request(struct request *req, void *data, bool reserved)
125{
126 int status;
127
128 if (!blk_mq_request_started(req))
129 return;
130
131 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
132 "Cancelling I/O %d", req->tag);
133
134 status = NVME_SC_ABORT_REQ;
135 if (blk_queue_dying(req->q))
136 status |= NVME_SC_DNR;
27fa9bc5 137 nvme_req(req)->status = status;
08e0029a 138 blk_mq_complete_request(req);
27fa9bc5 139
c55a2fd4
ML		 140}
141EXPORT_SYMBOL_GPL(nvme_cancel_request);
142
bb8d261e
CH		 143bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
144 enum nvme_ctrl_state new_state)
145{
f6b6a28e 146 enum nvme_ctrl_state old_state;
bb8d261e
CH		 147 bool changed = false;
148
149 spin_lock_irq(&ctrl->lock);
f6b6a28e
GKB		 150
151 old_state = ctrl->state;
bb8d261e
CH		 152 switch (new_state) {
153 case NVME_CTRL_LIVE:
154 switch (old_state) {
7d2e8008 155 case NVME_CTRL_NEW:
bb8d261e 156 case NVME_CTRL_RESETTING:
def61eca 157 case NVME_CTRL_RECONNECTING:
bb8d261e
CH		 158 changed = true;
159 /* FALLTHRU */
160 default:
161 break;
162 }
163 break;
164 case NVME_CTRL_RESETTING:
165 switch (old_state) {
166 case NVME_CTRL_NEW:
def61eca
CH		 167 case NVME_CTRL_LIVE:
168 case NVME_CTRL_RECONNECTING:
169 changed = true;
170 /* FALLTHRU */
171 default:
172 break;
173 }
174 break;
175 case NVME_CTRL_RECONNECTING:
176 switch (old_state) {
bb8d261e
CH		 177 case NVME_CTRL_LIVE:
178 changed = true;
179 /* FALLTHRU */
180 default:
181 break;
182 }
183 break;
184 case NVME_CTRL_DELETING:
185 switch (old_state) {
186 case NVME_CTRL_LIVE:
187 case NVME_CTRL_RESETTING:
def61eca 188 case NVME_CTRL_RECONNECTING:
bb8d261e
CH		 189 changed = true;
190 /* FALLTHRU */
191 default:
192 break;
193 }
194 break;
0ff9d4e1
KB		 195 case NVME_CTRL_DEAD:
196 switch (old_state) {
197 case NVME_CTRL_DELETING:
198 changed = true;
199 /* FALLTHRU */
200 default:
201 break;
202 }
203 break;
bb8d261e
CH		 204 default:
205 break;
206 }
bb8d261e
CH		 207
208 if (changed)
209 ctrl->state = new_state;
210
f6b6a28e
GKB		 211 spin_unlock_irq(&ctrl->lock);
212
bb8d261e
CH		 213 return changed;
214}
215EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
216
1673f1f0
CH		 217static void nvme_free_ns(struct kref *kref)
218{
219 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
220
b0b4e09c
MB		 221 if (ns->ndev)
222 nvme_nvm_unregister(ns);
1673f1f0 223
b0b4e09c
MB		 224 if (ns->disk) {
225 spin_lock(&dev_list_lock);
226 ns->disk->private_data = NULL;
227 spin_unlock(&dev_list_lock);
228 }
1673f1f0 229
1673f1f0 230 put_disk(ns->disk);
075790eb
KB		 231 ida_simple_remove(&ns->ctrl->ns_ida, ns->instance);
232 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH		 233 kfree(ns);
234}
235
5bae7f73 236static void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH		 237{
238 kref_put(&ns->kref, nvme_free_ns);
239}
240
241static struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk)
242{
243 struct nvme_ns *ns;
244
245 spin_lock(&dev_list_lock);
246 ns = disk->private_data;
e439bb12
SG		 247 if (ns) {
248 if (!kref_get_unless_zero(&ns->kref))
249 goto fail;
250 if (!try_module_get(ns->ctrl->ops->module))
251 goto fail_put_ns;
252 }
1673f1f0
CH		 253 spin_unlock(&dev_list_lock);
254
255 return ns;
e439bb12
SG		 256
257fail_put_ns:
258 kref_put(&ns->kref, nvme_free_ns);
259fail:
260 spin_unlock(&dev_list_lock);
261 return NULL;
1673f1f0
CH		 262}
263
4160982e 264struct request *nvme_alloc_request(struct request_queue *q,
eb71f435 265 struct nvme_command *cmd, unsigned int flags, int qid)
21d34711 266{
aebf526b 267 unsigned op = nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN;
21d34711 268 struct request *req;
21d34711 269
eb71f435 270 if (qid == NVME_QID_ANY) {
aebf526b 271 req = blk_mq_alloc_request(q, op, flags);
eb71f435 272 } else {
aebf526b 273 req = blk_mq_alloc_request_hctx(q, op, flags,
eb71f435
CH		 274 qid ? qid - 1 : 0);
275 }
21d34711 276 if (IS_ERR(req))
4160982e 277 return req;
21d34711 278
21d34711 279 req->cmd_flags |= REQ_FAILFAST_DRIVER;
d49187e9 280 nvme_req(req)->cmd = cmd;
21d34711 281
4160982e
CH		 282 return req;
283}
576d55d6 284EXPORT_SYMBOL_GPL(nvme_alloc_request);
4160982e 285
8093f7ca
ML		 286static inline void nvme_setup_flush(struct nvme_ns *ns,
287 struct nvme_command *cmnd)
288{
289 memset(cmnd, 0, sizeof(*cmnd));
290 cmnd->common.opcode = nvme_cmd_flush;
291 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
292}
293
294static inline int nvme_setup_discard(struct nvme_ns *ns, struct request *req,
295 struct nvme_command *cmnd)
296{
b35ba01e 297 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
8093f7ca 298 struct nvme_dsm_range *range;
b35ba01e 299 struct bio *bio;
8093f7ca 300
b35ba01e 301 range = kmalloc_array(segments, sizeof(*range), GFP_ATOMIC);
8093f7ca
ML		 302 if (!range)
303 return BLK_MQ_RQ_QUEUE_BUSY;
304
b35ba01e
CH		 305 __rq_for_each_bio(bio, req) {
306 u64 slba = nvme_block_nr(ns, bio->bi_iter.bi_sector);
307 u32 nlb = bio->bi_iter.bi_size >> ns->lba_shift;
308
309 range[n].cattr = cpu_to_le32(0);
310 range[n].nlb = cpu_to_le32(nlb);
311 range[n].slba = cpu_to_le64(slba);
312 n++;
313 }
314
315 if (WARN_ON_ONCE(n != segments)) {
316 kfree(range);
317 return BLK_MQ_RQ_QUEUE_ERROR;
318 }
8093f7ca
ML		 319
320 memset(cmnd, 0, sizeof(*cmnd));
321 cmnd->dsm.opcode = nvme_cmd_dsm;
322 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
f1dd03a8 323 cmnd->dsm.nr = cpu_to_le32(segments - 1);
8093f7ca
ML		 324 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
325
f9d03f96
CH		 326 req->special_vec.bv_page = virt_to_page(range);
327 req->special_vec.bv_offset = offset_in_page(range);
b35ba01e 328 req->special_vec.bv_len = sizeof(*range) * segments;
f9d03f96 329 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 330
bac0000a 331 return BLK_MQ_RQ_QUEUE_OK;
8093f7ca 332}
8093f7ca 333
8093f7ca
ML		 334static inline void nvme_setup_rw(struct nvme_ns *ns, struct request *req,
335 struct nvme_command *cmnd)
336{
337 u16 control = 0;
338 u32 dsmgmt = 0;
339
340 if (req->cmd_flags & REQ_FUA)
341 control |= NVME_RW_FUA;
342 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
343 control |= NVME_RW_LR;
344
345 if (req->cmd_flags & REQ_RAHEAD)
346 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
347
348 memset(cmnd, 0, sizeof(*cmnd));
349 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
8093f7ca
ML		 350 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
351 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
352 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
353
354 if (ns->ms) {
355 switch (ns->pi_type) {
356 case NVME_NS_DPS_PI_TYPE3:
357 control |= NVME_RW_PRINFO_PRCHK_GUARD;
358 break;
359 case NVME_NS_DPS_PI_TYPE1:
360 case NVME_NS_DPS_PI_TYPE2:
361 control |= NVME_RW_PRINFO_PRCHK_GUARD |
362 NVME_RW_PRINFO_PRCHK_REF;
363 cmnd->rw.reftag = cpu_to_le32(
364 nvme_block_nr(ns, blk_rq_pos(req)));
365 break;
366 }
367 if (!blk_integrity_rq(req))
368 control |= NVME_RW_PRINFO_PRACT;
369 }
370
371 cmnd->rw.control = cpu_to_le16(control);
372 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
373}
374
375int nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
376 struct nvme_command *cmd)
377{
bac0000a 378 int ret = BLK_MQ_RQ_QUEUE_OK;
8093f7ca 379
987f699a 380 if (!(req->rq_flags & RQF_DONTPREP)) {
44e44b29 381 nvme_req(req)->retries = 0;
27fa9bc5 382 nvme_req(req)->flags = 0;
987f699a
CH		 383 req->rq_flags |= RQF_DONTPREP;
384 }
385
aebf526b
CH		 386 switch (req_op(req)) {
387 case REQ_OP_DRV_IN:
388 case REQ_OP_DRV_OUT:
d49187e9 389 memcpy(cmd, nvme_req(req)->cmd, sizeof(*cmd));
aebf526b
CH		 390 break;
391 case REQ_OP_FLUSH:
8093f7ca 392 nvme_setup_flush(ns, cmd);
aebf526b 393 break;
e850fd16
CH		 394 case REQ_OP_WRITE_ZEROES:
395 /* currently only aliased to deallocate for a few ctrls: */
aebf526b 396 case REQ_OP_DISCARD:
8093f7ca 397 ret = nvme_setup_discard(ns, req, cmd);
aebf526b
CH		 398 break;
399 case REQ_OP_READ:
400 case REQ_OP_WRITE:
8093f7ca 401 nvme_setup_rw(ns, req, cmd);
aebf526b
CH		 402 break;
403 default:
404 WARN_ON_ONCE(1);
405 return BLK_MQ_RQ_QUEUE_ERROR;
406 }
8093f7ca 407
721b3917 408 cmd->common.command_id = req->tag;
8093f7ca
ML		 409 return ret;
410}
411EXPORT_SYMBOL_GPL(nvme_setup_cmd);
412
4160982e
CH		 413/*
414 * Returns 0 on success. If the result is negative, it's a Linux error code;
415 * if the result is positive, it's an NVM Express status code
416 */
417int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 418 union nvme_result *result, void *buffer, unsigned bufflen,
eb71f435 419 unsigned timeout, int qid, int at_head, int flags)
4160982e
CH		 420{
421 struct request *req;
422 int ret;
423
eb71f435 424 req = nvme_alloc_request(q, cmd, flags, qid);
4160982e
CH		 425 if (IS_ERR(req))
426 return PTR_ERR(req);
427
428 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
429
21d34711
CH		 430 if (buffer && bufflen) {
431 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
432 if (ret)
433 goto out;
4160982e
CH		 434 }
435
eb71f435 436 blk_execute_rq(req->q, NULL, req, at_head);
d49187e9
CH		 437 if (result)
438 *result = nvme_req(req)->result;
27fa9bc5
CH		 439 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
440 ret = -EINTR;
441 else
442 ret = nvme_req(req)->status;
4160982e
CH		 443 out:
444 blk_mq_free_request(req);
445 return ret;
446}
eb71f435 447EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH		 448
449int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
450 void *buffer, unsigned bufflen)
451{
eb71f435
CH		 452 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 0,
453 NVME_QID_ANY, 0, 0);
4160982e 454}
576d55d6 455EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 456
0b7f1f26
KB		 457int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
458 void __user *ubuffer, unsigned bufflen,
459 void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
460 u32 *result, unsigned timeout)
4160982e 461{
7a5abb4b 462 bool write = nvme_is_write(cmd);
0b7f1f26
KB		 463 struct nvme_ns *ns = q->queuedata;
464 struct gendisk *disk = ns ? ns->disk : NULL;
4160982e 465 struct request *req;
0b7f1f26
KB		 466 struct bio *bio = NULL;
467 void *meta = NULL;
4160982e
CH		 468 int ret;
469
eb71f435 470 req = nvme_alloc_request(q, cmd, 0, NVME_QID_ANY);
4160982e
CH		 471 if (IS_ERR(req))
472 return PTR_ERR(req);
473
474 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
475
476 if (ubuffer && bufflen) {
21d34711
CH		 477 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
478 GFP_KERNEL);
479 if (ret)
480 goto out;
481 bio = req->bio;
21d34711 482
0b7f1f26
KB		 483 if (!disk)
484 goto submit;
485 bio->bi_bdev = bdget_disk(disk, 0);
486 if (!bio->bi_bdev) {
487 ret = -ENODEV;
488 goto out_unmap;
489 }
490
e9fc63d6 491 if (meta_buffer && meta_len) {
0b7f1f26
KB		 492 struct bio_integrity_payload *bip;
493
494 meta = kmalloc(meta_len, GFP_KERNEL);
495 if (!meta) {
496 ret = -ENOMEM;
497 goto out_unmap;
498 }
499
500 if (write) {
501 if (copy_from_user(meta, meta_buffer,
502 meta_len)) {
503 ret = -EFAULT;
504 goto out_free_meta;
505 }
506 }
507
508 bip = bio_integrity_alloc(bio, GFP_KERNEL, 1);
06c1e390
KB		 509 if (IS_ERR(bip)) {
510 ret = PTR_ERR(bip);
0b7f1f26
KB		 511 goto out_free_meta;
512 }
513
514 bip->bip_iter.bi_size = meta_len;
515 bip->bip_iter.bi_sector = meta_seed;
516
517 ret = bio_integrity_add_page(bio, virt_to_page(meta),
518 meta_len, offset_in_page(meta));
519 if (ret != meta_len) {
520 ret = -ENOMEM;
521 goto out_free_meta;
522 }
523 }
524 }
525 submit:
526 blk_execute_rq(req->q, disk, req, 0);
27fa9bc5
CH		 527 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
528 ret = -EINTR;
529 else
530 ret = nvme_req(req)->status;
21d34711 531 if (result)
d49187e9 532 *result = le32_to_cpu(nvme_req(req)->result.u32);
0b7f1f26
KB		 533 if (meta && !ret && !write) {
534 if (copy_to_user(meta_buffer, meta, meta_len))
535 ret = -EFAULT;
536 }
537 out_free_meta:
538 kfree(meta);
539 out_unmap:
540 if (bio) {
541 if (disk && bio->bi_bdev)
542 bdput(bio->bi_bdev);
543 blk_rq_unmap_user(bio);
544 }
21d34711
CH		 545 out:
546 blk_mq_free_request(req);
547 return ret;
548}
549
0b7f1f26
KB		 550int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
551 void __user *ubuffer, unsigned bufflen, u32 *result,
552 unsigned timeout)
553{
554 return __nvme_submit_user_cmd(q, cmd, ubuffer, bufflen, NULL, 0, 0,
555 result, timeout);
556}
557
038bd4cb
SG		 558static void nvme_keep_alive_end_io(struct request *rq, int error)
559{
560 struct nvme_ctrl *ctrl = rq->end_io_data;
561
562 blk_mq_free_request(rq);
563
564 if (error) {
565 dev_err(ctrl->device,
566 "failed nvme_keep_alive_end_io error=%d\n", error);
567 return;
568 }
569
570 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
571}
572
573static int nvme_keep_alive(struct nvme_ctrl *ctrl)
574{
575 struct nvme_command c;
576 struct request *rq;
577
578 memset(&c, 0, sizeof(c));
579 c.common.opcode = nvme_admin_keep_alive;
580
581 rq = nvme_alloc_request(ctrl->admin_q, &c, BLK_MQ_REQ_RESERVED,
582 NVME_QID_ANY);
583 if (IS_ERR(rq))
584 return PTR_ERR(rq);
585
586 rq->timeout = ctrl->kato * HZ;
587 rq->end_io_data = ctrl;
588
589 blk_execute_rq_nowait(rq->q, NULL, rq, 0, nvme_keep_alive_end_io);
590
591 return 0;
592}
593
594static void nvme_keep_alive_work(struct work_struct *work)
595{
596 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
597 struct nvme_ctrl, ka_work);
598
599 if (nvme_keep_alive(ctrl)) {
600 /* allocation failure, reset the controller */
601 dev_err(ctrl->device, "keep-alive failed\n");
602 ctrl->ops->reset_ctrl(ctrl);
603 return;
604 }
605}
606
607void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
608{
609 if (unlikely(ctrl->kato == 0))
610 return;
611
612 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
613 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
614}
615EXPORT_SYMBOL_GPL(nvme_start_keep_alive);
616
617void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
618{
619 if (unlikely(ctrl->kato == 0))
620 return;
621
622 cancel_delayed_work_sync(&ctrl->ka_work);
623}
624EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
625
1c63dc66 626int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH		 627{
628 struct nvme_command c = { };
629 int error;
630
631 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
632 c.identify.opcode = nvme_admin_identify;
986994a2 633 c.identify.cns = NVME_ID_CNS_CTRL;
21d34711
CH		 634
635 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
636 if (!*id)
637 return -ENOMEM;
638
639 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
640 sizeof(struct nvme_id_ctrl));
641 if (error)
642 kfree(*id);
643 return error;
644}
645
540c801c
KB		 646static int nvme_identify_ns_list(struct nvme_ctrl *dev, unsigned nsid, __le32 *ns_list)
647{
648 struct nvme_command c = { };
649
650 c.identify.opcode = nvme_admin_identify;
986994a2 651 c.identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST;
540c801c
KB		 652 c.identify.nsid = cpu_to_le32(nsid);
653 return nvme_submit_sync_cmd(dev->admin_q, &c, ns_list, 0x1000);
654}
655
1c63dc66 656int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
21d34711
CH		 657 struct nvme_id_ns **id)
658{
659 struct nvme_command c = { };
660 int error;
661
662 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
778f067c
MG		 663 c.identify.opcode = nvme_admin_identify;
664 c.identify.nsid = cpu_to_le32(nsid);
986994a2 665 c.identify.cns = NVME_ID_CNS_NS;
21d34711
CH		 666
667 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
668 if (!*id)
669 return -ENOMEM;
670
671 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
672 sizeof(struct nvme_id_ns));
673 if (error)
674 kfree(*id);
675 return error;
676}
677
1c63dc66 678int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
1a6fe74d 679 void *buffer, size_t buflen, u32 *result)
21d34711
CH		 680{
681 struct nvme_command c;
d49187e9 682 union nvme_result res;
1cb3cce5 683 int ret;
21d34711
CH		 684
685 memset(&c, 0, sizeof(c));
686 c.features.opcode = nvme_admin_get_features;
687 c.features.nsid = cpu_to_le32(nsid);
21d34711
CH		 688 c.features.fid = cpu_to_le32(fid);
689
d49187e9 690 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res, buffer, buflen, 0,
eb71f435 691 NVME_QID_ANY, 0, 0);
9b47f77a 692 if (ret >= 0 && result)
d49187e9 693 *result = le32_to_cpu(res.u32);
1cb3cce5 694 return ret;
21d34711
CH		 695}
696
1c63dc66 697int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
1a6fe74d 698 void *buffer, size_t buflen, u32 *result)
21d34711
CH		 699{
700 struct nvme_command c;
d49187e9 701 union nvme_result res;
1cb3cce5 702 int ret;
21d34711
CH		 703
704 memset(&c, 0, sizeof(c));
705 c.features.opcode = nvme_admin_set_features;
21d34711
CH		 706 c.features.fid = cpu_to_le32(fid);
707 c.features.dword11 = cpu_to_le32(dword11);
708
d49187e9 709 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
1a6fe74d 710 buffer, buflen, 0, NVME_QID_ANY, 0, 0);
9b47f77a 711 if (ret >= 0 && result)
d49187e9 712 *result = le32_to_cpu(res.u32);
1cb3cce5 713 return ret;
21d34711
CH		 714}
715
1c63dc66 716int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log)
21d34711
CH		 717{
718 struct nvme_command c = { };
719 int error;
720
721 c.common.opcode = nvme_admin_get_log_page,
722 c.common.nsid = cpu_to_le32(0xFFFFFFFF),
723 c.common.cdw10[0] = cpu_to_le32(
724 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
725 NVME_LOG_SMART),
726
727 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
728 if (!*log)
729 return -ENOMEM;
730
731 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
732 sizeof(struct nvme_smart_log));
733 if (error)
734 kfree(*log);
735 return error;
736}
1673f1f0 737
9a0be7ab
CH		 738int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
739{
740 u32 q_count = (*count - 1) | ((*count - 1) << 16);
741 u32 result;
742 int status, nr_io_queues;
743
1a6fe74d 744 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 745 &result);
f5fa90dc 746 if (status < 0)
9a0be7ab
CH		 747 return status;
748
f5fa90dc
CH		 749 /*
750 * Degraded controllers might return an error when setting the queue
751 * count. We still want to be able to bring them online and offer
752 * access to the admin queue, as that might be only way to fix them up.
753 */
754 if (status > 0) {
755 dev_err(ctrl->dev, "Could not set queue count (%d)\n", status);
756 *count = 0;
757 } else {
758 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
759 *count = min(*count, nr_io_queues);
760 }
761
9a0be7ab
CH		 762 return 0;
763}
576d55d6 764EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 765
1673f1f0
CH		 766static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
767{
768 struct nvme_user_io io;
769 struct nvme_command c;
770 unsigned length, meta_len;
771 void __user *metadata;
772
773 if (copy_from_user(&io, uio, sizeof(io)))
774 return -EFAULT;
63088ec7
KB		 775 if (io.flags)
776 return -EINVAL;
1673f1f0
CH		 777
778 switch (io.opcode) {
779 case nvme_cmd_write:
780 case nvme_cmd_read:
781 case nvme_cmd_compare:
782 break;
783 default:
784 return -EINVAL;
785 }
786
787 length = (io.nblocks + 1) << ns->lba_shift;
788 meta_len = (io.nblocks + 1) * ns->ms;
789 metadata = (void __user *)(uintptr_t)io.metadata;
790
791 if (ns->ext) {
792 length += meta_len;
793 meta_len = 0;
794 } else if (meta_len) {
795 if ((io.metadata & 3) || !io.metadata)
796 return -EINVAL;
797 }
798
799 memset(&c, 0, sizeof(c));
800 c.rw.opcode = io.opcode;
801 c.rw.flags = io.flags;
802 c.rw.nsid = cpu_to_le32(ns->ns_id);
803 c.rw.slba = cpu_to_le64(io.slba);
804 c.rw.length = cpu_to_le16(io.nblocks);
805 c.rw.control = cpu_to_le16(io.control);
806 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
807 c.rw.reftag = cpu_to_le32(io.reftag);
808 c.rw.apptag = cpu_to_le16(io.apptag);
809 c.rw.appmask = cpu_to_le16(io.appmask);
810
811 return __nvme_submit_user_cmd(ns->queue, &c,
812 (void __user *)(uintptr_t)io.addr, length,
813 metadata, meta_len, io.slba, NULL, 0);
814}
815
f3ca80fc 816static int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1673f1f0
CH		 817 struct nvme_passthru_cmd __user *ucmd)
818{
819 struct nvme_passthru_cmd cmd;
820 struct nvme_command c;
821 unsigned timeout = 0;
822 int status;
823
824 if (!capable(CAP_SYS_ADMIN))
825 return -EACCES;
826 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
827 return -EFAULT;
63088ec7
KB		 828 if (cmd.flags)
829 return -EINVAL;
1673f1f0
CH		 830
831 memset(&c, 0, sizeof(c));
832 c.common.opcode = cmd.opcode;
833 c.common.flags = cmd.flags;
834 c.common.nsid = cpu_to_le32(cmd.nsid);
835 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
836 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
837 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
838 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
839 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
840 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
841 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
842 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
843
844 if (cmd.timeout_ms)
845 timeout = msecs_to_jiffies(cmd.timeout_ms);
846
847 status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c,
d1ea7be5 848 (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
1673f1f0
CH		 849 &cmd.result, timeout);
850 if (status >= 0) {
851 if (put_user(cmd.result, &ucmd->result))
852 return -EFAULT;
853 }
854
855 return status;
856}
857
858static int nvme_ioctl(struct block_device *bdev, fmode_t mode,
859 unsigned int cmd, unsigned long arg)
860{
861 struct nvme_ns *ns = bdev->bd_disk->private_data;
862
863 switch (cmd) {
864 case NVME_IOCTL_ID:
865 force_successful_syscall_return();
866 return ns->ns_id;
867 case NVME_IOCTL_ADMIN_CMD:
868 return nvme_user_cmd(ns->ctrl, NULL, (void __user *)arg);
869 case NVME_IOCTL_IO_CMD:
870 return nvme_user_cmd(ns->ctrl, ns, (void __user *)arg);
871 case NVME_IOCTL_SUBMIT_IO:
872 return nvme_submit_io(ns, (void __user *)arg);
44907332 873#ifdef CONFIG_BLK_DEV_NVME_SCSI
1673f1f0
CH		 874 case SG_GET_VERSION_NUM:
875 return nvme_sg_get_version_num((void __user *)arg);
876 case SG_IO:
877 return nvme_sg_io(ns, (void __user *)arg);
44907332 878#endif
1673f1f0 879 default:
84d4add7
MB		 880#ifdef CONFIG_NVM
881 if (ns->ndev)
882 return nvme_nvm_ioctl(ns, cmd, arg);
883#endif
a98e58e5 884 if (is_sed_ioctl(cmd))
4f1244c8 885 return sed_ioctl(ns->ctrl->opal_dev, cmd,
e225c20e 886 (void __user *) arg);
1673f1f0
CH		 887 return -ENOTTY;
888 }
889}
890
891#ifdef CONFIG_COMPAT
892static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
893 unsigned int cmd, unsigned long arg)
894{
895 switch (cmd) {
896 case SG_IO:
897 return -ENOIOCTLCMD;
898 }
899 return nvme_ioctl(bdev, mode, cmd, arg);
900}
901#else
902#define nvme_compat_ioctl NULL
903#endif
904
905static int nvme_open(struct block_device *bdev, fmode_t mode)
906{
907 return nvme_get_ns_from_disk(bdev->bd_disk) ? 0 : -ENXIO;
908}
909
910static void nvme_release(struct gendisk *disk, fmode_t mode)
911{
e439bb12
SG		 912 struct nvme_ns *ns = disk->private_data;
913
914 module_put(ns->ctrl->ops->module);
915 nvme_put_ns(ns);
1673f1f0
CH		 916}
917
918static int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
919{
920 /* some standard values */
921 geo->heads = 1 << 6;
922 geo->sectors = 1 << 5;
923 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
924 return 0;
925}
926
927#ifdef CONFIG_BLK_DEV_INTEGRITY
c81bfba9
CH		 928static void nvme_prep_integrity(struct gendisk *disk, struct nvme_id_ns *id,
929 u16 bs)
930{
931 struct nvme_ns *ns = disk->private_data;
932 u16 old_ms = ns->ms;
933 u8 pi_type = 0;
934
935 ns->ms = le16_to_cpu(id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ms);
936 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
937
938 /* PI implementation requires metadata equal t10 pi tuple size */
939 if (ns->ms == sizeof(struct t10_pi_tuple))
940 pi_type = id->dps & NVME_NS_DPS_PI_MASK;
941
942 if (blk_get_integrity(disk) &&
943 (ns->pi_type != pi_type || ns->ms != old_ms ||
944 bs != queue_logical_block_size(disk->queue) ||
945 (ns->ms && ns->ext)))
946 blk_integrity_unregister(disk);
947
948 ns->pi_type = pi_type;
949}
950
1673f1f0
CH		 951static void nvme_init_integrity(struct nvme_ns *ns)
952{
953 struct blk_integrity integrity;
954
fa9a89fc 955 memset(&integrity, 0, sizeof(integrity));
1673f1f0
CH		 956 switch (ns->pi_type) {
957 case NVME_NS_DPS_PI_TYPE3:
958 integrity.profile = &t10_pi_type3_crc;
ba36c21b
NB		 959 integrity.tag_size = sizeof(u16) + sizeof(u32);
960 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 961 break;
962 case NVME_NS_DPS_PI_TYPE1:
963 case NVME_NS_DPS_PI_TYPE2:
964 integrity.profile = &t10_pi_type1_crc;
ba36c21b
NB		 965 integrity.tag_size = sizeof(u16);
966 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 967 break;
968 default:
969 integrity.profile = NULL;
970 break;
971 }
972 integrity.tuple_size = ns->ms;
973 blk_integrity_register(ns->disk, &integrity);
974 blk_queue_max_integrity_segments(ns->queue, 1);
975}
976#else
c81bfba9
CH		 977static void nvme_prep_integrity(struct gendisk *disk, struct nvme_id_ns *id,
978 u16 bs)
979{
980}
1673f1f0
CH		 981static void nvme_init_integrity(struct nvme_ns *ns)
982{
983}
984#endif /* CONFIG_BLK_DEV_INTEGRITY */
985
986static void nvme_config_discard(struct nvme_ns *ns)
987{
08095e70 988 struct nvme_ctrl *ctrl = ns->ctrl;
1673f1f0 989 u32 logical_block_size = queue_logical_block_size(ns->queue);
08095e70 990
b35ba01e
CH		 991 BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) <
992 NVME_DSM_MAX_RANGES);
993
1673f1f0
CH		 994 ns->queue->limits.discard_alignment = logical_block_size;
995 ns->queue->limits.discard_granularity = logical_block_size;
bd0fc288 996 blk_queue_max_discard_sectors(ns->queue, UINT_MAX);
b35ba01e 997 blk_queue_max_discard_segments(ns->queue, NVME_DSM_MAX_RANGES);
1673f1f0 998 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
e850fd16
CH		 999
1000 if (ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
1001 blk_queue_max_write_zeroes_sectors(ns->queue, UINT_MAX);
1673f1f0
CH		 1002}
1003
ac81bfa9 1004static int nvme_revalidate_ns(struct nvme_ns *ns, struct nvme_id_ns **id)
1673f1f0 1005{
ac81bfa9 1006 if (nvme_identify_ns(ns->ctrl, ns->ns_id, id)) {
b0b4e09c 1007 dev_warn(ns->ctrl->dev, "%s: Identify failure\n", __func__);
1673f1f0
CH		 1008 return -ENODEV;
1009 }
1673f1f0 1010
ac81bfa9
MB		 1011 if ((*id)->ncap == 0) {
1012 kfree(*id);
1013 return -ENODEV;
1673f1f0
CH		 1014 }
1015
8ef2074d 1016 if (ns->ctrl->vs >= NVME_VS(1, 1, 0))
ac81bfa9 1017 memcpy(ns->eui, (*id)->eui64, sizeof(ns->eui));
8ef2074d 1018 if (ns->ctrl->vs >= NVME_VS(1, 2, 0))
ac81bfa9
MB		 1019 memcpy(ns->uuid, (*id)->nguid, sizeof(ns->uuid));
1020
1021 return 0;
1022}
1023
1024static void __nvme_revalidate_disk(struct gendisk *disk, struct nvme_id_ns *id)
1025{
1026 struct nvme_ns *ns = disk->private_data;
c81bfba9 1027 u16 bs;
1673f1f0
CH		 1028
1029 /*
1030 * If identify namespace failed, use default 512 byte block size so
1031 * block layer can use before failing read/write for 0 capacity.
1032 */
c81bfba9 1033 ns->lba_shift = id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ds;
1673f1f0
CH		 1034 if (ns->lba_shift == 0)
1035 ns->lba_shift = 9;
1036 bs = 1 << ns->lba_shift;
1673f1f0
CH		 1037
1038 blk_mq_freeze_queue(disk->queue);
1673f1f0 1039
c81bfba9
CH		 1040 if (ns->ctrl->ops->flags & NVME_F_METADATA_SUPPORTED)
1041 nvme_prep_integrity(disk, id, bs);
1673f1f0 1042 blk_queue_logical_block_size(ns->queue, bs);
4b9d5b15 1043 if (ns->ms && !blk_get_integrity(disk) && !ns->ext)
1673f1f0 1044 nvme_init_integrity(ns);
1673f1f0
CH		 1045 if (ns->ms && !(ns->ms == 8 && ns->pi_type) && !blk_get_integrity(disk))
1046 set_capacity(disk, 0);
1047 else
1048 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1049
1050 if (ns->ctrl->oncs & NVME_CTRL_ONCS_DSM)
1051 nvme_config_discard(ns);
1052 blk_mq_unfreeze_queue(disk->queue);
ac81bfa9 1053}
1673f1f0 1054
ac81bfa9
MB		 1055static int nvme_revalidate_disk(struct gendisk *disk)
1056{
1057 struct nvme_ns *ns = disk->private_data;
1058 struct nvme_id_ns *id = NULL;
1059 int ret;
1060
1061 if (test_bit(NVME_NS_DEAD, &ns->flags)) {
1062 set_capacity(disk, 0);
1063 return -ENODEV;
1064 }
1065
1066 ret = nvme_revalidate_ns(ns, &id);
1067 if (ret)
1068 return ret;
1069
1070 __nvme_revalidate_disk(disk, id);
1673f1f0 1071 kfree(id);
ac81bfa9 1072
1673f1f0
CH		 1073 return 0;
1074}
1075
1076static char nvme_pr_type(enum pr_type type)
1077{
1078 switch (type) {
1079 case PR_WRITE_EXCLUSIVE:
1080 return 1;
1081 case PR_EXCLUSIVE_ACCESS:
1082 return 2;
1083 case PR_WRITE_EXCLUSIVE_REG_ONLY:
1084 return 3;
1085 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
1086 return 4;
1087 case PR_WRITE_EXCLUSIVE_ALL_REGS:
1088 return 5;
1089 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
1090 return 6;
1091 default:
1092 return 0;
1093 }
1094};
1095
1096static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
1097 u64 key, u64 sa_key, u8 op)
1098{
1099 struct nvme_ns *ns = bdev->bd_disk->private_data;
1100 struct nvme_command c;
1101 u8 data[16] = { 0, };
1102
1103 put_unaligned_le64(key, &data[0]);
1104 put_unaligned_le64(sa_key, &data[8]);
1105
1106 memset(&c, 0, sizeof(c));
1107 c.common.opcode = op;
1108 c.common.nsid = cpu_to_le32(ns->ns_id);
1109 c.common.cdw10[0] = cpu_to_le32(cdw10);
1110
1111 return nvme_submit_sync_cmd(ns->queue, &c, data, 16);
1112}
1113
1114static int nvme_pr_register(struct block_device *bdev, u64 old,
1115 u64 new, unsigned flags)
1116{
1117 u32 cdw10;
1118
1119 if (flags & ~PR_FL_IGNORE_KEY)
1120 return -EOPNOTSUPP;
1121
1122 cdw10 = old ? 2 : 0;
1123 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
1124 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
1125 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
1126}
1127
1128static int nvme_pr_reserve(struct block_device *bdev, u64 key,
1129 enum pr_type type, unsigned flags)
1130{
1131 u32 cdw10;
1132
1133 if (flags & ~PR_FL_IGNORE_KEY)
1134 return -EOPNOTSUPP;
1135
1136 cdw10 = nvme_pr_type(type) << 8;
1137 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
1138 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
1139}
1140
1141static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
1142 enum pr_type type, bool abort)
1143{
1144 u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
1145 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
1146}
1147
1148static int nvme_pr_clear(struct block_device *bdev, u64 key)
1149{
8c0b3915 1150 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
1673f1f0
CH		 1151 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
1152}
1153
1154static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
1155{
1156 u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
1157 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
1158}
1159
1160static const struct pr_ops nvme_pr_ops = {
1161 .pr_register = nvme_pr_register,
1162 .pr_reserve = nvme_pr_reserve,
1163 .pr_release = nvme_pr_release,
1164 .pr_preempt = nvme_pr_preempt,
1165 .pr_clear = nvme_pr_clear,
1166};
1167
a98e58e5 1168#ifdef CONFIG_BLK_SED_OPAL
4f1244c8
CH		 1169int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
1170 bool send)
a98e58e5 1171{
4f1244c8 1172 struct nvme_ctrl *ctrl = data;
a98e58e5 1173 struct nvme_command cmd;
a98e58e5
SB		 1174
1175 memset(&cmd, 0, sizeof(cmd));
1176 if (send)
1177 cmd.common.opcode = nvme_admin_security_send;
1178 else
1179 cmd.common.opcode = nvme_admin_security_recv;
a98e58e5
SB		 1180 cmd.common.nsid = 0;
1181 cmd.common.cdw10[0] = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
1182 cmd.common.cdw10[1] = cpu_to_le32(len);
1183
1184 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len,
1185 ADMIN_TIMEOUT, NVME_QID_ANY, 1, 0);
1186}
1187EXPORT_SYMBOL_GPL(nvme_sec_submit);
1188#endif /* CONFIG_BLK_SED_OPAL */
1189
5bae7f73 1190static const struct block_device_operations nvme_fops = {
1673f1f0
CH		 1191 .owner = THIS_MODULE,
1192 .ioctl = nvme_ioctl,
1193 .compat_ioctl = nvme_compat_ioctl,
1194 .open = nvme_open,
1195 .release = nvme_release,
1196 .getgeo = nvme_getgeo,
1197 .revalidate_disk= nvme_revalidate_disk,
1198 .pr_ops = &nvme_pr_ops,
1199};
1200
5fd4ce1b
CH		 1201static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
1202{
1203 unsigned long timeout =
1204 ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1205 u32 csts, bit = enabled ? NVME_CSTS_RDY : 0;
1206 int ret;
1207
1208 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB		 1209 if (csts == ~0)
1210 return -ENODEV;
5fd4ce1b
CH		 1211 if ((csts & NVME_CSTS_RDY) == bit)
1212 break;
1213
1214 msleep(100);
1215 if (fatal_signal_pending(current))
1216 return -EINTR;
1217 if (time_after(jiffies, timeout)) {
1b3c47c1 1218 dev_err(ctrl->device,
5fd4ce1b
CH		 1219 "Device not ready; aborting %s\n", enabled ?
1220 "initialisation" : "reset");
1221 return -ENODEV;
1222 }
1223 }
1224
1225 return ret;
1226}
1227
1228/*
1229 * If the device has been passed off to us in an enabled state, just clear
1230 * the enabled bit. The spec says we should set the 'shutdown notification
1231 * bits', but doing so may cause the device to complete commands to the
1232 * admin queue ... and we don't know what memory that might be pointing at!
1233 */
1234int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1235{
1236 int ret;
1237
1238 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1239 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
1240
1241 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1242 if (ret)
1243 return ret;
54adc010 1244
b5a10c5f 1245 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010
GP		 1246 msleep(NVME_QUIRK_DELAY_AMOUNT);
1247
5fd4ce1b
CH		 1248 return nvme_wait_ready(ctrl, cap, false);
1249}
576d55d6 1250EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b
CH		 1251
1252int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1253{
1254 /*
1255 * Default to a 4K page size, with the intention to update this
1256 * path in the future to accomodate architectures with differing
1257 * kernel and IO page sizes.
1258 */
1259 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12, page_shift = 12;
1260 int ret;
1261
1262 if (page_shift < dev_page_min) {
1b3c47c1 1263 dev_err(ctrl->device,
5fd4ce1b
CH		 1264 "Minimum device page size %u too large for host (%u)\n",
1265 1 << dev_page_min, 1 << page_shift);
1266 return -ENODEV;
1267 }
1268
1269 ctrl->page_size = 1 << page_shift;
1270
1271 ctrl->ctrl_config = NVME_CC_CSS_NVM;
1272 ctrl->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1273 ctrl->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1274 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1275 ctrl->ctrl_config |= NVME_CC_ENABLE;
1276
1277 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1278 if (ret)
1279 return ret;
1280 return nvme_wait_ready(ctrl, cap, true);
1281}
576d55d6 1282EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b
CH		 1283
1284int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl)
1285{
1286 unsigned long timeout = SHUTDOWN_TIMEOUT + jiffies;
1287 u32 csts;
1288 int ret;
1289
1290 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1291 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
1292
1293 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1294 if (ret)
1295 return ret;
1296
1297 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
1298 if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_CMPLT)
1299 break;
1300
1301 msleep(100);
1302 if (fatal_signal_pending(current))
1303 return -EINTR;
1304 if (time_after(jiffies, timeout)) {
1b3c47c1 1305 dev_err(ctrl->device,
5fd4ce1b
CH		 1306 "Device shutdown incomplete; abort shutdown\n");
1307 return -ENODEV;
1308 }
1309 }
1310
1311 return ret;
1312}
576d55d6 1313EXPORT_SYMBOL_GPL(nvme_shutdown_ctrl);
5fd4ce1b 1314
da35825d
CH		 1315static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
1316 struct request_queue *q)
1317{
7c88cb00
JA		 1318 bool vwc = false;
1319
da35825d 1320 if (ctrl->max_hw_sectors) {
45686b61
CH		 1321 u32 max_segments =
1322 (ctrl->max_hw_sectors / (ctrl->page_size >> 9)) + 1;
1323
da35825d 1324 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
45686b61 1325 blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
da35825d 1326 }
e6282aef
KB		 1327 if (ctrl->quirks & NVME_QUIRK_STRIPE_SIZE)
1328 blk_queue_chunk_sectors(q, ctrl->max_hw_sectors);
da35825d 1329 blk_queue_virt_boundary(q, ctrl->page_size - 1);
7c88cb00
JA		 1330 if (ctrl->vwc & NVME_CTRL_VWC_PRESENT)
1331 vwc = true;
1332 blk_queue_write_cache(q, vwc, vwc);
da35825d
CH		 1333}
1334
c5552fde
AL		 1335static void nvme_configure_apst(struct nvme_ctrl *ctrl)
1336{
1337 /*
1338 * APST (Autonomous Power State Transition) lets us program a
1339 * table of power state transitions that the controller will
1340 * perform automatically. We configure it with a simple
1341 * heuristic: we are willing to spend at most 2% of the time
1342 * transitioning between power states. Therefore, when running
1343 * in any given state, we will enter the next lower-power
76e4ad09 1344 * non-operational state after waiting 50 * (enlat + exlat)
c5552fde
AL		 1345 * microseconds, as long as that state's total latency is under
1346 * the requested maximum latency.
1347 *
1348 * We will not autonomously enter any non-operational state for
1349 * which the total latency exceeds ps_max_latency_us. Users
1350 * can set ps_max_latency_us to zero to turn off APST.
1351 */
1352
1353 unsigned apste;
1354 struct nvme_feat_auto_pst *table;
fb0dc399
AL		 1355 u64 max_lat_us = 0;
1356 int max_ps = -1;
c5552fde
AL		 1357 int ret;
1358
1359 /*
1360 * If APST isn't supported or if we haven't been initialized yet,
1361 * then don't do anything.
1362 */
1363 if (!ctrl->apsta)
1364 return;
1365
1366 if (ctrl->npss > 31) {
1367 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
1368 return;
1369 }
1370
1371 table = kzalloc(sizeof(*table), GFP_KERNEL);
1372 if (!table)
1373 return;
1374
1375 if (ctrl->ps_max_latency_us == 0) {
1376 /* Turn off APST. */
1377 apste = 0;
fb0dc399 1378 dev_dbg(ctrl->device, "APST disabled\n");
c5552fde
AL		 1379 } else {
1380 __le64 target = cpu_to_le64(0);
1381 int state;
1382
1383 /*
1384 * Walk through all states from lowest- to highest-power.
1385 * According to the spec, lower-numbered states use more
1386 * power. NPSS, despite the name, is the index of the
1387 * lowest-power state, not the number of states.
1388 */
1389 for (state = (int)ctrl->npss; state >= 0; state--) {
1390 u64 total_latency_us, transition_ms;
1391
1392 if (target)
1393 table->entries[state] = target;
1394
ff5350a8
AL		 1395 /*
1396 * Don't allow transitions to the deepest state
1397 * if it's quirked off.
1398 */
1399 if (state == ctrl->npss &&
1400 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
1401 continue;
1402
c5552fde
AL		 1403 /*
1404 * Is this state a useful non-operational state for
1405 * higher-power states to autonomously transition to?
1406 */
1407 if (!(ctrl->psd[state].flags &
1408 NVME_PS_FLAGS_NON_OP_STATE))
1409 continue;
1410
1411 total_latency_us =
1412 (u64)le32_to_cpu(ctrl->psd[state].entry_lat) +
1413 + le32_to_cpu(ctrl->psd[state].exit_lat);
1414 if (total_latency_us > ctrl->ps_max_latency_us)
1415 continue;
1416
1417 /*
1418 * This state is good. Use it as the APST idle
1419 * target for higher power states.
1420 */
1421 transition_ms = total_latency_us + 19;
1422 do_div(transition_ms, 20);
1423 if (transition_ms > (1 << 24) - 1)
1424 transition_ms = (1 << 24) - 1;
1425
1426 target = cpu_to_le64((state << 3) |
1427 (transition_ms << 8));
fb0dc399
AL		 1428
1429 if (max_ps == -1)
1430 max_ps = state;
1431
1432 if (total_latency_us > max_lat_us)
1433 max_lat_us = total_latency_us;
c5552fde
AL		 1434 }
1435
1436 apste = 1;
fb0dc399
AL		 1437
1438 if (max_ps == -1) {
1439 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n");
1440 } else {
1441 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n",
1442 max_ps, max_lat_us, (int)sizeof(*table), table);
1443 }
c5552fde
AL		 1444 }
1445
1446 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
1447 table, sizeof(*table), NULL);
1448 if (ret)
1449 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
1450
1451 kfree(table);
1452}
1453
1454static void nvme_set_latency_tolerance(struct device *dev, s32 val)
1455{
1456 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1457 u64 latency;
1458
1459 switch (val) {
1460 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
1461 case PM_QOS_LATENCY_ANY:
1462 latency = U64_MAX;
1463 break;
1464
1465 default:
1466 latency = val;
1467 }
1468
1469 if (ctrl->ps_max_latency_us != latency) {
1470 ctrl->ps_max_latency_us = latency;
1471 nvme_configure_apst(ctrl);
1472 }
1473}
1474
bd4da3ab
AL		 1475struct nvme_core_quirk_entry {
1476 /*
1477 * NVMe model and firmware strings are padded with spaces. For
1478 * simplicity, strings in the quirk table are padded with NULLs
1479 * instead.
1480 */
1481 u16 vid;
1482 const char *mn;
1483 const char *fr;
1484 unsigned long quirks;
1485};
1486
1487static const struct nvme_core_quirk_entry core_quirks[] = {
c5552fde 1488 {
be56945c
AL		 1489 /*
1490 * This Toshiba device seems to die using any APST states. See:
1491 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
1492 */
1493 .vid = 0x1179,
1494 .mn = "THNSF5256GPUK TOSHIBA",
c5552fde 1495 .quirks = NVME_QUIRK_NO_APST,
be56945c 1496 }
bd4da3ab
AL		 1497};
1498
1499/* match is null-terminated but idstr is space-padded. */
1500static bool string_matches(const char *idstr, const char *match, size_t len)
1501{
1502 size_t matchlen;
1503
1504 if (!match)
1505 return true;
1506
1507 matchlen = strlen(match);
1508 WARN_ON_ONCE(matchlen > len);
1509
1510 if (memcmp(idstr, match, matchlen))
1511 return false;
1512
1513 for (; matchlen < len; matchlen++)
1514 if (idstr[matchlen] != ' ')
1515 return false;
1516
1517 return true;
1518}
1519
1520static bool quirk_matches(const struct nvme_id_ctrl *id,
1521 const struct nvme_core_quirk_entry *q)
1522{
1523 return q->vid == le16_to_cpu(id->vid) &&
1524 string_matches(id->mn, q->mn, sizeof(id->mn)) &&
1525 string_matches(id->fr, q->fr, sizeof(id->fr));
1526}
1527
7fd8930f
CH		 1528/*
1529 * Initialize the cached copies of the Identify data and various controller
1530 * register in our nvme_ctrl structure. This should be called as soon as
1531 * the admin queue is fully up and running.
1532 */
1533int nvme_init_identify(struct nvme_ctrl *ctrl)
1534{
1535 struct nvme_id_ctrl *id;
1536 u64 cap;
1537 int ret, page_shift;
a229dbf6 1538 u32 max_hw_sectors;
c5552fde 1539 u8 prev_apsta;
7fd8930f 1540
f3ca80fc
CH		 1541 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
1542 if (ret) {
1b3c47c1 1543 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
f3ca80fc
CH		 1544 return ret;
1545 }
1546
7fd8930f
CH		 1547 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &cap);
1548 if (ret) {
1b3c47c1 1549 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
7fd8930f
CH		 1550 return ret;
1551 }
1552 page_shift = NVME_CAP_MPSMIN(cap) + 12;
1553
8ef2074d 1554 if (ctrl->vs >= NVME_VS(1, 1, 0))
f3ca80fc
CH		 1555 ctrl->subsystem = NVME_CAP_NSSRC(cap);
1556
7fd8930f
CH		 1557 ret = nvme_identify_ctrl(ctrl, &id);
1558 if (ret) {
1b3c47c1 1559 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH		 1560 return -EIO;
1561 }
1562
bd4da3ab
AL		 1563 if (!ctrl->identified) {
1564 /*
1565 * Check for quirks. Quirk can depend on firmware version,
1566 * so, in principle, the set of quirks present can change
1567 * across a reset. As a possible future enhancement, we
1568 * could re-scan for quirks every time we reinitialize
1569 * the device, but we'd have to make sure that the driver
1570 * behaves intelligently if the quirks change.
1571 */
1572
1573 int i;
1574
1575 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
1576 if (quirk_matches(id, &core_quirks[i]))
1577 ctrl->quirks |= core_quirks[i].quirks;
1578 }
1579 }
1580
c35e30b4
AL		 1581 if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) {
1582 dev_warn(ctrl->dev, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n");
1583 ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS;
1584 }
1585
8a9ae523 1586 ctrl->oacs = le16_to_cpu(id->oacs);
118472ab 1587 ctrl->vid = le16_to_cpu(id->vid);
7fd8930f 1588 ctrl->oncs = le16_to_cpup(&id->oncs);
6bf25d16 1589 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 1590 ctrl->vwc = id->vwc;
931e1c22 1591 ctrl->cntlid = le16_to_cpup(&id->cntlid);
7fd8930f
CH		 1592 memcpy(ctrl->serial, id->sn, sizeof(id->sn));
1593 memcpy(ctrl->model, id->mn, sizeof(id->mn));
1594 memcpy(ctrl->firmware_rev, id->fr, sizeof(id->fr));
1595 if (id->mdts)
a229dbf6 1596 max_hw_sectors = 1 << (id->mdts + page_shift - 9);
7fd8930f 1597 else
a229dbf6
CH		 1598 max_hw_sectors = UINT_MAX;
1599 ctrl->max_hw_sectors =
1600 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 1601
da35825d 1602 nvme_set_queue_limits(ctrl, ctrl->admin_q);
07bfcd09 1603 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 1604 ctrl->kas = le16_to_cpu(id->kas);
07bfcd09 1605
c5552fde
AL		 1606 ctrl->npss = id->npss;
1607 prev_apsta = ctrl->apsta;
c35e30b4
AL		 1608 if (ctrl->quirks & NVME_QUIRK_NO_APST) {
1609 if (force_apst && id->apsta) {
1610 dev_warn(ctrl->dev, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n");
1611 ctrl->apsta = 1;
1612 } else {
1613 ctrl->apsta = 0;
1614 }
1615 } else {
1616 ctrl->apsta = id->apsta;
1617 }
c5552fde
AL		 1618 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
1619
d3d5b87d 1620 if (ctrl->ops->flags & NVME_F_FABRICS) {
07bfcd09
CH		 1621 ctrl->icdoff = le16_to_cpu(id->icdoff);
1622 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
1623 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
1624 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
1625
1626 /*
1627 * In fabrics we need to verify the cntlid matches the
1628 * admin connect
1629 */
1630 if (ctrl->cntlid != le16_to_cpu(id->cntlid))
1631 ret = -EINVAL;
038bd4cb
SG		 1632
1633 if (!ctrl->opts->discovery_nqn && !ctrl->kas) {
1634 dev_err(ctrl->dev,
1635 "keep-alive support is mandatory for fabrics\n");
1636 ret = -EINVAL;
1637 }
07bfcd09
CH		 1638 } else {
1639 ctrl->cntlid = le16_to_cpu(id->cntlid);
1640 }
da35825d 1641
7fd8930f 1642 kfree(id);
bd4da3ab 1643
c5552fde
AL		 1644 if (ctrl->apsta && !prev_apsta)
1645 dev_pm_qos_expose_latency_tolerance(ctrl->device);
1646 else if (!ctrl->apsta && prev_apsta)
1647 dev_pm_qos_hide_latency_tolerance(ctrl->device);
1648
1649 nvme_configure_apst(ctrl);
1650
bd4da3ab 1651 ctrl->identified = true;
c5552fde 1652
07bfcd09 1653 return ret;
7fd8930f 1654}
576d55d6 1655EXPORT_SYMBOL_GPL(nvme_init_identify);
7fd8930f 1656
f3ca80fc 1657static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 1658{
f3ca80fc
CH		 1659 struct nvme_ctrl *ctrl;
1660 int instance = iminor(inode);
1661 int ret = -ENODEV;
1673f1f0 1662
f3ca80fc
CH		 1663 spin_lock(&dev_list_lock);
1664 list_for_each_entry(ctrl, &nvme_ctrl_list, node) {
1665 if (ctrl->instance != instance)
1666 continue;
1667
1668 if (!ctrl->admin_q) {
1669 ret = -EWOULDBLOCK;
1670 break;
1671 }
1672 if (!kref_get_unless_zero(&ctrl->kref))
1673 break;
1674 file->private_data = ctrl;
1675 ret = 0;
1676 break;
1677 }
1678 spin_unlock(&dev_list_lock);
1679
1680 return ret;
1673f1f0
CH		 1681}
1682
f3ca80fc 1683static int nvme_dev_release(struct inode *inode, struct file *file)
1673f1f0 1684{
f3ca80fc
CH		 1685 nvme_put_ctrl(file->private_data);
1686 return 0;
1687}
1688
bfd89471
CH		 1689static int nvme_dev_user_cmd(struct nvme_ctrl *ctrl, void __user *argp)
1690{
1691 struct nvme_ns *ns;
1692 int ret;
1693
1694 mutex_lock(&ctrl->namespaces_mutex);
1695 if (list_empty(&ctrl->namespaces)) {
1696 ret = -ENOTTY;
1697 goto out_unlock;
1698 }
1699
1700 ns = list_first_entry(&ctrl->namespaces, struct nvme_ns, list);
1701 if (ns != list_last_entry(&ctrl->namespaces, struct nvme_ns, list)) {
1b3c47c1 1702 dev_warn(ctrl->device,
bfd89471
CH		 1703 "NVME_IOCTL_IO_CMD not supported when multiple namespaces present!\n");
1704 ret = -EINVAL;
1705 goto out_unlock;
1706 }
1707
1b3c47c1 1708 dev_warn(ctrl->device,
bfd89471
CH		 1709 "using deprecated NVME_IOCTL_IO_CMD ioctl on the char device!\n");
1710 kref_get(&ns->kref);
1711 mutex_unlock(&ctrl->namespaces_mutex);
1712
1713 ret = nvme_user_cmd(ctrl, ns, argp);
1714 nvme_put_ns(ns);
1715 return ret;
1716
1717out_unlock:
1718 mutex_unlock(&ctrl->namespaces_mutex);
1719 return ret;
1720}
1721
f3ca80fc
CH		 1722static long nvme_dev_ioctl(struct file *file, unsigned int cmd,
1723 unsigned long arg)
1724{
1725 struct nvme_ctrl *ctrl = file->private_data;
1726 void __user *argp = (void __user *)arg;
f3ca80fc
CH		 1727
1728 switch (cmd) {
1729 case NVME_IOCTL_ADMIN_CMD:
1730 return nvme_user_cmd(ctrl, NULL, argp);
1731 case NVME_IOCTL_IO_CMD:
bfd89471 1732 return nvme_dev_user_cmd(ctrl, argp);
f3ca80fc 1733 case NVME_IOCTL_RESET:
1b3c47c1 1734 dev_warn(ctrl->device, "resetting controller\n");
f3ca80fc
CH		 1735 return ctrl->ops->reset_ctrl(ctrl);
1736 case NVME_IOCTL_SUBSYS_RESET:
1737 return nvme_reset_subsystem(ctrl);
9ec3bb2f
KB		 1738 case NVME_IOCTL_RESCAN:
1739 nvme_queue_scan(ctrl);
1740 return 0;
f3ca80fc
CH		 1741 default:
1742 return -ENOTTY;
1743 }
1744}
1745
1746static const struct file_operations nvme_dev_fops = {
1747 .owner = THIS_MODULE,
1748 .open = nvme_dev_open,
1749 .release = nvme_dev_release,
1750 .unlocked_ioctl = nvme_dev_ioctl,
1751 .compat_ioctl = nvme_dev_ioctl,
1752};
1753
1754static ssize_t nvme_sysfs_reset(struct device *dev,
1755 struct device_attribute *attr, const char *buf,
1756 size_t count)
1757{
1758 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1759 int ret;
1760
1761 ret = ctrl->ops->reset_ctrl(ctrl);
1762 if (ret < 0)
1763 return ret;
1764 return count;
1673f1f0 1765}
f3ca80fc 1766static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
1673f1f0 1767
9ec3bb2f
KB		 1768static ssize_t nvme_sysfs_rescan(struct device *dev,
1769 struct device_attribute *attr, const char *buf,
1770 size_t count)
1771{
1772 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1773
1774 nvme_queue_scan(ctrl);
1775 return count;
1776}
1777static DEVICE_ATTR(rescan_controller, S_IWUSR, NULL, nvme_sysfs_rescan);
1778
118472ab
KB		 1779static ssize_t wwid_show(struct device *dev, struct device_attribute *attr,
1780 char *buf)
1781{
40267efd 1782 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
118472ab
KB		 1783 struct nvme_ctrl *ctrl = ns->ctrl;
1784 int serial_len = sizeof(ctrl->serial);
1785 int model_len = sizeof(ctrl->model);
1786
1787 if (memchr_inv(ns->uuid, 0, sizeof(ns->uuid)))
1788 return sprintf(buf, "eui.%16phN\n", ns->uuid);
1789
1790 if (memchr_inv(ns->eui, 0, sizeof(ns->eui)))
1791 return sprintf(buf, "eui.%8phN\n", ns->eui);
1792
1793 while (ctrl->serial[serial_len - 1] == ' ')
1794 serial_len--;
1795 while (ctrl->model[model_len - 1] == ' ')
1796 model_len--;
1797
1798 return sprintf(buf, "nvme.%04x-%*phN-%*phN-%08x\n", ctrl->vid,
1799 serial_len, ctrl->serial, model_len, ctrl->model, ns->ns_id);
1800}
1801static DEVICE_ATTR(wwid, S_IRUGO, wwid_show, NULL);
1802
2b9b6e86
KB		 1803static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,
1804 char *buf)
1805{
40267efd 1806 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 1807 return sprintf(buf, "%pU\n", ns->uuid);
1808}
1809static DEVICE_ATTR(uuid, S_IRUGO, uuid_show, NULL);
1810
1811static ssize_t eui_show(struct device *dev, struct device_attribute *attr,
1812 char *buf)
1813{
40267efd 1814 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 1815 return sprintf(buf, "%8phd\n", ns->eui);
1816}
1817static DEVICE_ATTR(eui, S_IRUGO, eui_show, NULL);
1818
1819static ssize_t nsid_show(struct device *dev, struct device_attribute *attr,
1820 char *buf)
1821{
40267efd 1822 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 1823 return sprintf(buf, "%d\n", ns->ns_id);
1824}
1825static DEVICE_ATTR(nsid, S_IRUGO, nsid_show, NULL);
1826
1827static struct attribute *nvme_ns_attrs[] = {
118472ab 1828 &dev_attr_wwid.attr,
2b9b6e86
KB		 1829 &dev_attr_uuid.attr,
1830 &dev_attr_eui.attr,
1831 &dev_attr_nsid.attr,
1832 NULL,
1833};
1834
1a353d85 1835static umode_t nvme_ns_attrs_are_visible(struct kobject *kobj,
2b9b6e86
KB		 1836 struct attribute *a, int n)
1837{
1838 struct device *dev = container_of(kobj, struct device, kobj);
40267efd 1839 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 1840
1841 if (a == &dev_attr_uuid.attr) {
1842 if (!memchr_inv(ns->uuid, 0, sizeof(ns->uuid)))
1843 return 0;
1844 }
1845 if (a == &dev_attr_eui.attr) {
1846 if (!memchr_inv(ns->eui, 0, sizeof(ns->eui)))
1847 return 0;
1848 }
1849 return a->mode;
1850}
1851
1852static const struct attribute_group nvme_ns_attr_group = {
1853 .attrs = nvme_ns_attrs,
1a353d85 1854 .is_visible = nvme_ns_attrs_are_visible,
2b9b6e86
KB		 1855};
1856
931e1c22 1857#define nvme_show_str_function(field) \
779ff756
KB		 1858static ssize_t field##_show(struct device *dev, \
1859 struct device_attribute *attr, char *buf) \
1860{ \
1861 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
1862 return sprintf(buf, "%.*s\n", (int)sizeof(ctrl->field), ctrl->field); \
1863} \
1864static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
1865
931e1c22
ML		 1866#define nvme_show_int_function(field) \
1867static ssize_t field##_show(struct device *dev, \
1868 struct device_attribute *attr, char *buf) \
1869{ \
1870 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
1871 return sprintf(buf, "%d\n", ctrl->field); \
1872} \
1873static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
1874
1875nvme_show_str_function(model);
1876nvme_show_str_function(serial);
1877nvme_show_str_function(firmware_rev);
1878nvme_show_int_function(cntlid);
779ff756 1879
1a353d85
ML		 1880static ssize_t nvme_sysfs_delete(struct device *dev,
1881 struct device_attribute *attr, const char *buf,
1882 size_t count)
1883{
1884 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1885
1886 if (device_remove_file_self(dev, attr))
1887 ctrl->ops->delete_ctrl(ctrl);
1888 return count;
1889}
1890static DEVICE_ATTR(delete_controller, S_IWUSR, NULL, nvme_sysfs_delete);
1891
1892static ssize_t nvme_sysfs_show_transport(struct device *dev,
1893 struct device_attribute *attr,
1894 char *buf)
1895{
1896 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1897
1898 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->ops->name);
1899}
1900static DEVICE_ATTR(transport, S_IRUGO, nvme_sysfs_show_transport, NULL);
1901
8432bdb2
SG		 1902static ssize_t nvme_sysfs_show_state(struct device *dev,
1903 struct device_attribute *attr,
1904 char *buf)
1905{
1906 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1907 static const char *const state_name[] = {
1908 [NVME_CTRL_NEW] = "new",
1909 [NVME_CTRL_LIVE] = "live",
1910 [NVME_CTRL_RESETTING] = "resetting",
1911 [NVME_CTRL_RECONNECTING]= "reconnecting",
1912 [NVME_CTRL_DELETING] = "deleting",
1913 [NVME_CTRL_DEAD] = "dead",
1914 };
1915
1916 if ((unsigned)ctrl->state < ARRAY_SIZE(state_name) &&
1917 state_name[ctrl->state])
1918 return sprintf(buf, "%s\n", state_name[ctrl->state]);
1919
1920 return sprintf(buf, "unknown state\n");
1921}
1922
1923static DEVICE_ATTR(state, S_IRUGO, nvme_sysfs_show_state, NULL);
1924
1a353d85
ML		 1925static ssize_t nvme_sysfs_show_subsysnqn(struct device *dev,
1926 struct device_attribute *attr,
1927 char *buf)
1928{
1929 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1930
1931 return snprintf(buf, PAGE_SIZE, "%s\n",
1932 ctrl->ops->get_subsysnqn(ctrl));
1933}
1934static DEVICE_ATTR(subsysnqn, S_IRUGO, nvme_sysfs_show_subsysnqn, NULL);
1935
1936static ssize_t nvme_sysfs_show_address(struct device *dev,
1937 struct device_attribute *attr,
1938 char *buf)
1939{
1940 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1941
1942 return ctrl->ops->get_address(ctrl, buf, PAGE_SIZE);
1943}
1944static DEVICE_ATTR(address, S_IRUGO, nvme_sysfs_show_address, NULL);
1945
779ff756
KB		 1946static struct attribute *nvme_dev_attrs[] = {
1947 &dev_attr_reset_controller.attr,
9ec3bb2f 1948 &dev_attr_rescan_controller.attr,
779ff756
KB		 1949 &dev_attr_model.attr,
1950 &dev_attr_serial.attr,
1951 &dev_attr_firmware_rev.attr,
931e1c22 1952 &dev_attr_cntlid.attr,
1a353d85
ML		 1953 &dev_attr_delete_controller.attr,
1954 &dev_attr_transport.attr,
1955 &dev_attr_subsysnqn.attr,
1956 &dev_attr_address.attr,
8432bdb2 1957 &dev_attr_state.attr,
779ff756
KB		 1958 NULL
1959};
1960
1a353d85
ML		 1961#define CHECK_ATTR(ctrl, a, name) \
1962 if ((a) == &dev_attr_##name.attr && \
1963 !(ctrl)->ops->get_##name) \
1964 return 0
1965
1966static umode_t nvme_dev_attrs_are_visible(struct kobject *kobj,
1967 struct attribute *a, int n)
1968{
1969 struct device *dev = container_of(kobj, struct device, kobj);
1970 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1971
1972 if (a == &dev_attr_delete_controller.attr) {
1973 if (!ctrl->ops->delete_ctrl)
1974 return 0;
1975 }
1976
1977 CHECK_ATTR(ctrl, a, subsysnqn);
1978 CHECK_ATTR(ctrl, a, address);
1979
1980 return a->mode;
1981}
1982
779ff756 1983static struct attribute_group nvme_dev_attrs_group = {
1a353d85
ML		 1984 .attrs = nvme_dev_attrs,
1985 .is_visible = nvme_dev_attrs_are_visible,
779ff756
KB		 1986};
1987
1988static const struct attribute_group *nvme_dev_attr_groups[] = {
1989 &nvme_dev_attrs_group,
1990 NULL,
1991};
1992
5bae7f73
CH		 1993static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
1994{
1995 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
1996 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
1997
1998 return nsa->ns_id - nsb->ns_id;
1999}
2000
32f0c4af 2001static struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 2002{
32f0c4af 2003 struct nvme_ns *ns, *ret = NULL;
69d3b8ac 2004
32f0c4af 2005 mutex_lock(&ctrl->namespaces_mutex);
5bae7f73 2006 list_for_each_entry(ns, &ctrl->namespaces, list) {
32f0c4af
KB		 2007 if (ns->ns_id == nsid) {
2008 kref_get(&ns->kref);
2009 ret = ns;
2010 break;
2011 }
5bae7f73
CH		 2012 if (ns->ns_id > nsid)
2013 break;
2014 }
32f0c4af
KB		 2015 mutex_unlock(&ctrl->namespaces_mutex);
2016 return ret;
5bae7f73
CH		 2017}
2018
2019static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
2020{
2021 struct nvme_ns *ns;
2022 struct gendisk *disk;
ac81bfa9
MB		 2023 struct nvme_id_ns *id;
2024 char disk_name[DISK_NAME_LEN];
5bae7f73
CH		 2025 int node = dev_to_node(ctrl->dev);
2026
2027 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
2028 if (!ns)
2029 return;
2030
075790eb
KB		 2031 ns->instance = ida_simple_get(&ctrl->ns_ida, 1, 0, GFP_KERNEL);
2032 if (ns->instance < 0)
2033 goto out_free_ns;
2034
5bae7f73
CH		 2035 ns->queue = blk_mq_init_queue(ctrl->tagset);
2036 if (IS_ERR(ns->queue))
075790eb 2037 goto out_release_instance;
5bae7f73
CH		 2038 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
2039 ns->queue->queuedata = ns;
2040 ns->ctrl = ctrl;
2041
5bae7f73
CH		 2042 kref_init(&ns->kref);
2043 ns->ns_id = nsid;
5bae7f73 2044 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
5bae7f73
CH		 2045
2046 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
da35825d 2047 nvme_set_queue_limits(ctrl, ns->queue);
5bae7f73 2048
ac81bfa9 2049 sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->instance);
5bae7f73 2050
ac81bfa9
MB		 2051 if (nvme_revalidate_ns(ns, &id))
2052 goto out_free_queue;
2053
3dc87dd0
MB		 2054 if (nvme_nvm_ns_supported(ns, id) &&
2055 nvme_nvm_register(ns, disk_name, node)) {
2056 dev_warn(ctrl->dev, "%s: LightNVM init failure\n", __func__);
2057 goto out_free_id;
2058 }
ac81bfa9 2059
3dc87dd0
MB		 2060 disk = alloc_disk_node(0, node);
2061 if (!disk)
2062 goto out_free_id;
ac81bfa9 2063
3dc87dd0
MB		 2064 disk->fops = &nvme_fops;
2065 disk->private_data = ns;
2066 disk->queue = ns->queue;
2067 disk->flags = GENHD_FL_EXT_DEVT;
2068 memcpy(disk->disk_name, disk_name, DISK_NAME_LEN);
2069 ns->disk = disk;
2070
2071 __nvme_revalidate_disk(disk, id);
5bae7f73 2072
32f0c4af
KB		 2073 mutex_lock(&ctrl->namespaces_mutex);
2074 list_add_tail(&ns->list, &ctrl->namespaces);
2075 mutex_unlock(&ctrl->namespaces_mutex);
2076
5bae7f73 2077 kref_get(&ctrl->kref);
ac81bfa9
MB		 2078
2079 kfree(id);
2080
0d52c756 2081 device_add_disk(ctrl->device, ns->disk);
2b9b6e86
KB		 2082 if (sysfs_create_group(&disk_to_dev(ns->disk)->kobj,
2083 &nvme_ns_attr_group))
2084 pr_warn("%s: failed to create sysfs group for identification\n",
2085 ns->disk->disk_name);
3dc87dd0
MB		 2086 if (ns->ndev && nvme_nvm_register_sysfs(ns))
2087 pr_warn("%s: failed to register lightnvm sysfs group for identification\n",
2088 ns->disk->disk_name);
5bae7f73 2089 return;
ac81bfa9
MB		 2090 out_free_id:
2091 kfree(id);
5bae7f73
CH		 2092 out_free_queue:
2093 blk_cleanup_queue(ns->queue);
075790eb
KB		 2094 out_release_instance:
2095 ida_simple_remove(&ctrl->ns_ida, ns->instance);
5bae7f73
CH		 2096 out_free_ns:
2097 kfree(ns);
2098}
2099
2100static void nvme_ns_remove(struct nvme_ns *ns)
2101{
646017a6
KB		 2102 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
2103 return;
69d3b8ac 2104
b0b4e09c 2105 if (ns->disk && ns->disk->flags & GENHD_FL_UP) {
5bae7f73
CH		 2106 if (blk_get_integrity(ns->disk))
2107 blk_integrity_unregister(ns->disk);
2b9b6e86
KB		 2108 sysfs_remove_group(&disk_to_dev(ns->disk)->kobj,
2109 &nvme_ns_attr_group);
3dc87dd0
MB		 2110 if (ns->ndev)
2111 nvme_nvm_unregister_sysfs(ns);
5bae7f73 2112 del_gendisk(ns->disk);
5bae7f73
CH		 2113 blk_cleanup_queue(ns->queue);
2114 }
32f0c4af
KB		 2115
2116 mutex_lock(&ns->ctrl->namespaces_mutex);
5bae7f73 2117 list_del_init(&ns->list);
32f0c4af
KB		 2118 mutex_unlock(&ns->ctrl->namespaces_mutex);
2119
5bae7f73
CH		 2120 nvme_put_ns(ns);
2121}
2122
540c801c
KB		 2123static void nvme_validate_ns(struct nvme_ctrl *ctrl, unsigned nsid)
2124{
2125 struct nvme_ns *ns;
2126
32f0c4af 2127 ns = nvme_find_get_ns(ctrl, nsid);
540c801c 2128 if (ns) {
b0b4e09c 2129 if (ns->disk && revalidate_disk(ns->disk))
540c801c 2130 nvme_ns_remove(ns);
32f0c4af 2131 nvme_put_ns(ns);
540c801c
KB		 2132 } else
2133 nvme_alloc_ns(ctrl, nsid);
2134}
2135
47b0e50a
SB		 2136static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
2137 unsigned nsid)
2138{
2139 struct nvme_ns *ns, *next;
2140
2141 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
2142 if (ns->ns_id > nsid)
2143 nvme_ns_remove(ns);
2144 }
2145}
2146
540c801c
KB		 2147static int nvme_scan_ns_list(struct nvme_ctrl *ctrl, unsigned nn)
2148{
2149 struct nvme_ns *ns;
2150 __le32 *ns_list;
2151 unsigned i, j, nsid, prev = 0, num_lists = DIV_ROUND_UP(nn, 1024);
2152 int ret = 0;
2153
2154 ns_list = kzalloc(0x1000, GFP_KERNEL);
2155 if (!ns_list)
2156 return -ENOMEM;
2157
2158 for (i = 0; i < num_lists; i++) {
2159 ret = nvme_identify_ns_list(ctrl, prev, ns_list);
2160 if (ret)
47b0e50a 2161 goto free;
540c801c
KB		 2162
2163 for (j = 0; j < min(nn, 1024U); j++) {
2164 nsid = le32_to_cpu(ns_list[j]);
2165 if (!nsid)
2166 goto out;
2167
2168 nvme_validate_ns(ctrl, nsid);
2169
2170 while (++prev < nsid) {
32f0c4af
KB		 2171 ns = nvme_find_get_ns(ctrl, prev);
2172 if (ns) {
540c801c 2173 nvme_ns_remove(ns);
32f0c4af
KB		 2174 nvme_put_ns(ns);
2175 }
540c801c
KB		 2176 }
2177 }
2178 nn -= j;
2179 }
2180 out:
47b0e50a
SB		 2181 nvme_remove_invalid_namespaces(ctrl, prev);
2182 free:
540c801c
KB		 2183 kfree(ns_list);
2184 return ret;
2185}
2186
5955be21 2187static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl, unsigned nn)
5bae7f73 2188{
5bae7f73
CH		 2189 unsigned i;
2190
540c801c
KB		 2191 for (i = 1; i <= nn; i++)
2192 nvme_validate_ns(ctrl, i);
2193
47b0e50a 2194 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH		 2195}
2196
5955be21 2197static void nvme_scan_work(struct work_struct *work)
5bae7f73 2198{
5955be21
CH		 2199 struct nvme_ctrl *ctrl =
2200 container_of(work, struct nvme_ctrl, scan_work);
5bae7f73 2201 struct nvme_id_ctrl *id;
540c801c 2202 unsigned nn;
5bae7f73 2203
5955be21
CH		 2204 if (ctrl->state != NVME_CTRL_LIVE)
2205 return;
2206
5bae7f73
CH		 2207 if (nvme_identify_ctrl(ctrl, &id))
2208 return;
540c801c
KB		 2209
2210 nn = le32_to_cpu(id->nn);
8ef2074d 2211 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
540c801c
KB		 2212 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
2213 if (!nvme_scan_ns_list(ctrl, nn))
2214 goto done;
2215 }
5955be21 2216 nvme_scan_ns_sequential(ctrl, nn);
540c801c 2217 done:
32f0c4af 2218 mutex_lock(&ctrl->namespaces_mutex);
540c801c 2219 list_sort(NULL, &ctrl->namespaces, ns_cmp);
69d3b8ac 2220 mutex_unlock(&ctrl->namespaces_mutex);
5bae7f73
CH		 2221 kfree(id);
2222}
5955be21
CH		 2223
2224void nvme_queue_scan(struct nvme_ctrl *ctrl)
2225{
2226 /*
2227 * Do not queue new scan work when a controller is reset during
2228 * removal.
2229 */
2230 if (ctrl->state == NVME_CTRL_LIVE)
2231 schedule_work(&ctrl->scan_work);
2232}
2233EXPORT_SYMBOL_GPL(nvme_queue_scan);
5bae7f73 2234
32f0c4af
KB		 2235/*
2236 * This function iterates the namespace list unlocked to allow recovery from
2237 * controller failure. It is up to the caller to ensure the namespace list is
2238 * not modified by scan work while this function is executing.
2239 */
5bae7f73
CH		 2240void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
2241{
2242 struct nvme_ns *ns, *next;
2243
0ff9d4e1
KB		 2244 /*
2245 * The dead states indicates the controller was not gracefully
2246 * disconnected. In that case, we won't be able to flush any data while
2247 * removing the namespaces' disks; fail all the queues now to avoid
2248 * potentially having to clean up the failed sync later.
2249 */
2250 if (ctrl->state == NVME_CTRL_DEAD)
2251 nvme_kill_queues(ctrl);
2252
5bae7f73
CH		 2253 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list)
2254 nvme_ns_remove(ns);
2255}
576d55d6 2256EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 2257
f866fc42
CH		 2258static void nvme_async_event_work(struct work_struct *work)
2259{
2260 struct nvme_ctrl *ctrl =
2261 container_of(work, struct nvme_ctrl, async_event_work);
2262
2263 spin_lock_irq(&ctrl->lock);
2264 while (ctrl->event_limit > 0) {
2265 int aer_idx = --ctrl->event_limit;
2266
2267 spin_unlock_irq(&ctrl->lock);
2268 ctrl->ops->submit_async_event(ctrl, aer_idx);
2269 spin_lock_irq(&ctrl->lock);
2270 }
2271 spin_unlock_irq(&ctrl->lock);
2272}
2273
7bf58533
CH		 2274void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
2275 union nvme_result *res)
f866fc42 2276{
7bf58533
CH		 2277 u32 result = le32_to_cpu(res->u32);
2278 bool done = true;
f866fc42 2279
7bf58533
CH		 2280 switch (le16_to_cpu(status) >> 1) {
2281 case NVME_SC_SUCCESS:
2282 done = false;
2283 /*FALLTHRU*/
2284 case NVME_SC_ABORT_REQ:
f866fc42
CH		 2285 ++ctrl->event_limit;
2286 schedule_work(&ctrl->async_event_work);
7bf58533
CH		 2287 break;
2288 default:
2289 break;
f866fc42
CH		 2290 }
2291
7bf58533 2292 if (done)
f866fc42
CH		 2293 return;
2294
2295 switch (result & 0xff07) {
2296 case NVME_AER_NOTICE_NS_CHANGED:
2297 dev_info(ctrl->device, "rescanning\n");
2298 nvme_queue_scan(ctrl);
2299 break;
2300 default:
2301 dev_warn(ctrl->device, "async event result %08x\n", result);
2302 }
2303}
2304EXPORT_SYMBOL_GPL(nvme_complete_async_event);
2305
2306void nvme_queue_async_events(struct nvme_ctrl *ctrl)
2307{
2308 ctrl->event_limit = NVME_NR_AERS;
2309 schedule_work(&ctrl->async_event_work);
2310}
2311EXPORT_SYMBOL_GPL(nvme_queue_async_events);
2312
f3ca80fc
CH		 2313static DEFINE_IDA(nvme_instance_ida);
2314
2315static int nvme_set_instance(struct nvme_ctrl *ctrl)
2316{
2317 int instance, error;
2318
2319 do {
2320 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2321 return -ENODEV;
2322
2323 spin_lock(&dev_list_lock);
2324 error = ida_get_new(&nvme_instance_ida, &instance);
2325 spin_unlock(&dev_list_lock);
2326 } while (error == -EAGAIN);
2327
2328 if (error)
2329 return -ENODEV;
2330
2331 ctrl->instance = instance;
2332 return 0;
2333}
2334
2335static void nvme_release_instance(struct nvme_ctrl *ctrl)
2336{
2337 spin_lock(&dev_list_lock);
2338 ida_remove(&nvme_instance_ida, ctrl->instance);
2339 spin_unlock(&dev_list_lock);
2340}
2341
53029b04 2342void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
576d55d6 2343{
f866fc42 2344 flush_work(&ctrl->async_event_work);
5955be21
CH		 2345 flush_work(&ctrl->scan_work);
2346 nvme_remove_namespaces(ctrl);
2347
53029b04 2348 device_destroy(nvme_class, MKDEV(nvme_char_major, ctrl->instance));
f3ca80fc
CH		 2349
2350 spin_lock(&dev_list_lock);
2351 list_del(&ctrl->node);
2352 spin_unlock(&dev_list_lock);
53029b04 2353}
576d55d6 2354EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04
KB		 2355
2356static void nvme_free_ctrl(struct kref *kref)
2357{
2358 struct nvme_ctrl *ctrl = container_of(kref, struct nvme_ctrl, kref);
f3ca80fc
CH		 2359
2360 put_device(ctrl->device);
2361 nvme_release_instance(ctrl);
075790eb 2362 ida_destroy(&ctrl->ns_ida);
f3ca80fc
CH		 2363
2364 ctrl->ops->free_ctrl(ctrl);
2365}
2366
2367void nvme_put_ctrl(struct nvme_ctrl *ctrl)
2368{
2369 kref_put(&ctrl->kref, nvme_free_ctrl);
2370}
576d55d6 2371EXPORT_SYMBOL_GPL(nvme_put_ctrl);
f3ca80fc
CH		 2372
2373/*
2374 * Initialize a NVMe controller structures. This needs to be called during
2375 * earliest initialization so that we have the initialized structured around
2376 * during probing.
2377 */
2378int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
2379 const struct nvme_ctrl_ops *ops, unsigned long quirks)
2380{
2381 int ret;
2382
bb8d261e
CH		 2383 ctrl->state = NVME_CTRL_NEW;
2384 spin_lock_init(&ctrl->lock);
f3ca80fc 2385 INIT_LIST_HEAD(&ctrl->namespaces);
69d3b8ac 2386 mutex_init(&ctrl->namespaces_mutex);
f3ca80fc
CH		 2387 kref_init(&ctrl->kref);
2388 ctrl->dev = dev;
2389 ctrl->ops = ops;
2390 ctrl->quirks = quirks;
5955be21 2391 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 2392 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
f3ca80fc
CH		 2393
2394 ret = nvme_set_instance(ctrl);
2395 if (ret)
2396 goto out;
2397
779ff756 2398 ctrl->device = device_create_with_groups(nvme_class, ctrl->dev,
f3ca80fc 2399 MKDEV(nvme_char_major, ctrl->instance),
f4f0f63e 2400 ctrl, nvme_dev_attr_groups,
779ff756 2401 "nvme%d", ctrl->instance);
f3ca80fc
CH		 2402 if (IS_ERR(ctrl->device)) {
2403 ret = PTR_ERR(ctrl->device);
2404 goto out_release_instance;
2405 }
2406 get_device(ctrl->device);
075790eb 2407 ida_init(&ctrl->ns_ida);
f3ca80fc 2408
f3ca80fc
CH		 2409 spin_lock(&dev_list_lock);
2410 list_add_tail(&ctrl->node, &nvme_ctrl_list);
2411 spin_unlock(&dev_list_lock);
2412
c5552fde
AL		 2413 /*
2414 * Initialize latency tolerance controls. The sysfs files won't
2415 * be visible to userspace unless the device actually supports APST.
2416 */
2417 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
2418 dev_pm_qos_update_user_latency_tolerance(ctrl->device,
2419 min(default_ps_max_latency_us, (unsigned long)S32_MAX));
2420
f3ca80fc 2421 return 0;
f3ca80fc
CH		 2422out_release_instance:
2423 nvme_release_instance(ctrl);
2424out:
2425 return ret;
2426}
576d55d6 2427EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 2428
69d9a99c
KB		 2429/**
2430 * nvme_kill_queues(): Ends all namespace queues
2431 * @ctrl: the dead controller that needs to end
2432 *
2433 * Call this function when the driver determines it is unable to get the
2434 * controller in a state capable of servicing IO.
2435 */
2436void nvme_kill_queues(struct nvme_ctrl *ctrl)
2437{
2438 struct nvme_ns *ns;
2439
32f0c4af
KB		 2440 mutex_lock(&ctrl->namespaces_mutex);
2441 list_for_each_entry(ns, &ctrl->namespaces, list) {
69d9a99c
KB		 2442 /*
2443 * Revalidating a dead namespace sets capacity to 0. This will
2444 * end buffered writers dirtying pages that can't be synced.
2445 */
f33447b9
KB		 2446 if (!ns->disk || test_and_set_bit(NVME_NS_DEAD, &ns->flags))
2447 continue;
2448 revalidate_disk(ns->disk);
69d9a99c 2449 blk_set_queue_dying(ns->queue);
806f026f
ML		 2450
2451 /*
2452 * Forcibly start all queues to avoid having stuck requests.
2453 * Note that we must ensure the queues are not stopped
2454 * when the final removal happens.
2455 */
2456 blk_mq_start_hw_queues(ns->queue);
986f75c8
ML		 2457
2458 /* draining requests in requeue list */
2459 blk_mq_kick_requeue_list(ns->queue);
69d9a99c 2460 }
32f0c4af 2461 mutex_unlock(&ctrl->namespaces_mutex);
69d9a99c 2462}
237045fc 2463EXPORT_SYMBOL_GPL(nvme_kill_queues);
69d9a99c 2464
302ad8cc
KB		 2465void nvme_unfreeze(struct nvme_ctrl *ctrl)
2466{
2467 struct nvme_ns *ns;
2468
2469 mutex_lock(&ctrl->namespaces_mutex);
2470 list_for_each_entry(ns, &ctrl->namespaces, list)
2471 blk_mq_unfreeze_queue(ns->queue);
2472 mutex_unlock(&ctrl->namespaces_mutex);
2473}
2474EXPORT_SYMBOL_GPL(nvme_unfreeze);
2475
2476void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout)
2477{
2478 struct nvme_ns *ns;
2479
2480 mutex_lock(&ctrl->namespaces_mutex);
2481 list_for_each_entry(ns, &ctrl->namespaces, list) {
2482 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout);
2483 if (timeout <= 0)
2484 break;
2485 }
2486 mutex_unlock(&ctrl->namespaces_mutex);
2487}
2488EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout);
2489
2490void nvme_wait_freeze(struct nvme_ctrl *ctrl)
2491{
2492 struct nvme_ns *ns;
2493
2494 mutex_lock(&ctrl->namespaces_mutex);
2495 list_for_each_entry(ns, &ctrl->namespaces, list)
2496 blk_mq_freeze_queue_wait(ns->queue);
2497 mutex_unlock(&ctrl->namespaces_mutex);
2498}
2499EXPORT_SYMBOL_GPL(nvme_wait_freeze);
2500
2501void nvme_start_freeze(struct nvme_ctrl *ctrl)
2502{
2503 struct nvme_ns *ns;
2504
2505 mutex_lock(&ctrl->namespaces_mutex);
2506 list_for_each_entry(ns, &ctrl->namespaces, list)
1671d522 2507 blk_freeze_queue_start(ns->queue);
302ad8cc
KB		 2508 mutex_unlock(&ctrl->namespaces_mutex);
2509}
2510EXPORT_SYMBOL_GPL(nvme_start_freeze);
2511
25646264 2512void nvme_stop_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 2513{
2514 struct nvme_ns *ns;
2515
32f0c4af 2516 mutex_lock(&ctrl->namespaces_mutex);
a6eaa884 2517 list_for_each_entry(ns, &ctrl->namespaces, list)
3174dd33 2518 blk_mq_quiesce_queue(ns->queue);
32f0c4af 2519 mutex_unlock(&ctrl->namespaces_mutex);
363c9aac 2520}
576d55d6 2521EXPORT_SYMBOL_GPL(nvme_stop_queues);
363c9aac 2522
25646264 2523void nvme_start_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 2524{
2525 struct nvme_ns *ns;
2526
32f0c4af
KB		 2527 mutex_lock(&ctrl->namespaces_mutex);
2528 list_for_each_entry(ns, &ctrl->namespaces, list) {
363c9aac
SG		 2529 blk_mq_start_stopped_hw_queues(ns->queue, true);
2530 blk_mq_kick_requeue_list(ns->queue);
2531 }
32f0c4af 2532 mutex_unlock(&ctrl->namespaces_mutex);
363c9aac 2533}
576d55d6 2534EXPORT_SYMBOL_GPL(nvme_start_queues);
363c9aac 2535
5bae7f73
CH		 2536int __init nvme_core_init(void)
2537{
2538 int result;
2539
f3ca80fc
CH		 2540 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
2541 &nvme_dev_fops);
2542 if (result < 0)
b09dcf58 2543 return result;
f3ca80fc
CH		 2544 else if (result > 0)
2545 nvme_char_major = result;
2546
2547 nvme_class = class_create(THIS_MODULE, "nvme");
2548 if (IS_ERR(nvme_class)) {
2549 result = PTR_ERR(nvme_class);
2550 goto unregister_chrdev;
2551 }
2552
5bae7f73 2553 return 0;
f3ca80fc
CH		 2554
2555 unregister_chrdev:
2556 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
f3ca80fc 2557 return result;
5bae7f73
CH		 2558}
2559
2560void nvme_core_exit(void)
2561{
f3ca80fc
CH		 2562 class_destroy(nvme_class);
2563 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
5bae7f73 2564}
576d55d6
ML		 2565
2566MODULE_LICENSE("GPL");
2567MODULE_VERSION("1.0");
2568module_init(nvme_core_init);
2569module_exit(nvme_core_exit);
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