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nvme: remove the GENHD_FL_UP check in nvme_ns_remove
[mirror_ubuntu-jammy-kernel.git] / drivers / nvme / host / core.c
CommitLineData
bc50ad75 1// SPDX-License-Identifier: GPL-2.0
21d34711
CH
2/*
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
21d34711
CH
5 */
6
7#include <linux/blkdev.h>
8#include <linux/blk-mq.h>
c95b708d 9#include <linux/compat.h>
5fd4ce1b 10#include <linux/delay.h>
21d34711 11#include <linux/errno.h>
1673f1f0 12#include <linux/hdreg.h>
21d34711 13#include <linux/kernel.h>
5bae7f73 14#include <linux/module.h>
958f2a0f 15#include <linux/backing-dev.h>
5bae7f73 16#include <linux/list_sort.h>
21d34711
CH
17#include <linux/slab.h>
18#include <linux/types.h>
1673f1f0
CH
19#include <linux/pr.h>
20#include <linux/ptrace.h>
21#include <linux/nvme_ioctl.h>
c5552fde 22#include <linux/pm_qos.h>
1673f1f0 23#include <asm/unaligned.h>
21d34711
CH
24
25#include "nvme.h"
038bd4cb 26#include "fabrics.h"
21d34711 27
35fe0d12
HR
28#define CREATE_TRACE_POINTS
29#include "trace.h"
30
f3ca80fc
CH
31#define NVME_MINORS (1U << MINORBITS)
32
8ae4e447
MO
33unsigned int admin_timeout = 60;
34module_param(admin_timeout, uint, 0644);
ba0ba7d3 35MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 36EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3 37
8ae4e447
MO
38unsigned int nvme_io_timeout = 30;
39module_param_named(io_timeout, nvme_io_timeout, uint, 0644);
ba0ba7d3 40MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 41EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3 42
b3b1b0b0 43static unsigned char shutdown_timeout = 5;
ba0ba7d3
ML
44module_param(shutdown_timeout, byte, 0644);
45MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
46
44e44b29
CH
47static u8 nvme_max_retries = 5;
48module_param_named(max_retries, nvme_max_retries, byte, 0644);
f80ec966 49MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
5bae7f73 50
9947d6a0 51static unsigned long default_ps_max_latency_us = 100000;
c5552fde
AL
52module_param(default_ps_max_latency_us, ulong, 0644);
53MODULE_PARM_DESC(default_ps_max_latency_us,
54 "max power saving latency for new devices; use PM QOS to change per device");
55
c35e30b4
AL
56static bool force_apst;
57module_param(force_apst, bool, 0644);
58MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off");
59
ebd8a93a
AB
60static unsigned long apst_primary_timeout_ms = 100;
61module_param(apst_primary_timeout_ms, ulong, 0644);
62MODULE_PARM_DESC(apst_primary_timeout_ms,
63 "primary APST timeout in ms");
64
65static unsigned long apst_secondary_timeout_ms = 2000;
66module_param(apst_secondary_timeout_ms, ulong, 0644);
67MODULE_PARM_DESC(apst_secondary_timeout_ms,
68 "secondary APST timeout in ms");
69
70static unsigned long apst_primary_latency_tol_us = 15000;
71module_param(apst_primary_latency_tol_us, ulong, 0644);
72MODULE_PARM_DESC(apst_primary_latency_tol_us,
73 "primary APST latency tolerance in us");
74
75static unsigned long apst_secondary_latency_tol_us = 100000;
76module_param(apst_secondary_latency_tol_us, ulong, 0644);
77MODULE_PARM_DESC(apst_secondary_latency_tol_us,
78 "secondary APST latency tolerance in us");
79
f5d11840
JA
80static bool streams;
81module_param(streams, bool, 0644);
82MODULE_PARM_DESC(streams, "turn on support for Streams write directives");
83
b227c59b
RS
84/*
85 * nvme_wq - hosts nvme related works that are not reset or delete
86 * nvme_reset_wq - hosts nvme reset works
87 * nvme_delete_wq - hosts nvme delete works
88 *
97b2512a
NK
89 * nvme_wq will host works such as scan, aen handling, fw activation,
90 * keep-alive, periodic reconnects etc. nvme_reset_wq
b227c59b
RS
91 * runs reset works which also flush works hosted on nvme_wq for
92 * serialization purposes. nvme_delete_wq host controller deletion
93 * works which flush reset works for serialization.
94 */
9a6327d2
SG
95struct workqueue_struct *nvme_wq;
96EXPORT_SYMBOL_GPL(nvme_wq);
97
b227c59b
RS
98struct workqueue_struct *nvme_reset_wq;
99EXPORT_SYMBOL_GPL(nvme_reset_wq);
100
101struct workqueue_struct *nvme_delete_wq;
102EXPORT_SYMBOL_GPL(nvme_delete_wq);
103
ab9e00cc
CH
104static LIST_HEAD(nvme_subsystems);
105static DEFINE_MUTEX(nvme_subsystems_lock);
1673f1f0 106
9843f685 107static DEFINE_IDA(nvme_instance_ida);
f68abd9c 108static dev_t nvme_ctrl_base_chr_devt;
f3ca80fc 109static struct class *nvme_class;
ab9e00cc 110static struct class *nvme_subsys_class;
f3ca80fc 111
2637baed
MI
112static DEFINE_IDA(nvme_ns_chr_minor_ida);
113static dev_t nvme_ns_chr_devt;
114static struct class *nvme_ns_chr_class;
115
12d9f070 116static void nvme_put_subsystem(struct nvme_subsystem *subsys);
cf39a6bc
SB
117static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
118 unsigned nsid);
119
c13f0fbc
CH
120/*
121 * Prepare a queue for teardown.
122 *
123 * This must forcibly unquiesce queues to avoid blocking dispatch, and only set
124 * the capacity to 0 after that to avoid blocking dispatchers that may be
125 * holding bd_butex. This will end buffered writers dirtying pages that can't
126 * be synced.
127 */
cf39a6bc
SB
128static void nvme_set_queue_dying(struct nvme_ns *ns)
129{
3913f4f3 130 if (test_and_set_bit(NVME_NS_DEAD, &ns->flags))
cf39a6bc 131 return;
c13f0fbc 132
cf39a6bc 133 blk_set_queue_dying(ns->queue);
cf39a6bc 134 blk_mq_unquiesce_queue(ns->queue);
c13f0fbc 135
d17e66aa 136 set_capacity_and_notify(ns->disk, 0);
cf39a6bc 137}
f3ca80fc 138
2405252a 139void nvme_queue_scan(struct nvme_ctrl *ctrl)
50e8d8ee
CH
140{
141 /*
142 * Only new queue scan work when admin and IO queues are both alive
143 */
5d02a5c1 144 if (ctrl->state == NVME_CTRL_LIVE && ctrl->tagset)
50e8d8ee
CH
145 queue_work(nvme_wq, &ctrl->scan_work);
146}
147
4c75f877
KB
148/*
149 * Use this function to proceed with scheduling reset_work for a controller
150 * that had previously been set to the resetting state. This is intended for
151 * code paths that can't be interrupted by other reset attempts. A hot removal
152 * may prevent this from succeeding.
153 */
c1ac9a4b 154int nvme_try_sched_reset(struct nvme_ctrl *ctrl)
4c75f877
KB
155{
156 if (ctrl->state != NVME_CTRL_RESETTING)
157 return -EBUSY;
158 if (!queue_work(nvme_reset_wq, &ctrl->reset_work))
159 return -EBUSY;
160 return 0;
161}
c1ac9a4b 162EXPORT_SYMBOL_GPL(nvme_try_sched_reset);
4c75f877 163
8c4dfea9
VG
164static void nvme_failfast_work(struct work_struct *work)
165{
166 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
167 struct nvme_ctrl, failfast_work);
168
169 if (ctrl->state != NVME_CTRL_CONNECTING)
170 return;
171
172 set_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags);
173 dev_info(ctrl->device, "failfast expired\n");
174 nvme_kick_requeue_lists(ctrl);
175}
176
177static inline void nvme_start_failfast_work(struct nvme_ctrl *ctrl)
178{
179 if (!ctrl->opts || ctrl->opts->fast_io_fail_tmo == -1)
180 return;
181
182 schedule_delayed_work(&ctrl->failfast_work,
183 ctrl->opts->fast_io_fail_tmo * HZ);
184}
185
186static inline void nvme_stop_failfast_work(struct nvme_ctrl *ctrl)
187{
188 if (!ctrl->opts)
189 return;
190
191 cancel_delayed_work_sync(&ctrl->failfast_work);
192 clear_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags);
193}
194
195
d86c4d8e
CH
196int nvme_reset_ctrl(struct nvme_ctrl *ctrl)
197{
198 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
199 return -EBUSY;
b227c59b 200 if (!queue_work(nvme_reset_wq, &ctrl->reset_work))
d86c4d8e
CH
201 return -EBUSY;
202 return 0;
203}
204EXPORT_SYMBOL_GPL(nvme_reset_ctrl);
205
2405252a 206int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
d86c4d8e
CH
207{
208 int ret;
209
210 ret = nvme_reset_ctrl(ctrl);
8000d1fd 211 if (!ret) {
d86c4d8e 212 flush_work(&ctrl->reset_work);
5d02a5c1 213 if (ctrl->state != NVME_CTRL_LIVE)
8000d1fd
NC
214 ret = -ENETRESET;
215 }
216
d86c4d8e
CH
217 return ret;
218}
219
a686ed75 220static void nvme_do_delete_ctrl(struct nvme_ctrl *ctrl)
c5017e85 221{
77d0612d
MG
222 dev_info(ctrl->device,
223 "Removing ctrl: NQN \"%s\"\n", ctrl->opts->subsysnqn);
224
4054637c 225 flush_work(&ctrl->reset_work);
6cd53d14
CH
226 nvme_stop_ctrl(ctrl);
227 nvme_remove_namespaces(ctrl);
c5017e85 228 ctrl->ops->delete_ctrl(ctrl);
6cd53d14 229 nvme_uninit_ctrl(ctrl);
c5017e85
CH
230}
231
a686ed75
BVA
232static void nvme_delete_ctrl_work(struct work_struct *work)
233{
234 struct nvme_ctrl *ctrl =
235 container_of(work, struct nvme_ctrl, delete_work);
236
237 nvme_do_delete_ctrl(ctrl);
238}
239
c5017e85
CH
240int nvme_delete_ctrl(struct nvme_ctrl *ctrl)
241{
242 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
243 return -EBUSY;
b227c59b 244 if (!queue_work(nvme_delete_wq, &ctrl->delete_work))
c5017e85
CH
245 return -EBUSY;
246 return 0;
247}
248EXPORT_SYMBOL_GPL(nvme_delete_ctrl);
249
6721c18a 250static void nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl)
c5017e85 251{
c5017e85 252 /*
01fc08ff
YY
253 * Keep a reference until nvme_do_delete_ctrl() complete,
254 * since ->delete_ctrl can free the controller.
c5017e85
CH
255 */
256 nvme_get_ctrl(ctrl);
6721c18a 257 if (nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
b9c77583 258 nvme_do_delete_ctrl(ctrl);
c5017e85 259 nvme_put_ctrl(ctrl);
c5017e85 260}
c5017e85 261
2f9c1736 262static blk_status_t nvme_error_status(u16 status)
27fa9bc5 263{
2f9c1736 264 switch (status & 0x7ff) {
27fa9bc5 265 case NVME_SC_SUCCESS:
2a842aca 266 return BLK_STS_OK;
27fa9bc5 267 case NVME_SC_CAP_EXCEEDED:
2a842aca 268 return BLK_STS_NOSPC;
e96fef2c 269 case NVME_SC_LBA_RANGE:
35038bff
KB
270 case NVME_SC_CMD_INTERRUPTED:
271 case NVME_SC_NS_NOT_READY:
e96fef2c
KB
272 return BLK_STS_TARGET;
273 case NVME_SC_BAD_ATTRIBUTES:
e02ab023 274 case NVME_SC_ONCS_NOT_SUPPORTED:
e96fef2c
KB
275 case NVME_SC_INVALID_OPCODE:
276 case NVME_SC_INVALID_FIELD:
277 case NVME_SC_INVALID_NS:
2a842aca 278 return BLK_STS_NOTSUPP;
e02ab023
JG
279 case NVME_SC_WRITE_FAULT:
280 case NVME_SC_READ_ERROR:
281 case NVME_SC_UNWRITTEN_BLOCK:
a751da33
CH
282 case NVME_SC_ACCESS_DENIED:
283 case NVME_SC_READ_ONLY:
e96fef2c 284 case NVME_SC_COMPARE_FAILED:
2a842aca 285 return BLK_STS_MEDIUM;
a751da33
CH
286 case NVME_SC_GUARD_CHECK:
287 case NVME_SC_APPTAG_CHECK:
288 case NVME_SC_REFTAG_CHECK:
289 case NVME_SC_INVALID_PI:
290 return BLK_STS_PROTECTION;
291 case NVME_SC_RESERVATION_CONFLICT:
292 return BLK_STS_NEXUS;
1c0d12c0
SG
293 case NVME_SC_HOST_PATH_ERROR:
294 return BLK_STS_TRANSPORT;
afaf5c6c
KB
295 case NVME_SC_ZONE_TOO_MANY_ACTIVE:
296 return BLK_STS_ZONE_ACTIVE_RESOURCE;
297 case NVME_SC_ZONE_TOO_MANY_OPEN:
298 return BLK_STS_ZONE_OPEN_RESOURCE;
2a842aca
CH
299 default:
300 return BLK_STS_IOERR;
27fa9bc5
CH
301 }
302}
27fa9bc5 303
49cd84b6
KB
304static void nvme_retry_req(struct request *req)
305{
49cd84b6
KB
306 unsigned long delay = 0;
307 u16 crd;
308
309 /* The mask and shift result must be <= 3 */
310 crd = (nvme_req(req)->status & NVME_SC_CRD) >> 11;
f9063a53
MI
311 if (crd)
312 delay = nvme_req(req)->ctrl->crdt[crd - 1] * 100;
49cd84b6
KB
313
314 nvme_req(req)->retries++;
315 blk_mq_requeue_request(req, false);
316 blk_mq_delay_kick_requeue_list(req->q, delay);
317}
318
5ddaabe8
CH
319enum nvme_disposition {
320 COMPLETE,
321 RETRY,
322 FAILOVER,
323};
324
325static inline enum nvme_disposition nvme_decide_disposition(struct request *req)
77f02a7a 326{
5ddaabe8
CH
327 if (likely(nvme_req(req)->status == 0))
328 return COMPLETE;
908e4564 329
5ddaabe8
CH
330 if (blk_noretry_request(req) ||
331 (nvme_req(req)->status & NVME_SC_DNR) ||
332 nvme_req(req)->retries >= nvme_max_retries)
333 return COMPLETE;
ca5554a6 334
5ddaabe8 335 if (req->cmd_flags & REQ_NVME_MPATH) {
5eac5f33
CL
336 if (nvme_is_path_error(nvme_req(req)->status) ||
337 blk_queue_dying(req->q))
5ddaabe8 338 return FAILOVER;
5eac5f33
CL
339 } else {
340 if (blk_queue_dying(req->q))
341 return COMPLETE;
5ddaabe8 342 }
16686f3a 343
5ddaabe8
CH
344 return RETRY;
345}
6e3ca03e 346
5ddaabe8
CH
347static inline void nvme_end_req(struct request *req)
348{
349 blk_status_t status = nvme_error_status(nvme_req(req)->status);
32acab31 350
5ddaabe8
CH
351 if (IS_ENABLED(CONFIG_BLK_DEV_ZONED) &&
352 req_op(req) == REQ_OP_ZONE_APPEND)
240e6ee2
KB
353 req->__sector = nvme_lba_to_sect(req->q->queuedata,
354 le64_to_cpu(nvme_req(req)->result.u64));
35fe0d12 355
2b59787a 356 nvme_trace_bio_complete(req);
908e4564 357 blk_mq_end_request(req, status);
77f02a7a 358}
5ddaabe8
CH
359
360void nvme_complete_rq(struct request *req)
361{
362 trace_nvme_complete_rq(req);
363 nvme_cleanup_cmd(req);
364
365 if (nvme_req(req)->ctrl->kas)
366 nvme_req(req)->ctrl->comp_seen = true;
367
368 switch (nvme_decide_disposition(req)) {
369 case COMPLETE:
370 nvme_end_req(req);
371 return;
372 case RETRY:
373 nvme_retry_req(req);
374 return;
375 case FAILOVER:
376 nvme_failover_req(req);
377 return;
378 }
379}
77f02a7a
CH
380EXPORT_SYMBOL_GPL(nvme_complete_rq);
381
dda3248e
CL
382/*
383 * Called to unwind from ->queue_rq on a failed command submission so that the
384 * multipathing code gets called to potentially failover to another path.
385 * The caller needs to unwind all transport specific resource allocations and
386 * must return propagate the return value.
387 */
388blk_status_t nvme_host_path_error(struct request *req)
389{
390 nvme_req(req)->status = NVME_SC_HOST_PATH_ERROR;
391 blk_mq_set_request_complete(req);
392 nvme_complete_rq(req);
393 return BLK_STS_OK;
394}
395EXPORT_SYMBOL_GPL(nvme_host_path_error);
396
7baa8572 397bool nvme_cancel_request(struct request *req, void *data, bool reserved)
c55a2fd4 398{
c55a2fd4
ML
399 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
400 "Cancelling I/O %d", req->tag);
401
78ca4072
ML
402 /* don't abort one completed request */
403 if (blk_mq_request_completed(req))
404 return true;
405
2dc3947b 406 nvme_req(req)->status = NVME_SC_HOST_ABORTED_CMD;
d3589381 407 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
15f73f5b 408 blk_mq_complete_request(req);
7baa8572 409 return true;
c55a2fd4
ML
410}
411EXPORT_SYMBOL_GPL(nvme_cancel_request);
412
25479069
CL
413void nvme_cancel_tagset(struct nvme_ctrl *ctrl)
414{
415 if (ctrl->tagset) {
416 blk_mq_tagset_busy_iter(ctrl->tagset,
417 nvme_cancel_request, ctrl);
418 blk_mq_tagset_wait_completed_request(ctrl->tagset);
419 }
420}
421EXPORT_SYMBOL_GPL(nvme_cancel_tagset);
422
423void nvme_cancel_admin_tagset(struct nvme_ctrl *ctrl)
424{
425 if (ctrl->admin_tagset) {
426 blk_mq_tagset_busy_iter(ctrl->admin_tagset,
427 nvme_cancel_request, ctrl);
428 blk_mq_tagset_wait_completed_request(ctrl->admin_tagset);
429 }
430}
431EXPORT_SYMBOL_GPL(nvme_cancel_admin_tagset);
432
bb8d261e
CH
433bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
434 enum nvme_ctrl_state new_state)
435{
f6b6a28e 436 enum nvme_ctrl_state old_state;
0a72bbba 437 unsigned long flags;
bb8d261e
CH
438 bool changed = false;
439
0a72bbba 440 spin_lock_irqsave(&ctrl->lock, flags);
f6b6a28e
GKB
441
442 old_state = ctrl->state;
bb8d261e
CH
443 switch (new_state) {
444 case NVME_CTRL_LIVE:
445 switch (old_state) {
7d2e8008 446 case NVME_CTRL_NEW:
bb8d261e 447 case NVME_CTRL_RESETTING:
ad6a0a52 448 case NVME_CTRL_CONNECTING:
bb8d261e 449 changed = true;
df561f66 450 fallthrough;
bb8d261e
CH
451 default:
452 break;
453 }
454 break;
455 case NVME_CTRL_RESETTING:
456 switch (old_state) {
457 case NVME_CTRL_NEW:
def61eca 458 case NVME_CTRL_LIVE:
def61eca 459 changed = true;
df561f66 460 fallthrough;
def61eca
CH
461 default:
462 break;
463 }
464 break;
ad6a0a52 465 case NVME_CTRL_CONNECTING:
def61eca 466 switch (old_state) {
b754a32c 467 case NVME_CTRL_NEW:
3cec7f9d 468 case NVME_CTRL_RESETTING:
bb8d261e 469 changed = true;
df561f66 470 fallthrough;
bb8d261e
CH
471 default:
472 break;
473 }
474 break;
475 case NVME_CTRL_DELETING:
476 switch (old_state) {
477 case NVME_CTRL_LIVE:
478 case NVME_CTRL_RESETTING:
ad6a0a52 479 case NVME_CTRL_CONNECTING:
bb8d261e 480 changed = true;
df561f66 481 fallthrough;
bb8d261e
CH
482 default:
483 break;
484 }
485 break;
ecca390e
SG
486 case NVME_CTRL_DELETING_NOIO:
487 switch (old_state) {
488 case NVME_CTRL_DELETING:
489 case NVME_CTRL_DEAD:
490 changed = true;
df561f66 491 fallthrough;
ecca390e
SG
492 default:
493 break;
494 }
495 break;
0ff9d4e1
KB
496 case NVME_CTRL_DEAD:
497 switch (old_state) {
498 case NVME_CTRL_DELETING:
499 changed = true;
df561f66 500 fallthrough;
0ff9d4e1
KB
501 default:
502 break;
503 }
504 break;
bb8d261e
CH
505 default:
506 break;
507 }
bb8d261e 508
c1ac9a4b 509 if (changed) {
bb8d261e 510 ctrl->state = new_state;
c1ac9a4b
KB
511 wake_up_all(&ctrl->state_wq);
512 }
bb8d261e 513
0a72bbba 514 spin_unlock_irqrestore(&ctrl->lock, flags);
8c4dfea9
VG
515 if (!changed)
516 return false;
517
518 if (ctrl->state == NVME_CTRL_LIVE) {
519 if (old_state == NVME_CTRL_CONNECTING)
520 nvme_stop_failfast_work(ctrl);
32acab31 521 nvme_kick_requeue_lists(ctrl);
8c4dfea9
VG
522 } else if (ctrl->state == NVME_CTRL_CONNECTING &&
523 old_state == NVME_CTRL_RESETTING) {
524 nvme_start_failfast_work(ctrl);
525 }
bb8d261e
CH
526 return changed;
527}
528EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
529
c1ac9a4b
KB
530/*
531 * Returns true for sink states that can't ever transition back to live.
532 */
533static bool nvme_state_terminal(struct nvme_ctrl *ctrl)
534{
535 switch (ctrl->state) {
536 case NVME_CTRL_NEW:
537 case NVME_CTRL_LIVE:
538 case NVME_CTRL_RESETTING:
539 case NVME_CTRL_CONNECTING:
540 return false;
541 case NVME_CTRL_DELETING:
ecca390e 542 case NVME_CTRL_DELETING_NOIO:
c1ac9a4b
KB
543 case NVME_CTRL_DEAD:
544 return true;
545 default:
546 WARN_ONCE(1, "Unhandled ctrl state:%d", ctrl->state);
547 return true;
548 }
549}
550
551/*
552 * Waits for the controller state to be resetting, or returns false if it is
553 * not possible to ever transition to that state.
554 */
555bool nvme_wait_reset(struct nvme_ctrl *ctrl)
556{
557 wait_event(ctrl->state_wq,
558 nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING) ||
559 nvme_state_terminal(ctrl));
560 return ctrl->state == NVME_CTRL_RESETTING;
561}
562EXPORT_SYMBOL_GPL(nvme_wait_reset);
563
ed754e5d
CH
564static void nvme_free_ns_head(struct kref *ref)
565{
566 struct nvme_ns_head *head =
567 container_of(ref, struct nvme_ns_head, ref);
568
32acab31 569 nvme_mpath_remove_disk(head);
ed754e5d 570 ida_simple_remove(&head->subsys->ns_ida, head->instance);
f5ad3991 571 cleanup_srcu_struct(&head->srcu);
12d9f070 572 nvme_put_subsystem(head->subsys);
ed754e5d
CH
573 kfree(head);
574}
575
1496bd49 576bool nvme_tryget_ns_head(struct nvme_ns_head *head)
871ca3ef
CH
577{
578 return kref_get_unless_zero(&head->ref);
579}
580
1496bd49 581void nvme_put_ns_head(struct nvme_ns_head *head)
ed754e5d
CH
582{
583 kref_put(&head->ref, nvme_free_ns_head);
584}
585
1673f1f0
CH
586static void nvme_free_ns(struct kref *kref)
587{
588 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
589
b0b4e09c
MB
590 if (ns->ndev)
591 nvme_nvm_unregister(ns);
1673f1f0 592
1673f1f0 593 put_disk(ns->disk);
ed754e5d 594 nvme_put_ns_head(ns->head);
075790eb 595 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH
596 kfree(ns);
597}
598
4c74d1f8
KJ
599static inline bool nvme_get_ns(struct nvme_ns *ns)
600{
601 return kref_get_unless_zero(&ns->kref);
602}
603
24493b8b 604void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH
605{
606 kref_put(&ns->kref, nvme_free_ns);
607}
24493b8b 608EXPORT_SYMBOL_NS_GPL(nvme_put_ns, NVME_TARGET_PASSTHRU);
1673f1f0 609
bb06ec31
JS
610static inline void nvme_clear_nvme_request(struct request *req)
611{
ae5e6886 612 nvme_req(req)->status = 0;
c03fd85d
CK
613 nvme_req(req)->retries = 0;
614 nvme_req(req)->flags = 0;
615 req->rq_flags |= RQF_DONTPREP;
bb06ec31
JS
616}
617
39dfe844 618static inline unsigned int nvme_req_op(struct nvme_command *cmd)
21d34711 619{
39dfe844
CK
620 return nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN;
621}
21d34711 622
39dfe844
CK
623static inline void nvme_init_request(struct request *req,
624 struct nvme_command *cmd)
625{
0d2e7c84
CK
626 if (req->q->queuedata)
627 req->timeout = NVME_IO_TIMEOUT;
628 else /* no queuedata implies admin queue */
dc96f938 629 req->timeout = NVME_ADMIN_TIMEOUT;
21d34711 630
f4b9e6c9
KB
631 /* passthru commands should let the driver set the SGL flags */
632 cmd->common.flags &= ~NVME_CMD_SGL_ALL;
633
21d34711 634 req->cmd_flags |= REQ_FAILFAST_DRIVER;
be42a33b
KB
635 if (req->mq_hctx->type == HCTX_TYPE_POLL)
636 req->cmd_flags |= REQ_HIPRI;
bb06ec31 637 nvme_clear_nvme_request(req);
f4b9e6c9 638 memcpy(nvme_req(req)->cmd, cmd, sizeof(*cmd));
39dfe844 639}
21d34711 640
39dfe844
CK
641struct request *nvme_alloc_request(struct request_queue *q,
642 struct nvme_command *cmd, blk_mq_req_flags_t flags)
643{
644 struct request *req;
645
646 req = blk_mq_alloc_request(q, nvme_req_op(cmd), flags);
647 if (!IS_ERR(req))
648 nvme_init_request(req, cmd);
4160982e
CH
649 return req;
650}
576d55d6 651EXPORT_SYMBOL_GPL(nvme_alloc_request);
4160982e 652
9b66fc02 653static struct request *nvme_alloc_request_qid(struct request_queue *q,
39dfe844
CK
654 struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid)
655{
656 struct request *req;
657
658 req = blk_mq_alloc_request_hctx(q, nvme_req_op(cmd), flags,
659 qid ? qid - 1 : 0);
660 if (!IS_ERR(req))
661 nvme_init_request(req, cmd);
662 return req;
663}
39dfe844 664
a9715744
TC
665/*
666 * For something we're not in a state to send to the device the default action
667 * is to busy it and retry it after the controller state is recovered. However,
668 * if the controller is deleting or if anything is marked for failfast or
669 * nvme multipath it is immediately failed.
670 *
671 * Note: commands used to initialize the controller will be marked for failfast.
672 * Note: nvme cli/ioctl commands are marked for failfast.
673 */
674blk_status_t nvme_fail_nonready_command(struct nvme_ctrl *ctrl,
675 struct request *rq)
676{
677 if (ctrl->state != NVME_CTRL_DELETING_NOIO &&
678 ctrl->state != NVME_CTRL_DEAD &&
679 !test_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags) &&
680 !blk_noretry_request(rq) && !(rq->cmd_flags & REQ_NVME_MPATH))
681 return BLK_STS_RESOURCE;
682 return nvme_host_path_error(rq);
683}
684EXPORT_SYMBOL_GPL(nvme_fail_nonready_command);
685
686bool __nvme_check_ready(struct nvme_ctrl *ctrl, struct request *rq,
687 bool queue_live)
688{
689 struct nvme_request *req = nvme_req(rq);
690
691 /*
692 * currently we have a problem sending passthru commands
693 * on the admin_q if the controller is not LIVE because we can't
694 * make sure that they are going out after the admin connect,
695 * controller enable and/or other commands in the initialization
696 * sequence. until the controller will be LIVE, fail with
697 * BLK_STS_RESOURCE so that they will be rescheduled.
698 */
699 if (rq->q == ctrl->admin_q && (req->flags & NVME_REQ_USERCMD))
700 return false;
701
702 if (ctrl->ops->flags & NVME_F_FABRICS) {
703 /*
704 * Only allow commands on a live queue, except for the connect
705 * command, which is require to set the queue live in the
706 * appropinquate states.
707 */
708 switch (ctrl->state) {
709 case NVME_CTRL_CONNECTING:
710 if (blk_rq_is_passthrough(rq) && nvme_is_fabrics(req->cmd) &&
711 req->cmd->fabrics.fctype == nvme_fabrics_type_connect)
712 return true;
713 break;
714 default:
715 break;
716 case NVME_CTRL_DEAD:
717 return false;
718 }
719 }
720
721 return queue_live;
722}
723EXPORT_SYMBOL_GPL(__nvme_check_ready);
724
f5d11840
JA
725static int nvme_toggle_streams(struct nvme_ctrl *ctrl, bool enable)
726{
cc72c442 727 struct nvme_command c = { };
f5d11840
JA
728
729 c.directive.opcode = nvme_admin_directive_send;
62346eae 730 c.directive.nsid = cpu_to_le32(NVME_NSID_ALL);
f5d11840
JA
731 c.directive.doper = NVME_DIR_SND_ID_OP_ENABLE;
732 c.directive.dtype = NVME_DIR_IDENTIFY;
733 c.directive.tdtype = NVME_DIR_STREAMS;
734 c.directive.endir = enable ? NVME_DIR_ENDIR : 0;
735
736 return nvme_submit_sync_cmd(ctrl->admin_q, &c, NULL, 0);
737}
738
739static int nvme_disable_streams(struct nvme_ctrl *ctrl)
740{
741 return nvme_toggle_streams(ctrl, false);
742}
743
744static int nvme_enable_streams(struct nvme_ctrl *ctrl)
745{
746 return nvme_toggle_streams(ctrl, true);
747}
748
749static int nvme_get_stream_params(struct nvme_ctrl *ctrl,
750 struct streams_directive_params *s, u32 nsid)
751{
cc72c442 752 struct nvme_command c = { };
f5d11840 753
f5d11840
JA
754 memset(s, 0, sizeof(*s));
755
756 c.directive.opcode = nvme_admin_directive_recv;
757 c.directive.nsid = cpu_to_le32(nsid);
71fb90eb 758 c.directive.numd = cpu_to_le32(nvme_bytes_to_numd(sizeof(*s)));
f5d11840
JA
759 c.directive.doper = NVME_DIR_RCV_ST_OP_PARAM;
760 c.directive.dtype = NVME_DIR_STREAMS;
761
762 return nvme_submit_sync_cmd(ctrl->admin_q, &c, s, sizeof(*s));
763}
764
765static int nvme_configure_directives(struct nvme_ctrl *ctrl)
766{
767 struct streams_directive_params s;
768 int ret;
769
770 if (!(ctrl->oacs & NVME_CTRL_OACS_DIRECTIVES))
771 return 0;
772 if (!streams)
773 return 0;
774
775 ret = nvme_enable_streams(ctrl);
776 if (ret)
777 return ret;
778
62346eae 779 ret = nvme_get_stream_params(ctrl, &s, NVME_NSID_ALL);
f5d11840 780 if (ret)
84e4c204 781 goto out_disable_stream;
f5d11840
JA
782
783 ctrl->nssa = le16_to_cpu(s.nssa);
784 if (ctrl->nssa < BLK_MAX_WRITE_HINTS - 1) {
785 dev_info(ctrl->device, "too few streams (%u) available\n",
786 ctrl->nssa);
84e4c204 787 goto out_disable_stream;
f5d11840
JA
788 }
789
a87835e9 790 ctrl->nr_streams = min_t(u16, ctrl->nssa, BLK_MAX_WRITE_HINTS - 1);
f5d11840
JA
791 dev_info(ctrl->device, "Using %u streams\n", ctrl->nr_streams);
792 return 0;
84e4c204
WB
793
794out_disable_stream:
795 nvme_disable_streams(ctrl);
796 return ret;
f5d11840
JA
797}
798
799/*
800 * Check if 'req' has a write hint associated with it. If it does, assign
801 * a valid namespace stream to the write.
802 */
803static void nvme_assign_write_stream(struct nvme_ctrl *ctrl,
804 struct request *req, u16 *control,
805 u32 *dsmgmt)
806{
807 enum rw_hint streamid = req->write_hint;
808
809 if (streamid == WRITE_LIFE_NOT_SET || streamid == WRITE_LIFE_NONE)
810 streamid = 0;
811 else {
812 streamid--;
813 if (WARN_ON_ONCE(streamid > ctrl->nr_streams))
814 return;
815
816 *control |= NVME_RW_DTYPE_STREAMS;
817 *dsmgmt |= streamid << 16;
818 }
819
820 if (streamid < ARRAY_SIZE(req->q->write_hints))
821 req->q->write_hints[streamid] += blk_rq_bytes(req) >> 9;
822}
823
8093f7ca
ML
824static inline void nvme_setup_flush(struct nvme_ns *ns,
825 struct nvme_command *cmnd)
826{
8093f7ca 827 cmnd->common.opcode = nvme_cmd_flush;
ed754e5d 828 cmnd->common.nsid = cpu_to_le32(ns->head->ns_id);
8093f7ca
ML
829}
830
fc17b653 831static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req,
8093f7ca
ML
832 struct nvme_command *cmnd)
833{
b35ba01e 834 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
8093f7ca 835 struct nvme_dsm_range *range;
b35ba01e 836 struct bio *bio;
8093f7ca 837
530436c4
EH
838 /*
839 * Some devices do not consider the DSM 'Number of Ranges' field when
840 * determining how much data to DMA. Always allocate memory for maximum
841 * number of segments to prevent device reading beyond end of buffer.
842 */
843 static const size_t alloc_size = sizeof(*range) * NVME_DSM_MAX_RANGES;
844
845 range = kzalloc(alloc_size, GFP_ATOMIC | __GFP_NOWARN);
cb5b7262
JA
846 if (!range) {
847 /*
848 * If we fail allocation our range, fallback to the controller
849 * discard page. If that's also busy, it's safe to return
850 * busy, as we know we can make progress once that's freed.
851 */
852 if (test_and_set_bit_lock(0, &ns->ctrl->discard_page_busy))
853 return BLK_STS_RESOURCE;
854
855 range = page_address(ns->ctrl->discard_page);
856 }
8093f7ca 857
b35ba01e 858 __rq_for_each_bio(bio, req) {
314d48dd 859 u64 slba = nvme_sect_to_lba(ns, bio->bi_iter.bi_sector);
b35ba01e
CH
860 u32 nlb = bio->bi_iter.bi_size >> ns->lba_shift;
861
8cb6af7b
KB
862 if (n < segments) {
863 range[n].cattr = cpu_to_le32(0);
864 range[n].nlb = cpu_to_le32(nlb);
865 range[n].slba = cpu_to_le64(slba);
866 }
b35ba01e
CH
867 n++;
868 }
869
870 if (WARN_ON_ONCE(n != segments)) {
cb5b7262
JA
871 if (virt_to_page(range) == ns->ctrl->discard_page)
872 clear_bit_unlock(0, &ns->ctrl->discard_page_busy);
873 else
874 kfree(range);
fc17b653 875 return BLK_STS_IOERR;
b35ba01e 876 }
8093f7ca 877
8093f7ca 878 cmnd->dsm.opcode = nvme_cmd_dsm;
ed754e5d 879 cmnd->dsm.nsid = cpu_to_le32(ns->head->ns_id);
f1dd03a8 880 cmnd->dsm.nr = cpu_to_le32(segments - 1);
8093f7ca
ML
881 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
882
f9d03f96
CH
883 req->special_vec.bv_page = virt_to_page(range);
884 req->special_vec.bv_offset = offset_in_page(range);
530436c4 885 req->special_vec.bv_len = alloc_size;
f9d03f96 886 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 887
fc17b653 888 return BLK_STS_OK;
8093f7ca 889}
8093f7ca 890
6e02318e
CK
891static inline blk_status_t nvme_setup_write_zeroes(struct nvme_ns *ns,
892 struct request *req, struct nvme_command *cmnd)
893{
894 if (ns->ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
895 return nvme_setup_discard(ns, req, cmnd);
896
897 cmnd->write_zeroes.opcode = nvme_cmd_write_zeroes;
898 cmnd->write_zeroes.nsid = cpu_to_le32(ns->head->ns_id);
899 cmnd->write_zeroes.slba =
314d48dd 900 cpu_to_le64(nvme_sect_to_lba(ns, blk_rq_pos(req)));
6e02318e
CK
901 cmnd->write_zeroes.length =
902 cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
aaeb7bb0
CH
903 if (nvme_ns_has_pi(ns))
904 cmnd->write_zeroes.control = cpu_to_le16(NVME_RW_PRINFO_PRACT);
905 else
906 cmnd->write_zeroes.control = 0;
6e02318e
CK
907 return BLK_STS_OK;
908}
909
ebe6d874 910static inline blk_status_t nvme_setup_rw(struct nvme_ns *ns,
240e6ee2
KB
911 struct request *req, struct nvme_command *cmnd,
912 enum nvme_opcode op)
8093f7ca 913{
f5d11840 914 struct nvme_ctrl *ctrl = ns->ctrl;
8093f7ca
ML
915 u16 control = 0;
916 u32 dsmgmt = 0;
917
918 if (req->cmd_flags & REQ_FUA)
919 control |= NVME_RW_FUA;
920 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
921 control |= NVME_RW_LR;
922
923 if (req->cmd_flags & REQ_RAHEAD)
924 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
925
240e6ee2 926 cmnd->rw.opcode = op;
ed754e5d 927 cmnd->rw.nsid = cpu_to_le32(ns->head->ns_id);
314d48dd 928 cmnd->rw.slba = cpu_to_le64(nvme_sect_to_lba(ns, blk_rq_pos(req)));
8093f7ca
ML
929 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
930
f5d11840
JA
931 if (req_op(req) == REQ_OP_WRITE && ctrl->nr_streams)
932 nvme_assign_write_stream(ctrl, req, &control, &dsmgmt);
933
8093f7ca 934 if (ns->ms) {
715ea9e0
CH
935 /*
936 * If formated with metadata, the block layer always provides a
937 * metadata buffer if CONFIG_BLK_DEV_INTEGRITY is enabled. Else
938 * we enable the PRACT bit for protection information or set the
939 * namespace capacity to zero to prevent any I/O.
940 */
941 if (!blk_integrity_rq(req)) {
942 if (WARN_ON_ONCE(!nvme_ns_has_pi(ns)))
943 return BLK_STS_NOTSUPP;
944 control |= NVME_RW_PRINFO_PRACT;
945 }
946
8093f7ca
ML
947 switch (ns->pi_type) {
948 case NVME_NS_DPS_PI_TYPE3:
949 control |= NVME_RW_PRINFO_PRCHK_GUARD;
950 break;
951 case NVME_NS_DPS_PI_TYPE1:
952 case NVME_NS_DPS_PI_TYPE2:
953 control |= NVME_RW_PRINFO_PRCHK_GUARD |
954 NVME_RW_PRINFO_PRCHK_REF;
240e6ee2
KB
955 if (op == nvme_cmd_zone_append)
956 control |= NVME_RW_APPEND_PIREMAP;
ddd0bc75 957 cmnd->rw.reftag = cpu_to_le32(t10_pi_ref_tag(req));
8093f7ca
ML
958 break;
959 }
8093f7ca
ML
960 }
961
962 cmnd->rw.control = cpu_to_le16(control);
963 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
ebe6d874 964 return 0;
8093f7ca
ML
965}
966
f7f1fc36
MG
967void nvme_cleanup_cmd(struct request *req)
968{
f7f1fc36 969 if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
fc97e942 970 struct nvme_ctrl *ctrl = nvme_req(req)->ctrl;
cb5b7262
JA
971 struct page *page = req->special_vec.bv_page;
972
fc97e942
MI
973 if (page == ctrl->discard_page)
974 clear_bit_unlock(0, &ctrl->discard_page_busy);
cb5b7262
JA
975 else
976 kfree(page_address(page) + req->special_vec.bv_offset);
f7f1fc36
MG
977 }
978}
979EXPORT_SYMBOL_GPL(nvme_cleanup_cmd);
980
f4b9e6c9 981blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req)
8093f7ca 982{
f4b9e6c9 983 struct nvme_command *cmd = nvme_req(req)->cmd;
fc17b653 984 blk_status_t ret = BLK_STS_OK;
8093f7ca 985
51ad06cd 986 if (!(req->rq_flags & RQF_DONTPREP)) {
c03fd85d 987 nvme_clear_nvme_request(req);
51ad06cd
KJ
988 memset(cmd, 0, sizeof(*cmd));
989 }
987f699a 990
aebf526b
CH
991 switch (req_op(req)) {
992 case REQ_OP_DRV_IN:
993 case REQ_OP_DRV_OUT:
f4b9e6c9 994 /* these are setup prior to execution in nvme_init_request() */
aebf526b
CH
995 break;
996 case REQ_OP_FLUSH:
8093f7ca 997 nvme_setup_flush(ns, cmd);
aebf526b 998 break;
240e6ee2
KB
999 case REQ_OP_ZONE_RESET_ALL:
1000 case REQ_OP_ZONE_RESET:
1001 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_RESET);
1002 break;
1003 case REQ_OP_ZONE_OPEN:
1004 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_OPEN);
1005 break;
1006 case REQ_OP_ZONE_CLOSE:
1007 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_CLOSE);
1008 break;
1009 case REQ_OP_ZONE_FINISH:
1010 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_FINISH);
1011 break;
e850fd16 1012 case REQ_OP_WRITE_ZEROES:
6e02318e
CK
1013 ret = nvme_setup_write_zeroes(ns, req, cmd);
1014 break;
aebf526b 1015 case REQ_OP_DISCARD:
8093f7ca 1016 ret = nvme_setup_discard(ns, req, cmd);
aebf526b
CH
1017 break;
1018 case REQ_OP_READ:
240e6ee2
KB
1019 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_read);
1020 break;
aebf526b 1021 case REQ_OP_WRITE:
240e6ee2
KB
1022 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_write);
1023 break;
1024 case REQ_OP_ZONE_APPEND:
1025 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_zone_append);
aebf526b
CH
1026 break;
1027 default:
1028 WARN_ON_ONCE(1);
fc17b653 1029 return BLK_STS_IOERR;
aebf526b 1030 }
8093f7ca 1031
721b3917 1032 cmd->common.command_id = req->tag;
5d87eb94 1033 trace_nvme_setup_cmd(req, cmd);
8093f7ca
ML
1034 return ret;
1035}
1036EXPORT_SYMBOL_GPL(nvme_setup_cmd);
1037
ae5e6886
KB
1038/*
1039 * Return values:
1040 * 0: success
1041 * >0: nvme controller's cqe status response
1042 * <0: kernel error in lieu of controller response
1043 */
1044static int nvme_execute_rq(struct gendisk *disk, struct request *rq,
1045 bool at_head)
1046{
1047 blk_status_t status;
1048
1049 status = blk_execute_rq(disk, rq, at_head);
1050 if (nvme_req(rq)->flags & NVME_REQ_CANCELLED)
1051 return -EINTR;
1052 if (nvme_req(rq)->status)
1053 return nvme_req(rq)->status;
1054 return blk_status_to_errno(status);
1055}
1056
4160982e
CH
1057/*
1058 * Returns 0 on success. If the result is negative, it's a Linux error code;
1059 * if the result is positive, it's an NVM Express status code
1060 */
1061int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 1062 union nvme_result *result, void *buffer, unsigned bufflen,
9a95e4ef 1063 unsigned timeout, int qid, int at_head,
be42a33b 1064 blk_mq_req_flags_t flags)
4160982e
CH
1065{
1066 struct request *req;
1067 int ret;
1068
39dfe844
CK
1069 if (qid == NVME_QID_ANY)
1070 req = nvme_alloc_request(q, cmd, flags);
1071 else
1072 req = nvme_alloc_request_qid(q, cmd, flags, qid);
4160982e
CH
1073 if (IS_ERR(req))
1074 return PTR_ERR(req);
1075
0d2e7c84
CK
1076 if (timeout)
1077 req->timeout = timeout;
4160982e 1078
21d34711
CH
1079 if (buffer && bufflen) {
1080 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
1081 if (ret)
1082 goto out;
4160982e
CH
1083 }
1084
ae5e6886
KB
1085 ret = nvme_execute_rq(NULL, req, at_head);
1086 if (result && ret >= 0)
d49187e9 1087 *result = nvme_req(req)->result;
4160982e
CH
1088 out:
1089 blk_mq_free_request(req);
1090 return ret;
1091}
eb71f435 1092EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH
1093
1094int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1095 void *buffer, unsigned bufflen)
1096{
eb71f435 1097 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 0,
be42a33b 1098 NVME_QID_ANY, 0, 0);
4160982e 1099}
576d55d6 1100EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 1101
df21b6b1
LG
1102static u32 nvme_known_admin_effects(u8 opcode)
1103{
1104 switch (opcode) {
1105 case nvme_admin_format_nvm:
75eb779e 1106 return NVME_CMD_EFFECTS_LBCC | NVME_CMD_EFFECTS_NCC |
df21b6b1
LG
1107 NVME_CMD_EFFECTS_CSE_MASK;
1108 case nvme_admin_sanitize_nvm:
75eb779e 1109 return NVME_CMD_EFFECTS_LBCC | NVME_CMD_EFFECTS_CSE_MASK;
df21b6b1
LG
1110 default:
1111 break;
1112 }
1113 return 0;
1114}
1115
1116u32 nvme_command_effects(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode)
1117{
1118 u32 effects = 0;
1119
1120 if (ns) {
1121 if (ns->head->effects)
1122 effects = le32_to_cpu(ns->head->effects->iocs[opcode]);
1123 if (effects & ~(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC))
ed4a854b
KB
1124 dev_warn_once(ctrl->device,
1125 "IO command:%02x has unhandled effects:%08x\n",
1126 opcode, effects);
df21b6b1
LG
1127 return 0;
1128 }
1129
1130 if (ctrl->effects)
1131 effects = le32_to_cpu(ctrl->effects->acs[opcode]);
1132 effects |= nvme_known_admin_effects(opcode);
1133
1134 return effects;
1135}
1136EXPORT_SYMBOL_NS_GPL(nvme_command_effects, NVME_TARGET_PASSTHRU);
1137
1138static u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1139 u8 opcode)
1140{
1141 u32 effects = nvme_command_effects(ctrl, ns, opcode);
1142
1143 /*
1144 * For simplicity, IO to all namespaces is quiesced even if the command
1145 * effects say only one namespace is affected.
1146 */
af0f446d 1147 if (effects & NVME_CMD_EFFECTS_CSE_MASK) {
df21b6b1
LG
1148 mutex_lock(&ctrl->scan_lock);
1149 mutex_lock(&ctrl->subsys->lock);
1150 nvme_mpath_start_freeze(ctrl->subsys);
1151 nvme_mpath_wait_freeze(ctrl->subsys);
1152 nvme_start_freeze(ctrl);
1153 nvme_wait_freeze(ctrl);
1154 }
1155 return effects;
1156}
1157
df21b6b1
LG
1158static void nvme_passthru_end(struct nvme_ctrl *ctrl, u32 effects)
1159{
af0f446d 1160 if (effects & NVME_CMD_EFFECTS_CSE_MASK) {
df21b6b1
LG
1161 nvme_unfreeze(ctrl);
1162 nvme_mpath_unfreeze(ctrl->subsys);
1163 mutex_unlock(&ctrl->subsys->lock);
1164 nvme_remove_invalid_namespaces(ctrl, NVME_NSID_ALL);
1165 mutex_unlock(&ctrl->scan_lock);
1166 }
1167 if (effects & NVME_CMD_EFFECTS_CCC)
f21c4769 1168 nvme_init_ctrl_finish(ctrl);
df21b6b1
LG
1169 if (effects & (NVME_CMD_EFFECTS_NIC | NVME_CMD_EFFECTS_NCC)) {
1170 nvme_queue_scan(ctrl);
1171 flush_work(&ctrl->scan_work);
1172 }
1173}
1174
ae5e6886 1175int nvme_execute_passthru_rq(struct request *rq)
17365ae6
LG
1176{
1177 struct nvme_command *cmd = nvme_req(rq)->cmd;
1178 struct nvme_ctrl *ctrl = nvme_req(rq)->ctrl;
1179 struct nvme_ns *ns = rq->q->queuedata;
1180 struct gendisk *disk = ns ? ns->disk : NULL;
1181 u32 effects;
ae5e6886 1182 int ret;
17365ae6
LG
1183
1184 effects = nvme_passthru_start(ctrl, ns, cmd->common.opcode);
ae5e6886 1185 ret = nvme_execute_rq(disk, rq, false);
18479ddb
KJ
1186 if (effects) /* nothing to be done for zero cmd effects */
1187 nvme_passthru_end(ctrl, effects);
ae5e6886
KB
1188
1189 return ret;
17365ae6
LG
1190}
1191EXPORT_SYMBOL_NS_GPL(nvme_execute_passthru_rq, NVME_TARGET_PASSTHRU);
1192
a70b81bd
HR
1193/*
1194 * Recommended frequency for KATO commands per NVMe 1.4 section 7.12.1:
1195 *
1196 * The host should send Keep Alive commands at half of the Keep Alive Timeout
1197 * accounting for transport roundtrip times [..].
1198 */
1199static void nvme_queue_keep_alive_work(struct nvme_ctrl *ctrl)
4160982e 1200{
a70b81bd 1201 queue_delayed_work(nvme_wq, &ctrl->ka_work, ctrl->kato * HZ / 2);
21d34711
CH
1202}
1203
2a842aca 1204static void nvme_keep_alive_end_io(struct request *rq, blk_status_t status)
038bd4cb
SG
1205{
1206 struct nvme_ctrl *ctrl = rq->end_io_data;
86880d64
JS
1207 unsigned long flags;
1208 bool startka = false;
038bd4cb
SG
1209
1210 blk_mq_free_request(rq);
1211
2a842aca 1212 if (status) {
038bd4cb 1213 dev_err(ctrl->device,
2a842aca
CH
1214 "failed nvme_keep_alive_end_io error=%d\n",
1215 status);
038bd4cb
SG
1216 return;
1217 }
1218
6e3ca03e 1219 ctrl->comp_seen = false;
86880d64
JS
1220 spin_lock_irqsave(&ctrl->lock, flags);
1221 if (ctrl->state == NVME_CTRL_LIVE ||
1222 ctrl->state == NVME_CTRL_CONNECTING)
1223 startka = true;
1224 spin_unlock_irqrestore(&ctrl->lock, flags);
1225 if (startka)
a70b81bd 1226 nvme_queue_keep_alive_work(ctrl);
038bd4cb
SG
1227}
1228
038bd4cb
SG
1229static void nvme_keep_alive_work(struct work_struct *work)
1230{
1231 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
1232 struct nvme_ctrl, ka_work);
6e3ca03e 1233 bool comp_seen = ctrl->comp_seen;
06c3c336 1234 struct request *rq;
6e3ca03e
SG
1235
1236 if ((ctrl->ctratt & NVME_CTRL_ATTR_TBKAS) && comp_seen) {
1237 dev_dbg(ctrl->device,
1238 "reschedule traffic based keep-alive timer\n");
1239 ctrl->comp_seen = false;
a70b81bd 1240 nvme_queue_keep_alive_work(ctrl);
6e3ca03e
SG
1241 return;
1242 }
038bd4cb 1243
06c3c336 1244 rq = nvme_alloc_request(ctrl->admin_q, &ctrl->ka_cmd,
985c5a32 1245 BLK_MQ_REQ_RESERVED | BLK_MQ_REQ_NOWAIT);
06c3c336 1246 if (IS_ERR(rq)) {
038bd4cb 1247 /* allocation failure, reset the controller */
985c5a32 1248 dev_err(ctrl->device, "keep-alive failed: %ld\n", PTR_ERR(rq));
39bdc590 1249 nvme_reset_ctrl(ctrl);
038bd4cb
SG
1250 return;
1251 }
06c3c336
CH
1252
1253 rq->timeout = ctrl->kato * HZ;
1254 rq->end_io_data = ctrl;
1255 blk_execute_rq_nowait(NULL, rq, 0, nvme_keep_alive_end_io);
038bd4cb
SG
1256}
1257
00b683db 1258static void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
038bd4cb
SG
1259{
1260 if (unlikely(ctrl->kato == 0))
1261 return;
1262
a70b81bd 1263 nvme_queue_keep_alive_work(ctrl);
038bd4cb 1264}
038bd4cb
SG
1265
1266void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
1267{
1268 if (unlikely(ctrl->kato == 0))
1269 return;
1270
1271 cancel_delayed_work_sync(&ctrl->ka_work);
1272}
1273EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
1274
b9a5c3d4
CH
1275/*
1276 * In NVMe 1.0 the CNS field was just a binary controller or namespace
1277 * flag, thus sending any new CNS opcodes has a big chance of not working.
1278 * Qemu unfortunately had that bug after reporting a 1.1 version compliance
1279 * (but not for any later version).
1280 */
1281static bool nvme_ctrl_limited_cns(struct nvme_ctrl *ctrl)
1282{
1283 if (ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)
1284 return ctrl->vs < NVME_VS(1, 2, 0);
1285 return ctrl->vs < NVME_VS(1, 1, 0);
1286}
1287
3f7f25a9 1288static int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH
1289{
1290 struct nvme_command c = { };
1291 int error;
1292
1293 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1294 c.identify.opcode = nvme_admin_identify;
986994a2 1295 c.identify.cns = NVME_ID_CNS_CTRL;
21d34711
CH
1296
1297 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1298 if (!*id)
1299 return -ENOMEM;
1300
1301 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1302 sizeof(struct nvme_id_ctrl));
1303 if (error)
1304 kfree(*id);
1305 return error;
1306}
1307
71010c30
NC
1308static bool nvme_multi_css(struct nvme_ctrl *ctrl)
1309{
1310 return (ctrl->ctrl_config & NVME_CC_CSS_MASK) == NVME_CC_CSS_CSI;
1311}
1312
ad95a613 1313static int nvme_process_ns_desc(struct nvme_ctrl *ctrl, struct nvme_ns_ids *ids,
71010c30 1314 struct nvme_ns_id_desc *cur, bool *csi_seen)
ad95a613
CK
1315{
1316 const char *warn_str = "ctrl returned bogus length:";
1317 void *data = cur;
1318
1319 switch (cur->nidt) {
1320 case NVME_NIDT_EUI64:
1321 if (cur->nidl != NVME_NIDT_EUI64_LEN) {
1322 dev_warn(ctrl->device, "%s %d for NVME_NIDT_EUI64\n",
1323 warn_str, cur->nidl);
1324 return -1;
1325 }
1326 memcpy(ids->eui64, data + sizeof(*cur), NVME_NIDT_EUI64_LEN);
1327 return NVME_NIDT_EUI64_LEN;
1328 case NVME_NIDT_NGUID:
1329 if (cur->nidl != NVME_NIDT_NGUID_LEN) {
1330 dev_warn(ctrl->device, "%s %d for NVME_NIDT_NGUID\n",
1331 warn_str, cur->nidl);
1332 return -1;
1333 }
1334 memcpy(ids->nguid, data + sizeof(*cur), NVME_NIDT_NGUID_LEN);
1335 return NVME_NIDT_NGUID_LEN;
1336 case NVME_NIDT_UUID:
1337 if (cur->nidl != NVME_NIDT_UUID_LEN) {
1338 dev_warn(ctrl->device, "%s %d for NVME_NIDT_UUID\n",
1339 warn_str, cur->nidl);
1340 return -1;
1341 }
1342 uuid_copy(&ids->uuid, data + sizeof(*cur));
1343 return NVME_NIDT_UUID_LEN;
71010c30
NC
1344 case NVME_NIDT_CSI:
1345 if (cur->nidl != NVME_NIDT_CSI_LEN) {
1346 dev_warn(ctrl->device, "%s %d for NVME_NIDT_CSI\n",
1347 warn_str, cur->nidl);
1348 return -1;
1349 }
1350 memcpy(&ids->csi, data + sizeof(*cur), NVME_NIDT_CSI_LEN);
1351 *csi_seen = true;
1352 return NVME_NIDT_CSI_LEN;
ad95a613
CK
1353 default:
1354 /* Skip unknown types */
1355 return cur->nidl;
1356 }
1357}
1358
cdbff4f2 1359static int nvme_identify_ns_descs(struct nvme_ctrl *ctrl, unsigned nsid,
002fab04 1360 struct nvme_ns_ids *ids)
3b22ba26
JT
1361{
1362 struct nvme_command c = { };
71010c30
NC
1363 bool csi_seen = false;
1364 int status, pos, len;
3b22ba26 1365 void *data;
3b22ba26 1366
8b7c0ff2
CH
1367 if (ctrl->vs < NVME_VS(1, 3, 0) && !nvme_multi_css(ctrl))
1368 return 0;
5bedd3af
CH
1369 if (ctrl->quirks & NVME_QUIRK_NO_NS_DESC_LIST)
1370 return 0;
1371
3b22ba26
JT
1372 c.identify.opcode = nvme_admin_identify;
1373 c.identify.nsid = cpu_to_le32(nsid);
1374 c.identify.cns = NVME_ID_CNS_NS_DESC_LIST;
1375
1376 data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
1377 if (!data)
1378 return -ENOMEM;
1379
cdbff4f2 1380 status = nvme_submit_sync_cmd(ctrl->admin_q, &c, data,
3b22ba26 1381 NVME_IDENTIFY_DATA_SIZE);
fb314eb0
CH
1382 if (status) {
1383 dev_warn(ctrl->device,
aa9d7295
MI
1384 "Identify Descriptors failed (nsid=%u, status=0x%x)\n",
1385 nsid, status);
3b22ba26 1386 goto free_data;
fb314eb0 1387 }
3b22ba26
JT
1388
1389 for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) {
1390 struct nvme_ns_id_desc *cur = data + pos;
1391
1392 if (cur->nidl == 0)
1393 break;
1394
71010c30 1395 len = nvme_process_ns_desc(ctrl, ids, cur, &csi_seen);
ad95a613 1396 if (len < 0)
71010c30 1397 break;
3b22ba26
JT
1398
1399 len += sizeof(*cur);
1400 }
71010c30
NC
1401
1402 if (nvme_multi_css(ctrl) && !csi_seen) {
1403 dev_warn(ctrl->device, "Command set not reported for nsid:%d\n",
1404 nsid);
1405 status = -EINVAL;
1406 }
1407
3b22ba26
JT
1408free_data:
1409 kfree(data);
1410 return status;
1411}
1412
8b7c0ff2
CH
1413static int nvme_identify_ns(struct nvme_ctrl *ctrl, unsigned nsid,
1414 struct nvme_ns_ids *ids, struct nvme_id_ns **id)
21d34711
CH
1415{
1416 struct nvme_command c = { };
1417 int error;
1418
1419 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
778f067c
MG
1420 c.identify.opcode = nvme_admin_identify;
1421 c.identify.nsid = cpu_to_le32(nsid);
986994a2 1422 c.identify.cns = NVME_ID_CNS_NS;
21d34711 1423
331813f6
SG
1424 *id = kmalloc(sizeof(**id), GFP_KERNEL);
1425 if (!*id)
1426 return -ENOMEM;
21d34711 1427
331813f6 1428 error = nvme_submit_sync_cmd(ctrl->admin_q, &c, *id, sizeof(**id));
cdbff4f2 1429 if (error) {
d0de579c 1430 dev_warn(ctrl->device, "Identify namespace failed (%d)\n", error);
b8b8cd01 1431 goto out_free_id;
cdbff4f2
CH
1432 }
1433
d95c1f41 1434 error = NVME_SC_INVALID_NS | NVME_SC_DNR;
b8b8cd01
CH
1435 if ((*id)->ncap == 0) /* namespace not allocated or attached */
1436 goto out_free_id;
8b7c0ff2
CH
1437
1438 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
1439 !memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
1440 memcpy(ids->eui64, (*id)->eui64, sizeof(ids->eui64));
1441 if (ctrl->vs >= NVME_VS(1, 2, 0) &&
1442 !memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
1443 memcpy(ids->nguid, (*id)->nguid, sizeof(ids->nguid));
1444
b8b8cd01
CH
1445 return 0;
1446
1447out_free_id:
1448 kfree(*id);
331813f6 1449 return error;
21d34711
CH
1450}
1451
1a87ee65
KB
1452static int nvme_features(struct nvme_ctrl *dev, u8 op, unsigned int fid,
1453 unsigned int dword11, void *buffer, size_t buflen, u32 *result)
21d34711 1454{
15755854 1455 union nvme_result res = { 0 };
cc72c442 1456 struct nvme_command c = { };
1cb3cce5 1457 int ret;
21d34711 1458
1a87ee65 1459 c.features.opcode = op;
21d34711
CH
1460 c.features.fid = cpu_to_le32(fid);
1461 c.features.dword11 = cpu_to_le32(dword11);
1462
d49187e9 1463 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
be42a33b 1464 buffer, buflen, 0, NVME_QID_ANY, 0, 0);
9b47f77a 1465 if (ret >= 0 && result)
d49187e9 1466 *result = le32_to_cpu(res.u32);
1cb3cce5 1467 return ret;
21d34711
CH
1468}
1469
1a87ee65
KB
1470int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid,
1471 unsigned int dword11, void *buffer, size_t buflen,
1472 u32 *result)
1473{
1474 return nvme_features(dev, nvme_admin_set_features, fid, dword11, buffer,
1475 buflen, result);
1476}
1477EXPORT_SYMBOL_GPL(nvme_set_features);
1478
1479int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid,
1480 unsigned int dword11, void *buffer, size_t buflen,
1481 u32 *result)
1482{
1483 return nvme_features(dev, nvme_admin_get_features, fid, dword11, buffer,
1484 buflen, result);
1485}
1486EXPORT_SYMBOL_GPL(nvme_get_features);
1487
9a0be7ab
CH
1488int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
1489{
1490 u32 q_count = (*count - 1) | ((*count - 1) << 16);
1491 u32 result;
1492 int status, nr_io_queues;
1493
1a6fe74d 1494 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 1495 &result);
f5fa90dc 1496 if (status < 0)
9a0be7ab
CH
1497 return status;
1498
f5fa90dc
CH
1499 /*
1500 * Degraded controllers might return an error when setting the queue
1501 * count. We still want to be able to bring them online and offer
1502 * access to the admin queue, as that might be only way to fix them up.
1503 */
1504 if (status > 0) {
f0425db0 1505 dev_err(ctrl->device, "Could not set queue count (%d)\n", status);
f5fa90dc
CH
1506 *count = 0;
1507 } else {
1508 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
1509 *count = min(*count, nr_io_queues);
1510 }
1511
9a0be7ab
CH
1512 return 0;
1513}
576d55d6 1514EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 1515
c0561f82 1516#define NVME_AEN_SUPPORTED \
85f8a435
SG
1517 (NVME_AEN_CFG_NS_ATTR | NVME_AEN_CFG_FW_ACT | \
1518 NVME_AEN_CFG_ANA_CHANGE | NVME_AEN_CFG_DISC_CHANGE)
c0561f82
HR
1519
1520static void nvme_enable_aen(struct nvme_ctrl *ctrl)
1521{
fa441b71 1522 u32 result, supported_aens = ctrl->oaes & NVME_AEN_SUPPORTED;
c0561f82
HR
1523 int status;
1524
fa441b71
WZ
1525 if (!supported_aens)
1526 return;
1527
1528 status = nvme_set_features(ctrl, NVME_FEAT_ASYNC_EVENT, supported_aens,
1529 NULL, 0, &result);
c0561f82
HR
1530 if (status)
1531 dev_warn(ctrl->device, "Failed to configure AEN (cfg %x)\n",
fa441b71 1532 supported_aens);
93da4023
SG
1533
1534 queue_work(nvme_wq, &ctrl->async_event_work);
c0561f82
HR
1535}
1536
f5b9a51d 1537static int nvme_ns_open(struct nvme_ns *ns)
c225b610 1538{
c225b610 1539
32acab31 1540 /* should never be called due to GENHD_FL_HIDDEN */
30897388 1541 if (WARN_ON_ONCE(nvme_ns_head_multipath(ns->head)))
85088c4a 1542 goto fail;
4c74d1f8 1543 if (!nvme_get_ns(ns))
85088c4a
NC
1544 goto fail;
1545 if (!try_module_get(ns->ctrl->ops->module))
1546 goto fail_put_ns;
1547
c6424a90 1548 return 0;
85088c4a
NC
1549
1550fail_put_ns:
1551 nvme_put_ns(ns);
1552fail:
1553 return -ENXIO;
1673f1f0
CH
1554}
1555
f5b9a51d 1556static void nvme_ns_release(struct nvme_ns *ns)
1673f1f0 1557{
85088c4a
NC
1558
1559 module_put(ns->ctrl->ops->module);
1560 nvme_put_ns(ns);
1673f1f0
CH
1561}
1562
f5b9a51d
CH
1563static int nvme_open(struct block_device *bdev, fmode_t mode)
1564{
1565 return nvme_ns_open(bdev->bd_disk->private_data);
1566}
1567
1568static void nvme_release(struct gendisk *disk, fmode_t mode)
1569{
1570 nvme_ns_release(disk->private_data);
1571}
1572
1496bd49 1573int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1673f1f0
CH
1574{
1575 /* some standard values */
1576 geo->heads = 1 << 6;
1577 geo->sectors = 1 << 5;
1578 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
1579 return 0;
1580}
1581
1582#ifdef CONFIG_BLK_DEV_INTEGRITY
95093350
MG
1583static void nvme_init_integrity(struct gendisk *disk, u16 ms, u8 pi_type,
1584 u32 max_integrity_segments)
1673f1f0 1585{
cc72c442 1586 struct blk_integrity integrity = { };
1673f1f0 1587
39b7baa4 1588 switch (pi_type) {
1673f1f0
CH
1589 case NVME_NS_DPS_PI_TYPE3:
1590 integrity.profile = &t10_pi_type3_crc;
ba36c21b
NB
1591 integrity.tag_size = sizeof(u16) + sizeof(u32);
1592 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH
1593 break;
1594 case NVME_NS_DPS_PI_TYPE1:
1595 case NVME_NS_DPS_PI_TYPE2:
1596 integrity.profile = &t10_pi_type1_crc;
ba36c21b
NB
1597 integrity.tag_size = sizeof(u16);
1598 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH
1599 break;
1600 default:
1601 integrity.profile = NULL;
1602 break;
1603 }
39b7baa4
CH
1604 integrity.tuple_size = ms;
1605 blk_integrity_register(disk, &integrity);
95093350 1606 blk_queue_max_integrity_segments(disk->queue, max_integrity_segments);
1673f1f0
CH
1607}
1608#else
95093350
MG
1609static void nvme_init_integrity(struct gendisk *disk, u16 ms, u8 pi_type,
1610 u32 max_integrity_segments)
1673f1f0
CH
1611{
1612}
1613#endif /* CONFIG_BLK_DEV_INTEGRITY */
1614
26318571 1615static void nvme_config_discard(struct gendisk *disk, struct nvme_ns *ns)
1673f1f0 1616{
3831761e 1617 struct nvme_ctrl *ctrl = ns->ctrl;
26318571 1618 struct request_queue *queue = disk->queue;
30e5e929
CH
1619 u32 size = queue_logical_block_size(queue);
1620
5befc7c2 1621 if (ctrl->max_discard_sectors == 0) {
3831761e
JA
1622 blk_queue_flag_clear(QUEUE_FLAG_DISCARD, queue);
1623 return;
1624 }
1625
1626 if (ctrl->nr_streams && ns->sws && ns->sgs)
1627 size *= ns->sws * ns->sgs;
08095e70 1628
b35ba01e
CH
1629 BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) <
1630 NVME_DSM_MAX_RANGES);
1631
b224f613 1632 queue->limits.discard_alignment = 0;
30e5e929 1633 queue->limits.discard_granularity = size;
f5d11840 1634
3831761e
JA
1635 /* If discard is already enabled, don't reset queue limits */
1636 if (blk_queue_flag_test_and_set(QUEUE_FLAG_DISCARD, queue))
1637 return;
1638
5befc7c2
KB
1639 blk_queue_max_discard_sectors(queue, ctrl->max_discard_sectors);
1640 blk_queue_max_discard_segments(queue, ctrl->max_discard_segments);
e850fd16
CH
1641
1642 if (ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
30e5e929 1643 blk_queue_max_write_zeroes_sectors(queue, UINT_MAX);
1673f1f0
CH
1644}
1645
ed754e5d
CH
1646static bool nvme_ns_ids_valid(struct nvme_ns_ids *ids)
1647{
1648 return !uuid_is_null(&ids->uuid) ||
1649 memchr_inv(ids->nguid, 0, sizeof(ids->nguid)) ||
1650 memchr_inv(ids->eui64, 0, sizeof(ids->eui64));
1651}
1652
002fab04
CH
1653static bool nvme_ns_ids_equal(struct nvme_ns_ids *a, struct nvme_ns_ids *b)
1654{
1655 return uuid_equal(&a->uuid, &b->uuid) &&
1656 memcmp(&a->nguid, &b->nguid, sizeof(a->nguid)) == 0 &&
71010c30
NC
1657 memcmp(&a->eui64, &b->eui64, sizeof(a->eui64)) == 0 &&
1658 a->csi == b->csi;
002fab04
CH
1659}
1660
31fdad7b
KB
1661static int nvme_setup_streams_ns(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1662 u32 *phys_bs, u32 *io_opt)
bc1af009
KB
1663{
1664 struct streams_directive_params s;
1665 int ret;
1666
1667 if (!ctrl->nr_streams)
1668 return 0;
1669
1670 ret = nvme_get_stream_params(ctrl, &s, ns->head->ns_id);
1671 if (ret)
1672 return ret;
1673
1674 ns->sws = le32_to_cpu(s.sws);
1675 ns->sgs = le16_to_cpu(s.sgs);
1676
1677 if (ns->sws) {
31fdad7b 1678 *phys_bs = ns->sws * (1 << ns->lba_shift);
bc1af009 1679 if (ns->sgs)
31fdad7b 1680 *io_opt = *phys_bs * ns->sgs;
bc1af009
KB
1681 }
1682
1683 return 0;
1684}
1685
d4609ea8
CH
1686static int nvme_configure_metadata(struct nvme_ns *ns, struct nvme_id_ns *id)
1687{
1688 struct nvme_ctrl *ctrl = ns->ctrl;
1689
1690 /*
1691 * The PI implementation requires the metadata size to be equal to the
1692 * t10 pi tuple size.
1693 */
1694 ns->ms = le16_to_cpu(id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ms);
1695 if (ns->ms == sizeof(struct t10_pi_tuple))
1696 ns->pi_type = id->dps & NVME_NS_DPS_PI_MASK;
1697 else
1698 ns->pi_type = 0;
1699
1700 ns->features &= ~(NVME_NS_METADATA_SUPPORTED | NVME_NS_EXT_LBAS);
1701 if (!ns->ms || !(ctrl->ops->flags & NVME_F_METADATA_SUPPORTED))
1702 return 0;
1703 if (ctrl->ops->flags & NVME_F_FABRICS) {
1704 /*
1705 * The NVMe over Fabrics specification only supports metadata as
1706 * part of the extended data LBA. We rely on HCA/HBA support to
1707 * remap the separate metadata buffer from the block layer.
1708 */
1709 if (WARN_ON_ONCE(!(id->flbas & NVME_NS_FLBAS_META_EXT)))
1710 return -EINVAL;
1711 if (ctrl->max_integrity_segments)
1712 ns->features |=
1713 (NVME_NS_METADATA_SUPPORTED | NVME_NS_EXT_LBAS);
1714 } else {
1715 /*
1716 * For PCIe controllers, we can't easily remap the separate
1717 * metadata buffer from the block layer and thus require a
1718 * separate metadata buffer for block layer metadata/PI support.
1719 * We allow extended LBAs for the passthrough interface, though.
1720 */
1721 if (id->flbas & NVME_NS_FLBAS_META_EXT)
1722 ns->features |= NVME_NS_EXT_LBAS;
1723 else
1724 ns->features |= NVME_NS_METADATA_SUPPORTED;
1725 }
1726
1727 return 0;
1728}
1729
658d9f7c
CH
1730static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
1731 struct request_queue *q)
1732{
c4485252 1733 bool vwc = ctrl->vwc & NVME_CTRL_VWC_PRESENT;
658d9f7c
CH
1734
1735 if (ctrl->max_hw_sectors) {
1736 u32 max_segments =
1737 (ctrl->max_hw_sectors / (NVME_CTRL_PAGE_SIZE >> 9)) + 1;
1738
1739 max_segments = min_not_zero(max_segments, ctrl->max_segments);
1740 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
1741 blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
1742 }
1743 blk_queue_virt_boundary(q, NVME_CTRL_PAGE_SIZE - 1);
1744 blk_queue_dma_alignment(q, 7);
658d9f7c
CH
1745 blk_queue_write_cache(q, vwc, vwc);
1746}
1747
24b0b58c
CH
1748static void nvme_update_disk_info(struct gendisk *disk,
1749 struct nvme_ns *ns, struct nvme_id_ns *id)
1750{
e08f2ae8 1751 sector_t capacity = nvme_lba_to_sect(ns, le64_to_cpu(id->nsze));
cee160fd 1752 unsigned short bs = 1 << ns->lba_shift;
68ab60ca 1753 u32 atomic_bs, phys_bs, io_opt = 0;
24b0b58c 1754
13f0b26b
CH
1755 /*
1756 * The block layer can't support LBA sizes larger than the page size
1757 * yet, so catch this early and don't allow block I/O.
1758 */
01fa0174 1759 if (ns->lba_shift > PAGE_SHIFT) {
13f0b26b 1760 capacity = 0;
01fa0174
SG
1761 bs = (1 << 9);
1762 }
f9d5f457 1763
24b0b58c
CH
1764 blk_integrity_unregister(disk);
1765
68ab60ca 1766 atomic_bs = phys_bs = bs;
31fdad7b 1767 nvme_setup_streams_ns(ns->ctrl, ns, &phys_bs, &io_opt);
81adb863
BVA
1768 if (id->nabo == 0) {
1769 /*
1770 * Bit 1 indicates whether NAWUPF is defined for this namespace
1771 * and whether it should be used instead of AWUPF. If NAWUPF ==
1772 * 0 then AWUPF must be used instead.
1773 */
92decf11 1774 if (id->nsfeat & NVME_NS_FEAT_ATOMICS && id->nawupf)
81adb863
BVA
1775 atomic_bs = (1 + le16_to_cpu(id->nawupf)) * bs;
1776 else
1777 atomic_bs = (1 + ns->ctrl->subsys->awupf) * bs;
81adb863 1778 }
31fdad7b 1779
92decf11 1780 if (id->nsfeat & NVME_NS_FEAT_IO_OPT) {
81adb863 1781 /* NPWG = Namespace Preferred Write Granularity */
31fdad7b 1782 phys_bs = bs * (1 + le16_to_cpu(id->npwg));
81adb863 1783 /* NOWS = Namespace Optimal Write Size */
31fdad7b 1784 io_opt = bs * (1 + le16_to_cpu(id->nows));
81adb863
BVA
1785 }
1786
cee160fd 1787 blk_queue_logical_block_size(disk->queue, bs);
81adb863
BVA
1788 /*
1789 * Linux filesystems assume writing a single physical block is
1790 * an atomic operation. Hence limit the physical block size to the
1791 * value of the Atomic Write Unit Power Fail parameter.
1792 */
1793 blk_queue_physical_block_size(disk->queue, min(phys_bs, atomic_bs));
1794 blk_queue_io_min(disk->queue, phys_bs);
1795 blk_queue_io_opt(disk->queue, io_opt);
cee160fd 1796
b29f8485
MG
1797 /*
1798 * Register a metadata profile for PI, or the plain non-integrity NVMe
1799 * metadata masquerading as Type 0 if supported, otherwise reject block
1800 * I/O to namespaces with metadata except when the namespace supports
1801 * PI, as it can strip/insert in that case.
1802 */
1803 if (ns->ms) {
1804 if (IS_ENABLED(CONFIG_BLK_DEV_INTEGRITY) &&
1805 (ns->features & NVME_NS_METADATA_SUPPORTED))
95093350
MG
1806 nvme_init_integrity(disk, ns->ms, ns->pi_type,
1807 ns->ctrl->max_integrity_segments);
b29f8485
MG
1808 else if (!nvme_ns_has_pi(ns))
1809 capacity = 0;
1810 }
1811
449f4ec9 1812 set_capacity_and_notify(disk, capacity);
b1aafb35 1813
26318571 1814 nvme_config_discard(disk, ns);
5befc7c2
KB
1815 blk_queue_max_write_zeroes_sectors(disk->queue,
1816 ns->ctrl->max_zeroes_sectors);
1293477f 1817
d11cd289
CH
1818 set_disk_ro(disk, (id->nsattr & NVME_NS_ATTR_RO) ||
1819 test_bit(NVME_NS_FORCE_RO, &ns->flags));
24b0b58c
CH
1820}
1821
e83d776f
KB
1822static inline bool nvme_first_scan(struct gendisk *disk)
1823{
1824 /* nvme_alloc_ns() scans the disk prior to adding it */
1825 return !(disk->flags & GENHD_FL_UP);
1826}
1827
1828static void nvme_set_chunk_sectors(struct nvme_ns *ns, struct nvme_id_ns *id)
1829{
1830 struct nvme_ctrl *ctrl = ns->ctrl;
1831 u32 iob;
1832
1833 if ((ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) &&
1834 is_power_of_2(ctrl->max_hw_sectors))
1835 iob = ctrl->max_hw_sectors;
1836 else
1837 iob = nvme_lba_to_sect(ns, le16_to_cpu(id->noiob));
1838
1839 if (!iob)
1840 return;
1841
1842 if (!is_power_of_2(iob)) {
1843 if (nvme_first_scan(ns->disk))
1844 pr_warn("%s: ignoring unaligned IO boundary:%u\n",
1845 ns->disk->disk_name, iob);
1846 return;
1847 }
1848
1849 if (blk_queue_is_zoned(ns->disk->queue)) {
1850 if (nvme_first_scan(ns->disk))
1851 pr_warn("%s: ignoring zoned namespace IO boundary\n",
1852 ns->disk->disk_name);
1853 return;
1854 }
1855
1856 blk_queue_chunk_sectors(ns->queue, iob);
1857}
1858
81382f17 1859static int nvme_update_ns_info(struct nvme_ns *ns, struct nvme_id_ns *id)
ac81bfa9 1860{
240e6ee2 1861 unsigned lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
240e6ee2 1862 int ret;
1673f1f0 1863
f9d5f457 1864 blk_mq_freeze_queue(ns->disk->queue);
240e6ee2 1865 ns->lba_shift = id->lbaf[lbaf].ds;
8b7c0ff2 1866 nvme_set_queue_limits(ns->ctrl, ns->queue);
38adf94e 1867
73d90386
DLM
1868 ret = nvme_configure_metadata(ns, id);
1869 if (ret)
1870 goto out_unfreeze;
1871 nvme_set_chunk_sectors(ns, id);
1872 nvme_update_disk_info(ns->disk, ns, id);
1873
8b7c0ff2 1874 if (ns->head->ids.csi == NVME_CSI_ZNS) {
d525c3c0 1875 ret = nvme_update_zone_info(ns, lbaf);
8b7c0ff2 1876 if (ret)
f9d5f457 1877 goto out_unfreeze;
71010c30
NC
1878 }
1879
f9d5f457 1880 blk_mq_unfreeze_queue(ns->disk->queue);
1673f1f0 1881
3a9967ba
CH
1882 if (blk_queue_is_zoned(ns->queue)) {
1883 ret = nvme_revalidate_zones(ns);
8685699c 1884 if (ret && !nvme_first_scan(ns->disk))
a9e0e6bc 1885 goto out;
b29f8485
MG
1886 }
1887
30897388 1888 if (nvme_ns_head_multipath(ns->head)) {
f9d5f457 1889 blk_mq_freeze_queue(ns->head->disk->queue);
32acab31 1890 nvme_update_disk_info(ns->head->disk, ns, id);
b9b1a5d7
CH
1891 blk_stack_limits(&ns->head->disk->queue->limits,
1892 &ns->queue->limits, 0);
471aa704 1893 disk_update_readahead(ns->head->disk);
f9d5f457 1894 blk_mq_unfreeze_queue(ns->head->disk->queue);
8f676b85 1895 }
33cfdc2a 1896 return 0;
ac81bfa9 1897
f9d5f457
CH
1898out_unfreeze:
1899 blk_mq_unfreeze_queue(ns->disk->queue);
a9e0e6bc
CH
1900out:
1901 /*
1902 * If probing fails due an unsupported feature, hide the block device,
1903 * but still allow other access.
1904 */
1905 if (ret == -ENODEV) {
1906 ns->disk->flags |= GENHD_FL_HIDDEN;
1907 ret = 0;
1908 }
240e6ee2
KB
1909 return ret;
1910}
1911
1673f1f0
CH
1912static char nvme_pr_type(enum pr_type type)
1913{
1914 switch (type) {
1915 case PR_WRITE_EXCLUSIVE:
1916 return 1;
1917 case PR_EXCLUSIVE_ACCESS:
1918 return 2;
1919 case PR_WRITE_EXCLUSIVE_REG_ONLY:
1920 return 3;
1921 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
1922 return 4;
1923 case PR_WRITE_EXCLUSIVE_ALL_REGS:
1924 return 5;
1925 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
1926 return 6;
1927 default:
1928 return 0;
1929 }
1930};
1931
f1cf35e1
CH
1932static int nvme_send_ns_head_pr_command(struct block_device *bdev,
1933 struct nvme_command *c, u8 data[16])
1934{
1935 struct nvme_ns_head *head = bdev->bd_disk->private_data;
1936 int srcu_idx = srcu_read_lock(&head->srcu);
1937 struct nvme_ns *ns = nvme_find_path(head);
1938 int ret = -EWOULDBLOCK;
1939
1940 if (ns) {
1941 c->common.nsid = cpu_to_le32(ns->head->ns_id);
1942 ret = nvme_submit_sync_cmd(ns->queue, c, data, 16);
1943 }
1944 srcu_read_unlock(&head->srcu, srcu_idx);
1945 return ret;
1946}
1947
1948static int nvme_send_ns_pr_command(struct nvme_ns *ns, struct nvme_command *c,
1949 u8 data[16])
1950{
1951 c->common.nsid = cpu_to_le32(ns->head->ns_id);
1952 return nvme_submit_sync_cmd(ns->queue, c, data, 16);
1953}
1954
1673f1f0
CH
1955static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
1956 u64 key, u64 sa_key, u8 op)
1957{
cc72c442 1958 struct nvme_command c = { };
1673f1f0
CH
1959 u8 data[16] = { 0, };
1960
1961 put_unaligned_le64(key, &data[0]);
1962 put_unaligned_le64(sa_key, &data[8]);
1963
1673f1f0 1964 c.common.opcode = op;
b7c8f366 1965 c.common.cdw10 = cpu_to_le32(cdw10);
1673f1f0 1966
f1cf35e1
CH
1967 if (IS_ENABLED(CONFIG_NVME_MULTIPATH) &&
1968 bdev->bd_disk->fops == &nvme_ns_head_ops)
1969 return nvme_send_ns_head_pr_command(bdev, &c, data);
1970 return nvme_send_ns_pr_command(bdev->bd_disk->private_data, &c, data);
1673f1f0
CH
1971}
1972
1973static int nvme_pr_register(struct block_device *bdev, u64 old,
1974 u64 new, unsigned flags)
1975{
1976 u32 cdw10;
1977
1978 if (flags & ~PR_FL_IGNORE_KEY)
1979 return -EOPNOTSUPP;
1980
1981 cdw10 = old ? 2 : 0;
1982 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
1983 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
1984 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
1985}
1986
1987static int nvme_pr_reserve(struct block_device *bdev, u64 key,
1988 enum pr_type type, unsigned flags)
1989{
1990 u32 cdw10;
1991
1992 if (flags & ~PR_FL_IGNORE_KEY)
1993 return -EOPNOTSUPP;
1994
1995 cdw10 = nvme_pr_type(type) << 8;
1996 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
1997 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
1998}
1999
2000static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
2001 enum pr_type type, bool abort)
2002{
e9a9853c 2003 u32 cdw10 = nvme_pr_type(type) << 8 | (abort ? 2 : 1);
f1c772d5 2004
1673f1f0
CH
2005 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
2006}
2007
2008static int nvme_pr_clear(struct block_device *bdev, u64 key)
2009{
8c0b3915 2010 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
f1c772d5 2011
1673f1f0
CH
2012 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
2013}
2014
2015static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
2016{
e9a9853c 2017 u32 cdw10 = nvme_pr_type(type) << 8 | (key ? 1 << 3 : 0);
f1c772d5 2018
1673f1f0
CH
2019 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
2020}
2021
1496bd49 2022const struct pr_ops nvme_pr_ops = {
1673f1f0
CH
2023 .pr_register = nvme_pr_register,
2024 .pr_reserve = nvme_pr_reserve,
2025 .pr_release = nvme_pr_release,
2026 .pr_preempt = nvme_pr_preempt,
2027 .pr_clear = nvme_pr_clear,
2028};
2029
a98e58e5 2030#ifdef CONFIG_BLK_SED_OPAL
4f1244c8
CH
2031int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
2032 bool send)
a98e58e5 2033{
4f1244c8 2034 struct nvme_ctrl *ctrl = data;
cc72c442 2035 struct nvme_command cmd = { };
a98e58e5 2036
a98e58e5
SB
2037 if (send)
2038 cmd.common.opcode = nvme_admin_security_send;
2039 else
2040 cmd.common.opcode = nvme_admin_security_recv;
a98e58e5 2041 cmd.common.nsid = 0;
b7c8f366
CK
2042 cmd.common.cdw10 = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
2043 cmd.common.cdw11 = cpu_to_le32(len);
a98e58e5 2044
dc96f938 2045 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len, 0,
be42a33b 2046 NVME_QID_ANY, 1, 0);
a98e58e5
SB
2047}
2048EXPORT_SYMBOL_GPL(nvme_sec_submit);
2049#endif /* CONFIG_BLK_SED_OPAL */
2050
8b4fb0f9
CH
2051#ifdef CONFIG_BLK_DEV_ZONED
2052static int nvme_report_zones(struct gendisk *disk, sector_t sector,
2053 unsigned int nr_zones, report_zones_cb cb, void *data)
2054{
2055 return nvme_ns_report_zones(disk->private_data, sector, nr_zones, cb,
2056 data);
2057}
2058#else
2059#define nvme_report_zones NULL
2060#endif /* CONFIG_BLK_DEV_ZONED */
2061
ba4fb320 2062static const struct block_device_operations nvme_bdev_ops = {
1673f1f0
CH
2063 .owner = THIS_MODULE,
2064 .ioctl = nvme_ioctl,
1673f1f0
CH
2065 .open = nvme_open,
2066 .release = nvme_release,
2067 .getgeo = nvme_getgeo,
240e6ee2 2068 .report_zones = nvme_report_zones,
1673f1f0
CH
2069 .pr_ops = &nvme_pr_ops,
2070};
2071
5fd4ce1b
CH
2072static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
2073{
2074 unsigned long timeout =
2075 ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
2076 u32 csts, bit = enabled ? NVME_CSTS_RDY : 0;
2077 int ret;
2078
2079 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB
2080 if (csts == ~0)
2081 return -ENODEV;
5fd4ce1b
CH
2082 if ((csts & NVME_CSTS_RDY) == bit)
2083 break;
2084
3e98c244 2085 usleep_range(1000, 2000);
5fd4ce1b
CH
2086 if (fatal_signal_pending(current))
2087 return -EINTR;
2088 if (time_after(jiffies, timeout)) {
1b3c47c1 2089 dev_err(ctrl->device,
94d2e705
RG
2090 "Device not ready; aborting %s, CSTS=0x%x\n",
2091 enabled ? "initialisation" : "reset", csts);
5fd4ce1b
CH
2092 return -ENODEV;
2093 }
2094 }
2095
2096 return ret;
2097}
2098
2099/*
2100 * If the device has been passed off to us in an enabled state, just clear
2101 * the enabled bit. The spec says we should set the 'shutdown notification
2102 * bits', but doing so may cause the device to complete commands to the
2103 * admin queue ... and we don't know what memory that might be pointing at!
2104 */
b5b05048 2105int nvme_disable_ctrl(struct nvme_ctrl *ctrl)
5fd4ce1b
CH
2106{
2107 int ret;
2108
2109 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
2110 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
2111
2112 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2113 if (ret)
2114 return ret;
54adc010 2115
b5a10c5f 2116 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010
GP
2117 msleep(NVME_QUIRK_DELAY_AMOUNT);
2118
b5b05048 2119 return nvme_wait_ready(ctrl, ctrl->cap, false);
5fd4ce1b 2120}
576d55d6 2121EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b 2122
c0f2f45b 2123int nvme_enable_ctrl(struct nvme_ctrl *ctrl)
5fd4ce1b 2124{
6c3c05b0 2125 unsigned dev_page_min;
5fd4ce1b
CH
2126 int ret;
2127
c0f2f45b
SG
2128 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &ctrl->cap);
2129 if (ret) {
2130 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
2131 return ret;
2132 }
2133 dev_page_min = NVME_CAP_MPSMIN(ctrl->cap) + 12;
2134
6c3c05b0 2135 if (NVME_CTRL_PAGE_SHIFT < dev_page_min) {
1b3c47c1 2136 dev_err(ctrl->device,
5fd4ce1b 2137 "Minimum device page size %u too large for host (%u)\n",
6c3c05b0 2138 1 << dev_page_min, 1 << NVME_CTRL_PAGE_SHIFT);
5fd4ce1b
CH
2139 return -ENODEV;
2140 }
2141
71010c30
NC
2142 if (NVME_CAP_CSS(ctrl->cap) & NVME_CAP_CSS_CSI)
2143 ctrl->ctrl_config = NVME_CC_CSS_CSI;
2144 else
2145 ctrl->ctrl_config = NVME_CC_CSS_NVM;
6c3c05b0 2146 ctrl->ctrl_config |= (NVME_CTRL_PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
60b43f62 2147 ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;
5fd4ce1b
CH
2148 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
2149 ctrl->ctrl_config |= NVME_CC_ENABLE;
2150
2151 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2152 if (ret)
2153 return ret;
c0f2f45b 2154 return nvme_wait_ready(ctrl, ctrl->cap, true);
5fd4ce1b 2155}
576d55d6 2156EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b
CH
2157
2158int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl)
2159{
07fbd32a 2160 unsigned long timeout = jiffies + (ctrl->shutdown_timeout * HZ);
5fd4ce1b
CH
2161 u32 csts;
2162 int ret;
2163
2164 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
2165 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
2166
2167 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2168 if (ret)
2169 return ret;
2170
2171 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
2172 if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_CMPLT)
2173 break;
2174
2175 msleep(100);
2176 if (fatal_signal_pending(current))
2177 return -EINTR;
2178 if (time_after(jiffies, timeout)) {
1b3c47c1 2179 dev_err(ctrl->device,
5fd4ce1b
CH
2180 "Device shutdown incomplete; abort shutdown\n");
2181 return -ENODEV;
2182 }
2183 }
2184
2185 return ret;
2186}
576d55d6 2187EXPORT_SYMBOL_GPL(nvme_shutdown_ctrl);
5fd4ce1b 2188
dbf86b39
JD
2189static int nvme_configure_timestamp(struct nvme_ctrl *ctrl)
2190{
2191 __le64 ts;
2192 int ret;
2193
2194 if (!(ctrl->oncs & NVME_CTRL_ONCS_TIMESTAMP))
2195 return 0;
2196
2197 ts = cpu_to_le64(ktime_to_ms(ktime_get_real()));
2198 ret = nvme_set_features(ctrl, NVME_FEAT_TIMESTAMP, 0, &ts, sizeof(ts),
2199 NULL);
2200 if (ret)
2201 dev_warn_once(ctrl->device,
2202 "could not set timestamp (%d)\n", ret);
2203 return ret;
2204}
2205
49cd84b6
KB
2206static int nvme_configure_acre(struct nvme_ctrl *ctrl)
2207{
2208 struct nvme_feat_host_behavior *host;
2209 int ret;
2210
2211 /* Don't bother enabling the feature if retry delay is not reported */
2212 if (!ctrl->crdt[0])
2213 return 0;
2214
2215 host = kzalloc(sizeof(*host), GFP_KERNEL);
2216 if (!host)
2217 return 0;
2218
2219 host->acre = NVME_ENABLE_ACRE;
2220 ret = nvme_set_features(ctrl, NVME_FEAT_HOST_BEHAVIOR, 0,
2221 host, sizeof(*host), NULL);
2222 kfree(host);
2223 return ret;
2224}
2225
ebd8a93a
AB
2226/*
2227 * The function checks whether the given total (exlat + enlat) latency of
2228 * a power state allows the latter to be used as an APST transition target.
2229 * It does so by comparing the latency to the primary and secondary latency
2230 * tolerances defined by module params. If there's a match, the corresponding
2231 * timeout value is returned and the matching tolerance index (1 or 2) is
2232 * reported.
2233 */
2234static bool nvme_apst_get_transition_time(u64 total_latency,
2235 u64 *transition_time, unsigned *last_index)
2236{
2237 if (total_latency <= apst_primary_latency_tol_us) {
2238 if (*last_index == 1)
2239 return false;
2240 *last_index = 1;
2241 *transition_time = apst_primary_timeout_ms;
2242 return true;
2243 }
2244 if (apst_secondary_timeout_ms &&
2245 total_latency <= apst_secondary_latency_tol_us) {
2246 if (*last_index <= 2)
2247 return false;
2248 *last_index = 2;
2249 *transition_time = apst_secondary_timeout_ms;
2250 return true;
2251 }
2252 return false;
2253}
2254
60df5de9
CH
2255/*
2256 * APST (Autonomous Power State Transition) lets us program a table of power
2257 * state transitions that the controller will perform automatically.
ebd8a93a
AB
2258 *
2259 * Depending on module params, one of the two supported techniques will be used:
2260 *
2261 * - If the parameters provide explicit timeouts and tolerances, they will be
2262 * used to build a table with up to 2 non-operational states to transition to.
2263 * The default parameter values were selected based on the values used by
2264 * Microsoft's and Intel's NVMe drivers. Yet, since we don't implement dynamic
2265 * regeneration of the APST table in the event of switching between external
2266 * and battery power, the timeouts and tolerances reflect a compromise
2267 * between values used by Microsoft for AC and battery scenarios.
2268 * - If not, we'll configure the table with a simple heuristic: we are willing
2269 * to spend at most 2% of the time transitioning between power states.
2270 * Therefore, when running in any given state, we will enter the next
2271 * lower-power non-operational state after waiting 50 * (enlat + exlat)
2272 * microseconds, as long as that state's exit latency is under the requested
2273 * maximum latency.
60df5de9
CH
2274 *
2275 * We will not autonomously enter any non-operational state for which the total
2276 * latency exceeds ps_max_latency_us.
2277 *
2278 * Users can set ps_max_latency_us to zero to turn off APST.
2279 */
634b8325 2280static int nvme_configure_apst(struct nvme_ctrl *ctrl)
c5552fde 2281{
c5552fde 2282 struct nvme_feat_auto_pst *table;
60df5de9 2283 unsigned apste = 0;
fb0dc399 2284 u64 max_lat_us = 0;
60df5de9 2285 __le64 target = 0;
fb0dc399 2286 int max_ps = -1;
60df5de9 2287 int state;
c5552fde 2288 int ret;
ebd8a93a 2289 unsigned last_lt_index = UINT_MAX;
c5552fde
AL
2290
2291 /*
2292 * If APST isn't supported or if we haven't been initialized yet,
2293 * then don't do anything.
2294 */
2295 if (!ctrl->apsta)
634b8325 2296 return 0;
c5552fde
AL
2297
2298 if (ctrl->npss > 31) {
2299 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
634b8325 2300 return 0;
c5552fde
AL
2301 }
2302
2303 table = kzalloc(sizeof(*table), GFP_KERNEL);
2304 if (!table)
634b8325 2305 return 0;
c5552fde 2306
76a5af84 2307 if (!ctrl->apst_enabled || ctrl->ps_max_latency_us == 0) {
c5552fde 2308 /* Turn off APST. */
fb0dc399 2309 dev_dbg(ctrl->device, "APST disabled\n");
60df5de9
CH
2310 goto done;
2311 }
c5552fde 2312
60df5de9
CH
2313 /*
2314 * Walk through all states from lowest- to highest-power.
2315 * According to the spec, lower-numbered states use more power. NPSS,
2316 * despite the name, is the index of the lowest-power state, not the
2317 * number of states.
2318 */
2319 for (state = (int)ctrl->npss; state >= 0; state--) {
2320 u64 total_latency_us, exit_latency_us, transition_ms;
da87591b 2321
60df5de9
CH
2322 if (target)
2323 table->entries[state] = target;
c5552fde 2324
c5552fde 2325 /*
60df5de9
CH
2326 * Don't allow transitions to the deepest state if it's quirked
2327 * off.
c5552fde 2328 */
60df5de9
CH
2329 if (state == ctrl->npss &&
2330 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
2331 continue;
fb0dc399 2332
60df5de9
CH
2333 /*
2334 * Is this state a useful non-operational state for higher-power
2335 * states to autonomously transition to?
2336 */
2337 if (!(ctrl->psd[state].flags & NVME_PS_FLAGS_NON_OP_STATE))
2338 continue;
fb0dc399 2339
60df5de9
CH
2340 exit_latency_us = (u64)le32_to_cpu(ctrl->psd[state].exit_lat);
2341 if (exit_latency_us > ctrl->ps_max_latency_us)
2342 continue;
c5552fde 2343
60df5de9
CH
2344 total_latency_us = exit_latency_us +
2345 le32_to_cpu(ctrl->psd[state].entry_lat);
fb0dc399 2346
60df5de9 2347 /*
ebd8a93a
AB
2348 * This state is good. It can be used as the APST idle target
2349 * for higher power states.
60df5de9 2350 */
ebd8a93a
AB
2351 if (apst_primary_timeout_ms && apst_primary_latency_tol_us) {
2352 if (!nvme_apst_get_transition_time(total_latency_us,
2353 &transition_ms, &last_lt_index))
2354 continue;
2355 } else {
2356 transition_ms = total_latency_us + 19;
2357 do_div(transition_ms, 20);
2358 if (transition_ms > (1 << 24) - 1)
2359 transition_ms = (1 << 24) - 1;
2360 }
60df5de9
CH
2361
2362 target = cpu_to_le64((state << 3) | (transition_ms << 8));
2363 if (max_ps == -1)
2364 max_ps = state;
2365 if (total_latency_us > max_lat_us)
2366 max_lat_us = total_latency_us;
c5552fde
AL
2367 }
2368
60df5de9
CH
2369 if (max_ps == -1)
2370 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n");
2371 else
2372 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n",
2373 max_ps, max_lat_us, (int)sizeof(*table), table);
2374 apste = 1;
2375
2376done:
c5552fde
AL
2377 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
2378 table, sizeof(*table), NULL);
2379 if (ret)
2380 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
c5552fde 2381 kfree(table);
634b8325 2382 return ret;
c5552fde
AL
2383}
2384
2385static void nvme_set_latency_tolerance(struct device *dev, s32 val)
2386{
2387 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2388 u64 latency;
2389
2390 switch (val) {
2391 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
2392 case PM_QOS_LATENCY_ANY:
2393 latency = U64_MAX;
2394 break;
2395
2396 default:
2397 latency = val;
2398 }
2399
2400 if (ctrl->ps_max_latency_us != latency) {
2401 ctrl->ps_max_latency_us = latency;
53fe2a30
CH
2402 if (ctrl->state == NVME_CTRL_LIVE)
2403 nvme_configure_apst(ctrl);
c5552fde
AL
2404 }
2405}
2406
bd4da3ab
AL
2407struct nvme_core_quirk_entry {
2408 /*
2409 * NVMe model and firmware strings are padded with spaces. For
2410 * simplicity, strings in the quirk table are padded with NULLs
2411 * instead.
2412 */
2413 u16 vid;
2414 const char *mn;
2415 const char *fr;
2416 unsigned long quirks;
2417};
2418
2419static const struct nvme_core_quirk_entry core_quirks[] = {
c5552fde 2420 {
be56945c
AL
2421 /*
2422 * This Toshiba device seems to die using any APST states. See:
2423 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
2424 */
2425 .vid = 0x1179,
2426 .mn = "THNSF5256GPUK TOSHIBA",
c5552fde 2427 .quirks = NVME_QUIRK_NO_APST,
cb32de1b
ML
2428 },
2429 {
2430 /*
2431 * This LiteON CL1-3D*-Q11 firmware version has a race
2432 * condition associated with actions related to suspend to idle
2433 * LiteON has resolved the problem in future firmware
2434 */
2435 .vid = 0x14a4,
2436 .fr = "22301111",
2437 .quirks = NVME_QUIRK_SIMPLE_SUSPEND,
be56945c 2438 }
bd4da3ab
AL
2439};
2440
2441/* match is null-terminated but idstr is space-padded. */
2442static bool string_matches(const char *idstr, const char *match, size_t len)
2443{
2444 size_t matchlen;
2445
2446 if (!match)
2447 return true;
2448
2449 matchlen = strlen(match);
2450 WARN_ON_ONCE(matchlen > len);
2451
2452 if (memcmp(idstr, match, matchlen))
2453 return false;
2454
2455 for (; matchlen < len; matchlen++)
2456 if (idstr[matchlen] != ' ')
2457 return false;
2458
2459 return true;
2460}
2461
2462static bool quirk_matches(const struct nvme_id_ctrl *id,
2463 const struct nvme_core_quirk_entry *q)
2464{
2465 return q->vid == le16_to_cpu(id->vid) &&
2466 string_matches(id->mn, q->mn, sizeof(id->mn)) &&
2467 string_matches(id->fr, q->fr, sizeof(id->fr));
2468}
2469
ab9e00cc
CH
2470static void nvme_init_subnqn(struct nvme_subsystem *subsys, struct nvme_ctrl *ctrl,
2471 struct nvme_id_ctrl *id)
180de007
CH
2472{
2473 size_t nqnlen;
2474 int off;
2475
6299358d
JD
2476 if(!(ctrl->quirks & NVME_QUIRK_IGNORE_DEV_SUBNQN)) {
2477 nqnlen = strnlen(id->subnqn, NVMF_NQN_SIZE);
2478 if (nqnlen > 0 && nqnlen < NVMF_NQN_SIZE) {
2479 strlcpy(subsys->subnqn, id->subnqn, NVMF_NQN_SIZE);
2480 return;
2481 }
180de007 2482
6299358d
JD
2483 if (ctrl->vs >= NVME_VS(1, 2, 1))
2484 dev_warn(ctrl->device, "missing or invalid SUBNQN field.\n");
2485 }
180de007
CH
2486
2487 /* Generate a "fake" NQN per Figure 254 in NVMe 1.3 + ECN 001 */
ab9e00cc 2488 off = snprintf(subsys->subnqn, NVMF_NQN_SIZE,
3da584f5 2489 "nqn.2014.08.org.nvmexpress:%04x%04x",
180de007 2490 le16_to_cpu(id->vid), le16_to_cpu(id->ssvid));
ab9e00cc 2491 memcpy(subsys->subnqn + off, id->sn, sizeof(id->sn));
180de007 2492 off += sizeof(id->sn);
ab9e00cc 2493 memcpy(subsys->subnqn + off, id->mn, sizeof(id->mn));
180de007 2494 off += sizeof(id->mn);
ab9e00cc
CH
2495 memset(subsys->subnqn + off, 0, sizeof(subsys->subnqn) - off);
2496}
2497
e654dfd3 2498static void nvme_release_subsystem(struct device *dev)
ab9e00cc 2499{
e654dfd3
LG
2500 struct nvme_subsystem *subsys =
2501 container_of(dev, struct nvme_subsystem, dev);
2502
733e4b69
KB
2503 if (subsys->instance >= 0)
2504 ida_simple_remove(&nvme_instance_ida, subsys->instance);
ab9e00cc
CH
2505 kfree(subsys);
2506}
2507
ab9e00cc
CH
2508static void nvme_destroy_subsystem(struct kref *ref)
2509{
2510 struct nvme_subsystem *subsys =
2511 container_of(ref, struct nvme_subsystem, ref);
2512
2513 mutex_lock(&nvme_subsystems_lock);
2514 list_del(&subsys->entry);
2515 mutex_unlock(&nvme_subsystems_lock);
2516
ed754e5d 2517 ida_destroy(&subsys->ns_ida);
ab9e00cc
CH
2518 device_del(&subsys->dev);
2519 put_device(&subsys->dev);
2520}
2521
2522static void nvme_put_subsystem(struct nvme_subsystem *subsys)
2523{
2524 kref_put(&subsys->ref, nvme_destroy_subsystem);
2525}
2526
2527static struct nvme_subsystem *__nvme_find_get_subsystem(const char *subsysnqn)
2528{
2529 struct nvme_subsystem *subsys;
2530
2531 lockdep_assert_held(&nvme_subsystems_lock);
2532
c26aa572
JS
2533 /*
2534 * Fail matches for discovery subsystems. This results
2535 * in each discovery controller bound to a unique subsystem.
2536 * This avoids issues with validating controller values
2537 * that can only be true when there is a single unique subsystem.
2538 * There may be multiple and completely independent entities
2539 * that provide discovery controllers.
2540 */
2541 if (!strcmp(subsysnqn, NVME_DISC_SUBSYS_NAME))
2542 return NULL;
2543
ab9e00cc
CH
2544 list_for_each_entry(subsys, &nvme_subsystems, entry) {
2545 if (strcmp(subsys->subnqn, subsysnqn))
2546 continue;
2547 if (!kref_get_unless_zero(&subsys->ref))
2548 continue;
2549 return subsys;
2550 }
2551
2552 return NULL;
2553}
2554
1e496938
HR
2555#define SUBSYS_ATTR_RO(_name, _mode, _show) \
2556 struct device_attribute subsys_attr_##_name = \
2557 __ATTR(_name, _mode, _show, NULL)
2558
2559static ssize_t nvme_subsys_show_nqn(struct device *dev,
2560 struct device_attribute *attr,
2561 char *buf)
2562{
2563 struct nvme_subsystem *subsys =
2564 container_of(dev, struct nvme_subsystem, dev);
2565
f720a8ed 2566 return sysfs_emit(buf, "%s\n", subsys->subnqn);
1e496938
HR
2567}
2568static SUBSYS_ATTR_RO(subsysnqn, S_IRUGO, nvme_subsys_show_nqn);
2569
2570#define nvme_subsys_show_str_function(field) \
2571static ssize_t subsys_##field##_show(struct device *dev, \
2572 struct device_attribute *attr, char *buf) \
2573{ \
2574 struct nvme_subsystem *subsys = \
2575 container_of(dev, struct nvme_subsystem, dev); \
bff4bcf3
DW
2576 return sysfs_emit(buf, "%.*s\n", \
2577 (int)sizeof(subsys->field), subsys->field); \
1e496938
HR
2578} \
2579static SUBSYS_ATTR_RO(field, S_IRUGO, subsys_##field##_show);
2580
2581nvme_subsys_show_str_function(model);
2582nvme_subsys_show_str_function(serial);
2583nvme_subsys_show_str_function(firmware_rev);
2584
2585static struct attribute *nvme_subsys_attrs[] = {
2586 &subsys_attr_model.attr,
2587 &subsys_attr_serial.attr,
2588 &subsys_attr_firmware_rev.attr,
2589 &subsys_attr_subsysnqn.attr,
75c10e73
HR
2590#ifdef CONFIG_NVME_MULTIPATH
2591 &subsys_attr_iopolicy.attr,
2592#endif
1e496938
HR
2593 NULL,
2594};
2595
60b152a5 2596static const struct attribute_group nvme_subsys_attrs_group = {
1e496938
HR
2597 .attrs = nvme_subsys_attrs,
2598};
2599
2600static const struct attribute_group *nvme_subsys_attrs_groups[] = {
2601 &nvme_subsys_attrs_group,
2602 NULL,
2603};
2604
5ab25a32
SG
2605static inline bool nvme_discovery_ctrl(struct nvme_ctrl *ctrl)
2606{
2607 return ctrl->opts && ctrl->opts->discovery_nqn;
2608}
2609
1b1031ca
CH
2610static bool nvme_validate_cntlid(struct nvme_subsystem *subsys,
2611 struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
b837b283 2612{
1b1031ca 2613 struct nvme_ctrl *tmp;
b837b283 2614
32fd90c4
CH
2615 lockdep_assert_held(&nvme_subsystems_lock);
2616
1b1031ca 2617 list_for_each_entry(tmp, &subsys->ctrls, subsys_entry) {
e7c43fea 2618 if (nvme_state_terminal(tmp))
1b1031ca
CH
2619 continue;
2620
2621 if (tmp->cntlid == ctrl->cntlid) {
2622 dev_err(ctrl->device,
2623 "Duplicate cntlid %u with %s, rejecting\n",
2624 ctrl->cntlid, dev_name(tmp->device));
2625 return false;
2626 }
b837b283 2627
92decf11 2628 if ((id->cmic & NVME_CTRL_CMIC_MULTI_CTRL) ||
5ab25a32 2629 nvme_discovery_ctrl(ctrl))
1b1031ca
CH
2630 continue;
2631
2632 dev_err(ctrl->device,
2633 "Subsystem does not support multiple controllers\n");
2634 return false;
b837b283 2635 }
b837b283 2636
1b1031ca 2637 return true;
b837b283
IR
2638}
2639
ab9e00cc
CH
2640static int nvme_init_subsystem(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
2641{
2642 struct nvme_subsystem *subsys, *found;
2643 int ret;
2644
2645 subsys = kzalloc(sizeof(*subsys), GFP_KERNEL);
2646 if (!subsys)
2647 return -ENOMEM;
733e4b69
KB
2648
2649 subsys->instance = -1;
ab9e00cc
CH
2650 mutex_init(&subsys->lock);
2651 kref_init(&subsys->ref);
2652 INIT_LIST_HEAD(&subsys->ctrls);
ed754e5d 2653 INIT_LIST_HEAD(&subsys->nsheads);
ab9e00cc
CH
2654 nvme_init_subnqn(subsys, ctrl, id);
2655 memcpy(subsys->serial, id->sn, sizeof(subsys->serial));
2656 memcpy(subsys->model, id->mn, sizeof(subsys->model));
2657 memcpy(subsys->firmware_rev, id->fr, sizeof(subsys->firmware_rev));
2658 subsys->vendor_id = le16_to_cpu(id->vid);
2659 subsys->cmic = id->cmic;
81adb863 2660 subsys->awupf = le16_to_cpu(id->awupf);
75c10e73
HR
2661#ifdef CONFIG_NVME_MULTIPATH
2662 subsys->iopolicy = NVME_IOPOLICY_NUMA;
2663#endif
ab9e00cc
CH
2664
2665 subsys->dev.class = nvme_subsys_class;
2666 subsys->dev.release = nvme_release_subsystem;
1e496938 2667 subsys->dev.groups = nvme_subsys_attrs_groups;
733e4b69 2668 dev_set_name(&subsys->dev, "nvme-subsys%d", ctrl->instance);
ab9e00cc
CH
2669 device_initialize(&subsys->dev);
2670
2671 mutex_lock(&nvme_subsystems_lock);
2672 found = __nvme_find_get_subsystem(subsys->subnqn);
2673 if (found) {
e654dfd3 2674 put_device(&subsys->dev);
ab9e00cc 2675 subsys = found;
32fd90c4 2676
1b1031ca 2677 if (!nvme_validate_cntlid(subsys, ctrl, id)) {
ab9e00cc 2678 ret = -EINVAL;
32fd90c4 2679 goto out_put_subsystem;
ab9e00cc 2680 }
ab9e00cc
CH
2681 } else {
2682 ret = device_add(&subsys->dev);
2683 if (ret) {
2684 dev_err(ctrl->device,
2685 "failed to register subsystem device.\n");
8c36e66f 2686 put_device(&subsys->dev);
ab9e00cc
CH
2687 goto out_unlock;
2688 }
ed754e5d 2689 ida_init(&subsys->ns_ida);
ab9e00cc
CH
2690 list_add_tail(&subsys->entry, &nvme_subsystems);
2691 }
2692
bc4f6e06
DC
2693 ret = sysfs_create_link(&subsys->dev.kobj, &ctrl->device->kobj,
2694 dev_name(ctrl->device));
2695 if (ret) {
ab9e00cc
CH
2696 dev_err(ctrl->device,
2697 "failed to create sysfs link from subsystem.\n");
32fd90c4 2698 goto out_put_subsystem;
ab9e00cc
CH
2699 }
2700
733e4b69
KB
2701 if (!found)
2702 subsys->instance = ctrl->instance;
32fd90c4 2703 ctrl->subsys = subsys;
ab9e00cc 2704 list_add_tail(&ctrl->subsys_entry, &subsys->ctrls);
32fd90c4 2705 mutex_unlock(&nvme_subsystems_lock);
ab9e00cc
CH
2706 return 0;
2707
32fd90c4
CH
2708out_put_subsystem:
2709 nvme_put_subsystem(subsys);
ab9e00cc
CH
2710out_unlock:
2711 mutex_unlock(&nvme_subsystems_lock);
ab9e00cc 2712 return ret;
180de007
CH
2713}
2714
be93e87e 2715int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, u8 csi,
0e98719b 2716 void *log, size_t size, u64 offset)
c627c487
KB
2717{
2718 struct nvme_command c = { };
71fb90eb 2719 u32 dwlen = nvme_bytes_to_numd(size);
70da6094
MB
2720
2721 c.get_log_page.opcode = nvme_admin_get_log_page;
0e98719b 2722 c.get_log_page.nsid = cpu_to_le32(nsid);
70da6094 2723 c.get_log_page.lid = log_page;
0e98719b 2724 c.get_log_page.lsp = lsp;
70da6094
MB
2725 c.get_log_page.numdl = cpu_to_le16(dwlen & ((1 << 16) - 1));
2726 c.get_log_page.numdu = cpu_to_le16(dwlen >> 16);
7ec6074f
MB
2727 c.get_log_page.lpol = cpu_to_le32(lower_32_bits(offset));
2728 c.get_log_page.lpou = cpu_to_le32(upper_32_bits(offset));
be93e87e 2729 c.get_log_page.csi = csi;
c627c487
KB
2730
2731 return nvme_submit_sync_cmd(ctrl->admin_q, &c, log, size);
2732}
2733
be93e87e
KB
2734static int nvme_get_effects_log(struct nvme_ctrl *ctrl, u8 csi,
2735 struct nvme_effects_log **log)
84fef62d 2736{
f6224b86 2737 struct nvme_effects_log *cel = xa_load(&ctrl->cels, csi);
84fef62d
KB
2738 int ret;
2739
be93e87e
KB
2740 if (cel)
2741 goto out;
84fef62d 2742
be93e87e
KB
2743 cel = kzalloc(sizeof(*cel), GFP_KERNEL);
2744 if (!cel)
2745 return -ENOMEM;
84fef62d 2746
46d2613e 2747 ret = nvme_get_log(ctrl, 0x00, NVME_LOG_CMD_EFFECTS, 0, csi,
f6224b86 2748 cel, sizeof(*cel), 0);
84fef62d 2749 if (ret) {
be93e87e
KB
2750 kfree(cel);
2751 return ret;
84fef62d 2752 }
be93e87e 2753
f6224b86 2754 xa_store(&ctrl->cels, csi, cel, GFP_KERNEL);
be93e87e 2755out:
f6224b86 2756 *log = cel;
be93e87e 2757 return 0;
180de007
CH
2758}
2759
5befc7c2 2760static inline u32 nvme_mps_to_sectors(struct nvme_ctrl *ctrl, u32 units)
7fd8930f 2761{
8609c63f 2762 u32 page_shift = NVME_CAP_MPSMIN(ctrl->cap) + 12, val;
7fd8930f 2763
8609c63f
BVA
2764 if (check_shl_overflow(1U, units + page_shift - 9, &val))
2765 return UINT_MAX;
2766 return val;
5befc7c2
KB
2767}
2768
2769static int nvme_init_non_mdts_limits(struct nvme_ctrl *ctrl)
2770{
2771 struct nvme_command c = { };
2772 struct nvme_id_ctrl_nvm *id;
2773 int ret;
2774
2775 if (ctrl->oncs & NVME_CTRL_ONCS_DSM) {
2776 ctrl->max_discard_sectors = UINT_MAX;
2777 ctrl->max_discard_segments = NVME_DSM_MAX_RANGES;
2778 } else {
2779 ctrl->max_discard_sectors = 0;
2780 ctrl->max_discard_segments = 0;
f3ca80fc 2781 }
7fd8930f 2782
5befc7c2
KB
2783 /*
2784 * Even though NVMe spec explicitly states that MDTS is not applicable
2785 * to the write-zeroes, we are cautious and limit the size to the
2786 * controllers max_hw_sectors value, which is based on the MDTS field
2787 * and possibly other limiting factors.
2788 */
2789 if ((ctrl->oncs & NVME_CTRL_ONCS_WRITE_ZEROES) &&
2790 !(ctrl->quirks & NVME_QUIRK_DISABLE_WRITE_ZEROES))
2791 ctrl->max_zeroes_sectors = ctrl->max_hw_sectors;
2792 else
2793 ctrl->max_zeroes_sectors = 0;
2794
2795 if (nvme_ctrl_limited_cns(ctrl))
2796 return 0;
2797
2798 id = kzalloc(sizeof(*id), GFP_KERNEL);
2799 if (!id)
2800 return 0;
2801
2802 c.identify.opcode = nvme_admin_identify;
2803 c.identify.cns = NVME_ID_CNS_CS_CTRL;
2804 c.identify.csi = NVME_CSI_NVM;
2805
2806 ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id));
2807 if (ret)
2808 goto free_data;
2809
2810 if (id->dmrl)
2811 ctrl->max_discard_segments = id->dmrl;
2812 if (id->dmrsl)
2813 ctrl->max_discard_sectors = le32_to_cpu(id->dmrsl);
2814 if (id->wzsl)
2815 ctrl->max_zeroes_sectors = nvme_mps_to_sectors(ctrl, id->wzsl);
2816
2817free_data:
2818 kfree(id);
2819 return ret;
2820}
2821
44ef5611 2822static int nvme_init_identify(struct nvme_ctrl *ctrl)
7fd8930f
CH
2823{
2824 struct nvme_id_ctrl *id;
a229dbf6 2825 u32 max_hw_sectors;
76a5af84 2826 bool prev_apst_enabled;
5befc7c2 2827 int ret;
f3ca80fc 2828
7fd8930f
CH
2829 ret = nvme_identify_ctrl(ctrl, &id);
2830 if (ret) {
1b3c47c1 2831 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH
2832 return -EIO;
2833 }
2834
84fef62d 2835 if (id->lpa & NVME_CTRL_LPA_CMD_EFFECTS_LOG) {
be93e87e 2836 ret = nvme_get_effects_log(ctrl, NVME_CSI_NVM, &ctrl->effects);
84fef62d 2837 if (ret < 0)
75c8b19a 2838 goto out_free;
84fef62d 2839 }
180de007 2840
a89fcca8
GP
2841 if (!(ctrl->ops->flags & NVME_F_FABRICS))
2842 ctrl->cntlid = le16_to_cpu(id->cntlid);
2843
bd4da3ab 2844 if (!ctrl->identified) {
44ef5611 2845 unsigned int i;
ab9e00cc
CH
2846
2847 ret = nvme_init_subsystem(ctrl, id);
2848 if (ret)
2849 goto out_free;
2850
bd4da3ab
AL
2851 /*
2852 * Check for quirks. Quirk can depend on firmware version,
2853 * so, in principle, the set of quirks present can change
2854 * across a reset. As a possible future enhancement, we
2855 * could re-scan for quirks every time we reinitialize
2856 * the device, but we'd have to make sure that the driver
2857 * behaves intelligently if the quirks change.
2858 */
bd4da3ab
AL
2859 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
2860 if (quirk_matches(id, &core_quirks[i]))
2861 ctrl->quirks |= core_quirks[i].quirks;
2862 }
2863 }
2864
c35e30b4 2865 if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) {
f0425db0 2866 dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n");
c35e30b4
AL
2867 ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS;
2868 }
2869
49cd84b6
KB
2870 ctrl->crdt[0] = le16_to_cpu(id->crdt1);
2871 ctrl->crdt[1] = le16_to_cpu(id->crdt2);
2872 ctrl->crdt[2] = le16_to_cpu(id->crdt3);
2873
8a9ae523 2874 ctrl->oacs = le16_to_cpu(id->oacs);
43e2d08d 2875 ctrl->oncs = le16_to_cpu(id->oncs);
2d466c7a 2876 ctrl->mtfa = le16_to_cpu(id->mtfa);
c0561f82 2877 ctrl->oaes = le32_to_cpu(id->oaes);
400b6a7b
GR
2878 ctrl->wctemp = le16_to_cpu(id->wctemp);
2879 ctrl->cctemp = le16_to_cpu(id->cctemp);
2880
6bf25d16 2881 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 2882 ctrl->vwc = id->vwc;
7fd8930f 2883 if (id->mdts)
5befc7c2 2884 max_hw_sectors = nvme_mps_to_sectors(ctrl, id->mdts);
7fd8930f 2885 else
a229dbf6
CH
2886 max_hw_sectors = UINT_MAX;
2887 ctrl->max_hw_sectors =
2888 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 2889
da35825d 2890 nvme_set_queue_limits(ctrl, ctrl->admin_q);
07bfcd09 2891 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 2892 ctrl->kas = le16_to_cpu(id->kas);
0d0b660f 2893 ctrl->max_namespaces = le32_to_cpu(id->mnan);
3e53ba38 2894 ctrl->ctratt = le32_to_cpu(id->ctratt);
07bfcd09 2895
07fbd32a
MP
2896 if (id->rtd3e) {
2897 /* us -> s */
f5af577d 2898 u32 transition_time = le32_to_cpu(id->rtd3e) / USEC_PER_SEC;
07fbd32a
MP
2899
2900 ctrl->shutdown_timeout = clamp_t(unsigned int, transition_time,
2901 shutdown_timeout, 60);
2902
2903 if (ctrl->shutdown_timeout != shutdown_timeout)
1a3838d7 2904 dev_info(ctrl->device,
07fbd32a
MP
2905 "Shutdown timeout set to %u seconds\n",
2906 ctrl->shutdown_timeout);
2907 } else
2908 ctrl->shutdown_timeout = shutdown_timeout;
2909
c5552fde 2910 ctrl->npss = id->npss;
76a5af84
KHF
2911 ctrl->apsta = id->apsta;
2912 prev_apst_enabled = ctrl->apst_enabled;
c35e30b4
AL
2913 if (ctrl->quirks & NVME_QUIRK_NO_APST) {
2914 if (force_apst && id->apsta) {
f0425db0 2915 dev_warn(ctrl->device, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n");
76a5af84 2916 ctrl->apst_enabled = true;
c35e30b4 2917 } else {
76a5af84 2918 ctrl->apst_enabled = false;
c35e30b4
AL
2919 }
2920 } else {
76a5af84 2921 ctrl->apst_enabled = id->apsta;
c35e30b4 2922 }
c5552fde
AL
2923 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
2924
d3d5b87d 2925 if (ctrl->ops->flags & NVME_F_FABRICS) {
07bfcd09
CH
2926 ctrl->icdoff = le16_to_cpu(id->icdoff);
2927 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
2928 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
2929 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
2930
2931 /*
2932 * In fabrics we need to verify the cntlid matches the
2933 * admin connect
2934 */
634b8325 2935 if (ctrl->cntlid != le16_to_cpu(id->cntlid)) {
a8157ff3
JS
2936 dev_err(ctrl->device,
2937 "Mismatching cntlid: Connect %u vs Identify "
2938 "%u, rejecting\n",
2939 ctrl->cntlid, le16_to_cpu(id->cntlid));
07bfcd09 2940 ret = -EINVAL;
634b8325
KB
2941 goto out_free;
2942 }
038bd4cb 2943
5ab25a32 2944 if (!nvme_discovery_ctrl(ctrl) && !ctrl->kas) {
f0425db0 2945 dev_err(ctrl->device,
038bd4cb
SG
2946 "keep-alive support is mandatory for fabrics\n");
2947 ret = -EINVAL;
634b8325 2948 goto out_free;
038bd4cb 2949 }
07bfcd09 2950 } else {
fe6d53c9
CH
2951 ctrl->hmpre = le32_to_cpu(id->hmpre);
2952 ctrl->hmmin = le32_to_cpu(id->hmmin);
044a9df1
CH
2953 ctrl->hmminds = le32_to_cpu(id->hmminds);
2954 ctrl->hmmaxd = le16_to_cpu(id->hmmaxd);
07bfcd09 2955 }
da35825d 2956
5e1f6899 2957 ret = nvme_mpath_init_identify(ctrl, id);
0d0b660f 2958 if (ret < 0)
44ef5611 2959 goto out_free;
0d0b660f 2960
76a5af84 2961 if (ctrl->apst_enabled && !prev_apst_enabled)
c5552fde 2962 dev_pm_qos_expose_latency_tolerance(ctrl->device);
76a5af84 2963 else if (!ctrl->apst_enabled && prev_apst_enabled)
c5552fde
AL
2964 dev_pm_qos_hide_latency_tolerance(ctrl->device);
2965
44ef5611
CK
2966out_free:
2967 kfree(id);
2968 return ret;
2969}
2970
2971/*
2972 * Initialize the cached copies of the Identify data and various controller
2973 * register in our nvme_ctrl structure. This should be called as soon as
2974 * the admin queue is fully up and running.
2975 */
2976int nvme_init_ctrl_finish(struct nvme_ctrl *ctrl)
2977{
2978 int ret;
2979
2980 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
2981 if (ret) {
2982 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
2983 return ret;
2984 }
2985
2986 ctrl->sqsize = min_t(u16, NVME_CAP_MQES(ctrl->cap), ctrl->sqsize);
2987
2988 if (ctrl->vs >= NVME_VS(1, 1, 0))
2989 ctrl->subsystem = NVME_CAP_NSSRC(ctrl->cap);
2990
2991 ret = nvme_init_identify(ctrl);
2992 if (ret)
2993 return ret;
2994
5befc7c2
KB
2995 ret = nvme_init_non_mdts_limits(ctrl);
2996 if (ret < 0)
2997 return ret;
2998
634b8325
KB
2999 ret = nvme_configure_apst(ctrl);
3000 if (ret < 0)
3001 return ret;
95d54bd1 3002
dbf86b39
JD
3003 ret = nvme_configure_timestamp(ctrl);
3004 if (ret < 0)
3005 return ret;
634b8325
KB
3006
3007 ret = nvme_configure_directives(ctrl);
3008 if (ret < 0)
3009 return ret;
c5552fde 3010
49cd84b6
KB
3011 ret = nvme_configure_acre(ctrl);
3012 if (ret < 0)
3013 return ret;
3014
5ab25a32 3015 if (!ctrl->identified && !nvme_discovery_ctrl(ctrl)) {
59e330f8
KB
3016 ret = nvme_hwmon_init(ctrl);
3017 if (ret < 0)
3018 return ret;
3019 }
400b6a7b 3020
bd4da3ab 3021 ctrl->identified = true;
c5552fde 3022
634b8325 3023 return 0;
7fd8930f 3024}
f21c4769 3025EXPORT_SYMBOL_GPL(nvme_init_ctrl_finish);
7fd8930f 3026
f3ca80fc 3027static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 3028{
a6a5149b
CH
3029 struct nvme_ctrl *ctrl =
3030 container_of(inode->i_cdev, struct nvme_ctrl, cdev);
1673f1f0 3031
2b1b7e78
JW
3032 switch (ctrl->state) {
3033 case NVME_CTRL_LIVE:
2b1b7e78
JW
3034 break;
3035 default:
a6a5149b 3036 return -EWOULDBLOCK;
2b1b7e78
JW
3037 }
3038
52a3974f 3039 nvme_get_ctrl(ctrl);
4bab6909
CK
3040 if (!try_module_get(ctrl->ops->module)) {
3041 nvme_put_ctrl(ctrl);
52a3974f 3042 return -EINVAL;
4bab6909 3043 }
52a3974f 3044
a6a5149b 3045 file->private_data = ctrl;
f3ca80fc
CH
3046 return 0;
3047}
3048
52a3974f
CK
3049static int nvme_dev_release(struct inode *inode, struct file *file)
3050{
3051 struct nvme_ctrl *ctrl =
3052 container_of(inode->i_cdev, struct nvme_ctrl, cdev);
3053
3054 module_put(ctrl->ops->module);
3055 nvme_put_ctrl(ctrl);
3056 return 0;
3057}
3058
f3ca80fc
CH
3059static const struct file_operations nvme_dev_fops = {
3060 .owner = THIS_MODULE,
3061 .open = nvme_dev_open,
52a3974f 3062 .release = nvme_dev_release,
f3ca80fc 3063 .unlocked_ioctl = nvme_dev_ioctl,
1832f2d8 3064 .compat_ioctl = compat_ptr_ioctl,
f3ca80fc
CH
3065};
3066
3067static ssize_t nvme_sysfs_reset(struct device *dev,
3068 struct device_attribute *attr, const char *buf,
3069 size_t count)
3070{
3071 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3072 int ret;
3073
d86c4d8e 3074 ret = nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH
3075 if (ret < 0)
3076 return ret;
3077 return count;
1673f1f0 3078}
f3ca80fc 3079static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
1673f1f0 3080
9ec3bb2f
KB
3081static ssize_t nvme_sysfs_rescan(struct device *dev,
3082 struct device_attribute *attr, const char *buf,
3083 size_t count)
3084{
3085 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3086
3087 nvme_queue_scan(ctrl);
3088 return count;
3089}
3090static DEVICE_ATTR(rescan_controller, S_IWUSR, NULL, nvme_sysfs_rescan);
3091
5b85b826
CH
3092static inline struct nvme_ns_head *dev_to_ns_head(struct device *dev)
3093{
3094 struct gendisk *disk = dev_to_disk(dev);
3095
ba4fb320 3096 if (disk->fops == &nvme_bdev_ops)
5b85b826
CH
3097 return nvme_get_ns_from_dev(dev)->head;
3098 else
3099 return disk->private_data;
3100}
3101
118472ab 3102static ssize_t wwid_show(struct device *dev, struct device_attribute *attr,
5b85b826 3103 char *buf)
118472ab 3104{
5b85b826
CH
3105 struct nvme_ns_head *head = dev_to_ns_head(dev);
3106 struct nvme_ns_ids *ids = &head->ids;
3107 struct nvme_subsystem *subsys = head->subsys;
ab9e00cc
CH
3108 int serial_len = sizeof(subsys->serial);
3109 int model_len = sizeof(subsys->model);
118472ab 3110
002fab04 3111 if (!uuid_is_null(&ids->uuid))
bff4bcf3 3112 return sysfs_emit(buf, "uuid.%pU\n", &ids->uuid);
6484f5d1 3113
002fab04 3114 if (memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
bff4bcf3 3115 return sysfs_emit(buf, "eui.%16phN\n", ids->nguid);
118472ab 3116
002fab04 3117 if (memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
bff4bcf3 3118 return sysfs_emit(buf, "eui.%8phN\n", ids->eui64);
118472ab 3119
ab9e00cc
CH
3120 while (serial_len > 0 && (subsys->serial[serial_len - 1] == ' ' ||
3121 subsys->serial[serial_len - 1] == '\0'))
118472ab 3122 serial_len--;
ab9e00cc
CH
3123 while (model_len > 0 && (subsys->model[model_len - 1] == ' ' ||
3124 subsys->model[model_len - 1] == '\0'))
118472ab
KB
3125 model_len--;
3126
bff4bcf3 3127 return sysfs_emit(buf, "nvme.%04x-%*phN-%*phN-%08x\n", subsys->vendor_id,
ab9e00cc 3128 serial_len, subsys->serial, model_len, subsys->model,
5b85b826 3129 head->ns_id);
118472ab 3130}
c828a892 3131static DEVICE_ATTR_RO(wwid);
118472ab 3132
d934f984 3133static ssize_t nguid_show(struct device *dev, struct device_attribute *attr,
5b85b826 3134 char *buf)
d934f984 3135{
bff4bcf3 3136 return sysfs_emit(buf, "%pU\n", dev_to_ns_head(dev)->ids.nguid);
d934f984 3137}
c828a892 3138static DEVICE_ATTR_RO(nguid);
d934f984 3139
2b9b6e86 3140static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,
5b85b826 3141 char *buf)
2b9b6e86 3142{
5b85b826 3143 struct nvme_ns_ids *ids = &dev_to_ns_head(dev)->ids;
d934f984
JT
3144
3145 /* For backward compatibility expose the NGUID to userspace if
3146 * we have no UUID set
3147 */
002fab04 3148 if (uuid_is_null(&ids->uuid)) {
d934f984
JT
3149 printk_ratelimited(KERN_WARNING
3150 "No UUID available providing old NGUID\n");
bff4bcf3 3151 return sysfs_emit(buf, "%pU\n", ids->nguid);
d934f984 3152 }
bff4bcf3 3153 return sysfs_emit(buf, "%pU\n", &ids->uuid);
2b9b6e86 3154}
c828a892 3155static DEVICE_ATTR_RO(uuid);
2b9b6e86
KB
3156
3157static ssize_t eui_show(struct device *dev, struct device_attribute *attr,
5b85b826 3158 char *buf)
2b9b6e86 3159{
bff4bcf3 3160 return sysfs_emit(buf, "%8ph\n", dev_to_ns_head(dev)->ids.eui64);
2b9b6e86 3161}
c828a892 3162static DEVICE_ATTR_RO(eui);
2b9b6e86
KB
3163
3164static ssize_t nsid_show(struct device *dev, struct device_attribute *attr,
5b85b826 3165 char *buf)
2b9b6e86 3166{
bff4bcf3 3167 return sysfs_emit(buf, "%d\n", dev_to_ns_head(dev)->ns_id);
2b9b6e86 3168}
c828a892 3169static DEVICE_ATTR_RO(nsid);
2b9b6e86 3170
5b85b826 3171static struct attribute *nvme_ns_id_attrs[] = {
118472ab 3172 &dev_attr_wwid.attr,
2b9b6e86 3173 &dev_attr_uuid.attr,
d934f984 3174 &dev_attr_nguid.attr,
2b9b6e86
KB
3175 &dev_attr_eui.attr,
3176 &dev_attr_nsid.attr,
0d0b660f
CH
3177#ifdef CONFIG_NVME_MULTIPATH
3178 &dev_attr_ana_grpid.attr,
3179 &dev_attr_ana_state.attr,
3180#endif
2b9b6e86
KB
3181 NULL,
3182};
3183
5b85b826 3184static umode_t nvme_ns_id_attrs_are_visible(struct kobject *kobj,
2b9b6e86
KB
3185 struct attribute *a, int n)
3186{
3187 struct device *dev = container_of(kobj, struct device, kobj);
5b85b826 3188 struct nvme_ns_ids *ids = &dev_to_ns_head(dev)->ids;
2b9b6e86
KB
3189
3190 if (a == &dev_attr_uuid.attr) {
a04b5de5 3191 if (uuid_is_null(&ids->uuid) &&
002fab04 3192 !memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
d934f984
JT
3193 return 0;
3194 }
3195 if (a == &dev_attr_nguid.attr) {
002fab04 3196 if (!memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
2b9b6e86
KB
3197 return 0;
3198 }
3199 if (a == &dev_attr_eui.attr) {
002fab04 3200 if (!memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
2b9b6e86
KB
3201 return 0;
3202 }
0d0b660f
CH
3203#ifdef CONFIG_NVME_MULTIPATH
3204 if (a == &dev_attr_ana_grpid.attr || a == &dev_attr_ana_state.attr) {
ba4fb320 3205 if (dev_to_disk(dev)->fops != &nvme_bdev_ops) /* per-path attr */
0d0b660f
CH
3206 return 0;
3207 if (!nvme_ctrl_use_ana(nvme_get_ns_from_dev(dev)->ctrl))
3208 return 0;
3209 }
3210#endif
2b9b6e86
KB
3211 return a->mode;
3212}
3213
eb090c4c 3214static const struct attribute_group nvme_ns_id_attr_group = {
5b85b826
CH
3215 .attrs = nvme_ns_id_attrs,
3216 .is_visible = nvme_ns_id_attrs_are_visible,
2b9b6e86
KB
3217};
3218
33b14f67
HR
3219const struct attribute_group *nvme_ns_id_attr_groups[] = {
3220 &nvme_ns_id_attr_group,
3221#ifdef CONFIG_NVM
3222 &nvme_nvm_attr_group,
3223#endif
3224 NULL,
3225};
3226
931e1c22 3227#define nvme_show_str_function(field) \
779ff756
KB
3228static ssize_t field##_show(struct device *dev, \
3229 struct device_attribute *attr, char *buf) \
3230{ \
3231 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
bff4bcf3 3232 return sysfs_emit(buf, "%.*s\n", \
ab9e00cc 3233 (int)sizeof(ctrl->subsys->field), ctrl->subsys->field); \
779ff756
KB
3234} \
3235static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
3236
ab9e00cc
CH
3237nvme_show_str_function(model);
3238nvme_show_str_function(serial);
3239nvme_show_str_function(firmware_rev);
3240
931e1c22
ML
3241#define nvme_show_int_function(field) \
3242static ssize_t field##_show(struct device *dev, \
3243 struct device_attribute *attr, char *buf) \
3244{ \
3245 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
bff4bcf3 3246 return sysfs_emit(buf, "%d\n", ctrl->field); \
931e1c22
ML
3247} \
3248static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
3249
931e1c22 3250nvme_show_int_function(cntlid);
103e515e 3251nvme_show_int_function(numa_node);
2b1ff255
JS
3252nvme_show_int_function(queue_count);
3253nvme_show_int_function(sqsize);
74c22990 3254nvme_show_int_function(kato);
779ff756 3255
1a353d85
ML
3256static ssize_t nvme_sysfs_delete(struct device *dev,
3257 struct device_attribute *attr, const char *buf,
3258 size_t count)
3259{
3260 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3261
3262 if (device_remove_file_self(dev, attr))
c5017e85 3263 nvme_delete_ctrl_sync(ctrl);
1a353d85
ML
3264 return count;
3265}
3266static DEVICE_ATTR(delete_controller, S_IWUSR, NULL, nvme_sysfs_delete);
3267
3268static ssize_t nvme_sysfs_show_transport(struct device *dev,
3269 struct device_attribute *attr,
3270 char *buf)
3271{
3272 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3273
f720a8ed 3274 return sysfs_emit(buf, "%s\n", ctrl->ops->name);
1a353d85
ML
3275}
3276static DEVICE_ATTR(transport, S_IRUGO, nvme_sysfs_show_transport, NULL);
3277
8432bdb2
SG
3278static ssize_t nvme_sysfs_show_state(struct device *dev,
3279 struct device_attribute *attr,
3280 char *buf)
3281{
3282 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3283 static const char *const state_name[] = {
3284 [NVME_CTRL_NEW] = "new",
3285 [NVME_CTRL_LIVE] = "live",
3286 [NVME_CTRL_RESETTING] = "resetting",
ad6a0a52 3287 [NVME_CTRL_CONNECTING] = "connecting",
8432bdb2 3288 [NVME_CTRL_DELETING] = "deleting",
ecca390e 3289 [NVME_CTRL_DELETING_NOIO]= "deleting (no IO)",
8432bdb2
SG
3290 [NVME_CTRL_DEAD] = "dead",
3291 };
3292
3293 if ((unsigned)ctrl->state < ARRAY_SIZE(state_name) &&
3294 state_name[ctrl->state])
bff4bcf3 3295 return sysfs_emit(buf, "%s\n", state_name[ctrl->state]);
8432bdb2 3296
bff4bcf3 3297 return sysfs_emit(buf, "unknown state\n");
8432bdb2
SG
3298}
3299
3300static DEVICE_ATTR(state, S_IRUGO, nvme_sysfs_show_state, NULL);
3301
1a353d85
ML
3302static ssize_t nvme_sysfs_show_subsysnqn(struct device *dev,
3303 struct device_attribute *attr,
3304 char *buf)
3305{
3306 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3307
f720a8ed 3308 return sysfs_emit(buf, "%s\n", ctrl->subsys->subnqn);
1a353d85
ML
3309}
3310static DEVICE_ATTR(subsysnqn, S_IRUGO, nvme_sysfs_show_subsysnqn, NULL);
3311
76171c6c
SG
3312static ssize_t nvme_sysfs_show_hostnqn(struct device *dev,
3313 struct device_attribute *attr,
3314 char *buf)
3315{
3316 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3317
f720a8ed 3318 return sysfs_emit(buf, "%s\n", ctrl->opts->host->nqn);
76171c6c
SG
3319}
3320static DEVICE_ATTR(hostnqn, S_IRUGO, nvme_sysfs_show_hostnqn, NULL);
3321
45fb19f7
SG
3322static ssize_t nvme_sysfs_show_hostid(struct device *dev,
3323 struct device_attribute *attr,
3324 char *buf)
3325{
3326 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3327
f720a8ed 3328 return sysfs_emit(buf, "%pU\n", &ctrl->opts->host->id);
45fb19f7
SG
3329}
3330static DEVICE_ATTR(hostid, S_IRUGO, nvme_sysfs_show_hostid, NULL);
3331
1a353d85
ML
3332static ssize_t nvme_sysfs_show_address(struct device *dev,
3333 struct device_attribute *attr,
3334 char *buf)
3335{
3336 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3337
3338 return ctrl->ops->get_address(ctrl, buf, PAGE_SIZE);
3339}
3340static DEVICE_ATTR(address, S_IRUGO, nvme_sysfs_show_address, NULL);
3341
764075fd
SG
3342static ssize_t nvme_ctrl_loss_tmo_show(struct device *dev,
3343 struct device_attribute *attr, char *buf)
3344{
3345 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3346 struct nvmf_ctrl_options *opts = ctrl->opts;
3347
3348 if (ctrl->opts->max_reconnects == -1)
bff4bcf3
DW
3349 return sysfs_emit(buf, "off\n");
3350 return sysfs_emit(buf, "%d\n",
3351 opts->max_reconnects * opts->reconnect_delay);
764075fd
SG
3352}
3353
3354static ssize_t nvme_ctrl_loss_tmo_store(struct device *dev,
3355 struct device_attribute *attr, const char *buf, size_t count)
3356{
3357 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3358 struct nvmf_ctrl_options *opts = ctrl->opts;
3359 int ctrl_loss_tmo, err;
3360
3361 err = kstrtoint(buf, 10, &ctrl_loss_tmo);
3362 if (err)
3363 return -EINVAL;
3364
25a64e4e 3365 if (ctrl_loss_tmo < 0)
764075fd
SG
3366 opts->max_reconnects = -1;
3367 else
3368 opts->max_reconnects = DIV_ROUND_UP(ctrl_loss_tmo,
3369 opts->reconnect_delay);
3370 return count;
3371}
3372static DEVICE_ATTR(ctrl_loss_tmo, S_IRUGO | S_IWUSR,
3373 nvme_ctrl_loss_tmo_show, nvme_ctrl_loss_tmo_store);
3374
3375static ssize_t nvme_ctrl_reconnect_delay_show(struct device *dev,
3376 struct device_attribute *attr, char *buf)
3377{
3378 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3379
3380 if (ctrl->opts->reconnect_delay == -1)
bff4bcf3
DW
3381 return sysfs_emit(buf, "off\n");
3382 return sysfs_emit(buf, "%d\n", ctrl->opts->reconnect_delay);
764075fd
SG
3383}
3384
3385static ssize_t nvme_ctrl_reconnect_delay_store(struct device *dev,
3386 struct device_attribute *attr, const char *buf, size_t count)
3387{
3388 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3389 unsigned int v;
3390 int err;
3391
3392 err = kstrtou32(buf, 10, &v);
eca9e827
DC
3393 if (err)
3394 return err;
764075fd
SG
3395
3396 ctrl->opts->reconnect_delay = v;
3397 return count;
3398}
3399static DEVICE_ATTR(reconnect_delay, S_IRUGO | S_IWUSR,
3400 nvme_ctrl_reconnect_delay_show, nvme_ctrl_reconnect_delay_store);
3401
09fbed63
DW
3402static ssize_t nvme_ctrl_fast_io_fail_tmo_show(struct device *dev,
3403 struct device_attribute *attr, char *buf)
3404{
3405 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3406
3407 if (ctrl->opts->fast_io_fail_tmo == -1)
3408 return sysfs_emit(buf, "off\n");
3409 return sysfs_emit(buf, "%d\n", ctrl->opts->fast_io_fail_tmo);
3410}
3411
3412static ssize_t nvme_ctrl_fast_io_fail_tmo_store(struct device *dev,
3413 struct device_attribute *attr, const char *buf, size_t count)
3414{
3415 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3416 struct nvmf_ctrl_options *opts = ctrl->opts;
3417 int fast_io_fail_tmo, err;
3418
3419 err = kstrtoint(buf, 10, &fast_io_fail_tmo);
3420 if (err)
3421 return -EINVAL;
3422
3423 if (fast_io_fail_tmo < 0)
3424 opts->fast_io_fail_tmo = -1;
3425 else
3426 opts->fast_io_fail_tmo = fast_io_fail_tmo;
3427 return count;
3428}
3429static DEVICE_ATTR(fast_io_fail_tmo, S_IRUGO | S_IWUSR,
3430 nvme_ctrl_fast_io_fail_tmo_show, nvme_ctrl_fast_io_fail_tmo_store);
3431
779ff756
KB
3432static struct attribute *nvme_dev_attrs[] = {
3433 &dev_attr_reset_controller.attr,
9ec3bb2f 3434 &dev_attr_rescan_controller.attr,
779ff756
KB
3435 &dev_attr_model.attr,
3436 &dev_attr_serial.attr,
3437 &dev_attr_firmware_rev.attr,
931e1c22 3438 &dev_attr_cntlid.attr,
1a353d85
ML
3439 &dev_attr_delete_controller.attr,
3440 &dev_attr_transport.attr,
3441 &dev_attr_subsysnqn.attr,
3442 &dev_attr_address.attr,
8432bdb2 3443 &dev_attr_state.attr,
103e515e 3444 &dev_attr_numa_node.attr,
2b1ff255
JS
3445 &dev_attr_queue_count.attr,
3446 &dev_attr_sqsize.attr,
76171c6c 3447 &dev_attr_hostnqn.attr,
45fb19f7 3448 &dev_attr_hostid.attr,
764075fd
SG
3449 &dev_attr_ctrl_loss_tmo.attr,
3450 &dev_attr_reconnect_delay.attr,
09fbed63 3451 &dev_attr_fast_io_fail_tmo.attr,
74c22990 3452 &dev_attr_kato.attr,
779ff756
KB
3453 NULL
3454};
3455
1a353d85
ML
3456static umode_t nvme_dev_attrs_are_visible(struct kobject *kobj,
3457 struct attribute *a, int n)
3458{
3459 struct device *dev = container_of(kobj, struct device, kobj);
3460 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3461
49d3d50b
CH
3462 if (a == &dev_attr_delete_controller.attr && !ctrl->ops->delete_ctrl)
3463 return 0;
3464 if (a == &dev_attr_address.attr && !ctrl->ops->get_address)
3465 return 0;
76171c6c
SG
3466 if (a == &dev_attr_hostnqn.attr && !ctrl->opts)
3467 return 0;
45fb19f7
SG
3468 if (a == &dev_attr_hostid.attr && !ctrl->opts)
3469 return 0;
7cd49f75
SG
3470 if (a == &dev_attr_ctrl_loss_tmo.attr && !ctrl->opts)
3471 return 0;
3472 if (a == &dev_attr_reconnect_delay.attr && !ctrl->opts)
3473 return 0;
d6609084
GT
3474 if (a == &dev_attr_fast_io_fail_tmo.attr && !ctrl->opts)
3475 return 0;
1a353d85
ML
3476
3477 return a->mode;
3478}
3479
60b152a5 3480static const struct attribute_group nvme_dev_attrs_group = {
1a353d85
ML
3481 .attrs = nvme_dev_attrs,
3482 .is_visible = nvme_dev_attrs_are_visible,
779ff756
KB
3483};
3484
3485static const struct attribute_group *nvme_dev_attr_groups[] = {
3486 &nvme_dev_attrs_group,
3487 NULL,
3488};
3489
026d2ef7 3490static struct nvme_ns_head *nvme_find_ns_head(struct nvme_subsystem *subsys,
ed754e5d
CH
3491 unsigned nsid)
3492{
3493 struct nvme_ns_head *h;
3494
3495 lockdep_assert_held(&subsys->lock);
3496
3497 list_for_each_entry(h, &subsys->nsheads, entry) {
871ca3ef 3498 if (h->ns_id == nsid && nvme_tryget_ns_head(h))
ed754e5d
CH
3499 return h;
3500 }
3501
3502 return NULL;
3503}
3504
3505static int __nvme_check_ids(struct nvme_subsystem *subsys,
3506 struct nvme_ns_head *new)
3507{
3508 struct nvme_ns_head *h;
3509
3510 lockdep_assert_held(&subsys->lock);
3511
3512 list_for_each_entry(h, &subsys->nsheads, entry) {
3513 if (nvme_ns_ids_valid(&new->ids) &&
3514 nvme_ns_ids_equal(&new->ids, &h->ids))
3515 return -EINVAL;
3516 }
3517
3518 return 0;
3519}
3520
2637baed
MI
3521void nvme_cdev_del(struct cdev *cdev, struct device *cdev_device)
3522{
3523 cdev_device_del(cdev, cdev_device);
3524 ida_simple_remove(&nvme_ns_chr_minor_ida, MINOR(cdev_device->devt));
3525}
3526
3527int nvme_cdev_add(struct cdev *cdev, struct device *cdev_device,
3528 const struct file_operations *fops, struct module *owner)
3529{
3530 int minor, ret;
3531
3532 minor = ida_simple_get(&nvme_ns_chr_minor_ida, 0, 0, GFP_KERNEL);
3533 if (minor < 0)
3534 return minor;
3535 cdev_device->devt = MKDEV(MAJOR(nvme_ns_chr_devt), minor);
3536 cdev_device->class = nvme_ns_chr_class;
3537 device_initialize(cdev_device);
3538 cdev_init(cdev, fops);
3539 cdev->owner = owner;
3540 ret = cdev_device_add(cdev, cdev_device);
3596a065
GJ
3541 if (ret) {
3542 put_device(cdev_device);
2637baed 3543 ida_simple_remove(&nvme_ns_chr_minor_ida, minor);
3596a065 3544 }
2637baed
MI
3545 return ret;
3546}
3547
3548static int nvme_ns_chr_open(struct inode *inode, struct file *file)
3549{
3550 return nvme_ns_open(container_of(inode->i_cdev, struct nvme_ns, cdev));
3551}
3552
3553static int nvme_ns_chr_release(struct inode *inode, struct file *file)
3554{
3555 nvme_ns_release(container_of(inode->i_cdev, struct nvme_ns, cdev));
3556 return 0;
3557}
3558
3559static const struct file_operations nvme_ns_chr_fops = {
3560 .owner = THIS_MODULE,
3561 .open = nvme_ns_chr_open,
3562 .release = nvme_ns_chr_release,
3563 .unlocked_ioctl = nvme_ns_chr_ioctl,
3564 .compat_ioctl = compat_ptr_ioctl,
3565};
3566
3567static int nvme_add_ns_cdev(struct nvme_ns *ns)
3568{
3569 int ret;
3570
3571 ns->cdev_device.parent = ns->ctrl->device;
3572 ret = dev_set_name(&ns->cdev_device, "ng%dn%d",
3573 ns->ctrl->instance, ns->head->instance);
3574 if (ret)
3575 return ret;
3576 ret = nvme_cdev_add(&ns->cdev, &ns->cdev_device, &nvme_ns_chr_fops,
3577 ns->ctrl->ops->module);
3578 if (ret)
3579 kfree_const(ns->cdev_device.kobj.name);
3580 return ret;
3581}
3582
ed754e5d 3583static struct nvme_ns_head *nvme_alloc_ns_head(struct nvme_ctrl *ctrl,
03f8cebc 3584 unsigned nsid, struct nvme_ns_ids *ids)
ed754e5d
CH
3585{
3586 struct nvme_ns_head *head;
f3334447 3587 size_t size = sizeof(*head);
ed754e5d
CH
3588 int ret = -ENOMEM;
3589
f3334447
CH
3590#ifdef CONFIG_NVME_MULTIPATH
3591 size += num_possible_nodes() * sizeof(struct nvme_ns *);
3592#endif
3593
3594 head = kzalloc(size, GFP_KERNEL);
ed754e5d
CH
3595 if (!head)
3596 goto out;
3597 ret = ida_simple_get(&ctrl->subsys->ns_ida, 1, 0, GFP_KERNEL);
3598 if (ret < 0)
3599 goto out_free_head;
3600 head->instance = ret;
3601 INIT_LIST_HEAD(&head->list);
fd92c77f
MG
3602 ret = init_srcu_struct(&head->srcu);
3603 if (ret)
3604 goto out_ida_remove;
ed754e5d
CH
3605 head->subsys = ctrl->subsys;
3606 head->ns_id = nsid;
43fcd9e1 3607 head->ids = *ids;
ed754e5d
CH
3608 kref_init(&head->ref);
3609
ed754e5d
CH
3610 ret = __nvme_check_ids(ctrl->subsys, head);
3611 if (ret) {
3612 dev_err(ctrl->device,
3613 "duplicate IDs for nsid %d\n", nsid);
3614 goto out_cleanup_srcu;
3615 }
3616
be93e87e
KB
3617 if (head->ids.csi) {
3618 ret = nvme_get_effects_log(ctrl, head->ids.csi, &head->effects);
3619 if (ret)
3620 goto out_cleanup_srcu;
3621 } else
3622 head->effects = ctrl->effects;
3623
32acab31
CH
3624 ret = nvme_mpath_alloc_disk(ctrl, head);
3625 if (ret)
3626 goto out_cleanup_srcu;
3627
ed754e5d 3628 list_add_tail(&head->entry, &ctrl->subsys->nsheads);
12d9f070
JW
3629
3630 kref_get(&ctrl->subsys->ref);
3631
ed754e5d
CH
3632 return head;
3633out_cleanup_srcu:
3634 cleanup_srcu_struct(&head->srcu);
fd92c77f 3635out_ida_remove:
ed754e5d
CH
3636 ida_simple_remove(&ctrl->subsys->ns_ida, head->instance);
3637out_free_head:
3638 kfree(head);
3639out:
538af88e
SG
3640 if (ret > 0)
3641 ret = blk_status_to_errno(nvme_error_status(ret));
ed754e5d
CH
3642 return ERR_PTR(ret);
3643}
3644
3645static int nvme_init_ns_head(struct nvme_ns *ns, unsigned nsid,
8b7c0ff2 3646 struct nvme_ns_ids *ids, bool is_shared)
ed754e5d
CH
3647{
3648 struct nvme_ctrl *ctrl = ns->ctrl;
ed754e5d
CH
3649 struct nvme_ns_head *head = NULL;
3650 int ret = 0;
3651
3652 mutex_lock(&ctrl->subsys->lock);
9ad1927a 3653 head = nvme_find_ns_head(ctrl->subsys, nsid);
ed754e5d 3654 if (!head) {
8b7c0ff2 3655 head = nvme_alloc_ns_head(ctrl, nsid, ids);
ed754e5d
CH
3656 if (IS_ERR(head)) {
3657 ret = PTR_ERR(head);
3658 goto out_unlock;
3659 }
0c284db7 3660 head->shared = is_shared;
ed754e5d 3661 } else {
6623c5b3 3662 ret = -EINVAL;
0c284db7 3663 if (!is_shared || !head->shared) {
9ad1927a 3664 dev_err(ctrl->device,
6623c5b3
CH
3665 "Duplicate unshared namespace %d\n", nsid);
3666 goto out_put_ns_head;
9ad1927a 3667 }
8b7c0ff2 3668 if (!nvme_ns_ids_equal(&head->ids, ids)) {
ed754e5d
CH
3669 dev_err(ctrl->device,
3670 "IDs don't match for shared namespace %d\n",
3671 nsid);
6623c5b3 3672 goto out_put_ns_head;
ed754e5d 3673 }
ed754e5d
CH
3674 }
3675
772ea326 3676 list_add_tail_rcu(&ns->siblings, &head->list);
ed754e5d 3677 ns->head = head;
6623c5b3
CH
3678 mutex_unlock(&ctrl->subsys->lock);
3679 return 0;
ed754e5d 3680
6623c5b3
CH
3681out_put_ns_head:
3682 nvme_put_ns_head(head);
ed754e5d
CH
3683out_unlock:
3684 mutex_unlock(&ctrl->subsys->lock);
3685 return ret;
3686}
3687
4f0f586b
ST
3688static int ns_cmp(void *priv, const struct list_head *a,
3689 const struct list_head *b)
5bae7f73
CH
3690{
3691 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
3692 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
3693
ed754e5d 3694 return nsa->head->ns_id - nsb->head->ns_id;
5bae7f73
CH
3695}
3696
24493b8b 3697struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 3698{
32f0c4af 3699 struct nvme_ns *ns, *ret = NULL;
69d3b8ac 3700
765cc031 3701 down_read(&ctrl->namespaces_rwsem);
5bae7f73 3702 list_for_each_entry(ns, &ctrl->namespaces, list) {
ed754e5d 3703 if (ns->head->ns_id == nsid) {
4c74d1f8 3704 if (!nvme_get_ns(ns))
2dd41228 3705 continue;
32f0c4af
KB
3706 ret = ns;
3707 break;
3708 }
ed754e5d 3709 if (ns->head->ns_id > nsid)
5bae7f73
CH
3710 break;
3711 }
765cc031 3712 up_read(&ctrl->namespaces_rwsem);
32f0c4af 3713 return ret;
5bae7f73 3714}
24493b8b 3715EXPORT_SYMBOL_NS_GPL(nvme_find_get_ns, NVME_TARGET_PASSTHRU);
5bae7f73 3716
8b7c0ff2
CH
3717static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid,
3718 struct nvme_ns_ids *ids)
5bae7f73
CH
3719{
3720 struct nvme_ns *ns;
3721 struct gendisk *disk;
ac81bfa9 3722 struct nvme_id_ns *id;
9953ab0c 3723 int node = ctrl->numa_node;
5bae7f73 3724
8b7c0ff2 3725 if (nvme_identify_ns(ctrl, nsid, ids, &id))
fab72f5a
CH
3726 return;
3727
5bae7f73
CH
3728 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
3729 if (!ns)
fab72f5a 3730 goto out_free_id;
5bae7f73
CH
3731
3732 ns->queue = blk_mq_init_queue(ctrl->tagset);
adce7e98 3733 if (IS_ERR(ns->queue))
ed754e5d 3734 goto out_free_ns;
e0596ab2 3735
7d30c81b 3736 if (ctrl->opts && ctrl->opts->data_digest)
1cb039f3 3737 blk_queue_flag_set(QUEUE_FLAG_STABLE_WRITES, ns->queue);
958f2a0f 3738
8b904b5b 3739 blk_queue_flag_set(QUEUE_FLAG_NONROT, ns->queue);
e0596ab2
LG
3740 if (ctrl->ops->flags & NVME_F_PCI_P2PDMA)
3741 blk_queue_flag_set(QUEUE_FLAG_PCI_P2PDMA, ns->queue);
3742
5bae7f73
CH
3743 ns->queue->queuedata = ns;
3744 ns->ctrl = ctrl;
5bae7f73 3745 kref_init(&ns->kref);
5bae7f73 3746
e1aaf5ca 3747 if (nvme_init_ns_head(ns, nsid, ids, id->nmic & NVME_NS_NMIC_SHARED))
ac81bfa9 3748 goto out_free_queue;
cdbff4f2 3749
3dc87dd0 3750 disk = alloc_disk_node(0, node);
adce7e98 3751 if (!disk)
ed754e5d 3752 goto out_unlink_ns;
ac81bfa9 3753
ba4fb320 3754 disk->fops = &nvme_bdev_ops;
3dc87dd0
MB
3755 disk->private_data = ns;
3756 disk->queue = ns->queue;
9953ab0c
CH
3757 /*
3758 * Without the multipath code enabled, multiple controller per
3759 * subsystems are visible as devices and thus we cannot use the
3760 * subsystem instance.
3761 */
3762 if (!nvme_mpath_set_disk_name(ns, disk->disk_name, &disk->flags))
3763 sprintf(disk->disk_name, "nvme%dn%d", ctrl->instance,
3764 ns->head->instance);
3dc87dd0
MB
3765 ns->disk = disk;
3766
81382f17 3767 if (nvme_update_ns_info(ns, id))
108a5858 3768 goto out_put_disk;
5bae7f73 3769
85136c01 3770 if ((ctrl->quirks & NVME_QUIRK_LIGHTNVM) && id->vs[0] == 0x1) {
9953ab0c 3771 if (nvme_nvm_register(ns, disk->disk_name, node)) {
85136c01
MB
3772 dev_warn(ctrl->device, "LightNVM init failure\n");
3773 goto out_put_disk;
3774 }
3775 }
3776
765cc031 3777 down_write(&ctrl->namespaces_rwsem);
32f0c4af 3778 list_add_tail(&ns->list, &ctrl->namespaces);
765cc031 3779 up_write(&ctrl->namespaces_rwsem);
32f0c4af 3780
d22524a4 3781 nvme_get_ctrl(ctrl);
ac81bfa9 3782
33b14f67 3783 device_add_disk(ctrl->device, ns->disk, nvme_ns_id_attr_groups);
2637baed
MI
3784 if (!nvme_ns_head_multipath(ns->head))
3785 nvme_add_ns_cdev(ns);
32acab31 3786
0d0b660f 3787 nvme_mpath_add_disk(ns, id);
a3646451 3788 nvme_fault_inject_init(&ns->fault_inject, ns->disk->disk_name);
0d0b660f
CH
3789 kfree(id);
3790
adce7e98 3791 return;
85136c01 3792 out_put_disk:
132be623
NC
3793 /* prevent double queue cleanup */
3794 ns->disk->queue = NULL;
85136c01 3795 put_disk(ns->disk);
ed754e5d
CH
3796 out_unlink_ns:
3797 mutex_lock(&ctrl->subsys->lock);
3798 list_del_rcu(&ns->siblings);
d5675729
KB
3799 if (list_empty(&ns->head->list))
3800 list_del_init(&ns->head->entry);
ed754e5d 3801 mutex_unlock(&ctrl->subsys->lock);
a63b8370 3802 nvme_put_ns_head(ns->head);
5bae7f73
CH
3803 out_free_queue:
3804 blk_cleanup_queue(ns->queue);
3805 out_free_ns:
3806 kfree(ns);
fab72f5a
CH
3807 out_free_id:
3808 kfree(id);
5bae7f73
CH
3809}
3810
3811static void nvme_ns_remove(struct nvme_ns *ns)
3812{
5396fdac
HR
3813 bool last_path = false;
3814
646017a6
KB
3815 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
3816 return;
69d3b8ac 3817
0a05226a 3818 set_capacity(ns->disk, 0);
a3646451 3819 nvme_fault_inject_fini(&ns->fault_inject);
2181e455
AE
3820
3821 mutex_lock(&ns->ctrl->subsys->lock);
3822 list_del_rcu(&ns->siblings);
3823 mutex_unlock(&ns->ctrl->subsys->lock);
d5675729 3824
2181e455
AE
3825 synchronize_rcu(); /* guarantee not available in head->list */
3826 nvme_mpath_clear_current_path(ns);
3827 synchronize_srcu(&ns->head->srcu); /* wait for concurrent submissions */
3828
5eba2005
CH
3829 if (!nvme_ns_head_multipath(ns->head))
3830 nvme_cdev_del(&ns->cdev, &ns->cdev_device);
3831 del_gendisk(ns->disk);
3832 blk_cleanup_queue(ns->queue);
3833 if (blk_get_integrity(ns->disk))
3834 blk_integrity_unregister(ns->disk);
32f0c4af 3835
765cc031 3836 down_write(&ns->ctrl->namespaces_rwsem);
5bae7f73 3837 list_del_init(&ns->list);
765cc031 3838 up_write(&ns->ctrl->namespaces_rwsem);
32f0c4af 3839
5396fdac
HR
3840 /* Synchronize with nvme_init_ns_head() */
3841 mutex_lock(&ns->head->subsys->lock);
3842 if (list_empty(&ns->head->list)) {
3843 list_del_init(&ns->head->entry);
3844 last_path = true;
3845 }
3846 mutex_unlock(&ns->head->subsys->lock);
3847 if (last_path)
3848 nvme_mpath_shutdown_disk(ns->head);
5bae7f73
CH
3849 nvme_put_ns(ns);
3850}
3851
4450ba3b
CH
3852static void nvme_ns_remove_by_nsid(struct nvme_ctrl *ctrl, u32 nsid)
3853{
3854 struct nvme_ns *ns = nvme_find_get_ns(ctrl, nsid);
3855
3856 if (ns) {
3857 nvme_ns_remove(ns);
3858 nvme_put_ns(ns);
3859 }
3860}
3861
0a05226a 3862static void nvme_validate_ns(struct nvme_ns *ns, struct nvme_ns_ids *ids)
b2dc748a 3863{
b2dc748a 3864 struct nvme_id_ns *id;
d95c1f41 3865 int ret = NVME_SC_INVALID_NS | NVME_SC_DNR;
b2dc748a 3866
0a05226a
CH
3867 if (test_bit(NVME_NS_DEAD, &ns->flags))
3868 goto out;
b2dc748a 3869
af5d6f7b 3870 ret = nvme_identify_ns(ns->ctrl, ns->head->ns_id, ids, &id);
b2dc748a
CH
3871 if (ret)
3872 goto out;
3873
d95c1f41 3874 ret = NVME_SC_INVALID_NS | NVME_SC_DNR;
b2dc748a 3875 if (!nvme_ns_ids_equal(&ns->head->ids, ids)) {
af5d6f7b 3876 dev_err(ns->ctrl->device,
b2dc748a 3877 "identifiers changed for nsid %d\n", ns->head->ns_id);
0a05226a 3878 goto out_free_id;
b2dc748a
CH
3879 }
3880
3881 ret = nvme_update_ns_info(ns, id);
0a05226a
CH
3882
3883out_free_id:
b2dc748a
CH
3884 kfree(id);
3885out:
3886 /*
0a05226a 3887 * Only remove the namespace if we got a fatal error back from the
b2dc748a 3888 * device, otherwise ignore the error and just move on.
0a05226a
CH
3889 *
3890 * TODO: we should probably schedule a delayed retry here.
b2dc748a 3891 */
d95c1f41 3892 if (ret > 0 && (ret & NVME_SC_DNR))
0a05226a 3893 nvme_ns_remove(ns);
b2dc748a
CH
3894}
3895
eba9bcf7 3896static void nvme_validate_or_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
540c801c 3897{
8b7c0ff2 3898 struct nvme_ns_ids ids = { };
540c801c
KB
3899 struct nvme_ns *ns;
3900
8b7c0ff2
CH
3901 if (nvme_identify_ns_descs(ctrl, nsid, &ids))
3902 return;
540c801c 3903
32f0c4af 3904 ns = nvme_find_get_ns(ctrl, nsid);
8b7c0ff2 3905 if (ns) {
0a05226a 3906 nvme_validate_ns(ns, &ids);
8b7c0ff2 3907 nvme_put_ns(ns);
b55d3d21
CH
3908 return;
3909 }
3910
8b7c0ff2
CH
3911 switch (ids.csi) {
3912 case NVME_CSI_NVM:
3913 nvme_alloc_ns(ctrl, nsid, &ids);
3914 break;
3915 case NVME_CSI_ZNS:
3916 if (!IS_ENABLED(CONFIG_BLK_DEV_ZONED)) {
3917 dev_warn(ctrl->device,
3918 "nsid %u not supported without CONFIG_BLK_DEV_ZONED\n",
3919 nsid);
3920 break;
3921 }
0ec84df4
CK
3922 if (!nvme_multi_css(ctrl)) {
3923 dev_warn(ctrl->device,
3924 "command set not reported for nsid: %d\n",
f4f9fc29 3925 nsid);
0ec84df4
CK
3926 break;
3927 }
8b7c0ff2
CH
3928 nvme_alloc_ns(ctrl, nsid, &ids);
3929 break;
3930 default:
3931 dev_warn(ctrl->device, "unknown csi %u for nsid %u\n",
3932 ids.csi, nsid);
3933 break;
3934 }
540c801c
KB
3935}
3936
47b0e50a
SB
3937static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
3938 unsigned nsid)
3939{
3940 struct nvme_ns *ns, *next;
6f8e0d78 3941 LIST_HEAD(rm_list);
47b0e50a 3942
765cc031 3943 down_write(&ctrl->namespaces_rwsem);
47b0e50a 3944 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
cf39a6bc 3945 if (ns->head->ns_id > nsid || test_bit(NVME_NS_DEAD, &ns->flags))
6f8e0d78 3946 list_move_tail(&ns->list, &rm_list);
47b0e50a 3947 }
765cc031 3948 up_write(&ctrl->namespaces_rwsem);
6f8e0d78
JW
3949
3950 list_for_each_entry_safe(ns, next, &rm_list, list)
3951 nvme_ns_remove(ns);
3952
47b0e50a
SB
3953}
3954
4005f28d 3955static int nvme_scan_ns_list(struct nvme_ctrl *ctrl)
540c801c 3956{
aec459b4 3957 const int nr_entries = NVME_IDENTIFY_DATA_SIZE / sizeof(__le32);
540c801c 3958 __le32 *ns_list;
4005f28d
CH
3959 u32 prev = 0;
3960 int ret = 0, i;
540c801c 3961
25dcaa92
CH
3962 if (nvme_ctrl_limited_cns(ctrl))
3963 return -EOPNOTSUPP;
540c801c 3964
42595eb7 3965 ns_list = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
540c801c
KB
3966 if (!ns_list)
3967 return -ENOMEM;
3968
4005f28d 3969 for (;;) {
7b153362
CH
3970 struct nvme_command cmd = {
3971 .identify.opcode = nvme_admin_identify,
3972 .identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST,
3973 .identify.nsid = cpu_to_le32(prev),
3974 };
3975
3976 ret = nvme_submit_sync_cmd(ctrl->admin_q, &cmd, ns_list,
3977 NVME_IDENTIFY_DATA_SIZE);
f781f3dd
MI
3978 if (ret) {
3979 dev_warn(ctrl->device,
3980 "Identify NS List failed (status=0x%x)\n", ret);
47b0e50a 3981 goto free;
f781f3dd 3982 }
540c801c 3983
aec459b4 3984 for (i = 0; i < nr_entries; i++) {
4005f28d 3985 u32 nsid = le32_to_cpu(ns_list[i]);
540c801c 3986
4005f28d
CH
3987 if (!nsid) /* end of the list? */
3988 goto out;
eba9bcf7 3989 nvme_validate_or_alloc_ns(ctrl, nsid);
4450ba3b
CH
3990 while (++prev < nsid)
3991 nvme_ns_remove_by_nsid(ctrl, prev);
540c801c 3992 }
540c801c
KB
3993 }
3994 out:
47b0e50a
SB
3995 nvme_remove_invalid_namespaces(ctrl, prev);
3996 free:
540c801c
KB
3997 kfree(ns_list);
3998 return ret;
3999}
4000
4005f28d 4001static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl)
5bae7f73 4002{
4005f28d
CH
4003 struct nvme_id_ctrl *id;
4004 u32 nn, i;
4005
4006 if (nvme_identify_ctrl(ctrl, &id))
4007 return;
4008 nn = le32_to_cpu(id->nn);
4009 kfree(id);
5bae7f73 4010
540c801c 4011 for (i = 1; i <= nn; i++)
eba9bcf7 4012 nvme_validate_or_alloc_ns(ctrl, i);
540c801c 4013
47b0e50a 4014 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH
4015}
4016
f493af37 4017static void nvme_clear_changed_ns_log(struct nvme_ctrl *ctrl)
30d90964
CH
4018{
4019 size_t log_size = NVME_MAX_CHANGED_NAMESPACES * sizeof(__le32);
4020 __le32 *log;
f493af37 4021 int error;
30d90964
CH
4022
4023 log = kzalloc(log_size, GFP_KERNEL);
4024 if (!log)
f493af37 4025 return;
30d90964 4026
f493af37
CH
4027 /*
4028 * We need to read the log to clear the AEN, but we don't want to rely
4029 * on it for the changed namespace information as userspace could have
4030 * raced with us in reading the log page, which could cause us to miss
4031 * updates.
4032 */
be93e87e
KB
4033 error = nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_CHANGED_NS, 0,
4034 NVME_CSI_NVM, log, log_size, 0);
f493af37 4035 if (error)
30d90964
CH
4036 dev_warn(ctrl->device,
4037 "reading changed ns log failed: %d\n", error);
30d90964 4038
30d90964 4039 kfree(log);
30d90964
CH
4040}
4041
5955be21 4042static void nvme_scan_work(struct work_struct *work)
5bae7f73 4043{
5955be21
CH
4044 struct nvme_ctrl *ctrl =
4045 container_of(work, struct nvme_ctrl, scan_work);
5bae7f73 4046
5d02a5c1
KB
4047 /* No tagset on a live ctrl means IO queues could not created */
4048 if (ctrl->state != NVME_CTRL_LIVE || !ctrl->tagset)
5955be21
CH
4049 return;
4050
77016199 4051 if (test_and_clear_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events)) {
30d90964 4052 dev_info(ctrl->device, "rescanning namespaces.\n");
f493af37 4053 nvme_clear_changed_ns_log(ctrl);
30d90964
CH
4054 }
4055
e7ad43c3 4056 mutex_lock(&ctrl->scan_lock);
4005f28d
CH
4057 if (nvme_scan_ns_list(ctrl) != 0)
4058 nvme_scan_ns_sequential(ctrl);
e7ad43c3 4059 mutex_unlock(&ctrl->scan_lock);
25dcaa92 4060
765cc031 4061 down_write(&ctrl->namespaces_rwsem);
540c801c 4062 list_sort(NULL, &ctrl->namespaces, ns_cmp);
765cc031 4063 up_write(&ctrl->namespaces_rwsem);
5955be21 4064}
5bae7f73 4065
32f0c4af
KB
4066/*
4067 * This function iterates the namespace list unlocked to allow recovery from
4068 * controller failure. It is up to the caller to ensure the namespace list is
4069 * not modified by scan work while this function is executing.
4070 */
5bae7f73
CH
4071void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
4072{
4073 struct nvme_ns *ns, *next;
6f8e0d78 4074 LIST_HEAD(ns_list);
5bae7f73 4075
0157ec8d
SG
4076 /*
4077 * make sure to requeue I/O to all namespaces as these
4078 * might result from the scan itself and must complete
4079 * for the scan_work to make progress
4080 */
4081 nvme_mpath_clear_ctrl_paths(ctrl);
4082
f6c8e432
SG
4083 /* prevent racing with ns scanning */
4084 flush_work(&ctrl->scan_work);
4085
0ff9d4e1
KB
4086 /*
4087 * The dead states indicates the controller was not gracefully
4088 * disconnected. In that case, we won't be able to flush any data while
4089 * removing the namespaces' disks; fail all the queues now to avoid
4090 * potentially having to clean up the failed sync later.
4091 */
4092 if (ctrl->state == NVME_CTRL_DEAD)
4093 nvme_kill_queues(ctrl);
4094
ecca390e
SG
4095 /* this is a no-op when called from the controller reset handler */
4096 nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING_NOIO);
4097
765cc031 4098 down_write(&ctrl->namespaces_rwsem);
6f8e0d78 4099 list_splice_init(&ctrl->namespaces, &ns_list);
765cc031 4100 up_write(&ctrl->namespaces_rwsem);
6f8e0d78
JW
4101
4102 list_for_each_entry_safe(ns, next, &ns_list, list)
5bae7f73
CH
4103 nvme_ns_remove(ns);
4104}
576d55d6 4105EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 4106
a42f42e5
SG
4107static int nvme_class_uevent(struct device *dev, struct kobj_uevent_env *env)
4108{
4109 struct nvme_ctrl *ctrl =
4110 container_of(dev, struct nvme_ctrl, ctrl_device);
4111 struct nvmf_ctrl_options *opts = ctrl->opts;
4112 int ret;
4113
4114 ret = add_uevent_var(env, "NVME_TRTYPE=%s", ctrl->ops->name);
4115 if (ret)
4116 return ret;
4117
4118 if (opts) {
4119 ret = add_uevent_var(env, "NVME_TRADDR=%s", opts->traddr);
4120 if (ret)
4121 return ret;
4122
4123 ret = add_uevent_var(env, "NVME_TRSVCID=%s",
4124 opts->trsvcid ?: "none");
4125 if (ret)
4126 return ret;
4127
4128 ret = add_uevent_var(env, "NVME_HOST_TRADDR=%s",
4129 opts->host_traddr ?: "none");
3ede8f72
MB
4130 if (ret)
4131 return ret;
4132
4133 ret = add_uevent_var(env, "NVME_HOST_IFACE=%s",
4134 opts->host_iface ?: "none");
a42f42e5
SG
4135 }
4136 return ret;
4137}
4138
e3d7874d
KB
4139static void nvme_aen_uevent(struct nvme_ctrl *ctrl)
4140{
4141 char *envp[2] = { NULL, NULL };
4142 u32 aen_result = ctrl->aen_result;
4143
4144 ctrl->aen_result = 0;
4145 if (!aen_result)
4146 return;
4147
4148 envp[0] = kasprintf(GFP_KERNEL, "NVME_AEN=%#08x", aen_result);
4149 if (!envp[0])
4150 return;
4151 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp);
4152 kfree(envp[0]);
4153}
4154
f866fc42
CH
4155static void nvme_async_event_work(struct work_struct *work)
4156{
4157 struct nvme_ctrl *ctrl =
4158 container_of(work, struct nvme_ctrl, async_event_work);
4159
e3d7874d 4160 nvme_aen_uevent(ctrl);
ad22c355 4161 ctrl->ops->submit_async_event(ctrl);
f866fc42
CH
4162}
4163
b6dccf7f
AD
4164static bool nvme_ctrl_pp_status(struct nvme_ctrl *ctrl)
4165{
4166
4167 u32 csts;
4168
4169 if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts))
4170 return false;
4171
4172 if (csts == ~0)
4173 return false;
4174
4175 return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP));
4176}
4177
4178static void nvme_get_fw_slot_info(struct nvme_ctrl *ctrl)
4179{
b6dccf7f
AD
4180 struct nvme_fw_slot_info_log *log;
4181
4182 log = kmalloc(sizeof(*log), GFP_KERNEL);
4183 if (!log)
4184 return;
4185
be93e87e
KB
4186 if (nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_FW_SLOT, 0, NVME_CSI_NVM,
4187 log, sizeof(*log), 0))
0e98719b 4188 dev_warn(ctrl->device, "Get FW SLOT INFO log error\n");
b6dccf7f
AD
4189 kfree(log);
4190}
4191
4192static void nvme_fw_act_work(struct work_struct *work)
4193{
4194 struct nvme_ctrl *ctrl = container_of(work,
4195 struct nvme_ctrl, fw_act_work);
4196 unsigned long fw_act_timeout;
4197
4198 if (ctrl->mtfa)
4199 fw_act_timeout = jiffies +
4200 msecs_to_jiffies(ctrl->mtfa * 100);
4201 else
4202 fw_act_timeout = jiffies +
4203 msecs_to_jiffies(admin_timeout * 1000);
4204
4205 nvme_stop_queues(ctrl);
4206 while (nvme_ctrl_pp_status(ctrl)) {
4207 if (time_after(jiffies, fw_act_timeout)) {
4208 dev_warn(ctrl->device,
4209 "Fw activation timeout, reset controller\n");
4c75f877
KB
4210 nvme_try_sched_reset(ctrl);
4211 return;
b6dccf7f
AD
4212 }
4213 msleep(100);
4214 }
4215
4c75f877 4216 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_LIVE))
b6dccf7f
AD
4217 return;
4218
4219 nvme_start_queues(ctrl);
a806c6c8 4220 /* read FW slot information to clear the AER */
b6dccf7f
AD
4221 nvme_get_fw_slot_info(ctrl);
4222}
4223
868c2392
CH
4224static void nvme_handle_aen_notice(struct nvme_ctrl *ctrl, u32 result)
4225{
09bd1ff4
CK
4226 u32 aer_notice_type = (result & 0xff00) >> 8;
4227
521cfb8e
CK
4228 trace_nvme_async_event(ctrl, aer_notice_type);
4229
09bd1ff4 4230 switch (aer_notice_type) {
868c2392 4231 case NVME_AER_NOTICE_NS_CHANGED:
77016199 4232 set_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events);
868c2392
CH
4233 nvme_queue_scan(ctrl);
4234 break;
4235 case NVME_AER_NOTICE_FW_ACT_STARTING:
4c75f877
KB
4236 /*
4237 * We are (ab)using the RESETTING state to prevent subsequent
4238 * recovery actions from interfering with the controller's
4239 * firmware activation.
4240 */
4241 if (nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
4242 queue_work(nvme_wq, &ctrl->fw_act_work);
868c2392 4243 break;
0d0b660f
CH
4244#ifdef CONFIG_NVME_MULTIPATH
4245 case NVME_AER_NOTICE_ANA:
4246 if (!ctrl->ana_log_buf)
4247 break;
4248 queue_work(nvme_wq, &ctrl->ana_work);
4249 break;
4250#endif
85f8a435
SG
4251 case NVME_AER_NOTICE_DISC_CHANGED:
4252 ctrl->aen_result = result;
4253 break;
868c2392
CH
4254 default:
4255 dev_warn(ctrl->device, "async event result %08x\n", result);
4256 }
4257}
4258
7bf58533 4259void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
287a63eb 4260 volatile union nvme_result *res)
f866fc42 4261{
7bf58533 4262 u32 result = le32_to_cpu(res->u32);
09bd1ff4 4263 u32 aer_type = result & 0x07;
f866fc42 4264
ad22c355 4265 if (le16_to_cpu(status) >> 1 != NVME_SC_SUCCESS)
f866fc42
CH
4266 return;
4267
09bd1ff4 4268 switch (aer_type) {
868c2392
CH
4269 case NVME_AER_NOTICE:
4270 nvme_handle_aen_notice(ctrl, result);
4271 break;
e3d7874d
KB
4272 case NVME_AER_ERROR:
4273 case NVME_AER_SMART:
4274 case NVME_AER_CSS:
4275 case NVME_AER_VS:
09bd1ff4 4276 trace_nvme_async_event(ctrl, aer_type);
e3d7874d 4277 ctrl->aen_result = result;
7bf58533
CH
4278 break;
4279 default:
4280 break;
f866fc42 4281 }
c669ccdc 4282 queue_work(nvme_wq, &ctrl->async_event_work);
f866fc42 4283}
f866fc42 4284EXPORT_SYMBOL_GPL(nvme_complete_async_event);
f3ca80fc 4285
d09f2b45 4286void nvme_stop_ctrl(struct nvme_ctrl *ctrl)
576d55d6 4287{
0d0b660f 4288 nvme_mpath_stop(ctrl);
d09f2b45 4289 nvme_stop_keep_alive(ctrl);
8c4dfea9 4290 nvme_stop_failfast_work(ctrl);
f866fc42 4291 flush_work(&ctrl->async_event_work);
b6dccf7f 4292 cancel_work_sync(&ctrl->fw_act_work);
d09f2b45
SG
4293}
4294EXPORT_SYMBOL_GPL(nvme_stop_ctrl);
4295
4296void nvme_start_ctrl(struct nvme_ctrl *ctrl)
4297{
5887450b 4298 nvme_start_keep_alive(ctrl);
d09f2b45 4299
93da4023
SG
4300 nvme_enable_aen(ctrl);
4301
d09f2b45
SG
4302 if (ctrl->queue_count > 1) {
4303 nvme_queue_scan(ctrl);
d09f2b45
SG
4304 nvme_start_queues(ctrl);
4305 }
4306}
4307EXPORT_SYMBOL_GPL(nvme_start_ctrl);
5955be21 4308
d09f2b45
SG
4309void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
4310{
ed7770f6 4311 nvme_hwmon_exit(ctrl);
f79d5fda 4312 nvme_fault_inject_fini(&ctrl->fault_inject);
510a405d 4313 dev_pm_qos_hide_latency_tolerance(ctrl->device);
a6a5149b 4314 cdev_device_del(&ctrl->cdev, ctrl->device);
726612b6 4315 nvme_put_ctrl(ctrl);
53029b04 4316}
576d55d6 4317EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04 4318
8168d23f
KB
4319static void nvme_free_cels(struct nvme_ctrl *ctrl)
4320{
4321 struct nvme_effects_log *cel;
4322 unsigned long i;
4323
8f8ea928 4324 xa_for_each(&ctrl->cels, i, cel) {
8168d23f
KB
4325 xa_erase(&ctrl->cels, i);
4326 kfree(cel);
4327 }
4328
4329 xa_destroy(&ctrl->cels);
4330}
4331
d22524a4 4332static void nvme_free_ctrl(struct device *dev)
53029b04 4333{
d22524a4
CH
4334 struct nvme_ctrl *ctrl =
4335 container_of(dev, struct nvme_ctrl, ctrl_device);
ab9e00cc 4336 struct nvme_subsystem *subsys = ctrl->subsys;
f3ca80fc 4337
192f6c29 4338 if (!subsys || ctrl->instance != subsys->instance)
733e4b69
KB
4339 ida_simple_remove(&nvme_instance_ida, ctrl->instance);
4340
8168d23f 4341 nvme_free_cels(ctrl);
0d0b660f 4342 nvme_mpath_uninit(ctrl);
092ff052 4343 __free_page(ctrl->discard_page);
f3ca80fc 4344
ab9e00cc 4345 if (subsys) {
32fd90c4 4346 mutex_lock(&nvme_subsystems_lock);
ab9e00cc 4347 list_del(&ctrl->subsys_entry);
ab9e00cc 4348 sysfs_remove_link(&subsys->dev.kobj, dev_name(ctrl->device));
32fd90c4 4349 mutex_unlock(&nvme_subsystems_lock);
ab9e00cc 4350 }
f3ca80fc
CH
4351
4352 ctrl->ops->free_ctrl(ctrl);
f3ca80fc 4353
ab9e00cc
CH
4354 if (subsys)
4355 nvme_put_subsystem(subsys);
f3ca80fc
CH
4356}
4357
4358/*
4359 * Initialize a NVMe controller structures. This needs to be called during
4360 * earliest initialization so that we have the initialized structured around
4361 * during probing.
4362 */
4363int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
4364 const struct nvme_ctrl_ops *ops, unsigned long quirks)
4365{
4366 int ret;
4367
bb8d261e 4368 ctrl->state = NVME_CTRL_NEW;
8c4dfea9 4369 clear_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags);
bb8d261e 4370 spin_lock_init(&ctrl->lock);
e7ad43c3 4371 mutex_init(&ctrl->scan_lock);
f3ca80fc 4372 INIT_LIST_HEAD(&ctrl->namespaces);
1cf7a12e 4373 xa_init(&ctrl->cels);
765cc031 4374 init_rwsem(&ctrl->namespaces_rwsem);
f3ca80fc
CH
4375 ctrl->dev = dev;
4376 ctrl->ops = ops;
4377 ctrl->quirks = quirks;
4fea243e 4378 ctrl->numa_node = NUMA_NO_NODE;
5955be21 4379 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 4380 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
b6dccf7f 4381 INIT_WORK(&ctrl->fw_act_work, nvme_fw_act_work);
c5017e85 4382 INIT_WORK(&ctrl->delete_work, nvme_delete_ctrl_work);
c1ac9a4b 4383 init_waitqueue_head(&ctrl->state_wq);
f3ca80fc 4384
230f1f9e 4385 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
8c4dfea9 4386 INIT_DELAYED_WORK(&ctrl->failfast_work, nvme_failfast_work);
230f1f9e
JS
4387 memset(&ctrl->ka_cmd, 0, sizeof(ctrl->ka_cmd));
4388 ctrl->ka_cmd.common.opcode = nvme_admin_keep_alive;
4389
cb5b7262
JA
4390 BUILD_BUG_ON(NVME_DSM_MAX_RANGES * sizeof(struct nvme_dsm_range) >
4391 PAGE_SIZE);
4392 ctrl->discard_page = alloc_page(GFP_KERNEL);
4393 if (!ctrl->discard_page) {
4394 ret = -ENOMEM;
4395 goto out;
4396 }
4397
9843f685
CH
4398 ret = ida_simple_get(&nvme_instance_ida, 0, 0, GFP_KERNEL);
4399 if (ret < 0)
f3ca80fc 4400 goto out;
9843f685 4401 ctrl->instance = ret;
f3ca80fc 4402
d22524a4
CH
4403 device_initialize(&ctrl->ctrl_device);
4404 ctrl->device = &ctrl->ctrl_device;
f68abd9c
JG
4405 ctrl->device->devt = MKDEV(MAJOR(nvme_ctrl_base_chr_devt),
4406 ctrl->instance);
d22524a4
CH
4407 ctrl->device->class = nvme_class;
4408 ctrl->device->parent = ctrl->dev;
4409 ctrl->device->groups = nvme_dev_attr_groups;
4410 ctrl->device->release = nvme_free_ctrl;
4411 dev_set_drvdata(ctrl->device, ctrl);
4412 ret = dev_set_name(ctrl->device, "nvme%d", ctrl->instance);
4413 if (ret)
f3ca80fc 4414 goto out_release_instance;
f3ca80fc 4415
b780d741 4416 nvme_get_ctrl(ctrl);
a6a5149b
CH
4417 cdev_init(&ctrl->cdev, &nvme_dev_fops);
4418 ctrl->cdev.owner = ops->module;
4419 ret = cdev_device_add(&ctrl->cdev, ctrl->device);
d22524a4
CH
4420 if (ret)
4421 goto out_free_name;
f3ca80fc 4422
c5552fde
AL
4423 /*
4424 * Initialize latency tolerance controls. The sysfs files won't
4425 * be visible to userspace unless the device actually supports APST.
4426 */
4427 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
4428 dev_pm_qos_update_user_latency_tolerance(ctrl->device,
4429 min(default_ps_max_latency_us, (unsigned long)S32_MAX));
4430
f79d5fda 4431 nvme_fault_inject_init(&ctrl->fault_inject, dev_name(ctrl->device));
5e1f6899 4432 nvme_mpath_init_ctrl(ctrl);
f79d5fda 4433
f3ca80fc 4434 return 0;
d22524a4 4435out_free_name:
b780d741 4436 nvme_put_ctrl(ctrl);
d6a2b953 4437 kfree_const(ctrl->device->kobj.name);
f3ca80fc 4438out_release_instance:
9843f685 4439 ida_simple_remove(&nvme_instance_ida, ctrl->instance);
f3ca80fc 4440out:
cb5b7262
JA
4441 if (ctrl->discard_page)
4442 __free_page(ctrl->discard_page);
f3ca80fc
CH
4443 return ret;
4444}
576d55d6 4445EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 4446
69d9a99c
KB
4447/**
4448 * nvme_kill_queues(): Ends all namespace queues
4449 * @ctrl: the dead controller that needs to end
4450 *
4451 * Call this function when the driver determines it is unable to get the
4452 * controller in a state capable of servicing IO.
4453 */
4454void nvme_kill_queues(struct nvme_ctrl *ctrl)
4455{
4456 struct nvme_ns *ns;
4457
765cc031 4458 down_read(&ctrl->namespaces_rwsem);
82654b6b 4459
443bd90f 4460 /* Forcibly unquiesce queues to avoid blocking dispatch */
751a0cc0 4461 if (ctrl->admin_q && !blk_queue_dying(ctrl->admin_q))
7dd1ab16 4462 blk_mq_unquiesce_queue(ctrl->admin_q);
443bd90f 4463
cf39a6bc
SB
4464 list_for_each_entry(ns, &ctrl->namespaces, list)
4465 nvme_set_queue_dying(ns);
806f026f 4466
765cc031 4467 up_read(&ctrl->namespaces_rwsem);
69d9a99c 4468}
237045fc 4469EXPORT_SYMBOL_GPL(nvme_kill_queues);
69d9a99c 4470
302ad8cc
KB
4471void nvme_unfreeze(struct nvme_ctrl *ctrl)
4472{
4473 struct nvme_ns *ns;
4474
765cc031 4475 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB
4476 list_for_each_entry(ns, &ctrl->namespaces, list)
4477 blk_mq_unfreeze_queue(ns->queue);
765cc031 4478 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB
4479}
4480EXPORT_SYMBOL_GPL(nvme_unfreeze);
4481
7cf0d7c0 4482int nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout)
302ad8cc
KB
4483{
4484 struct nvme_ns *ns;
4485
765cc031 4486 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB
4487 list_for_each_entry(ns, &ctrl->namespaces, list) {
4488 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout);
4489 if (timeout <= 0)
4490 break;
4491 }
765cc031 4492 up_read(&ctrl->namespaces_rwsem);
7cf0d7c0 4493 return timeout;
302ad8cc
KB
4494}
4495EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout);
4496
4497void nvme_wait_freeze(struct nvme_ctrl *ctrl)
4498{
4499 struct nvme_ns *ns;
4500
765cc031 4501 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB
4502 list_for_each_entry(ns, &ctrl->namespaces, list)
4503 blk_mq_freeze_queue_wait(ns->queue);
765cc031 4504 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB
4505}
4506EXPORT_SYMBOL_GPL(nvme_wait_freeze);
4507
4508void nvme_start_freeze(struct nvme_ctrl *ctrl)
4509{
4510 struct nvme_ns *ns;
4511
765cc031 4512 down_read(&ctrl->namespaces_rwsem);
302ad8cc 4513 list_for_each_entry(ns, &ctrl->namespaces, list)
1671d522 4514 blk_freeze_queue_start(ns->queue);
765cc031 4515 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB
4516}
4517EXPORT_SYMBOL_GPL(nvme_start_freeze);
4518
25646264 4519void nvme_stop_queues(struct nvme_ctrl *ctrl)
363c9aac
SG
4520{
4521 struct nvme_ns *ns;
4522
765cc031 4523 down_read(&ctrl->namespaces_rwsem);
a6eaa884 4524 list_for_each_entry(ns, &ctrl->namespaces, list)
3174dd33 4525 blk_mq_quiesce_queue(ns->queue);
765cc031 4526 up_read(&ctrl->namespaces_rwsem);
363c9aac 4527}
576d55d6 4528EXPORT_SYMBOL_GPL(nvme_stop_queues);
363c9aac 4529
25646264 4530void nvme_start_queues(struct nvme_ctrl *ctrl)
363c9aac
SG
4531{
4532 struct nvme_ns *ns;
4533
765cc031 4534 down_read(&ctrl->namespaces_rwsem);
8d7b8faf 4535 list_for_each_entry(ns, &ctrl->namespaces, list)
f660174e 4536 blk_mq_unquiesce_queue(ns->queue);
765cc031 4537 up_read(&ctrl->namespaces_rwsem);
363c9aac 4538}
576d55d6 4539EXPORT_SYMBOL_GPL(nvme_start_queues);
363c9aac 4540
04800fbf 4541void nvme_sync_io_queues(struct nvme_ctrl *ctrl)
d6135c3a
KB
4542{
4543 struct nvme_ns *ns;
4544
4545 down_read(&ctrl->namespaces_rwsem);
4546 list_for_each_entry(ns, &ctrl->namespaces, list)
4547 blk_sync_queue(ns->queue);
4548 up_read(&ctrl->namespaces_rwsem);
04800fbf
CL
4549}
4550EXPORT_SYMBOL_GPL(nvme_sync_io_queues);
03894b7a 4551
04800fbf
CL
4552void nvme_sync_queues(struct nvme_ctrl *ctrl)
4553{
4554 nvme_sync_io_queues(ctrl);
03894b7a
EN
4555 if (ctrl->admin_q)
4556 blk_sync_queue(ctrl->admin_q);
d6135c3a
KB
4557}
4558EXPORT_SYMBOL_GPL(nvme_sync_queues);
4559
b2702aaa 4560struct nvme_ctrl *nvme_ctrl_from_file(struct file *file)
f783f444 4561{
b2702aaa
CK
4562 if (file->f_op != &nvme_dev_fops)
4563 return NULL;
4564 return file->private_data;
f783f444 4565}
b2702aaa 4566EXPORT_SYMBOL_NS_GPL(nvme_ctrl_from_file, NVME_TARGET_PASSTHRU);
f783f444 4567
81101540
CH
4568/*
4569 * Check we didn't inadvertently grow the command structure sizes:
4570 */
4571static inline void _nvme_check_size(void)
4572{
4573 BUILD_BUG_ON(sizeof(struct nvme_common_command) != 64);
4574 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
4575 BUILD_BUG_ON(sizeof(struct nvme_identify) != 64);
4576 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
4577 BUILD_BUG_ON(sizeof(struct nvme_download_firmware) != 64);
4578 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
4579 BUILD_BUG_ON(sizeof(struct nvme_dsm_cmd) != 64);
4580 BUILD_BUG_ON(sizeof(struct nvme_write_zeroes_cmd) != 64);
4581 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
4582 BUILD_BUG_ON(sizeof(struct nvme_get_log_page_command) != 64);
4583 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
4584 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
4585 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
240e6ee2
KB
4586 BUILD_BUG_ON(sizeof(struct nvme_id_ns_zns) != NVME_IDENTIFY_DATA_SIZE);
4587 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl_zns) != NVME_IDENTIFY_DATA_SIZE);
5befc7c2 4588 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl_nvm) != NVME_IDENTIFY_DATA_SIZE);
81101540
CH
4589 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
4590 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
4591 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
4592 BUILD_BUG_ON(sizeof(struct nvme_directive_cmd) != 64);
4593}
4594
4595
893a74b7 4596static int __init nvme_core_init(void)
5bae7f73 4597{
b227c59b 4598 int result = -ENOMEM;
5bae7f73 4599
81101540
CH
4600 _nvme_check_size();
4601
9a6327d2
SG
4602 nvme_wq = alloc_workqueue("nvme-wq",
4603 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4604 if (!nvme_wq)
b227c59b
RS
4605 goto out;
4606
4607 nvme_reset_wq = alloc_workqueue("nvme-reset-wq",
4608 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4609 if (!nvme_reset_wq)
4610 goto destroy_wq;
4611
4612 nvme_delete_wq = alloc_workqueue("nvme-delete-wq",
4613 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4614 if (!nvme_delete_wq)
4615 goto destroy_reset_wq;
9a6327d2 4616
f68abd9c
JG
4617 result = alloc_chrdev_region(&nvme_ctrl_base_chr_devt, 0,
4618 NVME_MINORS, "nvme");
f3ca80fc 4619 if (result < 0)
b227c59b 4620 goto destroy_delete_wq;
f3ca80fc
CH
4621
4622 nvme_class = class_create(THIS_MODULE, "nvme");
4623 if (IS_ERR(nvme_class)) {
4624 result = PTR_ERR(nvme_class);
4625 goto unregister_chrdev;
4626 }
a42f42e5 4627 nvme_class->dev_uevent = nvme_class_uevent;
f3ca80fc 4628
ab9e00cc
CH
4629 nvme_subsys_class = class_create(THIS_MODULE, "nvme-subsystem");
4630 if (IS_ERR(nvme_subsys_class)) {
4631 result = PTR_ERR(nvme_subsys_class);
4632 goto destroy_class;
4633 }
2637baed
MI
4634
4635 result = alloc_chrdev_region(&nvme_ns_chr_devt, 0, NVME_MINORS,
4636 "nvme-generic");
4637 if (result < 0)
4638 goto destroy_subsys_class;
4639
4640 nvme_ns_chr_class = class_create(THIS_MODULE, "nvme-generic");
4641 if (IS_ERR(nvme_ns_chr_class)) {
4642 result = PTR_ERR(nvme_ns_chr_class);
4643 goto unregister_generic_ns;
4644 }
4645
5bae7f73 4646 return 0;
f3ca80fc 4647
2637baed
MI
4648unregister_generic_ns:
4649 unregister_chrdev_region(nvme_ns_chr_devt, NVME_MINORS);
4650destroy_subsys_class:
4651 class_destroy(nvme_subsys_class);
ab9e00cc
CH
4652destroy_class:
4653 class_destroy(nvme_class);
9a6327d2 4654unregister_chrdev:
f68abd9c 4655 unregister_chrdev_region(nvme_ctrl_base_chr_devt, NVME_MINORS);
b227c59b
RS
4656destroy_delete_wq:
4657 destroy_workqueue(nvme_delete_wq);
4658destroy_reset_wq:
4659 destroy_workqueue(nvme_reset_wq);
9a6327d2
SG
4660destroy_wq:
4661 destroy_workqueue(nvme_wq);
b227c59b 4662out:
f3ca80fc 4663 return result;
5bae7f73
CH
4664}
4665
893a74b7 4666static void __exit nvme_core_exit(void)
5bae7f73 4667{
2637baed 4668 class_destroy(nvme_ns_chr_class);
ab9e00cc 4669 class_destroy(nvme_subsys_class);
f3ca80fc 4670 class_destroy(nvme_class);
2637baed 4671 unregister_chrdev_region(nvme_ns_chr_devt, NVME_MINORS);
f68abd9c 4672 unregister_chrdev_region(nvme_ctrl_base_chr_devt, NVME_MINORS);
b227c59b
RS
4673 destroy_workqueue(nvme_delete_wq);
4674 destroy_workqueue(nvme_reset_wq);
9a6327d2 4675 destroy_workqueue(nvme_wq);
2637baed 4676 ida_destroy(&nvme_ns_chr_minor_ida);
f41cfd5d 4677 ida_destroy(&nvme_instance_ida);
5bae7f73 4678}
576d55d6
ML
4679
4680MODULE_LICENSE("GPL");
4681MODULE_VERSION("1.0");
4682module_init(nvme_core_init);
4683module_exit(nvme_core_exit);