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21d34711
CH		 1/*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/blkdev.h>
16#include <linux/blk-mq.h>
5fd4ce1b 17#include <linux/delay.h>
21d34711 18#include <linux/errno.h>
1673f1f0 19#include <linux/hdreg.h>
21d34711 20#include <linux/kernel.h>
5bae7f73
CH		 21#include <linux/module.h>
22#include <linux/list_sort.h>
21d34711
CH		 23#include <linux/slab.h>
24#include <linux/types.h>
1673f1f0
CH		 25#include <linux/pr.h>
26#include <linux/ptrace.h>
27#include <linux/nvme_ioctl.h>
28#include <linux/t10-pi.h>
c5552fde 29#include <linux/pm_qos.h>
1673f1f0 30#include <asm/unaligned.h>
21d34711
CH		 31
32#include "nvme.h"
038bd4cb 33#include "fabrics.h"
21d34711 34
f3ca80fc
CH		 35#define NVME_MINORS (1U << MINORBITS)
36
8ae4e447
MO		 37unsigned int admin_timeout = 60;
38module_param(admin_timeout, uint, 0644);
ba0ba7d3 39MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 40EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3 41
8ae4e447
MO		 42unsigned int nvme_io_timeout = 30;
43module_param_named(io_timeout, nvme_io_timeout, uint, 0644);
ba0ba7d3 44MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 45EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3 46
b3b1b0b0 47static unsigned char shutdown_timeout = 5;
ba0ba7d3
ML		 48module_param(shutdown_timeout, byte, 0644);
49MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
50
44e44b29
CH		 51static u8 nvme_max_retries = 5;
52module_param_named(max_retries, nvme_max_retries, byte, 0644);
f80ec966 53MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
5bae7f73 54
9947d6a0 55static unsigned long default_ps_max_latency_us = 100000;
c5552fde
AL		 56module_param(default_ps_max_latency_us, ulong, 0644);
57MODULE_PARM_DESC(default_ps_max_latency_us,
58 "max power saving latency for new devices; use PM QOS to change per device");
59
c35e30b4
AL		 60static bool force_apst;
61module_param(force_apst, bool, 0644);
62MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off");
63
f5d11840
JA		 64static bool streams;
65module_param(streams, bool, 0644);
66MODULE_PARM_DESC(streams, "turn on support for Streams write directives");
67
9a6327d2
SG		 68struct workqueue_struct *nvme_wq;
69EXPORT_SYMBOL_GPL(nvme_wq);
70
ab9e00cc
CH		 71static DEFINE_IDA(nvme_subsystems_ida);
72static LIST_HEAD(nvme_subsystems);
73static DEFINE_MUTEX(nvme_subsystems_lock);
1673f1f0 74
9843f685 75static DEFINE_IDA(nvme_instance_ida);
a6a5149b 76static dev_t nvme_chr_devt;
f3ca80fc 77static struct class *nvme_class;
ab9e00cc 78static struct class *nvme_subsys_class;
f3ca80fc 79
84fef62d
KB		 80static void nvme_ns_remove(struct nvme_ns *ns);
81static int nvme_revalidate_disk(struct gendisk *disk);
f3ca80fc 82
b6dccf7f
AD		 83static __le32 nvme_get_log_dw10(u8 lid, size_t size)
84{
85 return cpu_to_le32((((size / 4) - 1) << 16) | lid);
86}
87
d86c4d8e
CH		 88int nvme_reset_ctrl(struct nvme_ctrl *ctrl)
89{
90 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
91 return -EBUSY;
92 if (!queue_work(nvme_wq, &ctrl->reset_work))
93 return -EBUSY;
94 return 0;
95}
96EXPORT_SYMBOL_GPL(nvme_reset_ctrl);
97
98static int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
99{
100 int ret;
101
102 ret = nvme_reset_ctrl(ctrl);
103 if (!ret)
104 flush_work(&ctrl->reset_work);
105 return ret;
106}
107
c5017e85
CH		 108static void nvme_delete_ctrl_work(struct work_struct *work)
109{
110 struct nvme_ctrl *ctrl =
111 container_of(work, struct nvme_ctrl, delete_work);
112
4054637c 113 flush_work(&ctrl->reset_work);
6cd53d14
CH		 114 nvme_stop_ctrl(ctrl);
115 nvme_remove_namespaces(ctrl);
c5017e85 116 ctrl->ops->delete_ctrl(ctrl);
6cd53d14
CH		 117 nvme_uninit_ctrl(ctrl);
118 nvme_put_ctrl(ctrl);
c5017e85
CH		 119}
120
121int nvme_delete_ctrl(struct nvme_ctrl *ctrl)
122{
123 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
124 return -EBUSY;
125 if (!queue_work(nvme_wq, &ctrl->delete_work))
126 return -EBUSY;
127 return 0;
128}
129EXPORT_SYMBOL_GPL(nvme_delete_ctrl);
130
131int nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl)
132{
133 int ret = 0;
134
135 /*
136 * Keep a reference until the work is flushed since ->delete_ctrl
137 * can free the controller.
138 */
139 nvme_get_ctrl(ctrl);
140 ret = nvme_delete_ctrl(ctrl);
141 if (!ret)
142 flush_work(&ctrl->delete_work);
143 nvme_put_ctrl(ctrl);
144 return ret;
145}
146EXPORT_SYMBOL_GPL(nvme_delete_ctrl_sync);
147
715ea9e0
CH		 148static inline bool nvme_ns_has_pi(struct nvme_ns *ns)
149{
150 return ns->pi_type && ns->ms == sizeof(struct t10_pi_tuple);
151}
152
2a842aca 153static blk_status_t nvme_error_status(struct request *req)
27fa9bc5
CH		 154{
155 switch (nvme_req(req)->status & 0x7ff) {
156 case NVME_SC_SUCCESS:
2a842aca 157 return BLK_STS_OK;
27fa9bc5 158 case NVME_SC_CAP_EXCEEDED:
2a842aca 159 return BLK_STS_NOSPC;
e02ab023 160 case NVME_SC_ONCS_NOT_SUPPORTED:
2a842aca 161 return BLK_STS_NOTSUPP;
e02ab023
JG		 162 case NVME_SC_WRITE_FAULT:
163 case NVME_SC_READ_ERROR:
164 case NVME_SC_UNWRITTEN_BLOCK:
a751da33
CH		 165 case NVME_SC_ACCESS_DENIED:
166 case NVME_SC_READ_ONLY:
2a842aca 167 return BLK_STS_MEDIUM;
a751da33
CH		 168 case NVME_SC_GUARD_CHECK:
169 case NVME_SC_APPTAG_CHECK:
170 case NVME_SC_REFTAG_CHECK:
171 case NVME_SC_INVALID_PI:
172 return BLK_STS_PROTECTION;
173 case NVME_SC_RESERVATION_CONFLICT:
174 return BLK_STS_NEXUS;
2a842aca
CH		 175 default:
176 return BLK_STS_IOERR;
27fa9bc5
CH		 177 }
178}
27fa9bc5 179
f6324b1b 180static inline bool nvme_req_needs_retry(struct request *req)
77f02a7a 181{
f6324b1b
CH		 182 if (blk_noretry_request(req))
183 return false;
27fa9bc5 184 if (nvme_req(req)->status & NVME_SC_DNR)
f6324b1b 185 return false;
44e44b29 186 if (nvme_req(req)->retries >= nvme_max_retries)
f6324b1b
CH		 187 return false;
188 return true;
77f02a7a
CH		 189}
190
191void nvme_complete_rq(struct request *req)
192{
27fa9bc5 193 if (unlikely(nvme_req(req)->status && nvme_req_needs_retry(req))) {
32acab31
CH		 194 if (nvme_req_needs_failover(req)) {
195 nvme_failover_req(req);
196 return;
197 }
198
199 if (!blk_queue_dying(req->q)) {
200 nvme_req(req)->retries++;
201 blk_mq_requeue_request(req, true);
202 return;
203 }
77f02a7a
CH		 204 }
205
27fa9bc5 206 blk_mq_end_request(req, nvme_error_status(req));
77f02a7a
CH		 207}
208EXPORT_SYMBOL_GPL(nvme_complete_rq);
209
c55a2fd4
ML		 210void nvme_cancel_request(struct request *req, void *data, bool reserved)
211{
c55a2fd4
ML		 212 if (!blk_mq_request_started(req))
213 return;
214
215 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
216 "Cancelling I/O %d", req->tag);
217
e54b064c 218 nvme_req(req)->status = NVME_SC_ABORT_REQ;
08e0029a 219 blk_mq_complete_request(req);
27fa9bc5 220
c55a2fd4
ML		 221}
222EXPORT_SYMBOL_GPL(nvme_cancel_request);
223
bb8d261e
CH		 224bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
225 enum nvme_ctrl_state new_state)
226{
f6b6a28e 227 enum nvme_ctrl_state old_state;
0a72bbba 228 unsigned long flags;
bb8d261e
CH		 229 bool changed = false;
230
0a72bbba 231 spin_lock_irqsave(&ctrl->lock, flags);
f6b6a28e
GKB		 232
233 old_state = ctrl->state;
bb8d261e
CH		 234 switch (new_state) {
235 case NVME_CTRL_LIVE:
236 switch (old_state) {
7d2e8008 237 case NVME_CTRL_NEW:
bb8d261e 238 case NVME_CTRL_RESETTING:
def61eca 239 case NVME_CTRL_RECONNECTING:
bb8d261e
CH		 240 changed = true;
241 /* FALLTHRU */
242 default:
243 break;
244 }
245 break;
246 case NVME_CTRL_RESETTING:
247 switch (old_state) {
248 case NVME_CTRL_NEW:
def61eca 249 case NVME_CTRL_LIVE:
def61eca
CH		 250 changed = true;
251 /* FALLTHRU */
252 default:
253 break;
254 }
255 break;
256 case NVME_CTRL_RECONNECTING:
257 switch (old_state) {
bb8d261e 258 case NVME_CTRL_LIVE:
3cec7f9d 259 case NVME_CTRL_RESETTING:
bb8d261e
CH		 260 changed = true;
261 /* FALLTHRU */
262 default:
263 break;
264 }
265 break;
266 case NVME_CTRL_DELETING:
267 switch (old_state) {
268 case NVME_CTRL_LIVE:
269 case NVME_CTRL_RESETTING:
def61eca 270 case NVME_CTRL_RECONNECTING:
bb8d261e
CH		 271 changed = true;
272 /* FALLTHRU */
273 default:
274 break;
275 }
276 break;
0ff9d4e1
KB		 277 case NVME_CTRL_DEAD:
278 switch (old_state) {
279 case NVME_CTRL_DELETING:
280 changed = true;
281 /* FALLTHRU */
282 default:
283 break;
284 }
285 break;
bb8d261e
CH		 286 default:
287 break;
288 }
bb8d261e
CH		 289
290 if (changed)
291 ctrl->state = new_state;
292
0a72bbba 293 spin_unlock_irqrestore(&ctrl->lock, flags);
32acab31
CH		 294 if (changed && ctrl->state == NVME_CTRL_LIVE)
295 nvme_kick_requeue_lists(ctrl);
bb8d261e
CH		 296 return changed;
297}
298EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
299
ed754e5d
CH		 300static void nvme_free_ns_head(struct kref *ref)
301{
302 struct nvme_ns_head *head =
303 container_of(ref, struct nvme_ns_head, ref);
304
32acab31 305 nvme_mpath_remove_disk(head);
ed754e5d
CH		 306 ida_simple_remove(&head->subsys->ns_ida, head->instance);
307 list_del_init(&head->entry);
308 cleanup_srcu_struct(&head->srcu);
309 kfree(head);
310}
311
312static void nvme_put_ns_head(struct nvme_ns_head *head)
313{
314 kref_put(&head->ref, nvme_free_ns_head);
315}
316
1673f1f0
CH		 317static void nvme_free_ns(struct kref *kref)
318{
319 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
320
b0b4e09c
MB		 321 if (ns->ndev)
322 nvme_nvm_unregister(ns);
1673f1f0 323
1673f1f0 324 put_disk(ns->disk);
ed754e5d 325 nvme_put_ns_head(ns->head);
075790eb 326 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH		 327 kfree(ns);
328}
329
5bae7f73 330static void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH		 331{
332 kref_put(&ns->kref, nvme_free_ns);
333}
334
4160982e 335struct request *nvme_alloc_request(struct request_queue *q,
9a95e4ef 336 struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid)
21d34711 337{
aebf526b 338 unsigned op = nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN;
21d34711 339 struct request *req;
21d34711 340
eb71f435 341 if (qid == NVME_QID_ANY) {
aebf526b 342 req = blk_mq_alloc_request(q, op, flags);
eb71f435 343 } else {
aebf526b 344 req = blk_mq_alloc_request_hctx(q, op, flags,
eb71f435
CH		 345 qid ? qid - 1 : 0);
346 }
21d34711 347 if (IS_ERR(req))
4160982e 348 return req;
21d34711 349
21d34711 350 req->cmd_flags |= REQ_FAILFAST_DRIVER;
d49187e9 351 nvme_req(req)->cmd = cmd;
21d34711 352
4160982e
CH		 353 return req;
354}
576d55d6 355EXPORT_SYMBOL_GPL(nvme_alloc_request);
4160982e 356
f5d11840
JA		 357static int nvme_toggle_streams(struct nvme_ctrl *ctrl, bool enable)
358{
359 struct nvme_command c;
360
361 memset(&c, 0, sizeof(c));
362
363 c.directive.opcode = nvme_admin_directive_send;
62346eae 364 c.directive.nsid = cpu_to_le32(NVME_NSID_ALL);
f5d11840
JA		 365 c.directive.doper = NVME_DIR_SND_ID_OP_ENABLE;
366 c.directive.dtype = NVME_DIR_IDENTIFY;
367 c.directive.tdtype = NVME_DIR_STREAMS;
368 c.directive.endir = enable ? NVME_DIR_ENDIR : 0;
369
370 return nvme_submit_sync_cmd(ctrl->admin_q, &c, NULL, 0);
371}
372
373static int nvme_disable_streams(struct nvme_ctrl *ctrl)
374{
375 return nvme_toggle_streams(ctrl, false);
376}
377
378static int nvme_enable_streams(struct nvme_ctrl *ctrl)
379{
380 return nvme_toggle_streams(ctrl, true);
381}
382
383static int nvme_get_stream_params(struct nvme_ctrl *ctrl,
384 struct streams_directive_params *s, u32 nsid)
385{
386 struct nvme_command c;
387
388 memset(&c, 0, sizeof(c));
389 memset(s, 0, sizeof(*s));
390
391 c.directive.opcode = nvme_admin_directive_recv;
392 c.directive.nsid = cpu_to_le32(nsid);
a082b426 393 c.directive.numd = cpu_to_le32((sizeof(*s) >> 2) - 1);
f5d11840
JA		 394 c.directive.doper = NVME_DIR_RCV_ST_OP_PARAM;
395 c.directive.dtype = NVME_DIR_STREAMS;
396
397 return nvme_submit_sync_cmd(ctrl->admin_q, &c, s, sizeof(*s));
398}
399
400static int nvme_configure_directives(struct nvme_ctrl *ctrl)
401{
402 struct streams_directive_params s;
403 int ret;
404
405 if (!(ctrl->oacs & NVME_CTRL_OACS_DIRECTIVES))
406 return 0;
407 if (!streams)
408 return 0;
409
410 ret = nvme_enable_streams(ctrl);
411 if (ret)
412 return ret;
413
62346eae 414 ret = nvme_get_stream_params(ctrl, &s, NVME_NSID_ALL);
f5d11840
JA		 415 if (ret)
416 return ret;
417
418 ctrl->nssa = le16_to_cpu(s.nssa);
419 if (ctrl->nssa < BLK_MAX_WRITE_HINTS - 1) {
420 dev_info(ctrl->device, "too few streams (%u) available\n",
421 ctrl->nssa);
422 nvme_disable_streams(ctrl);
423 return 0;
424 }
425
426 ctrl->nr_streams = min_t(unsigned, ctrl->nssa, BLK_MAX_WRITE_HINTS - 1);
427 dev_info(ctrl->device, "Using %u streams\n", ctrl->nr_streams);
428 return 0;
429}
430
431/*
432 * Check if 'req' has a write hint associated with it. If it does, assign
433 * a valid namespace stream to the write.
434 */
435static void nvme_assign_write_stream(struct nvme_ctrl *ctrl,
436 struct request *req, u16 *control,
437 u32 *dsmgmt)
438{
439 enum rw_hint streamid = req->write_hint;
440
441 if (streamid == WRITE_LIFE_NOT_SET || streamid == WRITE_LIFE_NONE)
442 streamid = 0;
443 else {
444 streamid--;
445 if (WARN_ON_ONCE(streamid > ctrl->nr_streams))
446 return;
447
448 *control |= NVME_RW_DTYPE_STREAMS;
449 *dsmgmt |= streamid << 16;
450 }
451
452 if (streamid < ARRAY_SIZE(req->q->write_hints))
453 req->q->write_hints[streamid] += blk_rq_bytes(req) >> 9;
454}
455
8093f7ca
ML		 456static inline void nvme_setup_flush(struct nvme_ns *ns,
457 struct nvme_command *cmnd)
458{
459 memset(cmnd, 0, sizeof(*cmnd));
460 cmnd->common.opcode = nvme_cmd_flush;
ed754e5d 461 cmnd->common.nsid = cpu_to_le32(ns->head->ns_id);
8093f7ca
ML		 462}
463
fc17b653 464static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 465 struct nvme_command *cmnd)
466{
b35ba01e 467 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
8093f7ca 468 struct nvme_dsm_range *range;
b35ba01e 469 struct bio *bio;
8093f7ca 470
b35ba01e 471 range = kmalloc_array(segments, sizeof(*range), GFP_ATOMIC);
8093f7ca 472 if (!range)
fc17b653 473 return BLK_STS_RESOURCE;
8093f7ca 474
b35ba01e
CH		 475 __rq_for_each_bio(bio, req) {
476 u64 slba = nvme_block_nr(ns, bio->bi_iter.bi_sector);
477 u32 nlb = bio->bi_iter.bi_size >> ns->lba_shift;
478
479 range[n].cattr = cpu_to_le32(0);
480 range[n].nlb = cpu_to_le32(nlb);
481 range[n].slba = cpu_to_le64(slba);
482 n++;
483 }
484
485 if (WARN_ON_ONCE(n != segments)) {
486 kfree(range);
fc17b653 487 return BLK_STS_IOERR;
b35ba01e 488 }
8093f7ca
ML		 489
490 memset(cmnd, 0, sizeof(*cmnd));
491 cmnd->dsm.opcode = nvme_cmd_dsm;
ed754e5d 492 cmnd->dsm.nsid = cpu_to_le32(ns->head->ns_id);
f1dd03a8 493 cmnd->dsm.nr = cpu_to_le32(segments - 1);
8093f7ca
ML		 494 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
495
f9d03f96
CH		 496 req->special_vec.bv_page = virt_to_page(range);
497 req->special_vec.bv_offset = offset_in_page(range);
b35ba01e 498 req->special_vec.bv_len = sizeof(*range) * segments;
f9d03f96 499 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 500
fc17b653 501 return BLK_STS_OK;
8093f7ca 502}
8093f7ca 503
ebe6d874
CH		 504static inline blk_status_t nvme_setup_rw(struct nvme_ns *ns,
505 struct request *req, struct nvme_command *cmnd)
8093f7ca 506{
f5d11840 507 struct nvme_ctrl *ctrl = ns->ctrl;
8093f7ca
ML		 508 u16 control = 0;
509 u32 dsmgmt = 0;
510
511 if (req->cmd_flags & REQ_FUA)
512 control |= NVME_RW_FUA;
513 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
514 control |= NVME_RW_LR;
515
516 if (req->cmd_flags & REQ_RAHEAD)
517 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
518
519 memset(cmnd, 0, sizeof(*cmnd));
520 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
ed754e5d 521 cmnd->rw.nsid = cpu_to_le32(ns->head->ns_id);
8093f7ca
ML		 522 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
523 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
524
f5d11840
JA		 525 if (req_op(req) == REQ_OP_WRITE && ctrl->nr_streams)
526 nvme_assign_write_stream(ctrl, req, &control, &dsmgmt);
527
8093f7ca 528 if (ns->ms) {
715ea9e0
CH		 529 /*
530 * If formated with metadata, the block layer always provides a
531 * metadata buffer if CONFIG_BLK_DEV_INTEGRITY is enabled. Else
532 * we enable the PRACT bit for protection information or set the
533 * namespace capacity to zero to prevent any I/O.
534 */
535 if (!blk_integrity_rq(req)) {
536 if (WARN_ON_ONCE(!nvme_ns_has_pi(ns)))
537 return BLK_STS_NOTSUPP;
538 control |= NVME_RW_PRINFO_PRACT;
539 }
540
8093f7ca
ML		 541 switch (ns->pi_type) {
542 case NVME_NS_DPS_PI_TYPE3:
543 control |= NVME_RW_PRINFO_PRCHK_GUARD;
544 break;
545 case NVME_NS_DPS_PI_TYPE1:
546 case NVME_NS_DPS_PI_TYPE2:
547 control |= NVME_RW_PRINFO_PRCHK_GUARD |
548 NVME_RW_PRINFO_PRCHK_REF;
549 cmnd->rw.reftag = cpu_to_le32(
550 nvme_block_nr(ns, blk_rq_pos(req)));
551 break;
552 }
8093f7ca
ML		 553 }
554
555 cmnd->rw.control = cpu_to_le16(control);
556 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
ebe6d874 557 return 0;
8093f7ca
ML		 558}
559
fc17b653 560blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 561 struct nvme_command *cmd)
562{
fc17b653 563 blk_status_t ret = BLK_STS_OK;
8093f7ca 564
987f699a 565 if (!(req->rq_flags & RQF_DONTPREP)) {
44e44b29 566 nvme_req(req)->retries = 0;
27fa9bc5 567 nvme_req(req)->flags = 0;
987f699a
CH		 568 req->rq_flags |= RQF_DONTPREP;
569 }
570
aebf526b
CH		 571 switch (req_op(req)) {
572 case REQ_OP_DRV_IN:
573 case REQ_OP_DRV_OUT:
d49187e9 574 memcpy(cmd, nvme_req(req)->cmd, sizeof(*cmd));
aebf526b
CH		 575 break;
576 case REQ_OP_FLUSH:
8093f7ca 577 nvme_setup_flush(ns, cmd);
aebf526b 578 break;
e850fd16
CH		 579 case REQ_OP_WRITE_ZEROES:
580 /* currently only aliased to deallocate for a few ctrls: */
aebf526b 581 case REQ_OP_DISCARD:
8093f7ca 582 ret = nvme_setup_discard(ns, req, cmd);
aebf526b
CH		 583 break;
584 case REQ_OP_READ:
585 case REQ_OP_WRITE:
ebe6d874 586 ret = nvme_setup_rw(ns, req, cmd);
aebf526b
CH		 587 break;
588 default:
589 WARN_ON_ONCE(1);
fc17b653 590 return BLK_STS_IOERR;
aebf526b 591 }
8093f7ca 592
721b3917 593 cmd->common.command_id = req->tag;
8093f7ca
ML		 594 return ret;
595}
596EXPORT_SYMBOL_GPL(nvme_setup_cmd);
597
4160982e
CH		 598/*
599 * Returns 0 on success. If the result is negative, it's a Linux error code;
600 * if the result is positive, it's an NVM Express status code
601 */
602int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 603 union nvme_result *result, void *buffer, unsigned bufflen,
9a95e4ef
BVA		 604 unsigned timeout, int qid, int at_head,
605 blk_mq_req_flags_t flags)
4160982e
CH		 606{
607 struct request *req;
608 int ret;
609
eb71f435 610 req = nvme_alloc_request(q, cmd, flags, qid);
4160982e
CH		 611 if (IS_ERR(req))
612 return PTR_ERR(req);
613
614 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
615
21d34711
CH		 616 if (buffer && bufflen) {
617 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
618 if (ret)
619 goto out;
4160982e
CH		 620 }
621
eb71f435 622 blk_execute_rq(req->q, NULL, req, at_head);
d49187e9
CH		 623 if (result)
624 *result = nvme_req(req)->result;
27fa9bc5
CH		 625 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
626 ret = -EINTR;
627 else
628 ret = nvme_req(req)->status;
4160982e
CH		 629 out:
630 blk_mq_free_request(req);
631 return ret;
632}
eb71f435 633EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH		 634
635int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
636 void *buffer, unsigned bufflen)
637{
eb71f435
CH		 638 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 0,
639 NVME_QID_ANY, 0, 0);
4160982e 640}
576d55d6 641EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 642
1cad6562
CH		 643static void *nvme_add_user_metadata(struct bio *bio, void __user *ubuf,
644 unsigned len, u32 seed, bool write)
645{
646 struct bio_integrity_payload *bip;
647 int ret = -ENOMEM;
648 void *buf;
649
650 buf = kmalloc(len, GFP_KERNEL);
651 if (!buf)
652 goto out;
653
654 ret = -EFAULT;
655 if (write && copy_from_user(buf, ubuf, len))
656 goto out_free_meta;
657
658 bip = bio_integrity_alloc(bio, GFP_KERNEL, 1);
659 if (IS_ERR(bip)) {
660 ret = PTR_ERR(bip);
661 goto out_free_meta;
662 }
663
664 bip->bip_iter.bi_size = len;
665 bip->bip_iter.bi_sector = seed;
666 ret = bio_integrity_add_page(bio, virt_to_page(buf), len,
667 offset_in_page(buf));
668 if (ret == len)
669 return buf;
670 ret = -ENOMEM;
671out_free_meta:
672 kfree(buf);
673out:
674 return ERR_PTR(ret);
675}
676
63263d60 677static int nvme_submit_user_cmd(struct request_queue *q,
485783ca
KB		 678 struct nvme_command *cmd, void __user *ubuffer,
679 unsigned bufflen, void __user *meta_buffer, unsigned meta_len,
680 u32 meta_seed, u32 *result, unsigned timeout)
4160982e 681{
7a5abb4b 682 bool write = nvme_is_write(cmd);
0b7f1f26
KB		 683 struct nvme_ns *ns = q->queuedata;
684 struct gendisk *disk = ns ? ns->disk : NULL;
4160982e 685 struct request *req;
0b7f1f26
KB		 686 struct bio *bio = NULL;
687 void *meta = NULL;
4160982e
CH		 688 int ret;
689
eb71f435 690 req = nvme_alloc_request(q, cmd, 0, NVME_QID_ANY);
4160982e
CH		 691 if (IS_ERR(req))
692 return PTR_ERR(req);
693
694 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
695
696 if (ubuffer && bufflen) {
21d34711
CH		 697 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
698 GFP_KERNEL);
699 if (ret)
700 goto out;
701 bio = req->bio;
74d46992 702 bio->bi_disk = disk;
1cad6562
CH		 703 if (disk && meta_buffer && meta_len) {
704 meta = nvme_add_user_metadata(bio, meta_buffer, meta_len,
705 meta_seed, write);
706 if (IS_ERR(meta)) {
707 ret = PTR_ERR(meta);
0b7f1f26
KB		 708 goto out_unmap;
709 }
0b7f1f26
KB		 710 }
711 }
1cad6562 712
0b7f1f26 713 blk_execute_rq(req->q, disk, req, 0);
27fa9bc5
CH		 714 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
715 ret = -EINTR;
716 else
717 ret = nvme_req(req)->status;
21d34711 718 if (result)
d49187e9 719 *result = le32_to_cpu(nvme_req(req)->result.u32);
0b7f1f26
KB		 720 if (meta && !ret && !write) {
721 if (copy_to_user(meta_buffer, meta, meta_len))
722 ret = -EFAULT;
723 }
0b7f1f26
KB		 724 kfree(meta);
725 out_unmap:
74d46992 726 if (bio)
0b7f1f26 727 blk_rq_unmap_user(bio);
21d34711
CH		 728 out:
729 blk_mq_free_request(req);
730 return ret;
731}
732
2a842aca 733static void nvme_keep_alive_end_io(struct request *rq, blk_status_t status)
038bd4cb
SG		 734{
735 struct nvme_ctrl *ctrl = rq->end_io_data;
736
737 blk_mq_free_request(rq);
738
2a842aca 739 if (status) {
038bd4cb 740 dev_err(ctrl->device,
2a842aca
CH		 741 "failed nvme_keep_alive_end_io error=%d\n",
742 status);
038bd4cb
SG		 743 return;
744 }
745
746 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
747}
748
749static int nvme_keep_alive(struct nvme_ctrl *ctrl)
750{
751 struct nvme_command c;
752 struct request *rq;
753
754 memset(&c, 0, sizeof(c));
755 c.common.opcode = nvme_admin_keep_alive;
756
757 rq = nvme_alloc_request(ctrl->admin_q, &c, BLK_MQ_REQ_RESERVED,
758 NVME_QID_ANY);
759 if (IS_ERR(rq))
760 return PTR_ERR(rq);
761
762 rq->timeout = ctrl->kato * HZ;
763 rq->end_io_data = ctrl;
764
765 blk_execute_rq_nowait(rq->q, NULL, rq, 0, nvme_keep_alive_end_io);
766
767 return 0;
768}
769
770static void nvme_keep_alive_work(struct work_struct *work)
771{
772 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
773 struct nvme_ctrl, ka_work);
774
775 if (nvme_keep_alive(ctrl)) {
776 /* allocation failure, reset the controller */
777 dev_err(ctrl->device, "keep-alive failed\n");
39bdc590 778 nvme_reset_ctrl(ctrl);
038bd4cb
SG		 779 return;
780 }
781}
782
783void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
784{
785 if (unlikely(ctrl->kato == 0))
786 return;
787
788 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
789 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
790}
791EXPORT_SYMBOL_GPL(nvme_start_keep_alive);
792
793void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
794{
795 if (unlikely(ctrl->kato == 0))
796 return;
797
798 cancel_delayed_work_sync(&ctrl->ka_work);
799}
800EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
801
3f7f25a9 802static int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH		 803{
804 struct nvme_command c = { };
805 int error;
806
807 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
808 c.identify.opcode = nvme_admin_identify;
986994a2 809 c.identify.cns = NVME_ID_CNS_CTRL;
21d34711
CH		 810
811 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
812 if (!*id)
813 return -ENOMEM;
814
815 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
816 sizeof(struct nvme_id_ctrl));
817 if (error)
818 kfree(*id);
819 return error;
820}
821
cdbff4f2 822static int nvme_identify_ns_descs(struct nvme_ctrl *ctrl, unsigned nsid,
002fab04 823 struct nvme_ns_ids *ids)
3b22ba26
JT		 824{
825 struct nvme_command c = { };
826 int status;
827 void *data;
828 int pos;
829 int len;
830
831 c.identify.opcode = nvme_admin_identify;
832 c.identify.nsid = cpu_to_le32(nsid);
833 c.identify.cns = NVME_ID_CNS_NS_DESC_LIST;
834
835 data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
836 if (!data)
837 return -ENOMEM;
838
cdbff4f2 839 status = nvme_submit_sync_cmd(ctrl->admin_q, &c, data,
3b22ba26
JT		 840 NVME_IDENTIFY_DATA_SIZE);
841 if (status)
842 goto free_data;
843
844 for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) {
845 struct nvme_ns_id_desc *cur = data + pos;
846
847 if (cur->nidl == 0)
848 break;
849
850 switch (cur->nidt) {
851 case NVME_NIDT_EUI64:
852 if (cur->nidl != NVME_NIDT_EUI64_LEN) {
cdbff4f2 853 dev_warn(ctrl->device,
3b22ba26
JT		 854 "ctrl returned bogus length: %d for NVME_NIDT_EUI64\n",
855 cur->nidl);
856 goto free_data;
857 }
858 len = NVME_NIDT_EUI64_LEN;
002fab04 859 memcpy(ids->eui64, data + pos + sizeof(*cur), len);
3b22ba26
JT		 860 break;
861 case NVME_NIDT_NGUID:
862 if (cur->nidl != NVME_NIDT_NGUID_LEN) {
cdbff4f2 863 dev_warn(ctrl->device,
3b22ba26
JT		 864 "ctrl returned bogus length: %d for NVME_NIDT_NGUID\n",
865 cur->nidl);
866 goto free_data;
867 }
868 len = NVME_NIDT_NGUID_LEN;
002fab04 869 memcpy(ids->nguid, data + pos + sizeof(*cur), len);
3b22ba26
JT		 870 break;
871 case NVME_NIDT_UUID:
872 if (cur->nidl != NVME_NIDT_UUID_LEN) {
cdbff4f2 873 dev_warn(ctrl->device,
3b22ba26
JT		 874 "ctrl returned bogus length: %d for NVME_NIDT_UUID\n",
875 cur->nidl);
876 goto free_data;
877 }
878 len = NVME_NIDT_UUID_LEN;
002fab04 879 uuid_copy(&ids->uuid, data + pos + sizeof(*cur));
3b22ba26
JT		 880 break;
881 default:
882 /* Skip unnkown types */
883 len = cur->nidl;
884 break;
885 }
886
887 len += sizeof(*cur);
888 }
889free_data:
890 kfree(data);
891 return status;
892}
893
540c801c
KB		 894static int nvme_identify_ns_list(struct nvme_ctrl *dev, unsigned nsid, __le32 *ns_list)
895{
896 struct nvme_command c = { };
897
898 c.identify.opcode = nvme_admin_identify;
986994a2 899 c.identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST;
540c801c
KB		 900 c.identify.nsid = cpu_to_le32(nsid);
901 return nvme_submit_sync_cmd(dev->admin_q, &c, ns_list, 0x1000);
902}
903
cdbff4f2
CH		 904static struct nvme_id_ns *nvme_identify_ns(struct nvme_ctrl *ctrl,
905 unsigned nsid)
21d34711 906{
cdbff4f2 907 struct nvme_id_ns *id;
21d34711
CH		 908 struct nvme_command c = { };
909 int error;
910
911 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
778f067c
MG		 912 c.identify.opcode = nvme_admin_identify;
913 c.identify.nsid = cpu_to_le32(nsid);
986994a2 914 c.identify.cns = NVME_ID_CNS_NS;
21d34711 915
cdbff4f2
CH		 916 id = kmalloc(sizeof(*id), GFP_KERNEL);
917 if (!id)
918 return NULL;
21d34711 919
cdbff4f2
CH		 920 error = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id));
921 if (error) {
922 dev_warn(ctrl->device, "Identify namespace failed\n");
923 kfree(id);
924 return NULL;
925 }
926
927 return id;
21d34711
CH		 928}
929
3f7f25a9 930static int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
1a6fe74d 931 void *buffer, size_t buflen, u32 *result)
21d34711
CH		 932{
933 struct nvme_command c;
d49187e9 934 union nvme_result res;
1cb3cce5 935 int ret;
21d34711
CH		 936
937 memset(&c, 0, sizeof(c));
938 c.features.opcode = nvme_admin_set_features;
21d34711
CH		 939 c.features.fid = cpu_to_le32(fid);
940 c.features.dword11 = cpu_to_le32(dword11);
941
d49187e9 942 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
1a6fe74d 943 buffer, buflen, 0, NVME_QID_ANY, 0, 0);
9b47f77a 944 if (ret >= 0 && result)
d49187e9 945 *result = le32_to_cpu(res.u32);
1cb3cce5 946 return ret;
21d34711
CH		 947}
948
9a0be7ab
CH		 949int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
950{
951 u32 q_count = (*count - 1) | ((*count - 1) << 16);
952 u32 result;
953 int status, nr_io_queues;
954
1a6fe74d 955 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 956 &result);
f5fa90dc 957 if (status < 0)
9a0be7ab
CH		 958 return status;
959
f5fa90dc
CH		 960 /*
961 * Degraded controllers might return an error when setting the queue
962 * count. We still want to be able to bring them online and offer
963 * access to the admin queue, as that might be only way to fix them up.
964 */
965 if (status > 0) {
f0425db0 966 dev_err(ctrl->device, "Could not set queue count (%d)\n", status);
f5fa90dc
CH		 967 *count = 0;
968 } else {
969 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
970 *count = min(*count, nr_io_queues);
971 }
972
9a0be7ab
CH		 973 return 0;
974}
576d55d6 975EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 976
1673f1f0
CH		 977static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
978{
979 struct nvme_user_io io;
980 struct nvme_command c;
981 unsigned length, meta_len;
982 void __user *metadata;
983
984 if (copy_from_user(&io, uio, sizeof(io)))
985 return -EFAULT;
63088ec7
KB		 986 if (io.flags)
987 return -EINVAL;
1673f1f0
CH		 988
989 switch (io.opcode) {
990 case nvme_cmd_write:
991 case nvme_cmd_read:
992 case nvme_cmd_compare:
993 break;
994 default:
995 return -EINVAL;
996 }
997
998 length = (io.nblocks + 1) << ns->lba_shift;
999 meta_len = (io.nblocks + 1) * ns->ms;
1000 metadata = (void __user *)(uintptr_t)io.metadata;
1001
1002 if (ns->ext) {
1003 length += meta_len;
1004 meta_len = 0;
1005 } else if (meta_len) {
1006 if ((io.metadata & 3) || !io.metadata)
1007 return -EINVAL;
1008 }
1009
1010 memset(&c, 0, sizeof(c));
1011 c.rw.opcode = io.opcode;
1012 c.rw.flags = io.flags;
ed754e5d 1013 c.rw.nsid = cpu_to_le32(ns->head->ns_id);
1673f1f0
CH		 1014 c.rw.slba = cpu_to_le64(io.slba);
1015 c.rw.length = cpu_to_le16(io.nblocks);
1016 c.rw.control = cpu_to_le16(io.control);
1017 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1018 c.rw.reftag = cpu_to_le32(io.reftag);
1019 c.rw.apptag = cpu_to_le16(io.apptag);
1020 c.rw.appmask = cpu_to_le16(io.appmask);
1021
63263d60 1022 return nvme_submit_user_cmd(ns->queue, &c,
1673f1f0
CH		 1023 (void __user *)(uintptr_t)io.addr, length,
1024 metadata, meta_len, io.slba, NULL, 0);
1025}
1026
84fef62d
KB		 1027static u32 nvme_known_admin_effects(u8 opcode)
1028{
1029 switch (opcode) {
1030 case nvme_admin_format_nvm:
1031 return NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC |
1032 NVME_CMD_EFFECTS_CSE_MASK;
1033 case nvme_admin_sanitize_nvm:
1034 return NVME_CMD_EFFECTS_CSE_MASK;
1035 default:
1036 break;
1037 }
1038 return 0;
1039}
1040
1041static u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1042 u8 opcode)
1043{
1044 u32 effects = 0;
1045
1046 if (ns) {
1047 if (ctrl->effects)
1048 effects = le32_to_cpu(ctrl->effects->iocs[opcode]);
1049 if (effects & ~NVME_CMD_EFFECTS_CSUPP)
1050 dev_warn(ctrl->device,
1051 "IO command:%02x has unhandled effects:%08x\n",
1052 opcode, effects);
1053 return 0;
1054 }
1055
1056 if (ctrl->effects)
1057 effects = le32_to_cpu(ctrl->effects->iocs[opcode]);
1058 else
1059 effects = nvme_known_admin_effects(opcode);
1060
1061 /*
1062 * For simplicity, IO to all namespaces is quiesced even if the command
1063 * effects say only one namespace is affected.
1064 */
1065 if (effects & (NVME_CMD_EFFECTS_LBCC | NVME_CMD_EFFECTS_CSE_MASK)) {
1066 nvme_start_freeze(ctrl);
1067 nvme_wait_freeze(ctrl);
1068 }
1069 return effects;
1070}
1071
1072static void nvme_update_formats(struct nvme_ctrl *ctrl)
1073{
1074 struct nvme_ns *ns;
1075
1076 mutex_lock(&ctrl->namespaces_mutex);
1077 list_for_each_entry(ns, &ctrl->namespaces, list) {
1078 if (ns->disk && nvme_revalidate_disk(ns->disk))
1079 nvme_ns_remove(ns);
1080 }
1081 mutex_unlock(&ctrl->namespaces_mutex);
1082}
1083
1084static void nvme_passthru_end(struct nvme_ctrl *ctrl, u32 effects)
1085{
1086 /*
1087 * Revalidate LBA changes prior to unfreezing. This is necessary to
1088 * prevent memory corruption if a logical block size was changed by
1089 * this command.
1090 */
1091 if (effects & NVME_CMD_EFFECTS_LBCC)
1092 nvme_update_formats(ctrl);
1093 if (effects & (NVME_CMD_EFFECTS_LBCC | NVME_CMD_EFFECTS_CSE_MASK))
1094 nvme_unfreeze(ctrl);
1095 if (effects & NVME_CMD_EFFECTS_CCC)
1096 nvme_init_identify(ctrl);
1097 if (effects & (NVME_CMD_EFFECTS_NIC | NVME_CMD_EFFECTS_NCC))
1098 nvme_queue_scan(ctrl);
1099}
1100
f3ca80fc 1101static int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1673f1f0
CH		 1102 struct nvme_passthru_cmd __user *ucmd)
1103{
1104 struct nvme_passthru_cmd cmd;
1105 struct nvme_command c;
1106 unsigned timeout = 0;
84fef62d 1107 u32 effects;
1673f1f0
CH		 1108 int status;
1109
1110 if (!capable(CAP_SYS_ADMIN))
1111 return -EACCES;
1112 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1113 return -EFAULT;
63088ec7
KB		 1114 if (cmd.flags)
1115 return -EINVAL;
1673f1f0
CH		 1116
1117 memset(&c, 0, sizeof(c));
1118 c.common.opcode = cmd.opcode;
1119 c.common.flags = cmd.flags;
1120 c.common.nsid = cpu_to_le32(cmd.nsid);
1121 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1122 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1123 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1124 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1125 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1126 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1127 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1128 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1129
1130 if (cmd.timeout_ms)
1131 timeout = msecs_to_jiffies(cmd.timeout_ms);
1132
84fef62d 1133 effects = nvme_passthru_start(ctrl, ns, cmd.opcode);
1673f1f0 1134 status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c,
d1ea7be5 1135 (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
63263d60
KB		 1136 (void __user *)(uintptr_t)cmd.metadata, cmd.metadata,
1137 0, &cmd.result, timeout);
84fef62d
KB		 1138 nvme_passthru_end(ctrl, effects);
1139
1673f1f0
CH		 1140 if (status >= 0) {
1141 if (put_user(cmd.result, &ucmd->result))
1142 return -EFAULT;
1143 }
1144
1145 return status;
1146}
1147
32acab31
CH		 1148/*
1149 * Issue ioctl requests on the first available path. Note that unlike normal
1150 * block layer requests we will not retry failed request on another controller.
1151 */
1152static struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk,
1153 struct nvme_ns_head **head, int *srcu_idx)
1673f1f0 1154{
32acab31
CH		 1155#ifdef CONFIG_NVME_MULTIPATH
1156 if (disk->fops == &nvme_ns_head_ops) {
1157 *head = disk->private_data;
1158 *srcu_idx = srcu_read_lock(&(*head)->srcu);
1159 return nvme_find_path(*head);
1160 }
1161#endif
1162 *head = NULL;
1163 *srcu_idx = -1;
1164 return disk->private_data;
1165}
1673f1f0 1166
32acab31
CH		 1167static void nvme_put_ns_from_disk(struct nvme_ns_head *head, int idx)
1168{
1169 if (head)
1170 srcu_read_unlock(&head->srcu, idx);
1171}
1673f1f0 1172
32acab31
CH		 1173static int nvme_ns_ioctl(struct nvme_ns *ns, unsigned cmd, unsigned long arg)
1174{
1673f1f0
CH		 1175 switch (cmd) {
1176 case NVME_IOCTL_ID:
1177 force_successful_syscall_return();
ed754e5d 1178 return ns->head->ns_id;
1673f1f0
CH		 1179 case NVME_IOCTL_ADMIN_CMD:
1180 return nvme_user_cmd(ns->ctrl, NULL, (void __user *)arg);
1181 case NVME_IOCTL_IO_CMD:
1182 return nvme_user_cmd(ns->ctrl, ns, (void __user *)arg);
1183 case NVME_IOCTL_SUBMIT_IO:
1184 return nvme_submit_io(ns, (void __user *)arg);
1673f1f0 1185 default:
84d4add7
MB		 1186#ifdef CONFIG_NVM
1187 if (ns->ndev)
1188 return nvme_nvm_ioctl(ns, cmd, arg);
1189#endif
a98e58e5 1190 if (is_sed_ioctl(cmd))
4f1244c8 1191 return sed_ioctl(ns->ctrl->opal_dev, cmd,
e225c20e 1192 (void __user *) arg);
1673f1f0
CH		 1193 return -ENOTTY;
1194 }
1195}
1196
32acab31
CH		 1197static int nvme_ioctl(struct block_device *bdev, fmode_t mode,
1198 unsigned int cmd, unsigned long arg)
1673f1f0 1199{
32acab31
CH		 1200 struct nvme_ns_head *head = NULL;
1201 struct nvme_ns *ns;
1202 int srcu_idx, ret;
1203
1204 ns = nvme_get_ns_from_disk(bdev->bd_disk, &head, &srcu_idx);
1205 if (unlikely(!ns))
1206 ret = -EWOULDBLOCK;
1207 else
1208 ret = nvme_ns_ioctl(ns, cmd, arg);
1209 nvme_put_ns_from_disk(head, srcu_idx);
1210 return ret;
1673f1f0 1211}
1673f1f0
CH		 1212
1213static int nvme_open(struct block_device *bdev, fmode_t mode)
1214{
c6424a90
CH		 1215 struct nvme_ns *ns = bdev->bd_disk->private_data;
1216
32acab31
CH		 1217#ifdef CONFIG_NVME_MULTIPATH
1218 /* should never be called due to GENHD_FL_HIDDEN */
1219 if (WARN_ON_ONCE(ns->head->disk))
1220 return -ENXIO;
1221#endif
c6424a90
CH		 1222 if (!kref_get_unless_zero(&ns->kref))
1223 return -ENXIO;
c6424a90 1224 return 0;
1673f1f0
CH		 1225}
1226
1227static void nvme_release(struct gendisk *disk, fmode_t mode)
1228{
a6a5149b 1229 nvme_put_ns(disk->private_data);
1673f1f0
CH		 1230}
1231
1232static int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1233{
1234 /* some standard values */
1235 geo->heads = 1 << 6;
1236 geo->sectors = 1 << 5;
1237 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
1238 return 0;
1239}
1240
1241#ifdef CONFIG_BLK_DEV_INTEGRITY
39b7baa4 1242static void nvme_init_integrity(struct gendisk *disk, u16 ms, u8 pi_type)
1673f1f0
CH		 1243{
1244 struct blk_integrity integrity;
1245
fa9a89fc 1246 memset(&integrity, 0, sizeof(integrity));
39b7baa4 1247 switch (pi_type) {
1673f1f0
CH		 1248 case NVME_NS_DPS_PI_TYPE3:
1249 integrity.profile = &t10_pi_type3_crc;
ba36c21b
NB		 1250 integrity.tag_size = sizeof(u16) + sizeof(u32);
1251 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1252 break;
1253 case NVME_NS_DPS_PI_TYPE1:
1254 case NVME_NS_DPS_PI_TYPE2:
1255 integrity.profile = &t10_pi_type1_crc;
ba36c21b
NB		 1256 integrity.tag_size = sizeof(u16);
1257 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1258 break;
1259 default:
1260 integrity.profile = NULL;
1261 break;
1262 }
39b7baa4
CH		 1263 integrity.tuple_size = ms;
1264 blk_integrity_register(disk, &integrity);
1265 blk_queue_max_integrity_segments(disk->queue, 1);
1673f1f0
CH		 1266}
1267#else
39b7baa4 1268static void nvme_init_integrity(struct gendisk *disk, u16 ms, u8 pi_type)
1673f1f0
CH		 1269{
1270}
1271#endif /* CONFIG_BLK_DEV_INTEGRITY */
1272
6b8190d6
SB		 1273static void nvme_set_chunk_size(struct nvme_ns *ns)
1274{
1275 u32 chunk_size = (((u32)ns->noiob) << (ns->lba_shift - 9));
1276 blk_queue_chunk_sectors(ns->queue, rounddown_pow_of_two(chunk_size));
1277}
1278
30e5e929
CH		 1279static void nvme_config_discard(struct nvme_ctrl *ctrl,
1280 unsigned stream_alignment, struct request_queue *queue)
1673f1f0 1281{
30e5e929
CH		 1282 u32 size = queue_logical_block_size(queue);
1283
1284 if (stream_alignment)
1285 size *= stream_alignment;
08095e70 1286
b35ba01e
CH		 1287 BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) <
1288 NVME_DSM_MAX_RANGES);
1289
b224f613 1290 queue->limits.discard_alignment = 0;
30e5e929 1291 queue->limits.discard_granularity = size;
f5d11840 1292
30e5e929
CH		 1293 blk_queue_max_discard_sectors(queue, UINT_MAX);
1294 blk_queue_max_discard_segments(queue, NVME_DSM_MAX_RANGES);
1295 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, queue);
e850fd16
CH		 1296
1297 if (ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
30e5e929 1298 blk_queue_max_write_zeroes_sectors(queue, UINT_MAX);
1673f1f0
CH		 1299}
1300
cdbff4f2 1301static void nvme_report_ns_ids(struct nvme_ctrl *ctrl, unsigned int nsid,
002fab04 1302 struct nvme_id_ns *id, struct nvme_ns_ids *ids)
1673f1f0 1303{
002fab04
CH		 1304 memset(ids, 0, sizeof(*ids));
1305
cdbff4f2 1306 if (ctrl->vs >= NVME_VS(1, 1, 0))
002fab04 1307 memcpy(ids->eui64, id->eui64, sizeof(id->eui64));
cdbff4f2 1308 if (ctrl->vs >= NVME_VS(1, 2, 0))
002fab04 1309 memcpy(ids->nguid, id->nguid, sizeof(id->nguid));
cdbff4f2 1310 if (ctrl->vs >= NVME_VS(1, 3, 0)) {
3b22ba26
JT		 1311 /* Don't treat error as fatal we potentially
1312 * already have a NGUID or EUI-64
1313 */
002fab04 1314 if (nvme_identify_ns_descs(ctrl, nsid, ids))
cdbff4f2 1315 dev_warn(ctrl->device,
3b22ba26
JT		 1316 "%s: Identify Descriptors failed\n", __func__);
1317 }
ac81bfa9
MB		 1318}
1319
ed754e5d
CH		 1320static bool nvme_ns_ids_valid(struct nvme_ns_ids *ids)
1321{
1322 return !uuid_is_null(&ids->uuid) ||
1323 memchr_inv(ids->nguid, 0, sizeof(ids->nguid)) ||
1324 memchr_inv(ids->eui64, 0, sizeof(ids->eui64));
1325}
1326
002fab04
CH		 1327static bool nvme_ns_ids_equal(struct nvme_ns_ids *a, struct nvme_ns_ids *b)
1328{
1329 return uuid_equal(&a->uuid, &b->uuid) &&
1330 memcmp(&a->nguid, &b->nguid, sizeof(a->nguid)) == 0 &&
1331 memcmp(&a->eui64, &b->eui64, sizeof(a->eui64)) == 0;
1332}
1333
24b0b58c
CH		 1334static void nvme_update_disk_info(struct gendisk *disk,
1335 struct nvme_ns *ns, struct nvme_id_ns *id)
1336{
1337 sector_t capacity = le64_to_cpup(&id->nsze) << (ns->lba_shift - 9);
cee160fd 1338 unsigned short bs = 1 << ns->lba_shift;
24b0b58c
CH		 1339 unsigned stream_alignment = 0;
1340
1341 if (ns->ctrl->nr_streams && ns->sws && ns->sgs)
1342 stream_alignment = ns->sws * ns->sgs;
1343
1344 blk_mq_freeze_queue(disk->queue);
1345 blk_integrity_unregister(disk);
1346
cee160fd
JL		 1347 blk_queue_logical_block_size(disk->queue, bs);
1348 blk_queue_physical_block_size(disk->queue, bs);
1349 blk_queue_io_min(disk->queue, bs);
1350
24b0b58c
CH		 1351 if (ns->ms && !ns->ext &&
1352 (ns->ctrl->ops->flags & NVME_F_METADATA_SUPPORTED))
1353 nvme_init_integrity(disk, ns->ms, ns->pi_type);
715ea9e0 1354 if (ns->ms && !nvme_ns_has_pi(ns) && !blk_get_integrity(disk))
24b0b58c
CH		 1355 capacity = 0;
1356 set_capacity(disk, capacity);
1357
1358 if (ns->ctrl->oncs & NVME_CTRL_ONCS_DSM)
1359 nvme_config_discard(ns->ctrl, stream_alignment, disk->queue);
1360 blk_mq_unfreeze_queue(disk->queue);
1361}
1362
ac81bfa9
MB		 1363static void __nvme_revalidate_disk(struct gendisk *disk, struct nvme_id_ns *id)
1364{
1365 struct nvme_ns *ns = disk->private_data;
1673f1f0
CH		 1366
1367 /*
1368 * If identify namespace failed, use default 512 byte block size so
1369 * block layer can use before failing read/write for 0 capacity.
1370 */
c81bfba9 1371 ns->lba_shift = id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ds;
1673f1f0
CH		 1372 if (ns->lba_shift == 0)
1373 ns->lba_shift = 9;
6b8190d6 1374 ns->noiob = le16_to_cpu(id->noiob);
b5be3b39
CH		 1375 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
1376 ns->ms = le16_to_cpu(id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ms);
1377 /* the PI implementation requires metadata equal t10 pi tuple size */
1378 if (ns->ms == sizeof(struct t10_pi_tuple))
1379 ns->pi_type = id->dps & NVME_NS_DPS_PI_MASK;
1380 else
1381 ns->pi_type = 0;
1673f1f0 1382
6b8190d6
SB		 1383 if (ns->noiob)
1384 nvme_set_chunk_size(ns);
24b0b58c 1385 nvme_update_disk_info(disk, ns, id);
32acab31
CH		 1386#ifdef CONFIG_NVME_MULTIPATH
1387 if (ns->head->disk)
1388 nvme_update_disk_info(ns->head->disk, ns, id);
1389#endif
ac81bfa9 1390}
1673f1f0 1391
ac81bfa9
MB		 1392static int nvme_revalidate_disk(struct gendisk *disk)
1393{
1394 struct nvme_ns *ns = disk->private_data;
cdbff4f2
CH		 1395 struct nvme_ctrl *ctrl = ns->ctrl;
1396 struct nvme_id_ns *id;
002fab04 1397 struct nvme_ns_ids ids;
cdbff4f2 1398 int ret = 0;
ac81bfa9
MB		 1399
1400 if (test_bit(NVME_NS_DEAD, &ns->flags)) {
1401 set_capacity(disk, 0);
1402 return -ENODEV;
1403 }
1404
ed754e5d 1405 id = nvme_identify_ns(ctrl, ns->head->ns_id);
cdbff4f2
CH		 1406 if (!id)
1407 return -ENODEV;
ac81bfa9 1408
cdbff4f2
CH		 1409 if (id->ncap == 0) {
1410 ret = -ENODEV;
1411 goto out;
1412 }
ac81bfa9 1413
5e0fab57 1414 __nvme_revalidate_disk(disk, id);
ed754e5d
CH		 1415 nvme_report_ns_ids(ctrl, ns->head->ns_id, id, &ids);
1416 if (!nvme_ns_ids_equal(&ns->head->ids, &ids)) {
1d5df6af 1417 dev_err(ctrl->device,
ed754e5d 1418 "identifiers changed for nsid %d\n", ns->head->ns_id);
1d5df6af
CH		 1419 ret = -ENODEV;
1420 }
1421
cdbff4f2
CH		 1422out:
1423 kfree(id);
1424 return ret;
1673f1f0
CH		 1425}
1426
1427static char nvme_pr_type(enum pr_type type)
1428{
1429 switch (type) {
1430 case PR_WRITE_EXCLUSIVE:
1431 return 1;
1432 case PR_EXCLUSIVE_ACCESS:
1433 return 2;
1434 case PR_WRITE_EXCLUSIVE_REG_ONLY:
1435 return 3;
1436 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
1437 return 4;
1438 case PR_WRITE_EXCLUSIVE_ALL_REGS:
1439 return 5;
1440 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
1441 return 6;
1442 default:
1443 return 0;
1444 }
1445};
1446
1447static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
1448 u64 key, u64 sa_key, u8 op)
1449{
32acab31
CH		 1450 struct nvme_ns_head *head = NULL;
1451 struct nvme_ns *ns;
1673f1f0 1452 struct nvme_command c;
32acab31 1453 int srcu_idx, ret;
1673f1f0
CH		 1454 u8 data[16] = { 0, };
1455
b0d61d58
KB		 1456 ns = nvme_get_ns_from_disk(bdev->bd_disk, &head, &srcu_idx);
1457 if (unlikely(!ns))
1458 return -EWOULDBLOCK;
1459
1673f1f0
CH		 1460 put_unaligned_le64(key, &data[0]);
1461 put_unaligned_le64(sa_key, &data[8]);
1462
1463 memset(&c, 0, sizeof(c));
1464 c.common.opcode = op;
b0d61d58 1465 c.common.nsid = cpu_to_le32(ns->head->ns_id);
1673f1f0
CH		 1466 c.common.cdw10[0] = cpu_to_le32(cdw10);
1467
b0d61d58 1468 ret = nvme_submit_sync_cmd(ns->queue, &c, data, 16);
32acab31
CH		 1469 nvme_put_ns_from_disk(head, srcu_idx);
1470 return ret;
1673f1f0
CH		 1471}
1472
1473static int nvme_pr_register(struct block_device *bdev, u64 old,
1474 u64 new, unsigned flags)
1475{
1476 u32 cdw10;
1477
1478 if (flags & ~PR_FL_IGNORE_KEY)
1479 return -EOPNOTSUPP;
1480
1481 cdw10 = old ? 2 : 0;
1482 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
1483 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
1484 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
1485}
1486
1487static int nvme_pr_reserve(struct block_device *bdev, u64 key,
1488 enum pr_type type, unsigned flags)
1489{
1490 u32 cdw10;
1491
1492 if (flags & ~PR_FL_IGNORE_KEY)
1493 return -EOPNOTSUPP;
1494
1495 cdw10 = nvme_pr_type(type) << 8;
1496 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
1497 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
1498}
1499
1500static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
1501 enum pr_type type, bool abort)
1502{
1503 u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
1504 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
1505}
1506
1507static int nvme_pr_clear(struct block_device *bdev, u64 key)
1508{
8c0b3915 1509 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
1673f1f0
CH		 1510 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
1511}
1512
1513static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
1514{
1515 u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
1516 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
1517}
1518
1519static const struct pr_ops nvme_pr_ops = {
1520 .pr_register = nvme_pr_register,
1521 .pr_reserve = nvme_pr_reserve,
1522 .pr_release = nvme_pr_release,
1523 .pr_preempt = nvme_pr_preempt,
1524 .pr_clear = nvme_pr_clear,
1525};
1526
a98e58e5 1527#ifdef CONFIG_BLK_SED_OPAL
4f1244c8
CH		 1528int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
1529 bool send)
a98e58e5 1530{
4f1244c8 1531 struct nvme_ctrl *ctrl = data;
a98e58e5 1532 struct nvme_command cmd;
a98e58e5
SB		 1533
1534 memset(&cmd, 0, sizeof(cmd));
1535 if (send)
1536 cmd.common.opcode = nvme_admin_security_send;
1537 else
1538 cmd.common.opcode = nvme_admin_security_recv;
a98e58e5
SB		 1539 cmd.common.nsid = 0;
1540 cmd.common.cdw10[0] = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
1541 cmd.common.cdw10[1] = cpu_to_le32(len);
1542
1543 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len,
1544 ADMIN_TIMEOUT, NVME_QID_ANY, 1, 0);
1545}
1546EXPORT_SYMBOL_GPL(nvme_sec_submit);
1547#endif /* CONFIG_BLK_SED_OPAL */
1548
5bae7f73 1549static const struct block_device_operations nvme_fops = {
1673f1f0
CH		 1550 .owner = THIS_MODULE,
1551 .ioctl = nvme_ioctl,
761f2e1e 1552 .compat_ioctl = nvme_ioctl,
1673f1f0
CH		 1553 .open = nvme_open,
1554 .release = nvme_release,
1555 .getgeo = nvme_getgeo,
1556 .revalidate_disk= nvme_revalidate_disk,
1557 .pr_ops = &nvme_pr_ops,
1558};
1559
32acab31
CH		 1560#ifdef CONFIG_NVME_MULTIPATH
1561static int nvme_ns_head_open(struct block_device *bdev, fmode_t mode)
1562{
1563 struct nvme_ns_head *head = bdev->bd_disk->private_data;
1564
1565 if (!kref_get_unless_zero(&head->ref))
1566 return -ENXIO;
1567 return 0;
1568}
1569
1570static void nvme_ns_head_release(struct gendisk *disk, fmode_t mode)
1571{
1572 nvme_put_ns_head(disk->private_data);
1573}
1574
1575const struct block_device_operations nvme_ns_head_ops = {
1576 .owner = THIS_MODULE,
1577 .open = nvme_ns_head_open,
1578 .release = nvme_ns_head_release,
1579 .ioctl = nvme_ioctl,
1580 .compat_ioctl = nvme_ioctl,
1581 .getgeo = nvme_getgeo,
1582 .pr_ops = &nvme_pr_ops,
1583};
1584#endif /* CONFIG_NVME_MULTIPATH */
1585
5fd4ce1b
CH		 1586static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
1587{
1588 unsigned long timeout =
1589 ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1590 u32 csts, bit = enabled ? NVME_CSTS_RDY : 0;
1591 int ret;
1592
1593 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB		 1594 if (csts == ~0)
1595 return -ENODEV;
5fd4ce1b
CH		 1596 if ((csts & NVME_CSTS_RDY) == bit)
1597 break;
1598
1599 msleep(100);
1600 if (fatal_signal_pending(current))
1601 return -EINTR;
1602 if (time_after(jiffies, timeout)) {
1b3c47c1 1603 dev_err(ctrl->device,
5fd4ce1b
CH		 1604 "Device not ready; aborting %s\n", enabled ?
1605 "initialisation" : "reset");
1606 return -ENODEV;
1607 }
1608 }
1609
1610 return ret;
1611}
1612
1613/*
1614 * If the device has been passed off to us in an enabled state, just clear
1615 * the enabled bit. The spec says we should set the 'shutdown notification
1616 * bits', but doing so may cause the device to complete commands to the
1617 * admin queue ... and we don't know what memory that might be pointing at!
1618 */
1619int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1620{
1621 int ret;
1622
1623 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1624 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
1625
1626 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1627 if (ret)
1628 return ret;
54adc010 1629
b5a10c5f 1630 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010
GP		 1631 msleep(NVME_QUIRK_DELAY_AMOUNT);
1632
5fd4ce1b
CH		 1633 return nvme_wait_ready(ctrl, cap, false);
1634}
576d55d6 1635EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b
CH		 1636
1637int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1638{
1639 /*
1640 * Default to a 4K page size, with the intention to update this
1641 * path in the future to accomodate architectures with differing
1642 * kernel and IO page sizes.
1643 */
1644 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12, page_shift = 12;
1645 int ret;
1646
1647 if (page_shift < dev_page_min) {
1b3c47c1 1648 dev_err(ctrl->device,
5fd4ce1b
CH		 1649 "Minimum device page size %u too large for host (%u)\n",
1650 1 << dev_page_min, 1 << page_shift);
1651 return -ENODEV;
1652 }
1653
1654 ctrl->page_size = 1 << page_shift;
1655
1656 ctrl->ctrl_config = NVME_CC_CSS_NVM;
1657 ctrl->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
60b43f62 1658 ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;
5fd4ce1b
CH		 1659 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1660 ctrl->ctrl_config |= NVME_CC_ENABLE;
1661
1662 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1663 if (ret)
1664 return ret;
1665 return nvme_wait_ready(ctrl, cap, true);
1666}
576d55d6 1667EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b
CH		 1668
1669int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl)
1670{
07fbd32a 1671 unsigned long timeout = jiffies + (ctrl->shutdown_timeout * HZ);
5fd4ce1b
CH		 1672 u32 csts;
1673 int ret;
1674
1675 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1676 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
1677
1678 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1679 if (ret)
1680 return ret;
1681
1682 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
1683 if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_CMPLT)
1684 break;
1685
1686 msleep(100);
1687 if (fatal_signal_pending(current))
1688 return -EINTR;
1689 if (time_after(jiffies, timeout)) {
1b3c47c1 1690 dev_err(ctrl->device,
5fd4ce1b
CH		 1691 "Device shutdown incomplete; abort shutdown\n");
1692 return -ENODEV;
1693 }
1694 }
1695
1696 return ret;
1697}
576d55d6 1698EXPORT_SYMBOL_GPL(nvme_shutdown_ctrl);
5fd4ce1b 1699
da35825d
CH		 1700static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
1701 struct request_queue *q)
1702{
7c88cb00
JA		 1703 bool vwc = false;
1704
da35825d 1705 if (ctrl->max_hw_sectors) {
45686b61
CH		 1706 u32 max_segments =
1707 (ctrl->max_hw_sectors / (ctrl->page_size >> 9)) + 1;
1708
da35825d 1709 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
45686b61 1710 blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
da35825d 1711 }
249159c5
KB		 1712 if ((ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) &&
1713 is_power_of_2(ctrl->max_hw_sectors))
e6282aef 1714 blk_queue_chunk_sectors(q, ctrl->max_hw_sectors);
da35825d 1715 blk_queue_virt_boundary(q, ctrl->page_size - 1);
7c88cb00
JA		 1716 if (ctrl->vwc & NVME_CTRL_VWC_PRESENT)
1717 vwc = true;
1718 blk_queue_write_cache(q, vwc, vwc);
da35825d
CH		 1719}
1720
dbf86b39
JD		 1721static int nvme_configure_timestamp(struct nvme_ctrl *ctrl)
1722{
1723 __le64 ts;
1724 int ret;
1725
1726 if (!(ctrl->oncs & NVME_CTRL_ONCS_TIMESTAMP))
1727 return 0;
1728
1729 ts = cpu_to_le64(ktime_to_ms(ktime_get_real()));
1730 ret = nvme_set_features(ctrl, NVME_FEAT_TIMESTAMP, 0, &ts, sizeof(ts),
1731 NULL);
1732 if (ret)
1733 dev_warn_once(ctrl->device,
1734 "could not set timestamp (%d)\n", ret);
1735 return ret;
1736}
1737
634b8325 1738static int nvme_configure_apst(struct nvme_ctrl *ctrl)
c5552fde
AL		 1739{
1740 /*
1741 * APST (Autonomous Power State Transition) lets us program a
1742 * table of power state transitions that the controller will
1743 * perform automatically. We configure it with a simple
1744 * heuristic: we are willing to spend at most 2% of the time
1745 * transitioning between power states. Therefore, when running
1746 * in any given state, we will enter the next lower-power
76e4ad09 1747 * non-operational state after waiting 50 * (enlat + exlat)
da87591b 1748 * microseconds, as long as that state's exit latency is under
c5552fde
AL		 1749 * the requested maximum latency.
1750 *
1751 * We will not autonomously enter any non-operational state for
1752 * which the total latency exceeds ps_max_latency_us. Users
1753 * can set ps_max_latency_us to zero to turn off APST.
1754 */
1755
1756 unsigned apste;
1757 struct nvme_feat_auto_pst *table;
fb0dc399
AL		 1758 u64 max_lat_us = 0;
1759 int max_ps = -1;
c5552fde
AL		 1760 int ret;
1761
1762 /*
1763 * If APST isn't supported or if we haven't been initialized yet,
1764 * then don't do anything.
1765 */
1766 if (!ctrl->apsta)
634b8325 1767 return 0;
c5552fde
AL		 1768
1769 if (ctrl->npss > 31) {
1770 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
634b8325 1771 return 0;
c5552fde
AL		 1772 }
1773
1774 table = kzalloc(sizeof(*table), GFP_KERNEL);
1775 if (!table)
634b8325 1776 return 0;
c5552fde 1777
76a5af84 1778 if (!ctrl->apst_enabled || ctrl->ps_max_latency_us == 0) {
c5552fde
AL		 1779 /* Turn off APST. */
1780 apste = 0;
fb0dc399 1781 dev_dbg(ctrl->device, "APST disabled\n");
c5552fde
AL		 1782 } else {
1783 __le64 target = cpu_to_le64(0);
1784 int state;
1785
1786 /*
1787 * Walk through all states from lowest- to highest-power.
1788 * According to the spec, lower-numbered states use more
1789 * power. NPSS, despite the name, is the index of the
1790 * lowest-power state, not the number of states.
1791 */
1792 for (state = (int)ctrl->npss; state >= 0; state--) {
da87591b 1793 u64 total_latency_us, exit_latency_us, transition_ms;
c5552fde
AL		 1794
1795 if (target)
1796 table->entries[state] = target;
1797
ff5350a8
AL		 1798 /*
1799 * Don't allow transitions to the deepest state
1800 * if it's quirked off.
1801 */
1802 if (state == ctrl->npss &&
1803 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
1804 continue;
1805
c5552fde
AL		 1806 /*
1807 * Is this state a useful non-operational state for
1808 * higher-power states to autonomously transition to?
1809 */
1810 if (!(ctrl->psd[state].flags &
1811 NVME_PS_FLAGS_NON_OP_STATE))
1812 continue;
1813
da87591b
KHF		 1814 exit_latency_us =
1815 (u64)le32_to_cpu(ctrl->psd[state].exit_lat);
1816 if (exit_latency_us > ctrl->ps_max_latency_us)
c5552fde
AL		 1817 continue;
1818
da87591b
KHF		 1819 total_latency_us =
1820 exit_latency_us +
1821 le32_to_cpu(ctrl->psd[state].entry_lat);
1822
c5552fde
AL		 1823 /*
1824 * This state is good. Use it as the APST idle
1825 * target for higher power states.
1826 */
1827 transition_ms = total_latency_us + 19;
1828 do_div(transition_ms, 20);
1829 if (transition_ms > (1 << 24) - 1)
1830 transition_ms = (1 << 24) - 1;
1831
1832 target = cpu_to_le64((state << 3) |
1833 (transition_ms << 8));
fb0dc399
AL		 1834
1835 if (max_ps == -1)
1836 max_ps = state;
1837
1838 if (total_latency_us > max_lat_us)
1839 max_lat_us = total_latency_us;
c5552fde
AL		 1840 }
1841
1842 apste = 1;
fb0dc399
AL		 1843
1844 if (max_ps == -1) {
1845 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n");
1846 } else {
1847 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n",
1848 max_ps, max_lat_us, (int)sizeof(*table), table);
1849 }
c5552fde
AL		 1850 }
1851
1852 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
1853 table, sizeof(*table), NULL);
1854 if (ret)
1855 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
1856
1857 kfree(table);
634b8325 1858 return ret;
c5552fde
AL		 1859}
1860
1861static void nvme_set_latency_tolerance(struct device *dev, s32 val)
1862{
1863 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1864 u64 latency;
1865
1866 switch (val) {
1867 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
1868 case PM_QOS_LATENCY_ANY:
1869 latency = U64_MAX;
1870 break;
1871
1872 default:
1873 latency = val;
1874 }
1875
1876 if (ctrl->ps_max_latency_us != latency) {
1877 ctrl->ps_max_latency_us = latency;
1878 nvme_configure_apst(ctrl);
1879 }
1880}
1881
bd4da3ab
AL		 1882struct nvme_core_quirk_entry {
1883 /*
1884 * NVMe model and firmware strings are padded with spaces. For
1885 * simplicity, strings in the quirk table are padded with NULLs
1886 * instead.
1887 */
1888 u16 vid;
1889 const char *mn;
1890 const char *fr;
1891 unsigned long quirks;
1892};
1893
1894static const struct nvme_core_quirk_entry core_quirks[] = {
c5552fde 1895 {
be56945c
AL		 1896 /*
1897 * This Toshiba device seems to die using any APST states. See:
1898 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
1899 */
1900 .vid = 0x1179,
1901 .mn = "THNSF5256GPUK TOSHIBA",
c5552fde 1902 .quirks = NVME_QUIRK_NO_APST,
be56945c 1903 }
bd4da3ab
AL		 1904};
1905
1906/* match is null-terminated but idstr is space-padded. */
1907static bool string_matches(const char *idstr, const char *match, size_t len)
1908{
1909 size_t matchlen;
1910
1911 if (!match)
1912 return true;
1913
1914 matchlen = strlen(match);
1915 WARN_ON_ONCE(matchlen > len);
1916
1917 if (memcmp(idstr, match, matchlen))
1918 return false;
1919
1920 for (; matchlen < len; matchlen++)
1921 if (idstr[matchlen] != ' ')
1922 return false;
1923
1924 return true;
1925}
1926
1927static bool quirk_matches(const struct nvme_id_ctrl *id,
1928 const struct nvme_core_quirk_entry *q)
1929{
1930 return q->vid == le16_to_cpu(id->vid) &&
1931 string_matches(id->mn, q->mn, sizeof(id->mn)) &&
1932 string_matches(id->fr, q->fr, sizeof(id->fr));
1933}
1934
ab9e00cc
CH		 1935static void nvme_init_subnqn(struct nvme_subsystem *subsys, struct nvme_ctrl *ctrl,
1936 struct nvme_id_ctrl *id)
180de007
CH		 1937{
1938 size_t nqnlen;
1939 int off;
1940
1941 nqnlen = strnlen(id->subnqn, NVMF_NQN_SIZE);
1942 if (nqnlen > 0 && nqnlen < NVMF_NQN_SIZE) {
ab9e00cc 1943 strncpy(subsys->subnqn, id->subnqn, NVMF_NQN_SIZE);
180de007
CH		 1944 return;
1945 }
1946
1947 if (ctrl->vs >= NVME_VS(1, 2, 1))
1948 dev_warn(ctrl->device, "missing or invalid SUBNQN field.\n");
1949
1950 /* Generate a "fake" NQN per Figure 254 in NVMe 1.3 + ECN 001 */
ab9e00cc 1951 off = snprintf(subsys->subnqn, NVMF_NQN_SIZE,
180de007
CH		 1952 "nqn.2014.08.org.nvmexpress:%4x%4x",
1953 le16_to_cpu(id->vid), le16_to_cpu(id->ssvid));
ab9e00cc 1954 memcpy(subsys->subnqn + off, id->sn, sizeof(id->sn));
180de007 1955 off += sizeof(id->sn);
ab9e00cc 1956 memcpy(subsys->subnqn + off, id->mn, sizeof(id->mn));
180de007 1957 off += sizeof(id->mn);
ab9e00cc
CH		 1958 memset(subsys->subnqn + off, 0, sizeof(subsys->subnqn) - off);
1959}
1960
1961static void __nvme_release_subsystem(struct nvme_subsystem *subsys)
1962{
1963 ida_simple_remove(&nvme_subsystems_ida, subsys->instance);
1964 kfree(subsys);
1965}
1966
1967static void nvme_release_subsystem(struct device *dev)
1968{
1969 __nvme_release_subsystem(container_of(dev, struct nvme_subsystem, dev));
1970}
1971
1972static void nvme_destroy_subsystem(struct kref *ref)
1973{
1974 struct nvme_subsystem *subsys =
1975 container_of(ref, struct nvme_subsystem, ref);
1976
1977 mutex_lock(&nvme_subsystems_lock);
1978 list_del(&subsys->entry);
1979 mutex_unlock(&nvme_subsystems_lock);
1980
ed754e5d 1981 ida_destroy(&subsys->ns_ida);
ab9e00cc
CH		 1982 device_del(&subsys->dev);
1983 put_device(&subsys->dev);
1984}
1985
1986static void nvme_put_subsystem(struct nvme_subsystem *subsys)
1987{
1988 kref_put(&subsys->ref, nvme_destroy_subsystem);
1989}
1990
1991static struct nvme_subsystem *__nvme_find_get_subsystem(const char *subsysnqn)
1992{
1993 struct nvme_subsystem *subsys;
1994
1995 lockdep_assert_held(&nvme_subsystems_lock);
1996
1997 list_for_each_entry(subsys, &nvme_subsystems, entry) {
1998 if (strcmp(subsys->subnqn, subsysnqn))
1999 continue;
2000 if (!kref_get_unless_zero(&subsys->ref))
2001 continue;
2002 return subsys;
2003 }
2004
2005 return NULL;
2006}
2007
1e496938
HR		 2008#define SUBSYS_ATTR_RO(_name, _mode, _show) \
2009 struct device_attribute subsys_attr_##_name = \
2010 __ATTR(_name, _mode, _show, NULL)
2011
2012static ssize_t nvme_subsys_show_nqn(struct device *dev,
2013 struct device_attribute *attr,
2014 char *buf)
2015{
2016 struct nvme_subsystem *subsys =
2017 container_of(dev, struct nvme_subsystem, dev);
2018
2019 return snprintf(buf, PAGE_SIZE, "%s\n", subsys->subnqn);
2020}
2021static SUBSYS_ATTR_RO(subsysnqn, S_IRUGO, nvme_subsys_show_nqn);
2022
2023#define nvme_subsys_show_str_function(field) \
2024static ssize_t subsys_##field##_show(struct device *dev, \
2025 struct device_attribute *attr, char *buf) \
2026{ \
2027 struct nvme_subsystem *subsys = \
2028 container_of(dev, struct nvme_subsystem, dev); \
2029 return sprintf(buf, "%.*s\n", \
2030 (int)sizeof(subsys->field), subsys->field); \
2031} \
2032static SUBSYS_ATTR_RO(field, S_IRUGO, subsys_##field##_show);
2033
2034nvme_subsys_show_str_function(model);
2035nvme_subsys_show_str_function(serial);
2036nvme_subsys_show_str_function(firmware_rev);
2037
2038static struct attribute *nvme_subsys_attrs[] = {
2039 &subsys_attr_model.attr,
2040 &subsys_attr_serial.attr,
2041 &subsys_attr_firmware_rev.attr,
2042 &subsys_attr_subsysnqn.attr,
2043 NULL,
2044};
2045
2046static struct attribute_group nvme_subsys_attrs_group = {
2047 .attrs = nvme_subsys_attrs,
2048};
2049
2050static const struct attribute_group *nvme_subsys_attrs_groups[] = {
2051 &nvme_subsys_attrs_group,
2052 NULL,
2053};
2054
ab9e00cc
CH		 2055static int nvme_init_subsystem(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
2056{
2057 struct nvme_subsystem *subsys, *found;
2058 int ret;
2059
2060 subsys = kzalloc(sizeof(*subsys), GFP_KERNEL);
2061 if (!subsys)
2062 return -ENOMEM;
2063 ret = ida_simple_get(&nvme_subsystems_ida, 0, 0, GFP_KERNEL);
2064 if (ret < 0) {
2065 kfree(subsys);
2066 return ret;
2067 }
2068 subsys->instance = ret;
2069 mutex_init(&subsys->lock);
2070 kref_init(&subsys->ref);
2071 INIT_LIST_HEAD(&subsys->ctrls);
ed754e5d 2072 INIT_LIST_HEAD(&subsys->nsheads);
ab9e00cc
CH		 2073 nvme_init_subnqn(subsys, ctrl, id);
2074 memcpy(subsys->serial, id->sn, sizeof(subsys->serial));
2075 memcpy(subsys->model, id->mn, sizeof(subsys->model));
2076 memcpy(subsys->firmware_rev, id->fr, sizeof(subsys->firmware_rev));
2077 subsys->vendor_id = le16_to_cpu(id->vid);
2078 subsys->cmic = id->cmic;
2079
2080 subsys->dev.class = nvme_subsys_class;
2081 subsys->dev.release = nvme_release_subsystem;
1e496938 2082 subsys->dev.groups = nvme_subsys_attrs_groups;
ab9e00cc
CH		 2083 dev_set_name(&subsys->dev, "nvme-subsys%d", subsys->instance);
2084 device_initialize(&subsys->dev);
2085
2086 mutex_lock(&nvme_subsystems_lock);
2087 found = __nvme_find_get_subsystem(subsys->subnqn);
2088 if (found) {
2089 /*
2090 * Verify that the subsystem actually supports multiple
2091 * controllers, else bail out.
2092 */
2093 if (!(id->cmic & (1 << 1))) {
2094 dev_err(ctrl->device,
2095 "ignoring ctrl due to duplicate subnqn (%s).\n",
2096 found->subnqn);
2097 nvme_put_subsystem(found);
2098 ret = -EINVAL;
2099 goto out_unlock;
2100 }
2101
2102 __nvme_release_subsystem(subsys);
2103 subsys = found;
2104 } else {
2105 ret = device_add(&subsys->dev);
2106 if (ret) {
2107 dev_err(ctrl->device,
2108 "failed to register subsystem device.\n");
2109 goto out_unlock;
2110 }
ed754e5d 2111 ida_init(&subsys->ns_ida);
ab9e00cc
CH		 2112 list_add_tail(&subsys->entry, &nvme_subsystems);
2113 }
2114
2115 ctrl->subsys = subsys;
2116 mutex_unlock(&nvme_subsystems_lock);
2117
2118 if (sysfs_create_link(&subsys->dev.kobj, &ctrl->device->kobj,
2119 dev_name(ctrl->device))) {
2120 dev_err(ctrl->device,
2121 "failed to create sysfs link from subsystem.\n");
2122 /* the transport driver will eventually put the subsystem */
2123 return -EINVAL;
2124 }
2125
2126 mutex_lock(&subsys->lock);
2127 list_add_tail(&ctrl->subsys_entry, &subsys->ctrls);
2128 mutex_unlock(&subsys->lock);
2129
2130 return 0;
2131
2132out_unlock:
2133 mutex_unlock(&nvme_subsystems_lock);
2134 put_device(&subsys->dev);
2135 return ret;
180de007
CH		 2136}
2137
c627c487
KB		 2138static int nvme_get_log(struct nvme_ctrl *ctrl, u8 log_page, void *log,
2139 size_t size)
2140{
2141 struct nvme_command c = { };
2142
2143 c.common.opcode = nvme_admin_get_log_page;
2144 c.common.nsid = cpu_to_le32(NVME_NSID_ALL);
2145 c.common.cdw10[0] = nvme_get_log_dw10(log_page, size);
2146
2147 return nvme_submit_sync_cmd(ctrl->admin_q, &c, log, size);
2148}
2149
84fef62d
KB		 2150static int nvme_get_effects_log(struct nvme_ctrl *ctrl)
2151{
2152 int ret;
2153
2154 if (!ctrl->effects)
2155 ctrl->effects = kzalloc(sizeof(*ctrl->effects), GFP_KERNEL);
2156
2157 if (!ctrl->effects)
2158 return 0;
2159
2160 ret = nvme_get_log(ctrl, NVME_LOG_CMD_EFFECTS, ctrl->effects,
2161 sizeof(*ctrl->effects));
2162 if (ret) {
2163 kfree(ctrl->effects);
2164 ctrl->effects = NULL;
2165 }
2166 return ret;
180de007
CH		 2167}
2168
7fd8930f
CH		 2169/*
2170 * Initialize the cached copies of the Identify data and various controller
2171 * register in our nvme_ctrl structure. This should be called as soon as
2172 * the admin queue is fully up and running.
2173 */
2174int nvme_init_identify(struct nvme_ctrl *ctrl)
2175{
2176 struct nvme_id_ctrl *id;
2177 u64 cap;
2178 int ret, page_shift;
a229dbf6 2179 u32 max_hw_sectors;
76a5af84 2180 bool prev_apst_enabled;
7fd8930f 2181
f3ca80fc
CH		 2182 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
2183 if (ret) {
1b3c47c1 2184 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
f3ca80fc
CH		 2185 return ret;
2186 }
2187
7fd8930f
CH		 2188 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &cap);
2189 if (ret) {
1b3c47c1 2190 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
7fd8930f
CH		 2191 return ret;
2192 }
2193 page_shift = NVME_CAP_MPSMIN(cap) + 12;
2194
8ef2074d 2195 if (ctrl->vs >= NVME_VS(1, 1, 0))
f3ca80fc
CH		 2196 ctrl->subsystem = NVME_CAP_NSSRC(cap);
2197
7fd8930f
CH		 2198 ret = nvme_identify_ctrl(ctrl, &id);
2199 if (ret) {
1b3c47c1 2200 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH		 2201 return -EIO;
2202 }
2203
84fef62d
KB		 2204 if (id->lpa & NVME_CTRL_LPA_CMD_EFFECTS_LOG) {
2205 ret = nvme_get_effects_log(ctrl);
2206 if (ret < 0)
2207 return ret;
2208 }
180de007 2209
bd4da3ab 2210 if (!ctrl->identified) {
ab9e00cc
CH		 2211 int i;
2212
2213 ret = nvme_init_subsystem(ctrl, id);
2214 if (ret)
2215 goto out_free;
2216
bd4da3ab
AL		 2217 /*
2218 * Check for quirks. Quirk can depend on firmware version,
2219 * so, in principle, the set of quirks present can change
2220 * across a reset. As a possible future enhancement, we
2221 * could re-scan for quirks every time we reinitialize
2222 * the device, but we'd have to make sure that the driver
2223 * behaves intelligently if the quirks change.
2224 */
bd4da3ab
AL		 2225 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
2226 if (quirk_matches(id, &core_quirks[i]))
2227 ctrl->quirks |= core_quirks[i].quirks;
2228 }
2229 }
2230
c35e30b4 2231 if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) {
f0425db0 2232 dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n");
c35e30b4
AL		 2233 ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS;
2234 }
2235
8a9ae523 2236 ctrl->oacs = le16_to_cpu(id->oacs);
7fd8930f 2237 ctrl->oncs = le16_to_cpup(&id->oncs);
6bf25d16 2238 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 2239 ctrl->vwc = id->vwc;
931e1c22 2240 ctrl->cntlid = le16_to_cpup(&id->cntlid);
7fd8930f 2241 if (id->mdts)
a229dbf6 2242 max_hw_sectors = 1 << (id->mdts + page_shift - 9);
7fd8930f 2243 else
a229dbf6
CH		 2244 max_hw_sectors = UINT_MAX;
2245 ctrl->max_hw_sectors =
2246 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 2247
da35825d 2248 nvme_set_queue_limits(ctrl, ctrl->admin_q);
07bfcd09 2249 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 2250 ctrl->kas = le16_to_cpu(id->kas);
07bfcd09 2251
07fbd32a
MP		 2252 if (id->rtd3e) {
2253 /* us -> s */
2254 u32 transition_time = le32_to_cpu(id->rtd3e) / 1000000;
2255
2256 ctrl->shutdown_timeout = clamp_t(unsigned int, transition_time,
2257 shutdown_timeout, 60);
2258
2259 if (ctrl->shutdown_timeout != shutdown_timeout)
2260 dev_warn(ctrl->device,
2261 "Shutdown timeout set to %u seconds\n",
2262 ctrl->shutdown_timeout);
2263 } else
2264 ctrl->shutdown_timeout = shutdown_timeout;
2265
c5552fde 2266 ctrl->npss = id->npss;
76a5af84
KHF		 2267 ctrl->apsta = id->apsta;
2268 prev_apst_enabled = ctrl->apst_enabled;
c35e30b4
AL		 2269 if (ctrl->quirks & NVME_QUIRK_NO_APST) {
2270 if (force_apst && id->apsta) {
f0425db0 2271 dev_warn(ctrl->device, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n");
76a5af84 2272 ctrl->apst_enabled = true;
c35e30b4 2273 } else {
76a5af84 2274 ctrl->apst_enabled = false;
c35e30b4
AL		 2275 }
2276 } else {
76a5af84 2277 ctrl->apst_enabled = id->apsta;
c35e30b4 2278 }
c5552fde
AL		 2279 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
2280
d3d5b87d 2281 if (ctrl->ops->flags & NVME_F_FABRICS) {
07bfcd09
CH		 2282 ctrl->icdoff = le16_to_cpu(id->icdoff);
2283 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
2284 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
2285 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
2286
2287 /*
2288 * In fabrics we need to verify the cntlid matches the
2289 * admin connect
2290 */
634b8325 2291 if (ctrl->cntlid != le16_to_cpu(id->cntlid)) {
07bfcd09 2292 ret = -EINVAL;
634b8325
KB		 2293 goto out_free;
2294 }
038bd4cb
SG		 2295
2296 if (!ctrl->opts->discovery_nqn && !ctrl->kas) {
f0425db0 2297 dev_err(ctrl->device,
038bd4cb
SG		 2298 "keep-alive support is mandatory for fabrics\n");
2299 ret = -EINVAL;
634b8325 2300 goto out_free;
038bd4cb 2301 }
07bfcd09
CH		 2302 } else {
2303 ctrl->cntlid = le16_to_cpu(id->cntlid);
fe6d53c9
CH		 2304 ctrl->hmpre = le32_to_cpu(id->hmpre);
2305 ctrl->hmmin = le32_to_cpu(id->hmmin);
044a9df1
CH		 2306 ctrl->hmminds = le32_to_cpu(id->hmminds);
2307 ctrl->hmmaxd = le16_to_cpu(id->hmmaxd);
07bfcd09 2308 }
da35825d 2309
7fd8930f 2310 kfree(id);
bd4da3ab 2311
76a5af84 2312 if (ctrl->apst_enabled && !prev_apst_enabled)
c5552fde 2313 dev_pm_qos_expose_latency_tolerance(ctrl->device);
76a5af84 2314 else if (!ctrl->apst_enabled && prev_apst_enabled)
c5552fde
AL		 2315 dev_pm_qos_hide_latency_tolerance(ctrl->device);
2316
634b8325
KB		 2317 ret = nvme_configure_apst(ctrl);
2318 if (ret < 0)
2319 return ret;
dbf86b39
JD		 2320
2321 ret = nvme_configure_timestamp(ctrl);
2322 if (ret < 0)
2323 return ret;
634b8325
KB		 2324
2325 ret = nvme_configure_directives(ctrl);
2326 if (ret < 0)
2327 return ret;
c5552fde 2328
bd4da3ab 2329 ctrl->identified = true;
c5552fde 2330
634b8325
KB		 2331 return 0;
2332
2333out_free:
2334 kfree(id);
07bfcd09 2335 return ret;
7fd8930f 2336}
576d55d6 2337EXPORT_SYMBOL_GPL(nvme_init_identify);
7fd8930f 2338
f3ca80fc 2339static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 2340{
a6a5149b
CH		 2341 struct nvme_ctrl *ctrl =
2342 container_of(inode->i_cdev, struct nvme_ctrl, cdev);
1673f1f0 2343
999ada28 2344 if (ctrl->state != NVME_CTRL_LIVE)
a6a5149b
CH		 2345 return -EWOULDBLOCK;
2346 file->private_data = ctrl;
f3ca80fc
CH		 2347 return 0;
2348}
2349
bfd89471
CH		 2350static int nvme_dev_user_cmd(struct nvme_ctrl *ctrl, void __user *argp)
2351{
2352 struct nvme_ns *ns;
2353 int ret;
2354
2355 mutex_lock(&ctrl->namespaces_mutex);
2356 if (list_empty(&ctrl->namespaces)) {
2357 ret = -ENOTTY;
2358 goto out_unlock;
2359 }
2360
2361 ns = list_first_entry(&ctrl->namespaces, struct nvme_ns, list);
2362 if (ns != list_last_entry(&ctrl->namespaces, struct nvme_ns, list)) {
1b3c47c1 2363 dev_warn(ctrl->device,
bfd89471
CH		 2364 "NVME_IOCTL_IO_CMD not supported when multiple namespaces present!\n");
2365 ret = -EINVAL;
2366 goto out_unlock;
2367 }
2368
1b3c47c1 2369 dev_warn(ctrl->device,
bfd89471
CH		 2370 "using deprecated NVME_IOCTL_IO_CMD ioctl on the char device!\n");
2371 kref_get(&ns->kref);
2372 mutex_unlock(&ctrl->namespaces_mutex);
2373
2374 ret = nvme_user_cmd(ctrl, ns, argp);
2375 nvme_put_ns(ns);
2376 return ret;
2377
2378out_unlock:
2379 mutex_unlock(&ctrl->namespaces_mutex);
2380 return ret;
2381}
2382
f3ca80fc
CH		 2383static long nvme_dev_ioctl(struct file *file, unsigned int cmd,
2384 unsigned long arg)
2385{
2386 struct nvme_ctrl *ctrl = file->private_data;
2387 void __user *argp = (void __user *)arg;
f3ca80fc
CH		 2388
2389 switch (cmd) {
2390 case NVME_IOCTL_ADMIN_CMD:
2391 return nvme_user_cmd(ctrl, NULL, argp);
2392 case NVME_IOCTL_IO_CMD:
bfd89471 2393 return nvme_dev_user_cmd(ctrl, argp);
f3ca80fc 2394 case NVME_IOCTL_RESET:
1b3c47c1 2395 dev_warn(ctrl->device, "resetting controller\n");
d86c4d8e 2396 return nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 2397 case NVME_IOCTL_SUBSYS_RESET:
2398 return nvme_reset_subsystem(ctrl);
9ec3bb2f
KB		 2399 case NVME_IOCTL_RESCAN:
2400 nvme_queue_scan(ctrl);
2401 return 0;
f3ca80fc
CH		 2402 default:
2403 return -ENOTTY;
2404 }
2405}
2406
2407static const struct file_operations nvme_dev_fops = {
2408 .owner = THIS_MODULE,
2409 .open = nvme_dev_open,
f3ca80fc
CH		 2410 .unlocked_ioctl = nvme_dev_ioctl,
2411 .compat_ioctl = nvme_dev_ioctl,
2412};
2413
2414static ssize_t nvme_sysfs_reset(struct device *dev,
2415 struct device_attribute *attr, const char *buf,
2416 size_t count)
2417{
2418 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2419 int ret;
2420
d86c4d8e 2421 ret = nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 2422 if (ret < 0)
2423 return ret;
2424 return count;
1673f1f0 2425}
f3ca80fc 2426static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
1673f1f0 2427
9ec3bb2f
KB		 2428static ssize_t nvme_sysfs_rescan(struct device *dev,
2429 struct device_attribute *attr, const char *buf,
2430 size_t count)
2431{
2432 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2433
2434 nvme_queue_scan(ctrl);
2435 return count;
2436}
2437static DEVICE_ATTR(rescan_controller, S_IWUSR, NULL, nvme_sysfs_rescan);
2438
5b85b826
CH		 2439static inline struct nvme_ns_head *dev_to_ns_head(struct device *dev)
2440{
2441 struct gendisk *disk = dev_to_disk(dev);
2442
2443 if (disk->fops == &nvme_fops)
2444 return nvme_get_ns_from_dev(dev)->head;
2445 else
2446 return disk->private_data;
2447}
2448
118472ab 2449static ssize_t wwid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2450 char *buf)
118472ab 2451{
5b85b826
CH		 2452 struct nvme_ns_head *head = dev_to_ns_head(dev);
2453 struct nvme_ns_ids *ids = &head->ids;
2454 struct nvme_subsystem *subsys = head->subsys;
ab9e00cc
CH		 2455 int serial_len = sizeof(subsys->serial);
2456 int model_len = sizeof(subsys->model);
118472ab 2457
002fab04
CH		 2458 if (!uuid_is_null(&ids->uuid))
2459 return sprintf(buf, "uuid.%pU\n", &ids->uuid);
6484f5d1 2460
002fab04
CH		 2461 if (memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
2462 return sprintf(buf, "eui.%16phN\n", ids->nguid);
118472ab 2463
002fab04
CH		 2464 if (memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
2465 return sprintf(buf, "eui.%8phN\n", ids->eui64);
118472ab 2466
ab9e00cc
CH		 2467 while (serial_len > 0 && (subsys->serial[serial_len - 1] == ' ' ||
2468 subsys->serial[serial_len - 1] == '\0'))
118472ab 2469 serial_len--;
ab9e00cc
CH		 2470 while (model_len > 0 && (subsys->model[model_len - 1] == ' ' ||
2471 subsys->model[model_len - 1] == '\0'))
118472ab
KB		 2472 model_len--;
2473
ab9e00cc
CH		 2474 return sprintf(buf, "nvme.%04x-%*phN-%*phN-%08x\n", subsys->vendor_id,
2475 serial_len, subsys->serial, model_len, subsys->model,
5b85b826 2476 head->ns_id);
118472ab 2477}
6096bb34 2478static DEVICE_ATTR_RO(wwid);
118472ab 2479
d934f984 2480static ssize_t nguid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2481 char *buf)
d934f984 2482{
5b85b826 2483 return sprintf(buf, "%pU\n", dev_to_ns_head(dev)->ids.nguid);
d934f984 2484}
6096bb34 2485static DEVICE_ATTR_RO(nguid);
d934f984 2486
2b9b6e86 2487static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2488 char *buf)
2b9b6e86 2489{
5b85b826 2490 struct nvme_ns_ids *ids = &dev_to_ns_head(dev)->ids;
d934f984
JT		 2491
2492 /* For backward compatibility expose the NGUID to userspace if
2493 * we have no UUID set
2494 */
002fab04 2495 if (uuid_is_null(&ids->uuid)) {
d934f984
JT		 2496 printk_ratelimited(KERN_WARNING
2497 "No UUID available providing old NGUID\n");
002fab04 2498 return sprintf(buf, "%pU\n", ids->nguid);
d934f984 2499 }
002fab04 2500 return sprintf(buf, "%pU\n", &ids->uuid);
2b9b6e86 2501}
6096bb34 2502static DEVICE_ATTR_RO(uuid);
2b9b6e86
KB		 2503
2504static ssize_t eui_show(struct device *dev, struct device_attribute *attr,
5b85b826 2505 char *buf)
2b9b6e86 2506{
5b85b826 2507 return sprintf(buf, "%8ph\n", dev_to_ns_head(dev)->ids.eui64);
2b9b6e86 2508}
6096bb34 2509static DEVICE_ATTR_RO(eui);
2b9b6e86
KB		 2510
2511static ssize_t nsid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2512 char *buf)
2b9b6e86 2513{
5b85b826 2514 return sprintf(buf, "%d\n", dev_to_ns_head(dev)->ns_id);
2b9b6e86 2515}
6096bb34 2516static DEVICE_ATTR_RO(nsid);
2b9b6e86 2517
5b85b826 2518static struct attribute *nvme_ns_id_attrs[] = {
118472ab 2519 &dev_attr_wwid.attr,
2b9b6e86 2520 &dev_attr_uuid.attr,
d934f984 2521 &dev_attr_nguid.attr,
2b9b6e86
KB		 2522 &dev_attr_eui.attr,
2523 &dev_attr_nsid.attr,
2524 NULL,
2525};
2526
5b85b826 2527static umode_t nvme_ns_id_attrs_are_visible(struct kobject *kobj,
2b9b6e86
KB		 2528 struct attribute *a, int n)
2529{
2530 struct device *dev = container_of(kobj, struct device, kobj);
5b85b826 2531 struct nvme_ns_ids *ids = &dev_to_ns_head(dev)->ids;
2b9b6e86
KB		 2532
2533 if (a == &dev_attr_uuid.attr) {
a04b5de5 2534 if (uuid_is_null(&ids->uuid) &&
002fab04 2535 !memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
d934f984
JT		 2536 return 0;
2537 }
2538 if (a == &dev_attr_nguid.attr) {
002fab04 2539 if (!memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
2b9b6e86
KB		 2540 return 0;
2541 }
2542 if (a == &dev_attr_eui.attr) {
002fab04 2543 if (!memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
2b9b6e86
KB		 2544 return 0;
2545 }
2546 return a->mode;
2547}
2548
5b85b826
CH		 2549const struct attribute_group nvme_ns_id_attr_group = {
2550 .attrs = nvme_ns_id_attrs,
2551 .is_visible = nvme_ns_id_attrs_are_visible,
2b9b6e86
KB		 2552};
2553
931e1c22 2554#define nvme_show_str_function(field) \
779ff756
KB		 2555static ssize_t field##_show(struct device *dev, \
2556 struct device_attribute *attr, char *buf) \
2557{ \
2558 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
ab9e00cc
CH		 2559 return sprintf(buf, "%.*s\n", \
2560 (int)sizeof(ctrl->subsys->field), ctrl->subsys->field); \
779ff756
KB		 2561} \
2562static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
2563
ab9e00cc
CH		 2564nvme_show_str_function(model);
2565nvme_show_str_function(serial);
2566nvme_show_str_function(firmware_rev);
2567
931e1c22
ML		 2568#define nvme_show_int_function(field) \
2569static ssize_t field##_show(struct device *dev, \
2570 struct device_attribute *attr, char *buf) \
2571{ \
2572 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
2573 return sprintf(buf, "%d\n", ctrl->field); \
2574} \
2575static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
2576
931e1c22 2577nvme_show_int_function(cntlid);
779ff756 2578
1a353d85
ML		 2579static ssize_t nvme_sysfs_delete(struct device *dev,
2580 struct device_attribute *attr, const char *buf,
2581 size_t count)
2582{
2583 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2584
2585 if (device_remove_file_self(dev, attr))
c5017e85 2586 nvme_delete_ctrl_sync(ctrl);
1a353d85
ML		 2587 return count;
2588}
2589static DEVICE_ATTR(delete_controller, S_IWUSR, NULL, nvme_sysfs_delete);
2590
2591static ssize_t nvme_sysfs_show_transport(struct device *dev,
2592 struct device_attribute *attr,
2593 char *buf)
2594{
2595 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2596
2597 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->ops->name);
2598}
2599static DEVICE_ATTR(transport, S_IRUGO, nvme_sysfs_show_transport, NULL);
2600
8432bdb2
SG		 2601static ssize_t nvme_sysfs_show_state(struct device *dev,
2602 struct device_attribute *attr,
2603 char *buf)
2604{
2605 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2606 static const char *const state_name[] = {
2607 [NVME_CTRL_NEW] = "new",
2608 [NVME_CTRL_LIVE] = "live",
2609 [NVME_CTRL_RESETTING] = "resetting",
2610 [NVME_CTRL_RECONNECTING]= "reconnecting",
2611 [NVME_CTRL_DELETING] = "deleting",
2612 [NVME_CTRL_DEAD] = "dead",
2613 };
2614
2615 if ((unsigned)ctrl->state < ARRAY_SIZE(state_name) &&
2616 state_name[ctrl->state])
2617 return sprintf(buf, "%s\n", state_name[ctrl->state]);
2618
2619 return sprintf(buf, "unknown state\n");
2620}
2621
2622static DEVICE_ATTR(state, S_IRUGO, nvme_sysfs_show_state, NULL);
2623
1a353d85
ML		 2624static ssize_t nvme_sysfs_show_subsysnqn(struct device *dev,
2625 struct device_attribute *attr,
2626 char *buf)
2627{
2628 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2629
ab9e00cc 2630 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->subsys->subnqn);
1a353d85
ML		 2631}
2632static DEVICE_ATTR(subsysnqn, S_IRUGO, nvme_sysfs_show_subsysnqn, NULL);
2633
2634static ssize_t nvme_sysfs_show_address(struct device *dev,
2635 struct device_attribute *attr,
2636 char *buf)
2637{
2638 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2639
2640 return ctrl->ops->get_address(ctrl, buf, PAGE_SIZE);
2641}
2642static DEVICE_ATTR(address, S_IRUGO, nvme_sysfs_show_address, NULL);
2643
779ff756
KB		 2644static struct attribute *nvme_dev_attrs[] = {
2645 &dev_attr_reset_controller.attr,
9ec3bb2f 2646 &dev_attr_rescan_controller.attr,
779ff756
KB		 2647 &dev_attr_model.attr,
2648 &dev_attr_serial.attr,
2649 &dev_attr_firmware_rev.attr,
931e1c22 2650 &dev_attr_cntlid.attr,
1a353d85
ML		 2651 &dev_attr_delete_controller.attr,
2652 &dev_attr_transport.attr,
2653 &dev_attr_subsysnqn.attr,
2654 &dev_attr_address.attr,
8432bdb2 2655 &dev_attr_state.attr,
779ff756
KB		 2656 NULL
2657};
2658
1a353d85
ML		 2659static umode_t nvme_dev_attrs_are_visible(struct kobject *kobj,
2660 struct attribute *a, int n)
2661{
2662 struct device *dev = container_of(kobj, struct device, kobj);
2663 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2664
49d3d50b
CH		 2665 if (a == &dev_attr_delete_controller.attr && !ctrl->ops->delete_ctrl)
2666 return 0;
2667 if (a == &dev_attr_address.attr && !ctrl->ops->get_address)
2668 return 0;
1a353d85
ML		 2669
2670 return a->mode;
2671}
2672
779ff756 2673static struct attribute_group nvme_dev_attrs_group = {
1a353d85
ML		 2674 .attrs = nvme_dev_attrs,
2675 .is_visible = nvme_dev_attrs_are_visible,
779ff756
KB		 2676};
2677
2678static const struct attribute_group *nvme_dev_attr_groups[] = {
2679 &nvme_dev_attrs_group,
2680 NULL,
2681};
2682
ed754e5d
CH		 2683static struct nvme_ns_head *__nvme_find_ns_head(struct nvme_subsystem *subsys,
2684 unsigned nsid)
2685{
2686 struct nvme_ns_head *h;
2687
2688 lockdep_assert_held(&subsys->lock);
2689
2690 list_for_each_entry(h, &subsys->nsheads, entry) {
2691 if (h->ns_id == nsid && kref_get_unless_zero(&h->ref))
2692 return h;
2693 }
2694
2695 return NULL;
2696}
2697
2698static int __nvme_check_ids(struct nvme_subsystem *subsys,
2699 struct nvme_ns_head *new)
2700{
2701 struct nvme_ns_head *h;
2702
2703 lockdep_assert_held(&subsys->lock);
2704
2705 list_for_each_entry(h, &subsys->nsheads, entry) {
2706 if (nvme_ns_ids_valid(&new->ids) &&
2707 nvme_ns_ids_equal(&new->ids, &h->ids))
2708 return -EINVAL;
2709 }
2710
2711 return 0;
2712}
2713
2714static struct nvme_ns_head *nvme_alloc_ns_head(struct nvme_ctrl *ctrl,
2715 unsigned nsid, struct nvme_id_ns *id)
2716{
2717 struct nvme_ns_head *head;
2718 int ret = -ENOMEM;
2719
2720 head = kzalloc(sizeof(*head), GFP_KERNEL);
2721 if (!head)
2722 goto out;
2723 ret = ida_simple_get(&ctrl->subsys->ns_ida, 1, 0, GFP_KERNEL);
2724 if (ret < 0)
2725 goto out_free_head;
2726 head->instance = ret;
2727 INIT_LIST_HEAD(&head->list);
2728 init_srcu_struct(&head->srcu);
2729 head->subsys = ctrl->subsys;
2730 head->ns_id = nsid;
2731 kref_init(&head->ref);
2732
2733 nvme_report_ns_ids(ctrl, nsid, id, &head->ids);
2734
2735 ret = __nvme_check_ids(ctrl->subsys, head);
2736 if (ret) {
2737 dev_err(ctrl->device,
2738 "duplicate IDs for nsid %d\n", nsid);
2739 goto out_cleanup_srcu;
2740 }
2741
32acab31
CH		 2742 ret = nvme_mpath_alloc_disk(ctrl, head);
2743 if (ret)
2744 goto out_cleanup_srcu;
2745
ed754e5d
CH		 2746 list_add_tail(&head->entry, &ctrl->subsys->nsheads);
2747 return head;
2748out_cleanup_srcu:
2749 cleanup_srcu_struct(&head->srcu);
2750 ida_simple_remove(&ctrl->subsys->ns_ida, head->instance);
2751out_free_head:
2752 kfree(head);
2753out:
2754 return ERR_PTR(ret);
2755}
2756
2757static int nvme_init_ns_head(struct nvme_ns *ns, unsigned nsid,
2758 struct nvme_id_ns *id, bool *new)
2759{
2760 struct nvme_ctrl *ctrl = ns->ctrl;
2761 bool is_shared = id->nmic & (1 << 0);
2762 struct nvme_ns_head *head = NULL;
2763 int ret = 0;
2764
2765 mutex_lock(&ctrl->subsys->lock);
2766 if (is_shared)
2767 head = __nvme_find_ns_head(ctrl->subsys, nsid);
2768 if (!head) {
2769 head = nvme_alloc_ns_head(ctrl, nsid, id);
2770 if (IS_ERR(head)) {
2771 ret = PTR_ERR(head);
2772 goto out_unlock;
2773 }
2774
2775 *new = true;
2776 } else {
2777 struct nvme_ns_ids ids;
2778
2779 nvme_report_ns_ids(ctrl, nsid, id, &ids);
2780 if (!nvme_ns_ids_equal(&head->ids, &ids)) {
2781 dev_err(ctrl->device,
2782 "IDs don't match for shared namespace %d\n",
2783 nsid);
2784 ret = -EINVAL;
2785 goto out_unlock;
2786 }
2787
2788 *new = false;
2789 }
2790
2791 list_add_tail(&ns->siblings, &head->list);
2792 ns->head = head;
2793
2794out_unlock:
2795 mutex_unlock(&ctrl->subsys->lock);
2796 return ret;
2797}
2798
5bae7f73
CH		 2799static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2800{
2801 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2802 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2803
ed754e5d 2804 return nsa->head->ns_id - nsb->head->ns_id;
5bae7f73
CH		 2805}
2806
32f0c4af 2807static struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 2808{
32f0c4af 2809 struct nvme_ns *ns, *ret = NULL;
69d3b8ac 2810
32f0c4af 2811 mutex_lock(&ctrl->namespaces_mutex);
5bae7f73 2812 list_for_each_entry(ns, &ctrl->namespaces, list) {
ed754e5d 2813 if (ns->head->ns_id == nsid) {
2dd41228
CH		 2814 if (!kref_get_unless_zero(&ns->kref))
2815 continue;
32f0c4af
KB		 2816 ret = ns;
2817 break;
2818 }
ed754e5d 2819 if (ns->head->ns_id > nsid)
5bae7f73
CH		 2820 break;
2821 }
32f0c4af
KB		 2822 mutex_unlock(&ctrl->namespaces_mutex);
2823 return ret;
5bae7f73
CH		 2824}
2825
f5d11840
JA		 2826static int nvme_setup_streams_ns(struct nvme_ctrl *ctrl, struct nvme_ns *ns)
2827{
2828 struct streams_directive_params s;
2829 int ret;
2830
2831 if (!ctrl->nr_streams)
2832 return 0;
2833
ed754e5d 2834 ret = nvme_get_stream_params(ctrl, &s, ns->head->ns_id);
f5d11840
JA		 2835 if (ret)
2836 return ret;
2837
2838 ns->sws = le32_to_cpu(s.sws);
2839 ns->sgs = le16_to_cpu(s.sgs);
2840
2841 if (ns->sws) {
2842 unsigned int bs = 1 << ns->lba_shift;
2843
2844 blk_queue_io_min(ns->queue, bs * ns->sws);
2845 if (ns->sgs)
2846 blk_queue_io_opt(ns->queue, bs * ns->sws * ns->sgs);
2847 }
2848
2849 return 0;
2850}
2851
5bae7f73
CH		 2852static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
2853{
2854 struct nvme_ns *ns;
2855 struct gendisk *disk;
ac81bfa9
MB		 2856 struct nvme_id_ns *id;
2857 char disk_name[DISK_NAME_LEN];
32acab31 2858 int node = dev_to_node(ctrl->dev), flags = GENHD_FL_EXT_DEVT;
ed754e5d 2859 bool new = true;
5bae7f73
CH		 2860
2861 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
2862 if (!ns)
2863 return;
2864
2865 ns->queue = blk_mq_init_queue(ctrl->tagset);
2866 if (IS_ERR(ns->queue))
ed754e5d 2867 goto out_free_ns;
5bae7f73
CH		 2868 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
2869 ns->queue->queuedata = ns;
2870 ns->ctrl = ctrl;
2871
5bae7f73 2872 kref_init(&ns->kref);
5bae7f73 2873 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
5bae7f73
CH		 2874
2875 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
da35825d 2876 nvme_set_queue_limits(ctrl, ns->queue);
5bae7f73 2877
cdbff4f2
CH		 2878 id = nvme_identify_ns(ctrl, nsid);
2879 if (!id)
ac81bfa9
MB		 2880 goto out_free_queue;
2881
cdbff4f2
CH		 2882 if (id->ncap == 0)
2883 goto out_free_id;
2884
ed754e5d
CH		 2885 if (nvme_init_ns_head(ns, nsid, id, &new))
2886 goto out_free_id;
654b4a4a 2887 nvme_setup_streams_ns(ctrl, ns);
ed754e5d 2888
32acab31
CH		 2889#ifdef CONFIG_NVME_MULTIPATH
2890 /*
2891 * If multipathing is enabled we need to always use the subsystem
2892 * instance number for numbering our devices to avoid conflicts
2893 * between subsystems that have multiple controllers and thus use
2894 * the multipath-aware subsystem node and those that have a single
2895 * controller and use the controller node directly.
2896 */
2897 if (ns->head->disk) {
2898 sprintf(disk_name, "nvme%dc%dn%d", ctrl->subsys->instance,
2899 ctrl->cntlid, ns->head->instance);
2900 flags = GENHD_FL_HIDDEN;
2901 } else {
2902 sprintf(disk_name, "nvme%dn%d", ctrl->subsys->instance,
2903 ns->head->instance);
2904 }
2905#else
2906 /*
2907 * But without the multipath code enabled, multiple controller per
2908 * subsystems are visible as devices and thus we cannot use the
2909 * subsystem instance.
2910 */
ed754e5d 2911 sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->head->instance);
32acab31 2912#endif
cdbff4f2 2913
608cc4b1
CH		 2914 if ((ctrl->quirks & NVME_QUIRK_LIGHTNVM) && id->vs[0] == 0x1) {
2915 if (nvme_nvm_register(ns, disk_name, node)) {
2916 dev_warn(ctrl->device, "LightNVM init failure\n");
ed754e5d 2917 goto out_unlink_ns;
608cc4b1 2918 }
3dc87dd0 2919 }
ac81bfa9 2920
3dc87dd0
MB		 2921 disk = alloc_disk_node(0, node);
2922 if (!disk)
ed754e5d 2923 goto out_unlink_ns;
ac81bfa9 2924
3dc87dd0
MB		 2925 disk->fops = &nvme_fops;
2926 disk->private_data = ns;
2927 disk->queue = ns->queue;
32acab31 2928 disk->flags = flags;
3dc87dd0
MB		 2929 memcpy(disk->disk_name, disk_name, DISK_NAME_LEN);
2930 ns->disk = disk;
2931
2932 __nvme_revalidate_disk(disk, id);
5bae7f73 2933
32f0c4af
KB		 2934 mutex_lock(&ctrl->namespaces_mutex);
2935 list_add_tail(&ns->list, &ctrl->namespaces);
2936 mutex_unlock(&ctrl->namespaces_mutex);
2937
d22524a4 2938 nvme_get_ctrl(ctrl);
ac81bfa9
MB		 2939
2940 kfree(id);
2941
0d52c756 2942 device_add_disk(ctrl->device, ns->disk);
2b9b6e86 2943 if (sysfs_create_group(&disk_to_dev(ns->disk)->kobj,
5b85b826 2944 &nvme_ns_id_attr_group))
2b9b6e86
KB		 2945 pr_warn("%s: failed to create sysfs group for identification\n",
2946 ns->disk->disk_name);
3dc87dd0
MB		 2947 if (ns->ndev && nvme_nvm_register_sysfs(ns))
2948 pr_warn("%s: failed to register lightnvm sysfs group for identification\n",
2949 ns->disk->disk_name);
32acab31
CH		 2950
2951 if (new)
2952 nvme_mpath_add_disk(ns->head);
5bae7f73 2953 return;
ed754e5d
CH		 2954 out_unlink_ns:
2955 mutex_lock(&ctrl->subsys->lock);
2956 list_del_rcu(&ns->siblings);
2957 mutex_unlock(&ctrl->subsys->lock);
ac81bfa9
MB		 2958 out_free_id:
2959 kfree(id);
5bae7f73
CH		 2960 out_free_queue:
2961 blk_cleanup_queue(ns->queue);
2962 out_free_ns:
2963 kfree(ns);
2964}
2965
2966static void nvme_ns_remove(struct nvme_ns *ns)
2967{
646017a6
KB		 2968 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
2969 return;
69d3b8ac 2970
b0b4e09c 2971 if (ns->disk && ns->disk->flags & GENHD_FL_UP) {
2b9b6e86 2972 sysfs_remove_group(&disk_to_dev(ns->disk)->kobj,
5b85b826 2973 &nvme_ns_id_attr_group);
3dc87dd0
MB		 2974 if (ns->ndev)
2975 nvme_nvm_unregister_sysfs(ns);
5bae7f73 2976 del_gendisk(ns->disk);
5bae7f73 2977 blk_cleanup_queue(ns->queue);
bd9f5d65
ML		 2978 if (blk_get_integrity(ns->disk))
2979 blk_integrity_unregister(ns->disk);
5bae7f73 2980 }
32f0c4af 2981
ed754e5d 2982 mutex_lock(&ns->ctrl->subsys->lock);
32acab31 2983 nvme_mpath_clear_current_path(ns);
9941a862 2984 list_del_rcu(&ns->siblings);
ed754e5d
CH		 2985 mutex_unlock(&ns->ctrl->subsys->lock);
2986
32f0c4af 2987 mutex_lock(&ns->ctrl->namespaces_mutex);
5bae7f73 2988 list_del_init(&ns->list);
32f0c4af
KB		 2989 mutex_unlock(&ns->ctrl->namespaces_mutex);
2990
9941a862 2991 synchronize_srcu(&ns->head->srcu);
479a322f 2992 nvme_mpath_check_last_path(ns);
5bae7f73
CH		 2993 nvme_put_ns(ns);
2994}
2995
540c801c
KB		 2996static void nvme_validate_ns(struct nvme_ctrl *ctrl, unsigned nsid)
2997{
2998 struct nvme_ns *ns;
2999
32f0c4af 3000 ns = nvme_find_get_ns(ctrl, nsid);
540c801c 3001 if (ns) {
b0b4e09c 3002 if (ns->disk && revalidate_disk(ns->disk))
540c801c 3003 nvme_ns_remove(ns);
32f0c4af 3004 nvme_put_ns(ns);
540c801c
KB		 3005 } else
3006 nvme_alloc_ns(ctrl, nsid);
3007}
3008
47b0e50a
SB		 3009static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
3010 unsigned nsid)
3011{
3012 struct nvme_ns *ns, *next;
3013
3014 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
ed754e5d 3015 if (ns->head->ns_id > nsid)
47b0e50a
SB		 3016 nvme_ns_remove(ns);
3017 }
3018}
3019
540c801c
KB		 3020static int nvme_scan_ns_list(struct nvme_ctrl *ctrl, unsigned nn)
3021{
3022 struct nvme_ns *ns;
3023 __le32 *ns_list;
3024 unsigned i, j, nsid, prev = 0, num_lists = DIV_ROUND_UP(nn, 1024);
3025 int ret = 0;
3026
3027 ns_list = kzalloc(0x1000, GFP_KERNEL);
3028 if (!ns_list)
3029 return -ENOMEM;
3030
3031 for (i = 0; i < num_lists; i++) {
3032 ret = nvme_identify_ns_list(ctrl, prev, ns_list);
3033 if (ret)
47b0e50a 3034 goto free;
540c801c
KB		 3035
3036 for (j = 0; j < min(nn, 1024U); j++) {
3037 nsid = le32_to_cpu(ns_list[j]);
3038 if (!nsid)
3039 goto out;
3040
3041 nvme_validate_ns(ctrl, nsid);
3042
3043 while (++prev < nsid) {
32f0c4af
KB		 3044 ns = nvme_find_get_ns(ctrl, prev);
3045 if (ns) {
540c801c 3046 nvme_ns_remove(ns);
32f0c4af
KB		 3047 nvme_put_ns(ns);
3048 }
540c801c
KB		 3049 }
3050 }
3051 nn -= j;
3052 }
3053 out:
47b0e50a
SB		 3054 nvme_remove_invalid_namespaces(ctrl, prev);
3055 free:
540c801c
KB		 3056 kfree(ns_list);
3057 return ret;
3058}
3059
5955be21 3060static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl, unsigned nn)
5bae7f73 3061{
5bae7f73
CH		 3062 unsigned i;
3063
540c801c
KB		 3064 for (i = 1; i <= nn; i++)
3065 nvme_validate_ns(ctrl, i);
3066
47b0e50a 3067 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH		 3068}
3069
5955be21 3070static void nvme_scan_work(struct work_struct *work)
5bae7f73 3071{
5955be21
CH		 3072 struct nvme_ctrl *ctrl =
3073 container_of(work, struct nvme_ctrl, scan_work);
5bae7f73 3074 struct nvme_id_ctrl *id;
540c801c 3075 unsigned nn;
5bae7f73 3076
5955be21
CH		 3077 if (ctrl->state != NVME_CTRL_LIVE)
3078 return;
3079
5bae7f73
CH		 3080 if (nvme_identify_ctrl(ctrl, &id))
3081 return;
540c801c
KB		 3082
3083 nn = le32_to_cpu(id->nn);
8ef2074d 3084 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
540c801c
KB		 3085 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
3086 if (!nvme_scan_ns_list(ctrl, nn))
3087 goto done;
3088 }
5955be21 3089 nvme_scan_ns_sequential(ctrl, nn);
540c801c 3090 done:
32f0c4af 3091 mutex_lock(&ctrl->namespaces_mutex);
540c801c 3092 list_sort(NULL, &ctrl->namespaces, ns_cmp);
69d3b8ac 3093 mutex_unlock(&ctrl->namespaces_mutex);
5bae7f73
CH		 3094 kfree(id);
3095}
5955be21
CH		 3096
3097void nvme_queue_scan(struct nvme_ctrl *ctrl)
3098{
3099 /*
3100 * Do not queue new scan work when a controller is reset during
3101 * removal.
3102 */
3103 if (ctrl->state == NVME_CTRL_LIVE)
c669ccdc 3104 queue_work(nvme_wq, &ctrl->scan_work);
5955be21
CH		 3105}
3106EXPORT_SYMBOL_GPL(nvme_queue_scan);
5bae7f73 3107
32f0c4af
KB		 3108/*
3109 * This function iterates the namespace list unlocked to allow recovery from
3110 * controller failure. It is up to the caller to ensure the namespace list is
3111 * not modified by scan work while this function is executing.
3112 */
5bae7f73
CH		 3113void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
3114{
3115 struct nvme_ns *ns, *next;
3116
0ff9d4e1
KB		 3117 /*
3118 * The dead states indicates the controller was not gracefully
3119 * disconnected. In that case, we won't be able to flush any data while
3120 * removing the namespaces' disks; fail all the queues now to avoid
3121 * potentially having to clean up the failed sync later.
3122 */
3123 if (ctrl->state == NVME_CTRL_DEAD)
3124 nvme_kill_queues(ctrl);
3125
5bae7f73
CH		 3126 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list)
3127 nvme_ns_remove(ns);
3128}
576d55d6 3129EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 3130
e3d7874d
KB		 3131static void nvme_aen_uevent(struct nvme_ctrl *ctrl)
3132{
3133 char *envp[2] = { NULL, NULL };
3134 u32 aen_result = ctrl->aen_result;
3135
3136 ctrl->aen_result = 0;
3137 if (!aen_result)
3138 return;
3139
3140 envp[0] = kasprintf(GFP_KERNEL, "NVME_AEN=%#08x", aen_result);
3141 if (!envp[0])
3142 return;
3143 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp);
3144 kfree(envp[0]);
3145}
3146
f866fc42
CH		 3147static void nvme_async_event_work(struct work_struct *work)
3148{
3149 struct nvme_ctrl *ctrl =
3150 container_of(work, struct nvme_ctrl, async_event_work);
3151
e3d7874d 3152 nvme_aen_uevent(ctrl);
ad22c355 3153 ctrl->ops->submit_async_event(ctrl);
f866fc42
CH		 3154}
3155
b6dccf7f
AD		 3156static bool nvme_ctrl_pp_status(struct nvme_ctrl *ctrl)
3157{
3158
3159 u32 csts;
3160
3161 if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts))
3162 return false;
3163
3164 if (csts == ~0)
3165 return false;
3166
3167 return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP));
3168}
3169
3170static void nvme_get_fw_slot_info(struct nvme_ctrl *ctrl)
3171{
b6dccf7f
AD		 3172 struct nvme_fw_slot_info_log *log;
3173
3174 log = kmalloc(sizeof(*log), GFP_KERNEL);
3175 if (!log)
3176 return;
3177
c627c487 3178 if (nvme_get_log(ctrl, NVME_LOG_FW_SLOT, log, sizeof(*log)))
b6dccf7f
AD		 3179 dev_warn(ctrl->device,
3180 "Get FW SLOT INFO log error\n");
3181 kfree(log);
3182}
3183
3184static void nvme_fw_act_work(struct work_struct *work)
3185{
3186 struct nvme_ctrl *ctrl = container_of(work,
3187 struct nvme_ctrl, fw_act_work);
3188 unsigned long fw_act_timeout;
3189
3190 if (ctrl->mtfa)
3191 fw_act_timeout = jiffies +
3192 msecs_to_jiffies(ctrl->mtfa * 100);
3193 else
3194 fw_act_timeout = jiffies +
3195 msecs_to_jiffies(admin_timeout * 1000);
3196
3197 nvme_stop_queues(ctrl);
3198 while (nvme_ctrl_pp_status(ctrl)) {
3199 if (time_after(jiffies, fw_act_timeout)) {
3200 dev_warn(ctrl->device,
3201 "Fw activation timeout, reset controller\n");
3202 nvme_reset_ctrl(ctrl);
3203 break;
3204 }
3205 msleep(100);
3206 }
3207
3208 if (ctrl->state != NVME_CTRL_LIVE)
3209 return;
3210
3211 nvme_start_queues(ctrl);
a806c6c8 3212 /* read FW slot information to clear the AER */
b6dccf7f
AD		 3213 nvme_get_fw_slot_info(ctrl);
3214}
3215
7bf58533
CH		 3216void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
3217 union nvme_result *res)
f866fc42 3218{
7bf58533 3219 u32 result = le32_to_cpu(res->u32);
f866fc42 3220
ad22c355 3221 if (le16_to_cpu(status) >> 1 != NVME_SC_SUCCESS)
f866fc42
CH		 3222 return;
3223
e3d7874d
KB		 3224 switch (result & 0x7) {
3225 case NVME_AER_ERROR:
3226 case NVME_AER_SMART:
3227 case NVME_AER_CSS:
3228 case NVME_AER_VS:
3229 ctrl->aen_result = result;
7bf58533
CH		 3230 break;
3231 default:
3232 break;
f866fc42
CH		 3233 }
3234
f866fc42
CH		 3235 switch (result & 0xff07) {
3236 case NVME_AER_NOTICE_NS_CHANGED:
3237 dev_info(ctrl->device, "rescanning\n");
3238 nvme_queue_scan(ctrl);
3239 break;
b6dccf7f 3240 case NVME_AER_NOTICE_FW_ACT_STARTING:
1a40d972 3241 queue_work(nvme_wq, &ctrl->fw_act_work);
b6dccf7f 3242 break;
f866fc42
CH		 3243 default:
3244 dev_warn(ctrl->device, "async event result %08x\n", result);
3245 }
c669ccdc 3246 queue_work(nvme_wq, &ctrl->async_event_work);
f866fc42 3247}
f866fc42 3248EXPORT_SYMBOL_GPL(nvme_complete_async_event);
f3ca80fc 3249
d09f2b45 3250void nvme_stop_ctrl(struct nvme_ctrl *ctrl)
576d55d6 3251{
d09f2b45 3252 nvme_stop_keep_alive(ctrl);
f866fc42 3253 flush_work(&ctrl->async_event_work);
5955be21 3254 flush_work(&ctrl->scan_work);
b6dccf7f 3255 cancel_work_sync(&ctrl->fw_act_work);
d09f2b45
SG		 3256}
3257EXPORT_SYMBOL_GPL(nvme_stop_ctrl);
3258
3259void nvme_start_ctrl(struct nvme_ctrl *ctrl)
3260{
3261 if (ctrl->kato)
3262 nvme_start_keep_alive(ctrl);
3263
3264 if (ctrl->queue_count > 1) {
3265 nvme_queue_scan(ctrl);
d99ca609 3266 queue_work(nvme_wq, &ctrl->async_event_work);
d09f2b45
SG		 3267 nvme_start_queues(ctrl);
3268 }
3269}
3270EXPORT_SYMBOL_GPL(nvme_start_ctrl);
5955be21 3271
d09f2b45
SG		 3272void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
3273{
a6a5149b 3274 cdev_device_del(&ctrl->cdev, ctrl->device);
53029b04 3275}
576d55d6 3276EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04 3277
d22524a4 3278static void nvme_free_ctrl(struct device *dev)
53029b04 3279{
d22524a4
CH		 3280 struct nvme_ctrl *ctrl =
3281 container_of(dev, struct nvme_ctrl, ctrl_device);
ab9e00cc 3282 struct nvme_subsystem *subsys = ctrl->subsys;
f3ca80fc 3283
9843f685 3284 ida_simple_remove(&nvme_instance_ida, ctrl->instance);
84fef62d 3285 kfree(ctrl->effects);
f3ca80fc 3286
ab9e00cc
CH		 3287 if (subsys) {
3288 mutex_lock(&subsys->lock);
3289 list_del(&ctrl->subsys_entry);
3290 mutex_unlock(&subsys->lock);
3291 sysfs_remove_link(&subsys->dev.kobj, dev_name(ctrl->device));
3292 }
f3ca80fc
CH		 3293
3294 ctrl->ops->free_ctrl(ctrl);
f3ca80fc 3295
ab9e00cc
CH		 3296 if (subsys)
3297 nvme_put_subsystem(subsys);
f3ca80fc
CH		 3298}
3299
3300/*
3301 * Initialize a NVMe controller structures. This needs to be called during
3302 * earliest initialization so that we have the initialized structured around
3303 * during probing.
3304 */
3305int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
3306 const struct nvme_ctrl_ops *ops, unsigned long quirks)
3307{
3308 int ret;
3309
bb8d261e
CH		 3310 ctrl->state = NVME_CTRL_NEW;
3311 spin_lock_init(&ctrl->lock);
f3ca80fc 3312 INIT_LIST_HEAD(&ctrl->namespaces);
69d3b8ac 3313 mutex_init(&ctrl->namespaces_mutex);
f3ca80fc
CH		 3314 ctrl->dev = dev;
3315 ctrl->ops = ops;
3316 ctrl->quirks = quirks;
5955be21 3317 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 3318 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
b6dccf7f 3319 INIT_WORK(&ctrl->fw_act_work, nvme_fw_act_work);
c5017e85 3320 INIT_WORK(&ctrl->delete_work, nvme_delete_ctrl_work);
f3ca80fc 3321
9843f685
CH		 3322 ret = ida_simple_get(&nvme_instance_ida, 0, 0, GFP_KERNEL);
3323 if (ret < 0)
f3ca80fc 3324 goto out;
9843f685 3325 ctrl->instance = ret;
f3ca80fc 3326
d22524a4
CH		 3327 device_initialize(&ctrl->ctrl_device);
3328 ctrl->device = &ctrl->ctrl_device;
a6a5149b 3329 ctrl->device->devt = MKDEV(MAJOR(nvme_chr_devt), ctrl->instance);
d22524a4
CH		 3330 ctrl->device->class = nvme_class;
3331 ctrl->device->parent = ctrl->dev;
3332 ctrl->device->groups = nvme_dev_attr_groups;
3333 ctrl->device->release = nvme_free_ctrl;
3334 dev_set_drvdata(ctrl->device, ctrl);
3335 ret = dev_set_name(ctrl->device, "nvme%d", ctrl->instance);
3336 if (ret)
f3ca80fc 3337 goto out_release_instance;
f3ca80fc 3338
a6a5149b
CH		 3339 cdev_init(&ctrl->cdev, &nvme_dev_fops);
3340 ctrl->cdev.owner = ops->module;
3341 ret = cdev_device_add(&ctrl->cdev, ctrl->device);
d22524a4
CH		 3342 if (ret)
3343 goto out_free_name;
f3ca80fc 3344
c5552fde
AL		 3345 /*
3346 * Initialize latency tolerance controls. The sysfs files won't
3347 * be visible to userspace unless the device actually supports APST.
3348 */
3349 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
3350 dev_pm_qos_update_user_latency_tolerance(ctrl->device,
3351 min(default_ps_max_latency_us, (unsigned long)S32_MAX));
3352
f3ca80fc 3353 return 0;
d22524a4
CH		 3354out_free_name:
3355 kfree_const(dev->kobj.name);
f3ca80fc 3356out_release_instance:
9843f685 3357 ida_simple_remove(&nvme_instance_ida, ctrl->instance);
f3ca80fc
CH		 3358out:
3359 return ret;
3360}
576d55d6 3361EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 3362
69d9a99c
KB		 3363/**
3364 * nvme_kill_queues(): Ends all namespace queues
3365 * @ctrl: the dead controller that needs to end
3366 *
3367 * Call this function when the driver determines it is unable to get the
3368 * controller in a state capable of servicing IO.
3369 */
3370void nvme_kill_queues(struct nvme_ctrl *ctrl)
3371{
3372 struct nvme_ns *ns;
3373
32f0c4af 3374 mutex_lock(&ctrl->namespaces_mutex);
82654b6b 3375
443bd90f 3376 /* Forcibly unquiesce queues to avoid blocking dispatch */
7dd1ab16
SB		 3377 if (ctrl->admin_q)
3378 blk_mq_unquiesce_queue(ctrl->admin_q);
443bd90f 3379
32f0c4af 3380 list_for_each_entry(ns, &ctrl->namespaces, list) {
69d9a99c
KB		 3381 /*
3382 * Revalidating a dead namespace sets capacity to 0. This will
3383 * end buffered writers dirtying pages that can't be synced.
3384 */
f33447b9
KB		 3385 if (!ns->disk || test_and_set_bit(NVME_NS_DEAD, &ns->flags))
3386 continue;
3387 revalidate_disk(ns->disk);
69d9a99c 3388 blk_set_queue_dying(ns->queue);
806f026f 3389
443bd90f
ML		 3390 /* Forcibly unquiesce queues to avoid blocking dispatch */
3391 blk_mq_unquiesce_queue(ns->queue);
69d9a99c 3392 }
32f0c4af 3393 mutex_unlock(&ctrl->namespaces_mutex);
69d9a99c 3394}
237045fc 3395EXPORT_SYMBOL_GPL(nvme_kill_queues);
69d9a99c 3396
302ad8cc
KB		 3397void nvme_unfreeze(struct nvme_ctrl *ctrl)
3398{
3399 struct nvme_ns *ns;
3400
3401 mutex_lock(&ctrl->namespaces_mutex);
3402 list_for_each_entry(ns, &ctrl->namespaces, list)
3403 blk_mq_unfreeze_queue(ns->queue);
3404 mutex_unlock(&ctrl->namespaces_mutex);
3405}
3406EXPORT_SYMBOL_GPL(nvme_unfreeze);
3407
3408void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout)
3409{
3410 struct nvme_ns *ns;
3411
3412 mutex_lock(&ctrl->namespaces_mutex);
3413 list_for_each_entry(ns, &ctrl->namespaces, list) {
3414 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout);
3415 if (timeout <= 0)
3416 break;
3417 }
3418 mutex_unlock(&ctrl->namespaces_mutex);
3419}
3420EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout);
3421
3422void nvme_wait_freeze(struct nvme_ctrl *ctrl)
3423{
3424 struct nvme_ns *ns;
3425
3426 mutex_lock(&ctrl->namespaces_mutex);
3427 list_for_each_entry(ns, &ctrl->namespaces, list)
3428 blk_mq_freeze_queue_wait(ns->queue);
3429 mutex_unlock(&ctrl->namespaces_mutex);
3430}
3431EXPORT_SYMBOL_GPL(nvme_wait_freeze);
3432
3433void nvme_start_freeze(struct nvme_ctrl *ctrl)
3434{
3435 struct nvme_ns *ns;
3436
3437 mutex_lock(&ctrl->namespaces_mutex);
3438 list_for_each_entry(ns, &ctrl->namespaces, list)
1671d522 3439 blk_freeze_queue_start(ns->queue);
302ad8cc
KB		 3440 mutex_unlock(&ctrl->namespaces_mutex);
3441}
3442EXPORT_SYMBOL_GPL(nvme_start_freeze);
3443
25646264 3444void nvme_stop_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 3445{
3446 struct nvme_ns *ns;
3447
32f0c4af 3448 mutex_lock(&ctrl->namespaces_mutex);
a6eaa884 3449 list_for_each_entry(ns, &ctrl->namespaces, list)
3174dd33 3450 blk_mq_quiesce_queue(ns->queue);
32f0c4af 3451 mutex_unlock(&ctrl->namespaces_mutex);
363c9aac 3452}
576d55d6 3453EXPORT_SYMBOL_GPL(nvme_stop_queues);
363c9aac 3454
25646264 3455void nvme_start_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 3456{
3457 struct nvme_ns *ns;
3458
32f0c4af 3459 mutex_lock(&ctrl->namespaces_mutex);
8d7b8faf 3460 list_for_each_entry(ns, &ctrl->namespaces, list)
f660174e 3461 blk_mq_unquiesce_queue(ns->queue);
32f0c4af 3462 mutex_unlock(&ctrl->namespaces_mutex);
363c9aac 3463}
576d55d6 3464EXPORT_SYMBOL_GPL(nvme_start_queues);
363c9aac 3465
31b84460
SG		 3466int nvme_reinit_tagset(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set)
3467{
3468 if (!ctrl->ops->reinit_request)
3469 return 0;
3470
3471 return blk_mq_tagset_iter(set, set->driver_data,
3472 ctrl->ops->reinit_request);
3473}
3474EXPORT_SYMBOL_GPL(nvme_reinit_tagset);
3475
5bae7f73
CH		 3476int __init nvme_core_init(void)
3477{
3478 int result;
3479
9a6327d2
SG		 3480 nvme_wq = alloc_workqueue("nvme-wq",
3481 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
3482 if (!nvme_wq)
3483 return -ENOMEM;
3484
a6a5149b 3485 result = alloc_chrdev_region(&nvme_chr_devt, 0, NVME_MINORS, "nvme");
f3ca80fc 3486 if (result < 0)
9a6327d2 3487 goto destroy_wq;
f3ca80fc
CH		 3488
3489 nvme_class = class_create(THIS_MODULE, "nvme");
3490 if (IS_ERR(nvme_class)) {
3491 result = PTR_ERR(nvme_class);
3492 goto unregister_chrdev;
3493 }
3494
ab9e00cc
CH		 3495 nvme_subsys_class = class_create(THIS_MODULE, "nvme-subsystem");
3496 if (IS_ERR(nvme_subsys_class)) {
3497 result = PTR_ERR(nvme_subsys_class);
3498 goto destroy_class;
3499 }
5bae7f73 3500 return 0;
f3ca80fc 3501
ab9e00cc
CH		 3502destroy_class:
3503 class_destroy(nvme_class);
9a6327d2 3504unregister_chrdev:
a6a5149b 3505 unregister_chrdev_region(nvme_chr_devt, NVME_MINORS);
9a6327d2
SG		 3506destroy_wq:
3507 destroy_workqueue(nvme_wq);
f3ca80fc 3508 return result;
5bae7f73
CH		 3509}
3510
3511void nvme_core_exit(void)
3512{
ab9e00cc
CH		 3513 ida_destroy(&nvme_subsystems_ida);
3514 class_destroy(nvme_subsys_class);
f3ca80fc 3515 class_destroy(nvme_class);
a6a5149b 3516 unregister_chrdev_region(nvme_chr_devt, NVME_MINORS);
9a6327d2 3517 destroy_workqueue(nvme_wq);
5bae7f73 3518}
576d55d6
ML		 3519
3520MODULE_LICENSE("GPL");
3521MODULE_VERSION("1.0");
3522module_init(nvme_core_init);
3523module_exit(nvme_core_exit);
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