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[mirror_ubuntu-bionic-kernel.git] / drivers / nvme / host / core.c
CommitLineData
21d34711
CH		 1/*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/blkdev.h>
16#include <linux/blk-mq.h>
5fd4ce1b 17#include <linux/delay.h>
21d34711 18#include <linux/errno.h>
1673f1f0 19#include <linux/hdreg.h>
21d34711 20#include <linux/kernel.h>
5bae7f73
CH		 21#include <linux/module.h>
22#include <linux/list_sort.h>
21d34711
CH		 23#include <linux/slab.h>
24#include <linux/types.h>
1673f1f0
CH		 25#include <linux/pr.h>
26#include <linux/ptrace.h>
27#include <linux/nvme_ioctl.h>
28#include <linux/t10-pi.h>
c5552fde 29#include <linux/pm_qos.h>
1673f1f0
CH		 30#include <scsi/sg.h>
31#include <asm/unaligned.h>
21d34711
CH		 32
33#include "nvme.h"
038bd4cb 34#include "fabrics.h"
21d34711 35
f3ca80fc
CH		 36#define NVME_MINORS (1U << MINORBITS)
37
ba0ba7d3
ML		 38unsigned char admin_timeout = 60;
39module_param(admin_timeout, byte, 0644);
40MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 41EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3
ML		 42
43unsigned char nvme_io_timeout = 30;
44module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
45MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 46EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3
ML		 47
48unsigned char shutdown_timeout = 5;
49module_param(shutdown_timeout, byte, 0644);
50MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
51
44e44b29
CH		 52static u8 nvme_max_retries = 5;
53module_param_named(max_retries, nvme_max_retries, byte, 0644);
f80ec966 54MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
5bae7f73 55
f3ca80fc
CH		 56static int nvme_char_major;
57module_param(nvme_char_major, int, 0);
58
c5552fde
AL		 59static unsigned long default_ps_max_latency_us = 25000;
60module_param(default_ps_max_latency_us, ulong, 0644);
61MODULE_PARM_DESC(default_ps_max_latency_us,
62 "max power saving latency for new devices; use PM QOS to change per device");
63
f3ca80fc 64static LIST_HEAD(nvme_ctrl_list);
9f2482b9 65static DEFINE_SPINLOCK(dev_list_lock);
1673f1f0 66
f3ca80fc
CH		 67static struct class *nvme_class;
68
65ba6b54 69static int nvme_error_status(struct request *req)
27fa9bc5
CH		 70{
71 switch (nvme_req(req)->status & 0x7ff) {
72 case NVME_SC_SUCCESS:
73 return 0;
74 case NVME_SC_CAP_EXCEEDED:
75 return -ENOSPC;
76 default:
77 return -EIO;
e02ab023
JG		 78
79 /*
80 * XXX: these errors are a nasty side-band protocol to
81 * drivers/md/dm-mpath.c:noretry_error() that aren't documented
82 * anywhere..
83 */
84 case NVME_SC_CMD_SEQ_ERROR:
85 return -EILSEQ;
86 case NVME_SC_ONCS_NOT_SUPPORTED:
87 return -EOPNOTSUPP;
88 case NVME_SC_WRITE_FAULT:
89 case NVME_SC_READ_ERROR:
90 case NVME_SC_UNWRITTEN_BLOCK:
91 return -ENODATA;
27fa9bc5
CH		 92 }
93}
27fa9bc5 94
f6324b1b 95static inline bool nvme_req_needs_retry(struct request *req)
77f02a7a 96{
f6324b1b
CH		 97 if (blk_noretry_request(req))
98 return false;
27fa9bc5 99 if (nvme_req(req)->status & NVME_SC_DNR)
f6324b1b
CH		 100 return false;
101 if (jiffies - req->start_time >= req->timeout)
102 return false;
44e44b29 103 if (nvme_req(req)->retries >= nvme_max_retries)
f6324b1b
CH		 104 return false;
105 return true;
77f02a7a
CH		 106}
107
108void nvme_complete_rq(struct request *req)
109{
27fa9bc5
CH		 110 if (unlikely(nvme_req(req)->status && nvme_req_needs_retry(req))) {
111 nvme_req(req)->retries++;
112 blk_mq_requeue_request(req, !blk_mq_queue_stopped(req->q));
113 return;
77f02a7a
CH		 114 }
115
27fa9bc5 116 blk_mq_end_request(req, nvme_error_status(req));
77f02a7a
CH		 117}
118EXPORT_SYMBOL_GPL(nvme_complete_rq);
119
c55a2fd4
ML		 120void nvme_cancel_request(struct request *req, void *data, bool reserved)
121{
122 int status;
123
124 if (!blk_mq_request_started(req))
125 return;
126
127 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
128 "Cancelling I/O %d", req->tag);
129
130 status = NVME_SC_ABORT_REQ;
131 if (blk_queue_dying(req->q))
132 status |= NVME_SC_DNR;
27fa9bc5 133 nvme_req(req)->status = status;
08e0029a 134 blk_mq_complete_request(req);
27fa9bc5 135
c55a2fd4
ML		 136}
137EXPORT_SYMBOL_GPL(nvme_cancel_request);
138
bb8d261e
CH		 139bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
140 enum nvme_ctrl_state new_state)
141{
f6b6a28e 142 enum nvme_ctrl_state old_state;
bb8d261e
CH		 143 bool changed = false;
144
145 spin_lock_irq(&ctrl->lock);
f6b6a28e
GKB		 146
147 old_state = ctrl->state;
bb8d261e
CH		 148 switch (new_state) {
149 case NVME_CTRL_LIVE:
150 switch (old_state) {
7d2e8008 151 case NVME_CTRL_NEW:
bb8d261e 152 case NVME_CTRL_RESETTING:
def61eca 153 case NVME_CTRL_RECONNECTING:
bb8d261e
CH		 154 changed = true;
155 /* FALLTHRU */
156 default:
157 break;
158 }
159 break;
160 case NVME_CTRL_RESETTING:
161 switch (old_state) {
162 case NVME_CTRL_NEW:
def61eca
CH		 163 case NVME_CTRL_LIVE:
164 case NVME_CTRL_RECONNECTING:
165 changed = true;
166 /* FALLTHRU */
167 default:
168 break;
169 }
170 break;
171 case NVME_CTRL_RECONNECTING:
172 switch (old_state) {
bb8d261e
CH		 173 case NVME_CTRL_LIVE:
174 changed = true;
175 /* FALLTHRU */
176 default:
177 break;
178 }
179 break;
180 case NVME_CTRL_DELETING:
181 switch (old_state) {
182 case NVME_CTRL_LIVE:
183 case NVME_CTRL_RESETTING:
def61eca 184 case NVME_CTRL_RECONNECTING:
bb8d261e
CH		 185 changed = true;
186 /* FALLTHRU */
187 default:
188 break;
189 }
190 break;
0ff9d4e1
KB		 191 case NVME_CTRL_DEAD:
192 switch (old_state) {
193 case NVME_CTRL_DELETING:
194 changed = true;
195 /* FALLTHRU */
196 default:
197 break;
198 }
199 break;
bb8d261e
CH		 200 default:
201 break;
202 }
bb8d261e
CH		 203
204 if (changed)
205 ctrl->state = new_state;
206
f6b6a28e
GKB		 207 spin_unlock_irq(&ctrl->lock);
208
bb8d261e
CH		 209 return changed;
210}
211EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
212
1673f1f0
CH		 213static void nvme_free_ns(struct kref *kref)
214{
215 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
216
b0b4e09c
MB		 217 if (ns->ndev)
218 nvme_nvm_unregister(ns);
1673f1f0 219
b0b4e09c
MB		 220 if (ns->disk) {
221 spin_lock(&dev_list_lock);
222 ns->disk->private_data = NULL;
223 spin_unlock(&dev_list_lock);
224 }
1673f1f0 225
1673f1f0 226 put_disk(ns->disk);
075790eb
KB		 227 ida_simple_remove(&ns->ctrl->ns_ida, ns->instance);
228 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH		 229 kfree(ns);
230}
231
5bae7f73 232static void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH		 233{
234 kref_put(&ns->kref, nvme_free_ns);
235}
236
237static struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk)
238{
239 struct nvme_ns *ns;
240
241 spin_lock(&dev_list_lock);
242 ns = disk->private_data;
e439bb12
SG		 243 if (ns) {
244 if (!kref_get_unless_zero(&ns->kref))
245 goto fail;
246 if (!try_module_get(ns->ctrl->ops->module))
247 goto fail_put_ns;
248 }
1673f1f0
CH		 249 spin_unlock(&dev_list_lock);
250
251 return ns;
e439bb12
SG		 252
253fail_put_ns:
254 kref_put(&ns->kref, nvme_free_ns);
255fail:
256 spin_unlock(&dev_list_lock);
257 return NULL;
1673f1f0
CH		 258}
259
4160982e 260struct request *nvme_alloc_request(struct request_queue *q,
eb71f435 261 struct nvme_command *cmd, unsigned int flags, int qid)
21d34711 262{
aebf526b 263 unsigned op = nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN;
21d34711 264 struct request *req;
21d34711 265
eb71f435 266 if (qid == NVME_QID_ANY) {
aebf526b 267 req = blk_mq_alloc_request(q, op, flags);
eb71f435 268 } else {
aebf526b 269 req = blk_mq_alloc_request_hctx(q, op, flags,
eb71f435
CH		 270 qid ? qid - 1 : 0);
271 }
21d34711 272 if (IS_ERR(req))
4160982e 273 return req;
21d34711 274
21d34711 275 req->cmd_flags |= REQ_FAILFAST_DRIVER;
d49187e9 276 nvme_req(req)->cmd = cmd;
21d34711 277
4160982e
CH		 278 return req;
279}
576d55d6 280EXPORT_SYMBOL_GPL(nvme_alloc_request);
4160982e 281
8093f7ca
ML		 282static inline void nvme_setup_flush(struct nvme_ns *ns,
283 struct nvme_command *cmnd)
284{
285 memset(cmnd, 0, sizeof(*cmnd));
286 cmnd->common.opcode = nvme_cmd_flush;
287 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
288}
289
290static inline int nvme_setup_discard(struct nvme_ns *ns, struct request *req,
291 struct nvme_command *cmnd)
292{
b35ba01e 293 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
8093f7ca 294 struct nvme_dsm_range *range;
b35ba01e 295 struct bio *bio;
8093f7ca 296
b35ba01e 297 range = kmalloc_array(segments, sizeof(*range), GFP_ATOMIC);
8093f7ca
ML		 298 if (!range)
299 return BLK_MQ_RQ_QUEUE_BUSY;
300
b35ba01e
CH		 301 __rq_for_each_bio(bio, req) {
302 u64 slba = nvme_block_nr(ns, bio->bi_iter.bi_sector);
303 u32 nlb = bio->bi_iter.bi_size >> ns->lba_shift;
304
305 range[n].cattr = cpu_to_le32(0);
306 range[n].nlb = cpu_to_le32(nlb);
307 range[n].slba = cpu_to_le64(slba);
308 n++;
309 }
310
311 if (WARN_ON_ONCE(n != segments)) {
312 kfree(range);
313 return BLK_MQ_RQ_QUEUE_ERROR;
314 }
8093f7ca
ML		 315
316 memset(cmnd, 0, sizeof(*cmnd));
317 cmnd->dsm.opcode = nvme_cmd_dsm;
318 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
f1dd03a8 319 cmnd->dsm.nr = cpu_to_le32(segments - 1);
8093f7ca
ML		 320 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
321
f9d03f96
CH		 322 req->special_vec.bv_page = virt_to_page(range);
323 req->special_vec.bv_offset = offset_in_page(range);
b35ba01e 324 req->special_vec.bv_len = sizeof(*range) * segments;
f9d03f96 325 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 326
bac0000a 327 return BLK_MQ_RQ_QUEUE_OK;
8093f7ca 328}
8093f7ca 329
8093f7ca
ML		 330static inline void nvme_setup_rw(struct nvme_ns *ns, struct request *req,
331 struct nvme_command *cmnd)
332{
333 u16 control = 0;
334 u32 dsmgmt = 0;
335
336 if (req->cmd_flags & REQ_FUA)
337 control |= NVME_RW_FUA;
338 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
339 control |= NVME_RW_LR;
340
341 if (req->cmd_flags & REQ_RAHEAD)
342 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
343
344 memset(cmnd, 0, sizeof(*cmnd));
345 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
8093f7ca
ML		 346 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
347 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
348 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
349
350 if (ns->ms) {
351 switch (ns->pi_type) {
352 case NVME_NS_DPS_PI_TYPE3:
353 control |= NVME_RW_PRINFO_PRCHK_GUARD;
354 break;
355 case NVME_NS_DPS_PI_TYPE1:
356 case NVME_NS_DPS_PI_TYPE2:
357 control |= NVME_RW_PRINFO_PRCHK_GUARD |
358 NVME_RW_PRINFO_PRCHK_REF;
359 cmnd->rw.reftag = cpu_to_le32(
360 nvme_block_nr(ns, blk_rq_pos(req)));
361 break;
362 }
363 if (!blk_integrity_rq(req))
364 control |= NVME_RW_PRINFO_PRACT;
365 }
366
367 cmnd->rw.control = cpu_to_le16(control);
368 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
369}
370
371int nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
372 struct nvme_command *cmd)
373{
bac0000a 374 int ret = BLK_MQ_RQ_QUEUE_OK;
8093f7ca 375
987f699a 376 if (!(req->rq_flags & RQF_DONTPREP)) {
44e44b29 377 nvme_req(req)->retries = 0;
27fa9bc5 378 nvme_req(req)->flags = 0;
987f699a
CH		 379 req->rq_flags |= RQF_DONTPREP;
380 }
381
aebf526b
CH		 382 switch (req_op(req)) {
383 case REQ_OP_DRV_IN:
384 case REQ_OP_DRV_OUT:
d49187e9 385 memcpy(cmd, nvme_req(req)->cmd, sizeof(*cmd));
aebf526b
CH		 386 break;
387 case REQ_OP_FLUSH:
8093f7ca 388 nvme_setup_flush(ns, cmd);
aebf526b 389 break;
e850fd16
CH		 390 case REQ_OP_WRITE_ZEROES:
391 /* currently only aliased to deallocate for a few ctrls: */
aebf526b 392 case REQ_OP_DISCARD:
8093f7ca 393 ret = nvme_setup_discard(ns, req, cmd);
aebf526b
CH		 394 break;
395 case REQ_OP_READ:
396 case REQ_OP_WRITE:
8093f7ca 397 nvme_setup_rw(ns, req, cmd);
aebf526b
CH		 398 break;
399 default:
400 WARN_ON_ONCE(1);
401 return BLK_MQ_RQ_QUEUE_ERROR;
402 }
8093f7ca 403
721b3917 404 cmd->common.command_id = req->tag;
8093f7ca
ML		 405 return ret;
406}
407EXPORT_SYMBOL_GPL(nvme_setup_cmd);
408
4160982e
CH		 409/*
410 * Returns 0 on success. If the result is negative, it's a Linux error code;
411 * if the result is positive, it's an NVM Express status code
412 */
413int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 414 union nvme_result *result, void *buffer, unsigned bufflen,
eb71f435 415 unsigned timeout, int qid, int at_head, int flags)
4160982e
CH		 416{
417 struct request *req;
418 int ret;
419
eb71f435 420 req = nvme_alloc_request(q, cmd, flags, qid);
4160982e
CH		 421 if (IS_ERR(req))
422 return PTR_ERR(req);
423
424 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
425
21d34711
CH		 426 if (buffer && bufflen) {
427 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
428 if (ret)
429 goto out;
4160982e
CH		 430 }
431
eb71f435 432 blk_execute_rq(req->q, NULL, req, at_head);
d49187e9
CH		 433 if (result)
434 *result = nvme_req(req)->result;
27fa9bc5
CH		 435 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
436 ret = -EINTR;
437 else
438 ret = nvme_req(req)->status;
4160982e
CH		 439 out:
440 blk_mq_free_request(req);
441 return ret;
442}
eb71f435 443EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH		 444
445int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
446 void *buffer, unsigned bufflen)
447{
eb71f435
CH		 448 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 0,
449 NVME_QID_ANY, 0, 0);
4160982e 450}
576d55d6 451EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 452
0b7f1f26
KB		 453int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
454 void __user *ubuffer, unsigned bufflen,
455 void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
456 u32 *result, unsigned timeout)
4160982e 457{
7a5abb4b 458 bool write = nvme_is_write(cmd);
0b7f1f26
KB		 459 struct nvme_ns *ns = q->queuedata;
460 struct gendisk *disk = ns ? ns->disk : NULL;
4160982e 461 struct request *req;
0b7f1f26
KB		 462 struct bio *bio = NULL;
463 void *meta = NULL;
4160982e
CH		 464 int ret;
465
eb71f435 466 req = nvme_alloc_request(q, cmd, 0, NVME_QID_ANY);
4160982e
CH		 467 if (IS_ERR(req))
468 return PTR_ERR(req);
469
470 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
471
472 if (ubuffer && bufflen) {
21d34711
CH		 473 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
474 GFP_KERNEL);
475 if (ret)
476 goto out;
477 bio = req->bio;
21d34711 478
0b7f1f26
KB		 479 if (!disk)
480 goto submit;
481 bio->bi_bdev = bdget_disk(disk, 0);
482 if (!bio->bi_bdev) {
483 ret = -ENODEV;
484 goto out_unmap;
485 }
486
e9fc63d6 487 if (meta_buffer && meta_len) {
0b7f1f26
KB		 488 struct bio_integrity_payload *bip;
489
490 meta = kmalloc(meta_len, GFP_KERNEL);
491 if (!meta) {
492 ret = -ENOMEM;
493 goto out_unmap;
494 }
495
496 if (write) {
497 if (copy_from_user(meta, meta_buffer,
498 meta_len)) {
499 ret = -EFAULT;
500 goto out_free_meta;
501 }
502 }
503
504 bip = bio_integrity_alloc(bio, GFP_KERNEL, 1);
06c1e390
KB		 505 if (IS_ERR(bip)) {
506 ret = PTR_ERR(bip);
0b7f1f26
KB		 507 goto out_free_meta;
508 }
509
510 bip->bip_iter.bi_size = meta_len;
511 bip->bip_iter.bi_sector = meta_seed;
512
513 ret = bio_integrity_add_page(bio, virt_to_page(meta),
514 meta_len, offset_in_page(meta));
515 if (ret != meta_len) {
516 ret = -ENOMEM;
517 goto out_free_meta;
518 }
519 }
520 }
521 submit:
522 blk_execute_rq(req->q, disk, req, 0);
27fa9bc5
CH		 523 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
524 ret = -EINTR;
525 else
526 ret = nvme_req(req)->status;
21d34711 527 if (result)
d49187e9 528 *result = le32_to_cpu(nvme_req(req)->result.u32);
0b7f1f26
KB		 529 if (meta && !ret && !write) {
530 if (copy_to_user(meta_buffer, meta, meta_len))
531 ret = -EFAULT;
532 }
533 out_free_meta:
534 kfree(meta);
535 out_unmap:
536 if (bio) {
537 if (disk && bio->bi_bdev)
538 bdput(bio->bi_bdev);
539 blk_rq_unmap_user(bio);
540 }
21d34711
CH		 541 out:
542 blk_mq_free_request(req);
543 return ret;
544}
545
0b7f1f26
KB		 546int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
547 void __user *ubuffer, unsigned bufflen, u32 *result,
548 unsigned timeout)
549{
550 return __nvme_submit_user_cmd(q, cmd, ubuffer, bufflen, NULL, 0, 0,
551 result, timeout);
552}
553
038bd4cb
SG		 554static void nvme_keep_alive_end_io(struct request *rq, int error)
555{
556 struct nvme_ctrl *ctrl = rq->end_io_data;
557
558 blk_mq_free_request(rq);
559
560 if (error) {
561 dev_err(ctrl->device,
562 "failed nvme_keep_alive_end_io error=%d\n", error);
563 return;
564 }
565
566 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
567}
568
569static int nvme_keep_alive(struct nvme_ctrl *ctrl)
570{
571 struct nvme_command c;
572 struct request *rq;
573
574 memset(&c, 0, sizeof(c));
575 c.common.opcode = nvme_admin_keep_alive;
576
577 rq = nvme_alloc_request(ctrl->admin_q, &c, BLK_MQ_REQ_RESERVED,
578 NVME_QID_ANY);
579 if (IS_ERR(rq))
580 return PTR_ERR(rq);
581
582 rq->timeout = ctrl->kato * HZ;
583 rq->end_io_data = ctrl;
584
585 blk_execute_rq_nowait(rq->q, NULL, rq, 0, nvme_keep_alive_end_io);
586
587 return 0;
588}
589
590static void nvme_keep_alive_work(struct work_struct *work)
591{
592 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
593 struct nvme_ctrl, ka_work);
594
595 if (nvme_keep_alive(ctrl)) {
596 /* allocation failure, reset the controller */
597 dev_err(ctrl->device, "keep-alive failed\n");
598 ctrl->ops->reset_ctrl(ctrl);
599 return;
600 }
601}
602
603void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
604{
605 if (unlikely(ctrl->kato == 0))
606 return;
607
608 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
609 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
610}
611EXPORT_SYMBOL_GPL(nvme_start_keep_alive);
612
613void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
614{
615 if (unlikely(ctrl->kato == 0))
616 return;
617
618 cancel_delayed_work_sync(&ctrl->ka_work);
619}
620EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
621
1c63dc66 622int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH		 623{
624 struct nvme_command c = { };
625 int error;
626
627 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
628 c.identify.opcode = nvme_admin_identify;
986994a2 629 c.identify.cns = NVME_ID_CNS_CTRL;
21d34711
CH		 630
631 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
632 if (!*id)
633 return -ENOMEM;
634
635 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
636 sizeof(struct nvme_id_ctrl));
637 if (error)
638 kfree(*id);
639 return error;
640}
641
540c801c
KB		 642static int nvme_identify_ns_list(struct nvme_ctrl *dev, unsigned nsid, __le32 *ns_list)
643{
644 struct nvme_command c = { };
645
646 c.identify.opcode = nvme_admin_identify;
986994a2 647 c.identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST;
540c801c
KB		 648 c.identify.nsid = cpu_to_le32(nsid);
649 return nvme_submit_sync_cmd(dev->admin_q, &c, ns_list, 0x1000);
650}
651
1c63dc66 652int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
21d34711
CH		 653 struct nvme_id_ns **id)
654{
655 struct nvme_command c = { };
656 int error;
657
658 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
778f067c
MG		 659 c.identify.opcode = nvme_admin_identify;
660 c.identify.nsid = cpu_to_le32(nsid);
986994a2 661 c.identify.cns = NVME_ID_CNS_NS;
21d34711
CH		 662
663 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
664 if (!*id)
665 return -ENOMEM;
666
667 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
668 sizeof(struct nvme_id_ns));
669 if (error)
670 kfree(*id);
671 return error;
672}
673
1c63dc66 674int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
1a6fe74d 675 void *buffer, size_t buflen, u32 *result)
21d34711
CH		 676{
677 struct nvme_command c;
d49187e9 678 union nvme_result res;
1cb3cce5 679 int ret;
21d34711
CH		 680
681 memset(&c, 0, sizeof(c));
682 c.features.opcode = nvme_admin_get_features;
683 c.features.nsid = cpu_to_le32(nsid);
21d34711
CH		 684 c.features.fid = cpu_to_le32(fid);
685
d49187e9 686 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res, buffer, buflen, 0,
eb71f435 687 NVME_QID_ANY, 0, 0);
9b47f77a 688 if (ret >= 0 && result)
d49187e9 689 *result = le32_to_cpu(res.u32);
1cb3cce5 690 return ret;
21d34711
CH		 691}
692
1c63dc66 693int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
1a6fe74d 694 void *buffer, size_t buflen, u32 *result)
21d34711
CH		 695{
696 struct nvme_command c;
d49187e9 697 union nvme_result res;
1cb3cce5 698 int ret;
21d34711
CH		 699
700 memset(&c, 0, sizeof(c));
701 c.features.opcode = nvme_admin_set_features;
21d34711
CH		 702 c.features.fid = cpu_to_le32(fid);
703 c.features.dword11 = cpu_to_le32(dword11);
704
d49187e9 705 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
1a6fe74d 706 buffer, buflen, 0, NVME_QID_ANY, 0, 0);
9b47f77a 707 if (ret >= 0 && result)
d49187e9 708 *result = le32_to_cpu(res.u32);
1cb3cce5 709 return ret;
21d34711
CH		 710}
711
1c63dc66 712int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log)
21d34711
CH		 713{
714 struct nvme_command c = { };
715 int error;
716
717 c.common.opcode = nvme_admin_get_log_page,
718 c.common.nsid = cpu_to_le32(0xFFFFFFFF),
719 c.common.cdw10[0] = cpu_to_le32(
720 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
721 NVME_LOG_SMART),
722
723 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
724 if (!*log)
725 return -ENOMEM;
726
727 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
728 sizeof(struct nvme_smart_log));
729 if (error)
730 kfree(*log);
731 return error;
732}
1673f1f0 733
9a0be7ab
CH		 734int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
735{
736 u32 q_count = (*count - 1) | ((*count - 1) << 16);
737 u32 result;
738 int status, nr_io_queues;
739
1a6fe74d 740 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 741 &result);
f5fa90dc 742 if (status < 0)
9a0be7ab
CH		 743 return status;
744
f5fa90dc
CH		 745 /*
746 * Degraded controllers might return an error when setting the queue
747 * count. We still want to be able to bring them online and offer
748 * access to the admin queue, as that might be only way to fix them up.
749 */
750 if (status > 0) {
751 dev_err(ctrl->dev, "Could not set queue count (%d)\n", status);
752 *count = 0;
753 } else {
754 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
755 *count = min(*count, nr_io_queues);
756 }
757
9a0be7ab
CH		 758 return 0;
759}
576d55d6 760EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 761
1673f1f0
CH		 762static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
763{
764 struct nvme_user_io io;
765 struct nvme_command c;
766 unsigned length, meta_len;
767 void __user *metadata;
768
769 if (copy_from_user(&io, uio, sizeof(io)))
770 return -EFAULT;
63088ec7
KB		 771 if (io.flags)
772 return -EINVAL;
1673f1f0
CH		 773
774 switch (io.opcode) {
775 case nvme_cmd_write:
776 case nvme_cmd_read:
777 case nvme_cmd_compare:
778 break;
779 default:
780 return -EINVAL;
781 }
782
783 length = (io.nblocks + 1) << ns->lba_shift;
784 meta_len = (io.nblocks + 1) * ns->ms;
785 metadata = (void __user *)(uintptr_t)io.metadata;
786
787 if (ns->ext) {
788 length += meta_len;
789 meta_len = 0;
790 } else if (meta_len) {
791 if ((io.metadata & 3) || !io.metadata)
792 return -EINVAL;
793 }
794
795 memset(&c, 0, sizeof(c));
796 c.rw.opcode = io.opcode;
797 c.rw.flags = io.flags;
798 c.rw.nsid = cpu_to_le32(ns->ns_id);
799 c.rw.slba = cpu_to_le64(io.slba);
800 c.rw.length = cpu_to_le16(io.nblocks);
801 c.rw.control = cpu_to_le16(io.control);
802 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
803 c.rw.reftag = cpu_to_le32(io.reftag);
804 c.rw.apptag = cpu_to_le16(io.apptag);
805 c.rw.appmask = cpu_to_le16(io.appmask);
806
807 return __nvme_submit_user_cmd(ns->queue, &c,
808 (void __user *)(uintptr_t)io.addr, length,
809 metadata, meta_len, io.slba, NULL, 0);
810}
811
f3ca80fc 812static int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1673f1f0
CH		 813 struct nvme_passthru_cmd __user *ucmd)
814{
815 struct nvme_passthru_cmd cmd;
816 struct nvme_command c;
817 unsigned timeout = 0;
818 int status;
819
820 if (!capable(CAP_SYS_ADMIN))
821 return -EACCES;
822 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
823 return -EFAULT;
63088ec7
KB		 824 if (cmd.flags)
825 return -EINVAL;
1673f1f0
CH		 826
827 memset(&c, 0, sizeof(c));
828 c.common.opcode = cmd.opcode;
829 c.common.flags = cmd.flags;
830 c.common.nsid = cpu_to_le32(cmd.nsid);
831 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
832 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
833 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
834 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
835 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
836 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
837 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
838 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
839
840 if (cmd.timeout_ms)
841 timeout = msecs_to_jiffies(cmd.timeout_ms);
842
843 status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c,
d1ea7be5 844 (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
1673f1f0
CH		 845 &cmd.result, timeout);
846 if (status >= 0) {
847 if (put_user(cmd.result, &ucmd->result))
848 return -EFAULT;
849 }
850
851 return status;
852}
853
854static int nvme_ioctl(struct block_device *bdev, fmode_t mode,
855 unsigned int cmd, unsigned long arg)
856{
857 struct nvme_ns *ns = bdev->bd_disk->private_data;
858
859 switch (cmd) {
860 case NVME_IOCTL_ID:
861 force_successful_syscall_return();
862 return ns->ns_id;
863 case NVME_IOCTL_ADMIN_CMD:
864 return nvme_user_cmd(ns->ctrl, NULL, (void __user *)arg);
865 case NVME_IOCTL_IO_CMD:
866 return nvme_user_cmd(ns->ctrl, ns, (void __user *)arg);
867 case NVME_IOCTL_SUBMIT_IO:
868 return nvme_submit_io(ns, (void __user *)arg);
44907332 869#ifdef CONFIG_BLK_DEV_NVME_SCSI
1673f1f0
CH		 870 case SG_GET_VERSION_NUM:
871 return nvme_sg_get_version_num((void __user *)arg);
872 case SG_IO:
873 return nvme_sg_io(ns, (void __user *)arg);
44907332 874#endif
1673f1f0 875 default:
84d4add7
MB		 876#ifdef CONFIG_NVM
877 if (ns->ndev)
878 return nvme_nvm_ioctl(ns, cmd, arg);
879#endif
a98e58e5 880 if (is_sed_ioctl(cmd))
4f1244c8 881 return sed_ioctl(ns->ctrl->opal_dev, cmd,
e225c20e 882 (void __user *) arg);
1673f1f0
CH		 883 return -ENOTTY;
884 }
885}
886
887#ifdef CONFIG_COMPAT
888static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
889 unsigned int cmd, unsigned long arg)
890{
891 switch (cmd) {
892 case SG_IO:
893 return -ENOIOCTLCMD;
894 }
895 return nvme_ioctl(bdev, mode, cmd, arg);
896}
897#else
898#define nvme_compat_ioctl NULL
899#endif
900
901static int nvme_open(struct block_device *bdev, fmode_t mode)
902{
903 return nvme_get_ns_from_disk(bdev->bd_disk) ? 0 : -ENXIO;
904}
905
906static void nvme_release(struct gendisk *disk, fmode_t mode)
907{
e439bb12
SG		 908 struct nvme_ns *ns = disk->private_data;
909
910 module_put(ns->ctrl->ops->module);
911 nvme_put_ns(ns);
1673f1f0
CH		 912}
913
914static int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
915{
916 /* some standard values */
917 geo->heads = 1 << 6;
918 geo->sectors = 1 << 5;
919 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
920 return 0;
921}
922
923#ifdef CONFIG_BLK_DEV_INTEGRITY
924static void nvme_init_integrity(struct nvme_ns *ns)
925{
926 struct blk_integrity integrity;
927
fa9a89fc 928 memset(&integrity, 0, sizeof(integrity));
1673f1f0
CH		 929 switch (ns->pi_type) {
930 case NVME_NS_DPS_PI_TYPE3:
931 integrity.profile = &t10_pi_type3_crc;
ba36c21b
NB		 932 integrity.tag_size = sizeof(u16) + sizeof(u32);
933 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 934 break;
935 case NVME_NS_DPS_PI_TYPE1:
936 case NVME_NS_DPS_PI_TYPE2:
937 integrity.profile = &t10_pi_type1_crc;
ba36c21b
NB		 938 integrity.tag_size = sizeof(u16);
939 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 940 break;
941 default:
942 integrity.profile = NULL;
943 break;
944 }
945 integrity.tuple_size = ns->ms;
946 blk_integrity_register(ns->disk, &integrity);
947 blk_queue_max_integrity_segments(ns->queue, 1);
948}
949#else
950static void nvme_init_integrity(struct nvme_ns *ns)
951{
952}
953#endif /* CONFIG_BLK_DEV_INTEGRITY */
954
955static void nvme_config_discard(struct nvme_ns *ns)
956{
08095e70 957 struct nvme_ctrl *ctrl = ns->ctrl;
1673f1f0 958 u32 logical_block_size = queue_logical_block_size(ns->queue);
08095e70 959
b35ba01e
CH		 960 BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) <
961 NVME_DSM_MAX_RANGES);
962
1673f1f0
CH		 963 ns->queue->limits.discard_alignment = logical_block_size;
964 ns->queue->limits.discard_granularity = logical_block_size;
bd0fc288 965 blk_queue_max_discard_sectors(ns->queue, UINT_MAX);
b35ba01e 966 blk_queue_max_discard_segments(ns->queue, NVME_DSM_MAX_RANGES);
1673f1f0 967 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
e850fd16
CH		 968
969 if (ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
970 blk_queue_max_write_zeroes_sectors(ns->queue, UINT_MAX);
1673f1f0
CH		 971}
972
ac81bfa9 973static int nvme_revalidate_ns(struct nvme_ns *ns, struct nvme_id_ns **id)
1673f1f0 974{
ac81bfa9 975 if (nvme_identify_ns(ns->ctrl, ns->ns_id, id)) {
b0b4e09c 976 dev_warn(ns->ctrl->dev, "%s: Identify failure\n", __func__);
1673f1f0
CH		 977 return -ENODEV;
978 }
1673f1f0 979
ac81bfa9
MB		 980 if ((*id)->ncap == 0) {
981 kfree(*id);
982 return -ENODEV;
1673f1f0
CH		 983 }
984
8ef2074d 985 if (ns->ctrl->vs >= NVME_VS(1, 1, 0))
ac81bfa9 986 memcpy(ns->eui, (*id)->eui64, sizeof(ns->eui));
8ef2074d 987 if (ns->ctrl->vs >= NVME_VS(1, 2, 0))
ac81bfa9
MB		 988 memcpy(ns->uuid, (*id)->nguid, sizeof(ns->uuid));
989
990 return 0;
991}
992
993static void __nvme_revalidate_disk(struct gendisk *disk, struct nvme_id_ns *id)
994{
995 struct nvme_ns *ns = disk->private_data;
996 u8 lbaf, pi_type;
997 u16 old_ms;
998 unsigned short bs;
2b9b6e86 999
1673f1f0
CH		 1000 old_ms = ns->ms;
1001 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
1002 ns->lba_shift = id->lbaf[lbaf].ds;
1003 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
1004 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
1005
1006 /*
1007 * If identify namespace failed, use default 512 byte block size so
1008 * block layer can use before failing read/write for 0 capacity.
1009 */
1010 if (ns->lba_shift == 0)
1011 ns->lba_shift = 9;
1012 bs = 1 << ns->lba_shift;
1673f1f0
CH		 1013 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
1014 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
1015 id->dps & NVME_NS_DPS_PI_MASK : 0;
1016
1017 blk_mq_freeze_queue(disk->queue);
1018 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
1019 ns->ms != old_ms ||
1020 bs != queue_logical_block_size(disk->queue) ||
1021 (ns->ms && ns->ext)))
1022 blk_integrity_unregister(disk);
1023
1024 ns->pi_type = pi_type;
1025 blk_queue_logical_block_size(ns->queue, bs);
1026
4b9d5b15 1027 if (ns->ms && !blk_get_integrity(disk) && !ns->ext)
1673f1f0 1028 nvme_init_integrity(ns);
1673f1f0
CH		 1029 if (ns->ms && !(ns->ms == 8 && ns->pi_type) && !blk_get_integrity(disk))
1030 set_capacity(disk, 0);
1031 else
1032 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1033
1034 if (ns->ctrl->oncs & NVME_CTRL_ONCS_DSM)
1035 nvme_config_discard(ns);
1036 blk_mq_unfreeze_queue(disk->queue);
ac81bfa9 1037}
1673f1f0 1038
ac81bfa9
MB		 1039static int nvme_revalidate_disk(struct gendisk *disk)
1040{
1041 struct nvme_ns *ns = disk->private_data;
1042 struct nvme_id_ns *id = NULL;
1043 int ret;
1044
1045 if (test_bit(NVME_NS_DEAD, &ns->flags)) {
1046 set_capacity(disk, 0);
1047 return -ENODEV;
1048 }
1049
1050 ret = nvme_revalidate_ns(ns, &id);
1051 if (ret)
1052 return ret;
1053
1054 __nvme_revalidate_disk(disk, id);
1673f1f0 1055 kfree(id);
ac81bfa9 1056
1673f1f0
CH		 1057 return 0;
1058}
1059
1060static char nvme_pr_type(enum pr_type type)
1061{
1062 switch (type) {
1063 case PR_WRITE_EXCLUSIVE:
1064 return 1;
1065 case PR_EXCLUSIVE_ACCESS:
1066 return 2;
1067 case PR_WRITE_EXCLUSIVE_REG_ONLY:
1068 return 3;
1069 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
1070 return 4;
1071 case PR_WRITE_EXCLUSIVE_ALL_REGS:
1072 return 5;
1073 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
1074 return 6;
1075 default:
1076 return 0;
1077 }
1078};
1079
1080static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
1081 u64 key, u64 sa_key, u8 op)
1082{
1083 struct nvme_ns *ns = bdev->bd_disk->private_data;
1084 struct nvme_command c;
1085 u8 data[16] = { 0, };
1086
1087 put_unaligned_le64(key, &data[0]);
1088 put_unaligned_le64(sa_key, &data[8]);
1089
1090 memset(&c, 0, sizeof(c));
1091 c.common.opcode = op;
1092 c.common.nsid = cpu_to_le32(ns->ns_id);
1093 c.common.cdw10[0] = cpu_to_le32(cdw10);
1094
1095 return nvme_submit_sync_cmd(ns->queue, &c, data, 16);
1096}
1097
1098static int nvme_pr_register(struct block_device *bdev, u64 old,
1099 u64 new, unsigned flags)
1100{
1101 u32 cdw10;
1102
1103 if (flags & ~PR_FL_IGNORE_KEY)
1104 return -EOPNOTSUPP;
1105
1106 cdw10 = old ? 2 : 0;
1107 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
1108 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
1109 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
1110}
1111
1112static int nvme_pr_reserve(struct block_device *bdev, u64 key,
1113 enum pr_type type, unsigned flags)
1114{
1115 u32 cdw10;
1116
1117 if (flags & ~PR_FL_IGNORE_KEY)
1118 return -EOPNOTSUPP;
1119
1120 cdw10 = nvme_pr_type(type) << 8;
1121 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
1122 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
1123}
1124
1125static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
1126 enum pr_type type, bool abort)
1127{
1128 u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
1129 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
1130}
1131
1132static int nvme_pr_clear(struct block_device *bdev, u64 key)
1133{
8c0b3915 1134 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
1673f1f0
CH		 1135 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
1136}
1137
1138static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
1139{
1140 u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
1141 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
1142}
1143
1144static const struct pr_ops nvme_pr_ops = {
1145 .pr_register = nvme_pr_register,
1146 .pr_reserve = nvme_pr_reserve,
1147 .pr_release = nvme_pr_release,
1148 .pr_preempt = nvme_pr_preempt,
1149 .pr_clear = nvme_pr_clear,
1150};
1151
a98e58e5 1152#ifdef CONFIG_BLK_SED_OPAL
4f1244c8
CH		 1153int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
1154 bool send)
a98e58e5 1155{
4f1244c8 1156 struct nvme_ctrl *ctrl = data;
a98e58e5 1157 struct nvme_command cmd;
a98e58e5
SB		 1158
1159 memset(&cmd, 0, sizeof(cmd));
1160 if (send)
1161 cmd.common.opcode = nvme_admin_security_send;
1162 else
1163 cmd.common.opcode = nvme_admin_security_recv;
a98e58e5
SB		 1164 cmd.common.nsid = 0;
1165 cmd.common.cdw10[0] = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
1166 cmd.common.cdw10[1] = cpu_to_le32(len);
1167
1168 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len,
1169 ADMIN_TIMEOUT, NVME_QID_ANY, 1, 0);
1170}
1171EXPORT_SYMBOL_GPL(nvme_sec_submit);
1172#endif /* CONFIG_BLK_SED_OPAL */
1173
5bae7f73 1174static const struct block_device_operations nvme_fops = {
1673f1f0
CH		 1175 .owner = THIS_MODULE,
1176 .ioctl = nvme_ioctl,
1177 .compat_ioctl = nvme_compat_ioctl,
1178 .open = nvme_open,
1179 .release = nvme_release,
1180 .getgeo = nvme_getgeo,
1181 .revalidate_disk= nvme_revalidate_disk,
1182 .pr_ops = &nvme_pr_ops,
1183};
1184
5fd4ce1b
CH		 1185static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
1186{
1187 unsigned long timeout =
1188 ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1189 u32 csts, bit = enabled ? NVME_CSTS_RDY : 0;
1190 int ret;
1191
1192 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB		 1193 if (csts == ~0)
1194 return -ENODEV;
5fd4ce1b
CH		 1195 if ((csts & NVME_CSTS_RDY) == bit)
1196 break;
1197
1198 msleep(100);
1199 if (fatal_signal_pending(current))
1200 return -EINTR;
1201 if (time_after(jiffies, timeout)) {
1b3c47c1 1202 dev_err(ctrl->device,
5fd4ce1b
CH		 1203 "Device not ready; aborting %s\n", enabled ?
1204 "initialisation" : "reset");
1205 return -ENODEV;
1206 }
1207 }
1208
1209 return ret;
1210}
1211
1212/*
1213 * If the device has been passed off to us in an enabled state, just clear
1214 * the enabled bit. The spec says we should set the 'shutdown notification
1215 * bits', but doing so may cause the device to complete commands to the
1216 * admin queue ... and we don't know what memory that might be pointing at!
1217 */
1218int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1219{
1220 int ret;
1221
1222 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1223 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
1224
1225 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1226 if (ret)
1227 return ret;
54adc010 1228
b5a10c5f 1229 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010
GP		 1230 msleep(NVME_QUIRK_DELAY_AMOUNT);
1231
5fd4ce1b
CH		 1232 return nvme_wait_ready(ctrl, cap, false);
1233}
576d55d6 1234EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b
CH		 1235
1236int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1237{
1238 /*
1239 * Default to a 4K page size, with the intention to update this
1240 * path in the future to accomodate architectures with differing
1241 * kernel and IO page sizes.
1242 */
1243 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12, page_shift = 12;
1244 int ret;
1245
1246 if (page_shift < dev_page_min) {
1b3c47c1 1247 dev_err(ctrl->device,
5fd4ce1b
CH		 1248 "Minimum device page size %u too large for host (%u)\n",
1249 1 << dev_page_min, 1 << page_shift);
1250 return -ENODEV;
1251 }
1252
1253 ctrl->page_size = 1 << page_shift;
1254
1255 ctrl->ctrl_config = NVME_CC_CSS_NVM;
1256 ctrl->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1257 ctrl->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1258 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1259 ctrl->ctrl_config |= NVME_CC_ENABLE;
1260
1261 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1262 if (ret)
1263 return ret;
1264 return nvme_wait_ready(ctrl, cap, true);
1265}
576d55d6 1266EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b
CH		 1267
1268int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl)
1269{
1270 unsigned long timeout = SHUTDOWN_TIMEOUT + jiffies;
1271 u32 csts;
1272 int ret;
1273
1274 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1275 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
1276
1277 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1278 if (ret)
1279 return ret;
1280
1281 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
1282 if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_CMPLT)
1283 break;
1284
1285 msleep(100);
1286 if (fatal_signal_pending(current))
1287 return -EINTR;
1288 if (time_after(jiffies, timeout)) {
1b3c47c1 1289 dev_err(ctrl->device,
5fd4ce1b
CH		 1290 "Device shutdown incomplete; abort shutdown\n");
1291 return -ENODEV;
1292 }
1293 }
1294
1295 return ret;
1296}
576d55d6 1297EXPORT_SYMBOL_GPL(nvme_shutdown_ctrl);
5fd4ce1b 1298
da35825d
CH		 1299static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
1300 struct request_queue *q)
1301{
7c88cb00
JA		 1302 bool vwc = false;
1303
da35825d 1304 if (ctrl->max_hw_sectors) {
45686b61
CH		 1305 u32 max_segments =
1306 (ctrl->max_hw_sectors / (ctrl->page_size >> 9)) + 1;
1307
da35825d 1308 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
45686b61 1309 blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
da35825d 1310 }
e6282aef
KB		 1311 if (ctrl->quirks & NVME_QUIRK_STRIPE_SIZE)
1312 blk_queue_chunk_sectors(q, ctrl->max_hw_sectors);
da35825d 1313 blk_queue_virt_boundary(q, ctrl->page_size - 1);
7c88cb00
JA		 1314 if (ctrl->vwc & NVME_CTRL_VWC_PRESENT)
1315 vwc = true;
1316 blk_queue_write_cache(q, vwc, vwc);
da35825d
CH		 1317}
1318
c5552fde
AL		 1319static void nvme_configure_apst(struct nvme_ctrl *ctrl)
1320{
1321 /*
1322 * APST (Autonomous Power State Transition) lets us program a
1323 * table of power state transitions that the controller will
1324 * perform automatically. We configure it with a simple
1325 * heuristic: we are willing to spend at most 2% of the time
1326 * transitioning between power states. Therefore, when running
1327 * in any given state, we will enter the next lower-power
76e4ad09 1328 * non-operational state after waiting 50 * (enlat + exlat)
c5552fde
AL		 1329 * microseconds, as long as that state's total latency is under
1330 * the requested maximum latency.
1331 *
1332 * We will not autonomously enter any non-operational state for
1333 * which the total latency exceeds ps_max_latency_us. Users
1334 * can set ps_max_latency_us to zero to turn off APST.
1335 */
1336
1337 unsigned apste;
1338 struct nvme_feat_auto_pst *table;
1339 int ret;
1340
1341 /*
1342 * If APST isn't supported or if we haven't been initialized yet,
1343 * then don't do anything.
1344 */
1345 if (!ctrl->apsta)
1346 return;
1347
1348 if (ctrl->npss > 31) {
1349 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
1350 return;
1351 }
1352
1353 table = kzalloc(sizeof(*table), GFP_KERNEL);
1354 if (!table)
1355 return;
1356
1357 if (ctrl->ps_max_latency_us == 0) {
1358 /* Turn off APST. */
1359 apste = 0;
1360 } else {
1361 __le64 target = cpu_to_le64(0);
1362 int state;
1363
1364 /*
1365 * Walk through all states from lowest- to highest-power.
1366 * According to the spec, lower-numbered states use more
1367 * power. NPSS, despite the name, is the index of the
1368 * lowest-power state, not the number of states.
1369 */
1370 for (state = (int)ctrl->npss; state >= 0; state--) {
1371 u64 total_latency_us, transition_ms;
1372
1373 if (target)
1374 table->entries[state] = target;
1375
ff5350a8
AL		 1376 /*
1377 * Don't allow transitions to the deepest state
1378 * if it's quirked off.
1379 */
1380 if (state == ctrl->npss &&
1381 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
1382 continue;
1383
c5552fde
AL		 1384 /*
1385 * Is this state a useful non-operational state for
1386 * higher-power states to autonomously transition to?
1387 */
1388 if (!(ctrl->psd[state].flags &
1389 NVME_PS_FLAGS_NON_OP_STATE))
1390 continue;
1391
1392 total_latency_us =
1393 (u64)le32_to_cpu(ctrl->psd[state].entry_lat) +
1394 + le32_to_cpu(ctrl->psd[state].exit_lat);
1395 if (total_latency_us > ctrl->ps_max_latency_us)
1396 continue;
1397
1398 /*
1399 * This state is good. Use it as the APST idle
1400 * target for higher power states.
1401 */
1402 transition_ms = total_latency_us + 19;
1403 do_div(transition_ms, 20);
1404 if (transition_ms > (1 << 24) - 1)
1405 transition_ms = (1 << 24) - 1;
1406
1407 target = cpu_to_le64((state << 3) |
1408 (transition_ms << 8));
1409 }
1410
1411 apste = 1;
1412 }
1413
1414 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
1415 table, sizeof(*table), NULL);
1416 if (ret)
1417 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
1418
1419 kfree(table);
1420}
1421
1422static void nvme_set_latency_tolerance(struct device *dev, s32 val)
1423{
1424 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1425 u64 latency;
1426
1427 switch (val) {
1428 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
1429 case PM_QOS_LATENCY_ANY:
1430 latency = U64_MAX;
1431 break;
1432
1433 default:
1434 latency = val;
1435 }
1436
1437 if (ctrl->ps_max_latency_us != latency) {
1438 ctrl->ps_max_latency_us = latency;
1439 nvme_configure_apst(ctrl);
1440 }
1441}
1442
bd4da3ab
AL		 1443struct nvme_core_quirk_entry {
1444 /*
1445 * NVMe model and firmware strings are padded with spaces. For
1446 * simplicity, strings in the quirk table are padded with NULLs
1447 * instead.
1448 */
1449 u16 vid;
1450 const char *mn;
1451 const char *fr;
1452 unsigned long quirks;
1453};
1454
1455static const struct nvme_core_quirk_entry core_quirks[] = {
c5552fde 1456 {
be56945c
AL		 1457 /*
1458 * This Toshiba device seems to die using any APST states. See:
1459 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
1460 */
1461 .vid = 0x1179,
1462 .mn = "THNSF5256GPUK TOSHIBA",
c5552fde 1463 .quirks = NVME_QUIRK_NO_APST,
be56945c 1464 }
bd4da3ab
AL		 1465};
1466
1467/* match is null-terminated but idstr is space-padded. */
1468static bool string_matches(const char *idstr, const char *match, size_t len)
1469{
1470 size_t matchlen;
1471
1472 if (!match)
1473 return true;
1474
1475 matchlen = strlen(match);
1476 WARN_ON_ONCE(matchlen > len);
1477
1478 if (memcmp(idstr, match, matchlen))
1479 return false;
1480
1481 for (; matchlen < len; matchlen++)
1482 if (idstr[matchlen] != ' ')
1483 return false;
1484
1485 return true;
1486}
1487
1488static bool quirk_matches(const struct nvme_id_ctrl *id,
1489 const struct nvme_core_quirk_entry *q)
1490{
1491 return q->vid == le16_to_cpu(id->vid) &&
1492 string_matches(id->mn, q->mn, sizeof(id->mn)) &&
1493 string_matches(id->fr, q->fr, sizeof(id->fr));
1494}
1495
7fd8930f
CH		 1496/*
1497 * Initialize the cached copies of the Identify data and various controller
1498 * register in our nvme_ctrl structure. This should be called as soon as
1499 * the admin queue is fully up and running.
1500 */
1501int nvme_init_identify(struct nvme_ctrl *ctrl)
1502{
1503 struct nvme_id_ctrl *id;
1504 u64 cap;
1505 int ret, page_shift;
a229dbf6 1506 u32 max_hw_sectors;
c5552fde 1507 u8 prev_apsta;
7fd8930f 1508
f3ca80fc
CH		 1509 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
1510 if (ret) {
1b3c47c1 1511 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
f3ca80fc
CH		 1512 return ret;
1513 }
1514
7fd8930f
CH		 1515 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &cap);
1516 if (ret) {
1b3c47c1 1517 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
7fd8930f
CH		 1518 return ret;
1519 }
1520 page_shift = NVME_CAP_MPSMIN(cap) + 12;
1521
8ef2074d 1522 if (ctrl->vs >= NVME_VS(1, 1, 0))
f3ca80fc
CH		 1523 ctrl->subsystem = NVME_CAP_NSSRC(cap);
1524
7fd8930f
CH		 1525 ret = nvme_identify_ctrl(ctrl, &id);
1526 if (ret) {
1b3c47c1 1527 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH		 1528 return -EIO;
1529 }
1530
bd4da3ab
AL		 1531 if (!ctrl->identified) {
1532 /*
1533 * Check for quirks. Quirk can depend on firmware version,
1534 * so, in principle, the set of quirks present can change
1535 * across a reset. As a possible future enhancement, we
1536 * could re-scan for quirks every time we reinitialize
1537 * the device, but we'd have to make sure that the driver
1538 * behaves intelligently if the quirks change.
1539 */
1540
1541 int i;
1542
1543 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
1544 if (quirk_matches(id, &core_quirks[i]))
1545 ctrl->quirks |= core_quirks[i].quirks;
1546 }
1547 }
1548
8a9ae523 1549 ctrl->oacs = le16_to_cpu(id->oacs);
118472ab 1550 ctrl->vid = le16_to_cpu(id->vid);
7fd8930f 1551 ctrl->oncs = le16_to_cpup(&id->oncs);
6bf25d16 1552 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 1553 ctrl->vwc = id->vwc;
931e1c22 1554 ctrl->cntlid = le16_to_cpup(&id->cntlid);
7fd8930f
CH		 1555 memcpy(ctrl->serial, id->sn, sizeof(id->sn));
1556 memcpy(ctrl->model, id->mn, sizeof(id->mn));
1557 memcpy(ctrl->firmware_rev, id->fr, sizeof(id->fr));
1558 if (id->mdts)
a229dbf6 1559 max_hw_sectors = 1 << (id->mdts + page_shift - 9);
7fd8930f 1560 else
a229dbf6
CH		 1561 max_hw_sectors = UINT_MAX;
1562 ctrl->max_hw_sectors =
1563 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 1564
da35825d 1565 nvme_set_queue_limits(ctrl, ctrl->admin_q);
07bfcd09 1566 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 1567 ctrl->kas = le16_to_cpu(id->kas);
07bfcd09 1568
c5552fde
AL		 1569 ctrl->npss = id->npss;
1570 prev_apsta = ctrl->apsta;
1571 ctrl->apsta = (ctrl->quirks & NVME_QUIRK_NO_APST) ? 0 : id->apsta;
1572 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
1573
07bfcd09
CH		 1574 if (ctrl->ops->is_fabrics) {
1575 ctrl->icdoff = le16_to_cpu(id->icdoff);
1576 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
1577 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
1578 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
1579
1580 /*
1581 * In fabrics we need to verify the cntlid matches the
1582 * admin connect
1583 */
1584 if (ctrl->cntlid != le16_to_cpu(id->cntlid))
1585 ret = -EINVAL;
038bd4cb
SG		 1586
1587 if (!ctrl->opts->discovery_nqn && !ctrl->kas) {
1588 dev_err(ctrl->dev,
1589 "keep-alive support is mandatory for fabrics\n");
1590 ret = -EINVAL;
1591 }
07bfcd09
CH		 1592 } else {
1593 ctrl->cntlid = le16_to_cpu(id->cntlid);
1594 }
da35825d 1595
7fd8930f 1596 kfree(id);
bd4da3ab 1597
c5552fde
AL		 1598 if (ctrl->apsta && !prev_apsta)
1599 dev_pm_qos_expose_latency_tolerance(ctrl->device);
1600 else if (!ctrl->apsta && prev_apsta)
1601 dev_pm_qos_hide_latency_tolerance(ctrl->device);
1602
1603 nvme_configure_apst(ctrl);
1604
bd4da3ab 1605 ctrl->identified = true;
c5552fde 1606
07bfcd09 1607 return ret;
7fd8930f 1608}
576d55d6 1609EXPORT_SYMBOL_GPL(nvme_init_identify);
7fd8930f 1610
f3ca80fc 1611static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 1612{
f3ca80fc
CH		 1613 struct nvme_ctrl *ctrl;
1614 int instance = iminor(inode);
1615 int ret = -ENODEV;
1673f1f0 1616
f3ca80fc
CH		 1617 spin_lock(&dev_list_lock);
1618 list_for_each_entry(ctrl, &nvme_ctrl_list, node) {
1619 if (ctrl->instance != instance)
1620 continue;
1621
1622 if (!ctrl->admin_q) {
1623 ret = -EWOULDBLOCK;
1624 break;
1625 }
1626 if (!kref_get_unless_zero(&ctrl->kref))
1627 break;
1628 file->private_data = ctrl;
1629 ret = 0;
1630 break;
1631 }
1632 spin_unlock(&dev_list_lock);
1633
1634 return ret;
1673f1f0
CH		 1635}
1636
f3ca80fc 1637static int nvme_dev_release(struct inode *inode, struct file *file)
1673f1f0 1638{
f3ca80fc
CH		 1639 nvme_put_ctrl(file->private_data);
1640 return 0;
1641}
1642
bfd89471
CH		 1643static int nvme_dev_user_cmd(struct nvme_ctrl *ctrl, void __user *argp)
1644{
1645 struct nvme_ns *ns;
1646 int ret;
1647
1648 mutex_lock(&ctrl->namespaces_mutex);
1649 if (list_empty(&ctrl->namespaces)) {
1650 ret = -ENOTTY;
1651 goto out_unlock;
1652 }
1653
1654 ns = list_first_entry(&ctrl->namespaces, struct nvme_ns, list);
1655 if (ns != list_last_entry(&ctrl->namespaces, struct nvme_ns, list)) {
1b3c47c1 1656 dev_warn(ctrl->device,
bfd89471
CH		 1657 "NVME_IOCTL_IO_CMD not supported when multiple namespaces present!\n");
1658 ret = -EINVAL;
1659 goto out_unlock;
1660 }
1661
1b3c47c1 1662 dev_warn(ctrl->device,
bfd89471
CH		 1663 "using deprecated NVME_IOCTL_IO_CMD ioctl on the char device!\n");
1664 kref_get(&ns->kref);
1665 mutex_unlock(&ctrl->namespaces_mutex);
1666
1667 ret = nvme_user_cmd(ctrl, ns, argp);
1668 nvme_put_ns(ns);
1669 return ret;
1670
1671out_unlock:
1672 mutex_unlock(&ctrl->namespaces_mutex);
1673 return ret;
1674}
1675
f3ca80fc
CH		 1676static long nvme_dev_ioctl(struct file *file, unsigned int cmd,
1677 unsigned long arg)
1678{
1679 struct nvme_ctrl *ctrl = file->private_data;
1680 void __user *argp = (void __user *)arg;
f3ca80fc
CH		 1681
1682 switch (cmd) {
1683 case NVME_IOCTL_ADMIN_CMD:
1684 return nvme_user_cmd(ctrl, NULL, argp);
1685 case NVME_IOCTL_IO_CMD:
bfd89471 1686 return nvme_dev_user_cmd(ctrl, argp);
f3ca80fc 1687 case NVME_IOCTL_RESET:
1b3c47c1 1688 dev_warn(ctrl->device, "resetting controller\n");
f3ca80fc
CH		 1689 return ctrl->ops->reset_ctrl(ctrl);
1690 case NVME_IOCTL_SUBSYS_RESET:
1691 return nvme_reset_subsystem(ctrl);
9ec3bb2f
KB		 1692 case NVME_IOCTL_RESCAN:
1693 nvme_queue_scan(ctrl);
1694 return 0;
f3ca80fc
CH		 1695 default:
1696 return -ENOTTY;
1697 }
1698}
1699
1700static const struct file_operations nvme_dev_fops = {
1701 .owner = THIS_MODULE,
1702 .open = nvme_dev_open,
1703 .release = nvme_dev_release,
1704 .unlocked_ioctl = nvme_dev_ioctl,
1705 .compat_ioctl = nvme_dev_ioctl,
1706};
1707
1708static ssize_t nvme_sysfs_reset(struct device *dev,
1709 struct device_attribute *attr, const char *buf,
1710 size_t count)
1711{
1712 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1713 int ret;
1714
1715 ret = ctrl->ops->reset_ctrl(ctrl);
1716 if (ret < 0)
1717 return ret;
1718 return count;
1673f1f0 1719}
f3ca80fc 1720static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
1673f1f0 1721
9ec3bb2f
KB		 1722static ssize_t nvme_sysfs_rescan(struct device *dev,
1723 struct device_attribute *attr, const char *buf,
1724 size_t count)
1725{
1726 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1727
1728 nvme_queue_scan(ctrl);
1729 return count;
1730}
1731static DEVICE_ATTR(rescan_controller, S_IWUSR, NULL, nvme_sysfs_rescan);
1732
118472ab
KB		 1733static ssize_t wwid_show(struct device *dev, struct device_attribute *attr,
1734 char *buf)
1735{
40267efd 1736 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
118472ab
KB		 1737 struct nvme_ctrl *ctrl = ns->ctrl;
1738 int serial_len = sizeof(ctrl->serial);
1739 int model_len = sizeof(ctrl->model);
1740
1741 if (memchr_inv(ns->uuid, 0, sizeof(ns->uuid)))
1742 return sprintf(buf, "eui.%16phN\n", ns->uuid);
1743
1744 if (memchr_inv(ns->eui, 0, sizeof(ns->eui)))
1745 return sprintf(buf, "eui.%8phN\n", ns->eui);
1746
1747 while (ctrl->serial[serial_len - 1] == ' ')
1748 serial_len--;
1749 while (ctrl->model[model_len - 1] == ' ')
1750 model_len--;
1751
1752 return sprintf(buf, "nvme.%04x-%*phN-%*phN-%08x\n", ctrl->vid,
1753 serial_len, ctrl->serial, model_len, ctrl->model, ns->ns_id);
1754}
1755static DEVICE_ATTR(wwid, S_IRUGO, wwid_show, NULL);
1756
2b9b6e86
KB		 1757static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,
1758 char *buf)
1759{
40267efd 1760 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 1761 return sprintf(buf, "%pU\n", ns->uuid);
1762}
1763static DEVICE_ATTR(uuid, S_IRUGO, uuid_show, NULL);
1764
1765static ssize_t eui_show(struct device *dev, struct device_attribute *attr,
1766 char *buf)
1767{
40267efd 1768 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 1769 return sprintf(buf, "%8phd\n", ns->eui);
1770}
1771static DEVICE_ATTR(eui, S_IRUGO, eui_show, NULL);
1772
1773static ssize_t nsid_show(struct device *dev, struct device_attribute *attr,
1774 char *buf)
1775{
40267efd 1776 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 1777 return sprintf(buf, "%d\n", ns->ns_id);
1778}
1779static DEVICE_ATTR(nsid, S_IRUGO, nsid_show, NULL);
1780
1781static struct attribute *nvme_ns_attrs[] = {
118472ab 1782 &dev_attr_wwid.attr,
2b9b6e86
KB		 1783 &dev_attr_uuid.attr,
1784 &dev_attr_eui.attr,
1785 &dev_attr_nsid.attr,
1786 NULL,
1787};
1788
1a353d85 1789static umode_t nvme_ns_attrs_are_visible(struct kobject *kobj,
2b9b6e86
KB		 1790 struct attribute *a, int n)
1791{
1792 struct device *dev = container_of(kobj, struct device, kobj);
40267efd 1793 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 1794
1795 if (a == &dev_attr_uuid.attr) {
1796 if (!memchr_inv(ns->uuid, 0, sizeof(ns->uuid)))
1797 return 0;
1798 }
1799 if (a == &dev_attr_eui.attr) {
1800 if (!memchr_inv(ns->eui, 0, sizeof(ns->eui)))
1801 return 0;
1802 }
1803 return a->mode;
1804}
1805
1806static const struct attribute_group nvme_ns_attr_group = {
1807 .attrs = nvme_ns_attrs,
1a353d85 1808 .is_visible = nvme_ns_attrs_are_visible,
2b9b6e86
KB		 1809};
1810
931e1c22 1811#define nvme_show_str_function(field) \
779ff756
KB		 1812static ssize_t field##_show(struct device *dev, \
1813 struct device_attribute *attr, char *buf) \
1814{ \
1815 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
1816 return sprintf(buf, "%.*s\n", (int)sizeof(ctrl->field), ctrl->field); \
1817} \
1818static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
1819
931e1c22
ML		 1820#define nvme_show_int_function(field) \
1821static ssize_t field##_show(struct device *dev, \
1822 struct device_attribute *attr, char *buf) \
1823{ \
1824 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
1825 return sprintf(buf, "%d\n", ctrl->field); \
1826} \
1827static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
1828
1829nvme_show_str_function(model);
1830nvme_show_str_function(serial);
1831nvme_show_str_function(firmware_rev);
1832nvme_show_int_function(cntlid);
779ff756 1833
1a353d85
ML		 1834static ssize_t nvme_sysfs_delete(struct device *dev,
1835 struct device_attribute *attr, const char *buf,
1836 size_t count)
1837{
1838 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1839
1840 if (device_remove_file_self(dev, attr))
1841 ctrl->ops->delete_ctrl(ctrl);
1842 return count;
1843}
1844static DEVICE_ATTR(delete_controller, S_IWUSR, NULL, nvme_sysfs_delete);
1845
1846static ssize_t nvme_sysfs_show_transport(struct device *dev,
1847 struct device_attribute *attr,
1848 char *buf)
1849{
1850 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1851
1852 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->ops->name);
1853}
1854static DEVICE_ATTR(transport, S_IRUGO, nvme_sysfs_show_transport, NULL);
1855
8432bdb2
SG		 1856static ssize_t nvme_sysfs_show_state(struct device *dev,
1857 struct device_attribute *attr,
1858 char *buf)
1859{
1860 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1861 static const char *const state_name[] = {
1862 [NVME_CTRL_NEW] = "new",
1863 [NVME_CTRL_LIVE] = "live",
1864 [NVME_CTRL_RESETTING] = "resetting",
1865 [NVME_CTRL_RECONNECTING]= "reconnecting",
1866 [NVME_CTRL_DELETING] = "deleting",
1867 [NVME_CTRL_DEAD] = "dead",
1868 };
1869
1870 if ((unsigned)ctrl->state < ARRAY_SIZE(state_name) &&
1871 state_name[ctrl->state])
1872 return sprintf(buf, "%s\n", state_name[ctrl->state]);
1873
1874 return sprintf(buf, "unknown state\n");
1875}
1876
1877static DEVICE_ATTR(state, S_IRUGO, nvme_sysfs_show_state, NULL);
1878
1a353d85
ML		 1879static ssize_t nvme_sysfs_show_subsysnqn(struct device *dev,
1880 struct device_attribute *attr,
1881 char *buf)
1882{
1883 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1884
1885 return snprintf(buf, PAGE_SIZE, "%s\n",
1886 ctrl->ops->get_subsysnqn(ctrl));
1887}
1888static DEVICE_ATTR(subsysnqn, S_IRUGO, nvme_sysfs_show_subsysnqn, NULL);
1889
1890static ssize_t nvme_sysfs_show_address(struct device *dev,
1891 struct device_attribute *attr,
1892 char *buf)
1893{
1894 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1895
1896 return ctrl->ops->get_address(ctrl, buf, PAGE_SIZE);
1897}
1898static DEVICE_ATTR(address, S_IRUGO, nvme_sysfs_show_address, NULL);
1899
779ff756
KB		 1900static struct attribute *nvme_dev_attrs[] = {
1901 &dev_attr_reset_controller.attr,
9ec3bb2f 1902 &dev_attr_rescan_controller.attr,
779ff756
KB		 1903 &dev_attr_model.attr,
1904 &dev_attr_serial.attr,
1905 &dev_attr_firmware_rev.attr,
931e1c22 1906 &dev_attr_cntlid.attr,
1a353d85
ML		 1907 &dev_attr_delete_controller.attr,
1908 &dev_attr_transport.attr,
1909 &dev_attr_subsysnqn.attr,
1910 &dev_attr_address.attr,
8432bdb2 1911 &dev_attr_state.attr,
779ff756
KB		 1912 NULL
1913};
1914
1a353d85
ML		 1915#define CHECK_ATTR(ctrl, a, name) \
1916 if ((a) == &dev_attr_##name.attr && \
1917 !(ctrl)->ops->get_##name) \
1918 return 0
1919
1920static umode_t nvme_dev_attrs_are_visible(struct kobject *kobj,
1921 struct attribute *a, int n)
1922{
1923 struct device *dev = container_of(kobj, struct device, kobj);
1924 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1925
1926 if (a == &dev_attr_delete_controller.attr) {
1927 if (!ctrl->ops->delete_ctrl)
1928 return 0;
1929 }
1930
1931 CHECK_ATTR(ctrl, a, subsysnqn);
1932 CHECK_ATTR(ctrl, a, address);
1933
1934 return a->mode;
1935}
1936
779ff756 1937static struct attribute_group nvme_dev_attrs_group = {
1a353d85
ML		 1938 .attrs = nvme_dev_attrs,
1939 .is_visible = nvme_dev_attrs_are_visible,
779ff756
KB		 1940};
1941
1942static const struct attribute_group *nvme_dev_attr_groups[] = {
1943 &nvme_dev_attrs_group,
1944 NULL,
1945};
1946
5bae7f73
CH		 1947static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
1948{
1949 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
1950 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
1951
1952 return nsa->ns_id - nsb->ns_id;
1953}
1954
32f0c4af 1955static struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 1956{
32f0c4af 1957 struct nvme_ns *ns, *ret = NULL;
69d3b8ac 1958
32f0c4af 1959 mutex_lock(&ctrl->namespaces_mutex);
5bae7f73 1960 list_for_each_entry(ns, &ctrl->namespaces, list) {
32f0c4af
KB		 1961 if (ns->ns_id == nsid) {
1962 kref_get(&ns->kref);
1963 ret = ns;
1964 break;
1965 }
5bae7f73
CH		 1966 if (ns->ns_id > nsid)
1967 break;
1968 }
32f0c4af
KB		 1969 mutex_unlock(&ctrl->namespaces_mutex);
1970 return ret;
5bae7f73
CH		 1971}
1972
1973static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
1974{
1975 struct nvme_ns *ns;
1976 struct gendisk *disk;
ac81bfa9
MB		 1977 struct nvme_id_ns *id;
1978 char disk_name[DISK_NAME_LEN];
5bae7f73
CH		 1979 int node = dev_to_node(ctrl->dev);
1980
1981 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
1982 if (!ns)
1983 return;
1984
075790eb
KB		 1985 ns->instance = ida_simple_get(&ctrl->ns_ida, 1, 0, GFP_KERNEL);
1986 if (ns->instance < 0)
1987 goto out_free_ns;
1988
5bae7f73
CH		 1989 ns->queue = blk_mq_init_queue(ctrl->tagset);
1990 if (IS_ERR(ns->queue))
075790eb 1991 goto out_release_instance;
5bae7f73
CH		 1992 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
1993 ns->queue->queuedata = ns;
1994 ns->ctrl = ctrl;
1995
5bae7f73
CH		 1996 kref_init(&ns->kref);
1997 ns->ns_id = nsid;
5bae7f73 1998 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
5bae7f73
CH		 1999
2000 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
da35825d 2001 nvme_set_queue_limits(ctrl, ns->queue);
5bae7f73 2002
ac81bfa9 2003 sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->instance);
5bae7f73 2004
ac81bfa9
MB		 2005 if (nvme_revalidate_ns(ns, &id))
2006 goto out_free_queue;
2007
3dc87dd0
MB		 2008 if (nvme_nvm_ns_supported(ns, id) &&
2009 nvme_nvm_register(ns, disk_name, node)) {
2010 dev_warn(ctrl->dev, "%s: LightNVM init failure\n", __func__);
2011 goto out_free_id;
2012 }
ac81bfa9 2013
3dc87dd0
MB		 2014 disk = alloc_disk_node(0, node);
2015 if (!disk)
2016 goto out_free_id;
ac81bfa9 2017
3dc87dd0
MB		 2018 disk->fops = &nvme_fops;
2019 disk->private_data = ns;
2020 disk->queue = ns->queue;
2021 disk->flags = GENHD_FL_EXT_DEVT;
2022 memcpy(disk->disk_name, disk_name, DISK_NAME_LEN);
2023 ns->disk = disk;
2024
2025 __nvme_revalidate_disk(disk, id);
5bae7f73 2026
32f0c4af
KB		 2027 mutex_lock(&ctrl->namespaces_mutex);
2028 list_add_tail(&ns->list, &ctrl->namespaces);
2029 mutex_unlock(&ctrl->namespaces_mutex);
2030
5bae7f73 2031 kref_get(&ctrl->kref);
ac81bfa9
MB		 2032
2033 kfree(id);
2034
0d52c756 2035 device_add_disk(ctrl->device, ns->disk);
2b9b6e86
KB		 2036 if (sysfs_create_group(&disk_to_dev(ns->disk)->kobj,
2037 &nvme_ns_attr_group))
2038 pr_warn("%s: failed to create sysfs group for identification\n",
2039 ns->disk->disk_name);
3dc87dd0
MB		 2040 if (ns->ndev && nvme_nvm_register_sysfs(ns))
2041 pr_warn("%s: failed to register lightnvm sysfs group for identification\n",
2042 ns->disk->disk_name);
5bae7f73 2043 return;
ac81bfa9
MB		 2044 out_free_id:
2045 kfree(id);
5bae7f73
CH		 2046 out_free_queue:
2047 blk_cleanup_queue(ns->queue);
075790eb
KB		 2048 out_release_instance:
2049 ida_simple_remove(&ctrl->ns_ida, ns->instance);
5bae7f73
CH		 2050 out_free_ns:
2051 kfree(ns);
2052}
2053
2054static void nvme_ns_remove(struct nvme_ns *ns)
2055{
646017a6
KB		 2056 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
2057 return;
69d3b8ac 2058
b0b4e09c 2059 if (ns->disk && ns->disk->flags & GENHD_FL_UP) {
5bae7f73
CH		 2060 if (blk_get_integrity(ns->disk))
2061 blk_integrity_unregister(ns->disk);
2b9b6e86
KB		 2062 sysfs_remove_group(&disk_to_dev(ns->disk)->kobj,
2063 &nvme_ns_attr_group);
3dc87dd0
MB		 2064 if (ns->ndev)
2065 nvme_nvm_unregister_sysfs(ns);
5bae7f73 2066 del_gendisk(ns->disk);
5bae7f73
CH		 2067 blk_mq_abort_requeue_list(ns->queue);
2068 blk_cleanup_queue(ns->queue);
2069 }
32f0c4af
KB		 2070
2071 mutex_lock(&ns->ctrl->namespaces_mutex);
5bae7f73 2072 list_del_init(&ns->list);
32f0c4af
KB		 2073 mutex_unlock(&ns->ctrl->namespaces_mutex);
2074
5bae7f73
CH		 2075 nvme_put_ns(ns);
2076}
2077
540c801c
KB		 2078static void nvme_validate_ns(struct nvme_ctrl *ctrl, unsigned nsid)
2079{
2080 struct nvme_ns *ns;
2081
32f0c4af 2082 ns = nvme_find_get_ns(ctrl, nsid);
540c801c 2083 if (ns) {
b0b4e09c 2084 if (ns->disk && revalidate_disk(ns->disk))
540c801c 2085 nvme_ns_remove(ns);
32f0c4af 2086 nvme_put_ns(ns);
540c801c
KB		 2087 } else
2088 nvme_alloc_ns(ctrl, nsid);
2089}
2090
47b0e50a
SB		 2091static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
2092 unsigned nsid)
2093{
2094 struct nvme_ns *ns, *next;
2095
2096 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
2097 if (ns->ns_id > nsid)
2098 nvme_ns_remove(ns);
2099 }
2100}
2101
540c801c
KB		 2102static int nvme_scan_ns_list(struct nvme_ctrl *ctrl, unsigned nn)
2103{
2104 struct nvme_ns *ns;
2105 __le32 *ns_list;
2106 unsigned i, j, nsid, prev = 0, num_lists = DIV_ROUND_UP(nn, 1024);
2107 int ret = 0;
2108
2109 ns_list = kzalloc(0x1000, GFP_KERNEL);
2110 if (!ns_list)
2111 return -ENOMEM;
2112
2113 for (i = 0; i < num_lists; i++) {
2114 ret = nvme_identify_ns_list(ctrl, prev, ns_list);
2115 if (ret)
47b0e50a 2116 goto free;
540c801c
KB		 2117
2118 for (j = 0; j < min(nn, 1024U); j++) {
2119 nsid = le32_to_cpu(ns_list[j]);
2120 if (!nsid)
2121 goto out;
2122
2123 nvme_validate_ns(ctrl, nsid);
2124
2125 while (++prev < nsid) {
32f0c4af
KB		 2126 ns = nvme_find_get_ns(ctrl, prev);
2127 if (ns) {
540c801c 2128 nvme_ns_remove(ns);
32f0c4af
KB		 2129 nvme_put_ns(ns);
2130 }
540c801c
KB		 2131 }
2132 }
2133 nn -= j;
2134 }
2135 out:
47b0e50a
SB		 2136 nvme_remove_invalid_namespaces(ctrl, prev);
2137 free:
540c801c
KB		 2138 kfree(ns_list);
2139 return ret;
2140}
2141
5955be21 2142static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl, unsigned nn)
5bae7f73 2143{
5bae7f73
CH		 2144 unsigned i;
2145
540c801c
KB		 2146 for (i = 1; i <= nn; i++)
2147 nvme_validate_ns(ctrl, i);
2148
47b0e50a 2149 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH		 2150}
2151
5955be21 2152static void nvme_scan_work(struct work_struct *work)
5bae7f73 2153{
5955be21
CH		 2154 struct nvme_ctrl *ctrl =
2155 container_of(work, struct nvme_ctrl, scan_work);
5bae7f73 2156 struct nvme_id_ctrl *id;
540c801c 2157 unsigned nn;
5bae7f73 2158
5955be21
CH		 2159 if (ctrl->state != NVME_CTRL_LIVE)
2160 return;
2161
5bae7f73
CH		 2162 if (nvme_identify_ctrl(ctrl, &id))
2163 return;
540c801c
KB		 2164
2165 nn = le32_to_cpu(id->nn);
8ef2074d 2166 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
540c801c
KB		 2167 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
2168 if (!nvme_scan_ns_list(ctrl, nn))
2169 goto done;
2170 }
5955be21 2171 nvme_scan_ns_sequential(ctrl, nn);
540c801c 2172 done:
32f0c4af 2173 mutex_lock(&ctrl->namespaces_mutex);
540c801c 2174 list_sort(NULL, &ctrl->namespaces, ns_cmp);
69d3b8ac 2175 mutex_unlock(&ctrl->namespaces_mutex);
5bae7f73
CH		 2176 kfree(id);
2177}
5955be21
CH		 2178
2179void nvme_queue_scan(struct nvme_ctrl *ctrl)
2180{
2181 /*
2182 * Do not queue new scan work when a controller is reset during
2183 * removal.
2184 */
2185 if (ctrl->state == NVME_CTRL_LIVE)
2186 schedule_work(&ctrl->scan_work);
2187}
2188EXPORT_SYMBOL_GPL(nvme_queue_scan);
5bae7f73 2189
32f0c4af
KB		 2190/*
2191 * This function iterates the namespace list unlocked to allow recovery from
2192 * controller failure. It is up to the caller to ensure the namespace list is
2193 * not modified by scan work while this function is executing.
2194 */
5bae7f73
CH		 2195void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
2196{
2197 struct nvme_ns *ns, *next;
2198
0ff9d4e1
KB		 2199 /*
2200 * The dead states indicates the controller was not gracefully
2201 * disconnected. In that case, we won't be able to flush any data while
2202 * removing the namespaces' disks; fail all the queues now to avoid
2203 * potentially having to clean up the failed sync later.
2204 */
2205 if (ctrl->state == NVME_CTRL_DEAD)
2206 nvme_kill_queues(ctrl);
2207
5bae7f73
CH		 2208 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list)
2209 nvme_ns_remove(ns);
2210}
576d55d6 2211EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 2212
f866fc42
CH		 2213static void nvme_async_event_work(struct work_struct *work)
2214{
2215 struct nvme_ctrl *ctrl =
2216 container_of(work, struct nvme_ctrl, async_event_work);
2217
2218 spin_lock_irq(&ctrl->lock);
2219 while (ctrl->event_limit > 0) {
2220 int aer_idx = --ctrl->event_limit;
2221
2222 spin_unlock_irq(&ctrl->lock);
2223 ctrl->ops->submit_async_event(ctrl, aer_idx);
2224 spin_lock_irq(&ctrl->lock);
2225 }
2226 spin_unlock_irq(&ctrl->lock);
2227}
2228
7bf58533
CH		 2229void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
2230 union nvme_result *res)
f866fc42 2231{
7bf58533
CH		 2232 u32 result = le32_to_cpu(res->u32);
2233 bool done = true;
f866fc42 2234
7bf58533
CH		 2235 switch (le16_to_cpu(status) >> 1) {
2236 case NVME_SC_SUCCESS:
2237 done = false;
2238 /*FALLTHRU*/
2239 case NVME_SC_ABORT_REQ:
f866fc42
CH		 2240 ++ctrl->event_limit;
2241 schedule_work(&ctrl->async_event_work);
7bf58533
CH		 2242 break;
2243 default:
2244 break;
f866fc42
CH		 2245 }
2246
7bf58533 2247 if (done)
f866fc42
CH		 2248 return;
2249
2250 switch (result & 0xff07) {
2251 case NVME_AER_NOTICE_NS_CHANGED:
2252 dev_info(ctrl->device, "rescanning\n");
2253 nvme_queue_scan(ctrl);
2254 break;
2255 default:
2256 dev_warn(ctrl->device, "async event result %08x\n", result);
2257 }
2258}
2259EXPORT_SYMBOL_GPL(nvme_complete_async_event);
2260
2261void nvme_queue_async_events(struct nvme_ctrl *ctrl)
2262{
2263 ctrl->event_limit = NVME_NR_AERS;
2264 schedule_work(&ctrl->async_event_work);
2265}
2266EXPORT_SYMBOL_GPL(nvme_queue_async_events);
2267
f3ca80fc
CH		 2268static DEFINE_IDA(nvme_instance_ida);
2269
2270static int nvme_set_instance(struct nvme_ctrl *ctrl)
2271{
2272 int instance, error;
2273
2274 do {
2275 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2276 return -ENODEV;
2277
2278 spin_lock(&dev_list_lock);
2279 error = ida_get_new(&nvme_instance_ida, &instance);
2280 spin_unlock(&dev_list_lock);
2281 } while (error == -EAGAIN);
2282
2283 if (error)
2284 return -ENODEV;
2285
2286 ctrl->instance = instance;
2287 return 0;
2288}
2289
2290static void nvme_release_instance(struct nvme_ctrl *ctrl)
2291{
2292 spin_lock(&dev_list_lock);
2293 ida_remove(&nvme_instance_ida, ctrl->instance);
2294 spin_unlock(&dev_list_lock);
2295}
2296
53029b04 2297void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
576d55d6 2298{
f866fc42 2299 flush_work(&ctrl->async_event_work);
5955be21
CH		 2300 flush_work(&ctrl->scan_work);
2301 nvme_remove_namespaces(ctrl);
2302
53029b04 2303 device_destroy(nvme_class, MKDEV(nvme_char_major, ctrl->instance));
f3ca80fc
CH		 2304
2305 spin_lock(&dev_list_lock);
2306 list_del(&ctrl->node);
2307 spin_unlock(&dev_list_lock);
53029b04 2308}
576d55d6 2309EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04
KB		 2310
2311static void nvme_free_ctrl(struct kref *kref)
2312{
2313 struct nvme_ctrl *ctrl = container_of(kref, struct nvme_ctrl, kref);
f3ca80fc
CH		 2314
2315 put_device(ctrl->device);
2316 nvme_release_instance(ctrl);
075790eb 2317 ida_destroy(&ctrl->ns_ida);
f3ca80fc
CH		 2318
2319 ctrl->ops->free_ctrl(ctrl);
2320}
2321
2322void nvme_put_ctrl(struct nvme_ctrl *ctrl)
2323{
2324 kref_put(&ctrl->kref, nvme_free_ctrl);
2325}
576d55d6 2326EXPORT_SYMBOL_GPL(nvme_put_ctrl);
f3ca80fc
CH		 2327
2328/*
2329 * Initialize a NVMe controller structures. This needs to be called during
2330 * earliest initialization so that we have the initialized structured around
2331 * during probing.
2332 */
2333int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
2334 const struct nvme_ctrl_ops *ops, unsigned long quirks)
2335{
2336 int ret;
2337
bb8d261e
CH		 2338 ctrl->state = NVME_CTRL_NEW;
2339 spin_lock_init(&ctrl->lock);
f3ca80fc 2340 INIT_LIST_HEAD(&ctrl->namespaces);
69d3b8ac 2341 mutex_init(&ctrl->namespaces_mutex);
f3ca80fc
CH		 2342 kref_init(&ctrl->kref);
2343 ctrl->dev = dev;
2344 ctrl->ops = ops;
2345 ctrl->quirks = quirks;
5955be21 2346 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 2347 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
f3ca80fc
CH		 2348
2349 ret = nvme_set_instance(ctrl);
2350 if (ret)
2351 goto out;
2352
779ff756 2353 ctrl->device = device_create_with_groups(nvme_class, ctrl->dev,
f3ca80fc 2354 MKDEV(nvme_char_major, ctrl->instance),
f4f0f63e 2355 ctrl, nvme_dev_attr_groups,
779ff756 2356 "nvme%d", ctrl->instance);
f3ca80fc
CH		 2357 if (IS_ERR(ctrl->device)) {
2358 ret = PTR_ERR(ctrl->device);
2359 goto out_release_instance;
2360 }
2361 get_device(ctrl->device);
075790eb 2362 ida_init(&ctrl->ns_ida);
f3ca80fc 2363
f3ca80fc
CH		 2364 spin_lock(&dev_list_lock);
2365 list_add_tail(&ctrl->node, &nvme_ctrl_list);
2366 spin_unlock(&dev_list_lock);
2367
c5552fde
AL		 2368 /*
2369 * Initialize latency tolerance controls. The sysfs files won't
2370 * be visible to userspace unless the device actually supports APST.
2371 */
2372 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
2373 dev_pm_qos_update_user_latency_tolerance(ctrl->device,
2374 min(default_ps_max_latency_us, (unsigned long)S32_MAX));
2375
f3ca80fc 2376 return 0;
f3ca80fc
CH		 2377out_release_instance:
2378 nvme_release_instance(ctrl);
2379out:
2380 return ret;
2381}
576d55d6 2382EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 2383
69d9a99c
KB		 2384/**
2385 * nvme_kill_queues(): Ends all namespace queues
2386 * @ctrl: the dead controller that needs to end
2387 *
2388 * Call this function when the driver determines it is unable to get the
2389 * controller in a state capable of servicing IO.
2390 */
2391void nvme_kill_queues(struct nvme_ctrl *ctrl)
2392{
2393 struct nvme_ns *ns;
2394
32f0c4af
KB		 2395 mutex_lock(&ctrl->namespaces_mutex);
2396 list_for_each_entry(ns, &ctrl->namespaces, list) {
69d9a99c
KB		 2397 /*
2398 * Revalidating a dead namespace sets capacity to 0. This will
2399 * end buffered writers dirtying pages that can't be synced.
2400 */
f33447b9
KB		 2401 if (!ns->disk || test_and_set_bit(NVME_NS_DEAD, &ns->flags))
2402 continue;
2403 revalidate_disk(ns->disk);
69d9a99c
KB		 2404 blk_set_queue_dying(ns->queue);
2405 blk_mq_abort_requeue_list(ns->queue);
2406 blk_mq_start_stopped_hw_queues(ns->queue, true);
69d9a99c 2407 }
32f0c4af 2408 mutex_unlock(&ctrl->namespaces_mutex);
69d9a99c 2409}
237045fc 2410EXPORT_SYMBOL_GPL(nvme_kill_queues);
69d9a99c 2411
302ad8cc
KB		 2412void nvme_unfreeze(struct nvme_ctrl *ctrl)
2413{
2414 struct nvme_ns *ns;
2415
2416 mutex_lock(&ctrl->namespaces_mutex);
2417 list_for_each_entry(ns, &ctrl->namespaces, list)
2418 blk_mq_unfreeze_queue(ns->queue);
2419 mutex_unlock(&ctrl->namespaces_mutex);
2420}
2421EXPORT_SYMBOL_GPL(nvme_unfreeze);
2422
2423void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout)
2424{
2425 struct nvme_ns *ns;
2426
2427 mutex_lock(&ctrl->namespaces_mutex);
2428 list_for_each_entry(ns, &ctrl->namespaces, list) {
2429 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout);
2430 if (timeout <= 0)
2431 break;
2432 }
2433 mutex_unlock(&ctrl->namespaces_mutex);
2434}
2435EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout);
2436
2437void nvme_wait_freeze(struct nvme_ctrl *ctrl)
2438{
2439 struct nvme_ns *ns;
2440
2441 mutex_lock(&ctrl->namespaces_mutex);
2442 list_for_each_entry(ns, &ctrl->namespaces, list)
2443 blk_mq_freeze_queue_wait(ns->queue);
2444 mutex_unlock(&ctrl->namespaces_mutex);
2445}
2446EXPORT_SYMBOL_GPL(nvme_wait_freeze);
2447
2448void nvme_start_freeze(struct nvme_ctrl *ctrl)
2449{
2450 struct nvme_ns *ns;
2451
2452 mutex_lock(&ctrl->namespaces_mutex);
2453 list_for_each_entry(ns, &ctrl->namespaces, list)
1671d522 2454 blk_freeze_queue_start(ns->queue);
302ad8cc
KB		 2455 mutex_unlock(&ctrl->namespaces_mutex);
2456}
2457EXPORT_SYMBOL_GPL(nvme_start_freeze);
2458
25646264 2459void nvme_stop_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 2460{
2461 struct nvme_ns *ns;
2462
32f0c4af 2463 mutex_lock(&ctrl->namespaces_mutex);
a6eaa884 2464 list_for_each_entry(ns, &ctrl->namespaces, list)
3174dd33 2465 blk_mq_quiesce_queue(ns->queue);
32f0c4af 2466 mutex_unlock(&ctrl->namespaces_mutex);
363c9aac 2467}
576d55d6 2468EXPORT_SYMBOL_GPL(nvme_stop_queues);
363c9aac 2469
25646264 2470void nvme_start_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 2471{
2472 struct nvme_ns *ns;
2473
32f0c4af
KB		 2474 mutex_lock(&ctrl->namespaces_mutex);
2475 list_for_each_entry(ns, &ctrl->namespaces, list) {
363c9aac
SG		 2476 blk_mq_start_stopped_hw_queues(ns->queue, true);
2477 blk_mq_kick_requeue_list(ns->queue);
2478 }
32f0c4af 2479 mutex_unlock(&ctrl->namespaces_mutex);
363c9aac 2480}
576d55d6 2481EXPORT_SYMBOL_GPL(nvme_start_queues);
363c9aac 2482
5bae7f73
CH		 2483int __init nvme_core_init(void)
2484{
2485 int result;
2486
f3ca80fc
CH		 2487 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
2488 &nvme_dev_fops);
2489 if (result < 0)
b09dcf58 2490 return result;
f3ca80fc
CH		 2491 else if (result > 0)
2492 nvme_char_major = result;
2493
2494 nvme_class = class_create(THIS_MODULE, "nvme");
2495 if (IS_ERR(nvme_class)) {
2496 result = PTR_ERR(nvme_class);
2497 goto unregister_chrdev;
2498 }
2499
5bae7f73 2500 return 0;
f3ca80fc
CH		 2501
2502 unregister_chrdev:
2503 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
f3ca80fc 2504 return result;
5bae7f73
CH		 2505}
2506
2507void nvme_core_exit(void)
2508{
f3ca80fc
CH		 2509 class_destroy(nvme_class);
2510 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
5bae7f73 2511}
576d55d6
ML		 2512
2513MODULE_LICENSE("GPL");
2514MODULE_VERSION("1.0");
2515module_init(nvme_core_init);
2516module_exit(nvme_core_exit);
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