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[mirror_ubuntu-jammy-kernel.git] / drivers / nvme / host / core.c
CommitLineData
bc50ad75 1// SPDX-License-Identifier: GPL-2.0
21d34711
CH		 2/*
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
21d34711
CH		 5 */
6
7#include <linux/blkdev.h>
8#include <linux/blk-mq.h>
5fd4ce1b 9#include <linux/delay.h>
21d34711 10#include <linux/errno.h>
1673f1f0 11#include <linux/hdreg.h>
21d34711 12#include <linux/kernel.h>
5bae7f73 13#include <linux/module.h>
958f2a0f 14#include <linux/backing-dev.h>
5bae7f73 15#include <linux/list_sort.h>
21d34711
CH		 16#include <linux/slab.h>
17#include <linux/types.h>
1673f1f0
CH		 18#include <linux/pr.h>
19#include <linux/ptrace.h>
20#include <linux/nvme_ioctl.h>
21#include <linux/t10-pi.h>
c5552fde 22#include <linux/pm_qos.h>
1673f1f0 23#include <asm/unaligned.h>
21d34711
CH		 24
25#include "nvme.h"
038bd4cb 26#include "fabrics.h"
21d34711 27
35fe0d12
HR		 28#define CREATE_TRACE_POINTS
29#include "trace.h"
30
f3ca80fc
CH		 31#define NVME_MINORS (1U << MINORBITS)
32
8ae4e447
MO		 33unsigned int admin_timeout = 60;
34module_param(admin_timeout, uint, 0644);
ba0ba7d3 35MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 36EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3 37
8ae4e447
MO		 38unsigned int nvme_io_timeout = 30;
39module_param_named(io_timeout, nvme_io_timeout, uint, 0644);
ba0ba7d3 40MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 41EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3 42
b3b1b0b0 43static unsigned char shutdown_timeout = 5;
ba0ba7d3
ML		 44module_param(shutdown_timeout, byte, 0644);
45MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
46
44e44b29
CH		 47static u8 nvme_max_retries = 5;
48module_param_named(max_retries, nvme_max_retries, byte, 0644);
f80ec966 49MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
5bae7f73 50
9947d6a0 51static unsigned long default_ps_max_latency_us = 100000;
c5552fde
AL		 52module_param(default_ps_max_latency_us, ulong, 0644);
53MODULE_PARM_DESC(default_ps_max_latency_us,
54 "max power saving latency for new devices; use PM QOS to change per device");
55
c35e30b4
AL		 56static bool force_apst;
57module_param(force_apst, bool, 0644);
58MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off");
59
f5d11840
JA		 60static bool streams;
61module_param(streams, bool, 0644);
62MODULE_PARM_DESC(streams, "turn on support for Streams write directives");
63
b227c59b
RS		 64/*
65 * nvme_wq - hosts nvme related works that are not reset or delete
66 * nvme_reset_wq - hosts nvme reset works
67 * nvme_delete_wq - hosts nvme delete works
68 *
69 * nvme_wq will host works such are scan, aen handling, fw activation,
70 * keep-alive error recovery, periodic reconnects etc. nvme_reset_wq
71 * runs reset works which also flush works hosted on nvme_wq for
72 * serialization purposes. nvme_delete_wq host controller deletion
73 * works which flush reset works for serialization.
74 */
9a6327d2
SG		 75struct workqueue_struct *nvme_wq;
76EXPORT_SYMBOL_GPL(nvme_wq);
77
b227c59b
RS		 78struct workqueue_struct *nvme_reset_wq;
79EXPORT_SYMBOL_GPL(nvme_reset_wq);
80
81struct workqueue_struct *nvme_delete_wq;
82EXPORT_SYMBOL_GPL(nvme_delete_wq);
83
ab9e00cc
CH		 84static LIST_HEAD(nvme_subsystems);
85static DEFINE_MUTEX(nvme_subsystems_lock);
1673f1f0 86
9843f685 87static DEFINE_IDA(nvme_instance_ida);
a6a5149b 88static dev_t nvme_chr_devt;
f3ca80fc 89static struct class *nvme_class;
ab9e00cc 90static struct class *nvme_subsys_class;
f3ca80fc 91
84fef62d 92static int nvme_revalidate_disk(struct gendisk *disk);
12d9f070 93static void nvme_put_subsystem(struct nvme_subsystem *subsys);
cf39a6bc
SB		 94static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
95 unsigned nsid);
96
97static void nvme_set_queue_dying(struct nvme_ns *ns)
98{
99 /*
100 * Revalidating a dead namespace sets capacity to 0. This will end
101 * buffered writers dirtying pages that can't be synced.
102 */
103 if (!ns->disk || test_and_set_bit(NVME_NS_DEAD, &ns->flags))
104 return;
cf39a6bc
SB		 105 blk_set_queue_dying(ns->queue);
106 /* Forcibly unquiesce queues to avoid blocking dispatch */
107 blk_mq_unquiesce_queue(ns->queue);
b224726d
BS		 108 /*
109 * Revalidate after unblocking dispatchers that may be holding bd_butex
110 */
111 revalidate_disk(ns->disk);
cf39a6bc 112}
f3ca80fc 113
50e8d8ee
CH		 114static void nvme_queue_scan(struct nvme_ctrl *ctrl)
115{
116 /*
117 * Only new queue scan work when admin and IO queues are both alive
118 */
5d02a5c1 119 if (ctrl->state == NVME_CTRL_LIVE && ctrl->tagset)
50e8d8ee
CH		 120 queue_work(nvme_wq, &ctrl->scan_work);
121}
122
4c75f877
KB		 123/*
124 * Use this function to proceed with scheduling reset_work for a controller
125 * that had previously been set to the resetting state. This is intended for
126 * code paths that can't be interrupted by other reset attempts. A hot removal
127 * may prevent this from succeeding.
128 */
c1ac9a4b 129int nvme_try_sched_reset(struct nvme_ctrl *ctrl)
4c75f877
KB		 130{
131 if (ctrl->state != NVME_CTRL_RESETTING)
132 return -EBUSY;
133 if (!queue_work(nvme_reset_wq, &ctrl->reset_work))
134 return -EBUSY;
135 return 0;
136}
c1ac9a4b 137EXPORT_SYMBOL_GPL(nvme_try_sched_reset);
4c75f877 138
d86c4d8e
CH		 139int nvme_reset_ctrl(struct nvme_ctrl *ctrl)
140{
141 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
142 return -EBUSY;
b227c59b 143 if (!queue_work(nvme_reset_wq, &ctrl->reset_work))
d86c4d8e
CH		 144 return -EBUSY;
145 return 0;
146}
147EXPORT_SYMBOL_GPL(nvme_reset_ctrl);
148
79c48ccf 149int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
d86c4d8e
CH		 150{
151 int ret;
152
153 ret = nvme_reset_ctrl(ctrl);
8000d1fd 154 if (!ret) {
d86c4d8e 155 flush_work(&ctrl->reset_work);
5d02a5c1 156 if (ctrl->state != NVME_CTRL_LIVE)
8000d1fd
NC		 157 ret = -ENETRESET;
158 }
159
d86c4d8e
CH		 160 return ret;
161}
79c48ccf 162EXPORT_SYMBOL_GPL(nvme_reset_ctrl_sync);
d86c4d8e 163
a686ed75 164static void nvme_do_delete_ctrl(struct nvme_ctrl *ctrl)
c5017e85 165{
77d0612d
MG		 166 dev_info(ctrl->device,
167 "Removing ctrl: NQN \"%s\"\n", ctrl->opts->subsysnqn);
168
4054637c 169 flush_work(&ctrl->reset_work);
6cd53d14
CH		 170 nvme_stop_ctrl(ctrl);
171 nvme_remove_namespaces(ctrl);
c5017e85 172 ctrl->ops->delete_ctrl(ctrl);
6cd53d14
CH		 173 nvme_uninit_ctrl(ctrl);
174 nvme_put_ctrl(ctrl);
c5017e85
CH		 175}
176
a686ed75
BVA		 177static void nvme_delete_ctrl_work(struct work_struct *work)
178{
179 struct nvme_ctrl *ctrl =
180 container_of(work, struct nvme_ctrl, delete_work);
181
182 nvme_do_delete_ctrl(ctrl);
183}
184
c5017e85
CH		 185int nvme_delete_ctrl(struct nvme_ctrl *ctrl)
186{
187 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
188 return -EBUSY;
b227c59b 189 if (!queue_work(nvme_delete_wq, &ctrl->delete_work))
c5017e85
CH		 190 return -EBUSY;
191 return 0;
192}
193EXPORT_SYMBOL_GPL(nvme_delete_ctrl);
194
d84c4b02 195static int nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl)
c5017e85
CH		 196{
197 int ret = 0;
198
199 /*
01fc08ff
YY		 200 * Keep a reference until nvme_do_delete_ctrl() complete,
201 * since ->delete_ctrl can free the controller.
c5017e85
CH		 202 */
203 nvme_get_ctrl(ctrl);
b9c77583
BVA		 204 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
205 ret = -EBUSY;
c5017e85 206 if (!ret)
b9c77583 207 nvme_do_delete_ctrl(ctrl);
c5017e85
CH		 208 nvme_put_ctrl(ctrl);
209 return ret;
210}
c5017e85 211
715ea9e0
CH		 212static inline bool nvme_ns_has_pi(struct nvme_ns *ns)
213{
214 return ns->pi_type && ns->ms == sizeof(struct t10_pi_tuple);
215}
216
2f9c1736 217static blk_status_t nvme_error_status(u16 status)
27fa9bc5 218{
2f9c1736 219 switch (status & 0x7ff) {
27fa9bc5 220 case NVME_SC_SUCCESS:
2a842aca 221 return BLK_STS_OK;
27fa9bc5 222 case NVME_SC_CAP_EXCEEDED:
2a842aca 223 return BLK_STS_NOSPC;
e96fef2c
KB		 224 case NVME_SC_LBA_RANGE:
225 return BLK_STS_TARGET;
226 case NVME_SC_BAD_ATTRIBUTES:
e02ab023 227 case NVME_SC_ONCS_NOT_SUPPORTED:
e96fef2c
KB		 228 case NVME_SC_INVALID_OPCODE:
229 case NVME_SC_INVALID_FIELD:
230 case NVME_SC_INVALID_NS:
2a842aca 231 return BLK_STS_NOTSUPP;
e02ab023
JG		 232 case NVME_SC_WRITE_FAULT:
233 case NVME_SC_READ_ERROR:
234 case NVME_SC_UNWRITTEN_BLOCK:
a751da33
CH		 235 case NVME_SC_ACCESS_DENIED:
236 case NVME_SC_READ_ONLY:
e96fef2c 237 case NVME_SC_COMPARE_FAILED:
2a842aca 238 return BLK_STS_MEDIUM;
a751da33
CH		 239 case NVME_SC_GUARD_CHECK:
240 case NVME_SC_APPTAG_CHECK:
241 case NVME_SC_REFTAG_CHECK:
242 case NVME_SC_INVALID_PI:
243 return BLK_STS_PROTECTION;
244 case NVME_SC_RESERVATION_CONFLICT:
245 return BLK_STS_NEXUS;
1c0d12c0
SG		 246 case NVME_SC_HOST_PATH_ERROR:
247 return BLK_STS_TRANSPORT;
2a842aca
CH		 248 default:
249 return BLK_STS_IOERR;
27fa9bc5
CH		 250 }
251}
27fa9bc5 252
f6324b1b 253static inline bool nvme_req_needs_retry(struct request *req)
77f02a7a 254{
f6324b1b
CH		 255 if (blk_noretry_request(req))
256 return false;
27fa9bc5 257 if (nvme_req(req)->status & NVME_SC_DNR)
f6324b1b 258 return false;
44e44b29 259 if (nvme_req(req)->retries >= nvme_max_retries)
f6324b1b
CH		 260 return false;
261 return true;
77f02a7a
CH		 262}
263
49cd84b6
KB		 264static void nvme_retry_req(struct request *req)
265{
266 struct nvme_ns *ns = req->q->queuedata;
267 unsigned long delay = 0;
268 u16 crd;
269
270 /* The mask and shift result must be <= 3 */
271 crd = (nvme_req(req)->status & NVME_SC_CRD) >> 11;
272 if (ns && crd)
273 delay = ns->ctrl->crdt[crd - 1] * 100;
274
275 nvme_req(req)->retries++;
276 blk_mq_requeue_request(req, false);
277 blk_mq_delay_kick_requeue_list(req->q, delay);
278}
279
77f02a7a
CH		 280void nvme_complete_rq(struct request *req)
281{
2f9c1736 282 blk_status_t status = nvme_error_status(nvme_req(req)->status);
908e4564 283
ca5554a6
JT		 284 trace_nvme_complete_rq(req);
285
16686f3a
MG		 286 nvme_cleanup_cmd(req);
287
6e3ca03e
SG		 288 if (nvme_req(req)->ctrl->kas)
289 nvme_req(req)->ctrl->comp_seen = true;
290
908e4564 291 if (unlikely(status != BLK_STS_OK && nvme_req_needs_retry(req))) {
8decf5d5
CH		 292 if ((req->cmd_flags & REQ_NVME_MPATH) &&
293 blk_path_error(status)) {
32acab31
CH		 294 nvme_failover_req(req);
295 return;
296 }
297
298 if (!blk_queue_dying(req->q)) {
49cd84b6 299 nvme_retry_req(req);
32acab31
CH		 300 return;
301 }
77f02a7a 302 }
35fe0d12
HR		 303
304 nvme_trace_bio_complete(req, status);
908e4564 305 blk_mq_end_request(req, status);
77f02a7a
CH		 306}
307EXPORT_SYMBOL_GPL(nvme_complete_rq);
308
7baa8572 309bool nvme_cancel_request(struct request *req, void *data, bool reserved)
c55a2fd4 310{
c55a2fd4
ML		 311 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
312 "Cancelling I/O %d", req->tag);
313
78ca4072
ML		 314 /* don't abort one completed request */
315 if (blk_mq_request_completed(req))
316 return true;
317
2dc3947b 318 nvme_req(req)->status = NVME_SC_HOST_ABORTED_CMD;
a87ccce0 319 blk_mq_complete_request(req);
7baa8572 320 return true;
c55a2fd4
ML		 321}
322EXPORT_SYMBOL_GPL(nvme_cancel_request);
323
bb8d261e
CH		 324bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
325 enum nvme_ctrl_state new_state)
326{
f6b6a28e 327 enum nvme_ctrl_state old_state;
0a72bbba 328 unsigned long flags;
bb8d261e
CH		 329 bool changed = false;
330
0a72bbba 331 spin_lock_irqsave(&ctrl->lock, flags);
f6b6a28e
GKB		 332
333 old_state = ctrl->state;
bb8d261e
CH		 334 switch (new_state) {
335 case NVME_CTRL_LIVE:
336 switch (old_state) {
7d2e8008 337 case NVME_CTRL_NEW:
bb8d261e 338 case NVME_CTRL_RESETTING:
ad6a0a52 339 case NVME_CTRL_CONNECTING:
bb8d261e
CH		 340 changed = true;
341 /* FALLTHRU */
342 default:
343 break;
344 }
345 break;
346 case NVME_CTRL_RESETTING:
347 switch (old_state) {
348 case NVME_CTRL_NEW:
def61eca 349 case NVME_CTRL_LIVE:
def61eca
CH		 350 changed = true;
351 /* FALLTHRU */
352 default:
353 break;
354 }
355 break;
ad6a0a52 356 case NVME_CTRL_CONNECTING:
def61eca 357 switch (old_state) {
b754a32c 358 case NVME_CTRL_NEW:
3cec7f9d 359 case NVME_CTRL_RESETTING:
bb8d261e
CH		 360 changed = true;
361 /* FALLTHRU */
362 default:
363 break;
364 }
365 break;
366 case NVME_CTRL_DELETING:
367 switch (old_state) {
368 case NVME_CTRL_LIVE:
369 case NVME_CTRL_RESETTING:
ad6a0a52 370 case NVME_CTRL_CONNECTING:
bb8d261e
CH		 371 changed = true;
372 /* FALLTHRU */
373 default:
374 break;
375 }
376 break;
0ff9d4e1
KB		 377 case NVME_CTRL_DEAD:
378 switch (old_state) {
379 case NVME_CTRL_DELETING:
380 changed = true;
381 /* FALLTHRU */
382 default:
383 break;
384 }
385 break;
bb8d261e
CH		 386 default:
387 break;
388 }
bb8d261e 389
c1ac9a4b 390 if (changed) {
bb8d261e 391 ctrl->state = new_state;
c1ac9a4b
KB		 392 wake_up_all(&ctrl->state_wq);
393 }
bb8d261e 394
0a72bbba 395 spin_unlock_irqrestore(&ctrl->lock, flags);
32acab31
CH		 396 if (changed && ctrl->state == NVME_CTRL_LIVE)
397 nvme_kick_requeue_lists(ctrl);
bb8d261e
CH		 398 return changed;
399}
400EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
401
c1ac9a4b
KB		 402/*
403 * Returns true for sink states that can't ever transition back to live.
404 */
405static bool nvme_state_terminal(struct nvme_ctrl *ctrl)
406{
407 switch (ctrl->state) {
408 case NVME_CTRL_NEW:
409 case NVME_CTRL_LIVE:
410 case NVME_CTRL_RESETTING:
411 case NVME_CTRL_CONNECTING:
412 return false;
413 case NVME_CTRL_DELETING:
414 case NVME_CTRL_DEAD:
415 return true;
416 default:
417 WARN_ONCE(1, "Unhandled ctrl state:%d", ctrl->state);
418 return true;
419 }
420}
421
422/*
423 * Waits for the controller state to be resetting, or returns false if it is
424 * not possible to ever transition to that state.
425 */
426bool nvme_wait_reset(struct nvme_ctrl *ctrl)
427{
428 wait_event(ctrl->state_wq,
429 nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING) ||
430 nvme_state_terminal(ctrl));
431 return ctrl->state == NVME_CTRL_RESETTING;
432}
433EXPORT_SYMBOL_GPL(nvme_wait_reset);
434
ed754e5d
CH		 435static void nvme_free_ns_head(struct kref *ref)
436{
437 struct nvme_ns_head *head =
438 container_of(ref, struct nvme_ns_head, ref);
439
32acab31 440 nvme_mpath_remove_disk(head);
ed754e5d
CH		 441 ida_simple_remove(&head->subsys->ns_ida, head->instance);
442 list_del_init(&head->entry);
f5ad3991 443 cleanup_srcu_struct(&head->srcu);
12d9f070 444 nvme_put_subsystem(head->subsys);
ed754e5d
CH		 445 kfree(head);
446}
447
448static void nvme_put_ns_head(struct nvme_ns_head *head)
449{
450 kref_put(&head->ref, nvme_free_ns_head);
451}
452
1673f1f0
CH		 453static void nvme_free_ns(struct kref *kref)
454{
455 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
456
b0b4e09c
MB		 457 if (ns->ndev)
458 nvme_nvm_unregister(ns);
1673f1f0 459
1673f1f0 460 put_disk(ns->disk);
ed754e5d 461 nvme_put_ns_head(ns->head);
075790eb 462 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH		 463 kfree(ns);
464}
465
5bae7f73 466static void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH		 467{
468 kref_put(&ns->kref, nvme_free_ns);
469}
470
bb06ec31
JS		 471static inline void nvme_clear_nvme_request(struct request *req)
472{
473 if (!(req->rq_flags & RQF_DONTPREP)) {
474 nvme_req(req)->retries = 0;
475 nvme_req(req)->flags = 0;
476 req->rq_flags |= RQF_DONTPREP;
477 }
478}
479
4160982e 480struct request *nvme_alloc_request(struct request_queue *q,
9a95e4ef 481 struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid)
21d34711 482{
aebf526b 483 unsigned op = nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN;
21d34711 484 struct request *req;
21d34711 485
eb71f435 486 if (qid == NVME_QID_ANY) {
aebf526b 487 req = blk_mq_alloc_request(q, op, flags);
eb71f435 488 } else {
aebf526b 489 req = blk_mq_alloc_request_hctx(q, op, flags,
eb71f435
CH		 490 qid ? qid - 1 : 0);
491 }
21d34711 492 if (IS_ERR(req))
4160982e 493 return req;
21d34711 494
21d34711 495 req->cmd_flags |= REQ_FAILFAST_DRIVER;
bb06ec31 496 nvme_clear_nvme_request(req);
d49187e9 497 nvme_req(req)->cmd = cmd;
21d34711 498
4160982e
CH		 499 return req;
500}
576d55d6 501EXPORT_SYMBOL_GPL(nvme_alloc_request);
4160982e 502
f5d11840
JA		 503static int nvme_toggle_streams(struct nvme_ctrl *ctrl, bool enable)
504{
505 struct nvme_command c;
506
507 memset(&c, 0, sizeof(c));
508
509 c.directive.opcode = nvme_admin_directive_send;
62346eae 510 c.directive.nsid = cpu_to_le32(NVME_NSID_ALL);
f5d11840
JA		 511 c.directive.doper = NVME_DIR_SND_ID_OP_ENABLE;
512 c.directive.dtype = NVME_DIR_IDENTIFY;
513 c.directive.tdtype = NVME_DIR_STREAMS;
514 c.directive.endir = enable ? NVME_DIR_ENDIR : 0;
515
516 return nvme_submit_sync_cmd(ctrl->admin_q, &c, NULL, 0);
517}
518
519static int nvme_disable_streams(struct nvme_ctrl *ctrl)
520{
521 return nvme_toggle_streams(ctrl, false);
522}
523
524static int nvme_enable_streams(struct nvme_ctrl *ctrl)
525{
526 return nvme_toggle_streams(ctrl, true);
527}
528
529static int nvme_get_stream_params(struct nvme_ctrl *ctrl,
530 struct streams_directive_params *s, u32 nsid)
531{
532 struct nvme_command c;
533
534 memset(&c, 0, sizeof(c));
535 memset(s, 0, sizeof(*s));
536
537 c.directive.opcode = nvme_admin_directive_recv;
538 c.directive.nsid = cpu_to_le32(nsid);
a082b426 539 c.directive.numd = cpu_to_le32((sizeof(*s) >> 2) - 1);
f5d11840
JA		 540 c.directive.doper = NVME_DIR_RCV_ST_OP_PARAM;
541 c.directive.dtype = NVME_DIR_STREAMS;
542
543 return nvme_submit_sync_cmd(ctrl->admin_q, &c, s, sizeof(*s));
544}
545
546static int nvme_configure_directives(struct nvme_ctrl *ctrl)
547{
548 struct streams_directive_params s;
549 int ret;
550
551 if (!(ctrl->oacs & NVME_CTRL_OACS_DIRECTIVES))
552 return 0;
553 if (!streams)
554 return 0;
555
556 ret = nvme_enable_streams(ctrl);
557 if (ret)
558 return ret;
559
62346eae 560 ret = nvme_get_stream_params(ctrl, &s, NVME_NSID_ALL);
f5d11840
JA		 561 if (ret)
562 return ret;
563
564 ctrl->nssa = le16_to_cpu(s.nssa);
565 if (ctrl->nssa < BLK_MAX_WRITE_HINTS - 1) {
566 dev_info(ctrl->device, "too few streams (%u) available\n",
567 ctrl->nssa);
568 nvme_disable_streams(ctrl);
569 return 0;
570 }
571
572 ctrl->nr_streams = min_t(unsigned, ctrl->nssa, BLK_MAX_WRITE_HINTS - 1);
573 dev_info(ctrl->device, "Using %u streams\n", ctrl->nr_streams);
574 return 0;
575}
576
577/*
578 * Check if 'req' has a write hint associated with it. If it does, assign
579 * a valid namespace stream to the write.
580 */
581static void nvme_assign_write_stream(struct nvme_ctrl *ctrl,
582 struct request *req, u16 *control,
583 u32 *dsmgmt)
584{
585 enum rw_hint streamid = req->write_hint;
586
587 if (streamid == WRITE_LIFE_NOT_SET || streamid == WRITE_LIFE_NONE)
588 streamid = 0;
589 else {
590 streamid--;
591 if (WARN_ON_ONCE(streamid > ctrl->nr_streams))
592 return;
593
594 *control |= NVME_RW_DTYPE_STREAMS;
595 *dsmgmt |= streamid << 16;
596 }
597
598 if (streamid < ARRAY_SIZE(req->q->write_hints))
599 req->q->write_hints[streamid] += blk_rq_bytes(req) >> 9;
600}
601
8093f7ca
ML		 602static inline void nvme_setup_flush(struct nvme_ns *ns,
603 struct nvme_command *cmnd)
604{
8093f7ca 605 cmnd->common.opcode = nvme_cmd_flush;
ed754e5d 606 cmnd->common.nsid = cpu_to_le32(ns->head->ns_id);
8093f7ca
ML		 607}
608
fc17b653 609static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 610 struct nvme_command *cmnd)
611{
b35ba01e 612 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
8093f7ca 613 struct nvme_dsm_range *range;
b35ba01e 614 struct bio *bio;
8093f7ca 615
530436c4
EH		 616 /*
617 * Some devices do not consider the DSM 'Number of Ranges' field when
618 * determining how much data to DMA. Always allocate memory for maximum
619 * number of segments to prevent device reading beyond end of buffer.
620 */
621 static const size_t alloc_size = sizeof(*range) * NVME_DSM_MAX_RANGES;
622
623 range = kzalloc(alloc_size, GFP_ATOMIC | __GFP_NOWARN);
cb5b7262
JA		 624 if (!range) {
625 /*
626 * If we fail allocation our range, fallback to the controller
627 * discard page. If that's also busy, it's safe to return
628 * busy, as we know we can make progress once that's freed.
629 */
630 if (test_and_set_bit_lock(0, &ns->ctrl->discard_page_busy))
631 return BLK_STS_RESOURCE;
632
633 range = page_address(ns->ctrl->discard_page);
634 }
8093f7ca 635
b35ba01e 636 __rq_for_each_bio(bio, req) {
314d48dd 637 u64 slba = nvme_sect_to_lba(ns, bio->bi_iter.bi_sector);
b35ba01e
CH		 638 u32 nlb = bio->bi_iter.bi_size >> ns->lba_shift;
639
8cb6af7b
KB		 640 if (n < segments) {
641 range[n].cattr = cpu_to_le32(0);
642 range[n].nlb = cpu_to_le32(nlb);
643 range[n].slba = cpu_to_le64(slba);
644 }
b35ba01e
CH		 645 n++;
646 }
647
648 if (WARN_ON_ONCE(n != segments)) {
cb5b7262
JA		 649 if (virt_to_page(range) == ns->ctrl->discard_page)
650 clear_bit_unlock(0, &ns->ctrl->discard_page_busy);
651 else
652 kfree(range);
fc17b653 653 return BLK_STS_IOERR;
b35ba01e 654 }
8093f7ca 655
8093f7ca 656 cmnd->dsm.opcode = nvme_cmd_dsm;
ed754e5d 657 cmnd->dsm.nsid = cpu_to_le32(ns->head->ns_id);
f1dd03a8 658 cmnd->dsm.nr = cpu_to_le32(segments - 1);
8093f7ca
ML		 659 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
660
f9d03f96
CH		 661 req->special_vec.bv_page = virt_to_page(range);
662 req->special_vec.bv_offset = offset_in_page(range);
530436c4 663 req->special_vec.bv_len = alloc_size;
f9d03f96 664 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 665
fc17b653 666 return BLK_STS_OK;
8093f7ca 667}
8093f7ca 668
6e02318e
CK		 669static inline blk_status_t nvme_setup_write_zeroes(struct nvme_ns *ns,
670 struct request *req, struct nvme_command *cmnd)
671{
672 if (ns->ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
673 return nvme_setup_discard(ns, req, cmnd);
674
675 cmnd->write_zeroes.opcode = nvme_cmd_write_zeroes;
676 cmnd->write_zeroes.nsid = cpu_to_le32(ns->head->ns_id);
677 cmnd->write_zeroes.slba =
314d48dd 678 cpu_to_le64(nvme_sect_to_lba(ns, blk_rq_pos(req)));
6e02318e
CK		 679 cmnd->write_zeroes.length =
680 cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
681 cmnd->write_zeroes.control = 0;
682 return BLK_STS_OK;
683}
684
ebe6d874
CH		 685static inline blk_status_t nvme_setup_rw(struct nvme_ns *ns,
686 struct request *req, struct nvme_command *cmnd)
8093f7ca 687{
f5d11840 688 struct nvme_ctrl *ctrl = ns->ctrl;
8093f7ca
ML		 689 u16 control = 0;
690 u32 dsmgmt = 0;
691
692 if (req->cmd_flags & REQ_FUA)
693 control |= NVME_RW_FUA;
694 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
695 control |= NVME_RW_LR;
696
697 if (req->cmd_flags & REQ_RAHEAD)
698 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
699
8093f7ca 700 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
ed754e5d 701 cmnd->rw.nsid = cpu_to_le32(ns->head->ns_id);
314d48dd 702 cmnd->rw.slba = cpu_to_le64(nvme_sect_to_lba(ns, blk_rq_pos(req)));
8093f7ca
ML		 703 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
704
f5d11840
JA		 705 if (req_op(req) == REQ_OP_WRITE && ctrl->nr_streams)
706 nvme_assign_write_stream(ctrl, req, &control, &dsmgmt);
707
8093f7ca 708 if (ns->ms) {
715ea9e0
CH		 709 /*
710 * If formated with metadata, the block layer always provides a
711 * metadata buffer if CONFIG_BLK_DEV_INTEGRITY is enabled. Else
712 * we enable the PRACT bit for protection information or set the
713 * namespace capacity to zero to prevent any I/O.
714 */
715 if (!blk_integrity_rq(req)) {
716 if (WARN_ON_ONCE(!nvme_ns_has_pi(ns)))
717 return BLK_STS_NOTSUPP;
718 control |= NVME_RW_PRINFO_PRACT;
719 }
720
8093f7ca
ML		 721 switch (ns->pi_type) {
722 case NVME_NS_DPS_PI_TYPE3:
723 control |= NVME_RW_PRINFO_PRCHK_GUARD;
724 break;
725 case NVME_NS_DPS_PI_TYPE1:
726 case NVME_NS_DPS_PI_TYPE2:
727 control |= NVME_RW_PRINFO_PRCHK_GUARD |
728 NVME_RW_PRINFO_PRCHK_REF;
ddd0bc75 729 cmnd->rw.reftag = cpu_to_le32(t10_pi_ref_tag(req));
8093f7ca
ML		 730 break;
731 }
8093f7ca
ML		 732 }
733
734 cmnd->rw.control = cpu_to_le16(control);
735 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
ebe6d874 736 return 0;
8093f7ca
ML		 737}
738
f7f1fc36
MG		 739void nvme_cleanup_cmd(struct request *req)
740{
f7f1fc36 741 if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
cb5b7262
JA		 742 struct nvme_ns *ns = req->rq_disk->private_data;
743 struct page *page = req->special_vec.bv_page;
744
745 if (page == ns->ctrl->discard_page)
746 clear_bit_unlock(0, &ns->ctrl->discard_page_busy);
747 else
748 kfree(page_address(page) + req->special_vec.bv_offset);
f7f1fc36
MG		 749 }
750}
751EXPORT_SYMBOL_GPL(nvme_cleanup_cmd);
752
fc17b653 753blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 754 struct nvme_command *cmd)
755{
fc17b653 756 blk_status_t ret = BLK_STS_OK;
8093f7ca 757
bb06ec31 758 nvme_clear_nvme_request(req);
987f699a 759
11902035 760 memset(cmd, 0, sizeof(*cmd));
aebf526b
CH		 761 switch (req_op(req)) {
762 case REQ_OP_DRV_IN:
763 case REQ_OP_DRV_OUT:
d49187e9 764 memcpy(cmd, nvme_req(req)->cmd, sizeof(*cmd));
aebf526b
CH		 765 break;
766 case REQ_OP_FLUSH:
8093f7ca 767 nvme_setup_flush(ns, cmd);
aebf526b 768 break;
e850fd16 769 case REQ_OP_WRITE_ZEROES:
6e02318e
CK		 770 ret = nvme_setup_write_zeroes(ns, req, cmd);
771 break;
aebf526b 772 case REQ_OP_DISCARD:
8093f7ca 773 ret = nvme_setup_discard(ns, req, cmd);
aebf526b
CH		 774 break;
775 case REQ_OP_READ:
776 case REQ_OP_WRITE:
ebe6d874 777 ret = nvme_setup_rw(ns, req, cmd);
aebf526b
CH		 778 break;
779 default:
780 WARN_ON_ONCE(1);
fc17b653 781 return BLK_STS_IOERR;
aebf526b 782 }
8093f7ca 783
721b3917 784 cmd->common.command_id = req->tag;
5d87eb94 785 trace_nvme_setup_cmd(req, cmd);
8093f7ca
ML		 786 return ret;
787}
788EXPORT_SYMBOL_GPL(nvme_setup_cmd);
789
6287b51c
SG		 790static void nvme_end_sync_rq(struct request *rq, blk_status_t error)
791{
792 struct completion *waiting = rq->end_io_data;
793
794 rq->end_io_data = NULL;
795 complete(waiting);
796}
797
798static void nvme_execute_rq_polled(struct request_queue *q,
799 struct gendisk *bd_disk, struct request *rq, int at_head)
800{
801 DECLARE_COMPLETION_ONSTACK(wait);
802
803 WARN_ON_ONCE(!test_bit(QUEUE_FLAG_POLL, &q->queue_flags));
804
805 rq->cmd_flags |= REQ_HIPRI;
806 rq->end_io_data = &wait;
807 blk_execute_rq_nowait(q, bd_disk, rq, at_head, nvme_end_sync_rq);
808
809 while (!completion_done(&wait)) {
810 blk_poll(q, request_to_qc_t(rq->mq_hctx, rq), true);
811 cond_resched();
812 }
813}
814
4160982e
CH		 815/*
816 * Returns 0 on success. If the result is negative, it's a Linux error code;
817 * if the result is positive, it's an NVM Express status code
818 */
819int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 820 union nvme_result *result, void *buffer, unsigned bufflen,
9a95e4ef 821 unsigned timeout, int qid, int at_head,
6287b51c 822 blk_mq_req_flags_t flags, bool poll)
4160982e
CH		 823{
824 struct request *req;
825 int ret;
826
eb71f435 827 req = nvme_alloc_request(q, cmd, flags, qid);
4160982e
CH		 828 if (IS_ERR(req))
829 return PTR_ERR(req);
830
831 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
832
21d34711
CH		 833 if (buffer && bufflen) {
834 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
835 if (ret)
836 goto out;
4160982e
CH		 837 }
838
6287b51c
SG		 839 if (poll)
840 nvme_execute_rq_polled(req->q, NULL, req, at_head);
841 else
842 blk_execute_rq(req->q, NULL, req, at_head);
d49187e9
CH		 843 if (result)
844 *result = nvme_req(req)->result;
27fa9bc5
CH		 845 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
846 ret = -EINTR;
847 else
848 ret = nvme_req(req)->status;
4160982e
CH		 849 out:
850 blk_mq_free_request(req);
851 return ret;
852}
eb71f435 853EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH		 854
855int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
856 void *buffer, unsigned bufflen)
857{
eb71f435 858 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 0,
6287b51c 859 NVME_QID_ANY, 0, 0, false);
4160982e 860}
576d55d6 861EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 862
1cad6562
CH		 863static void *nvme_add_user_metadata(struct bio *bio, void __user *ubuf,
864 unsigned len, u32 seed, bool write)
865{
866 struct bio_integrity_payload *bip;
867 int ret = -ENOMEM;
868 void *buf;
869
870 buf = kmalloc(len, GFP_KERNEL);
871 if (!buf)
872 goto out;
873
874 ret = -EFAULT;
875 if (write && copy_from_user(buf, ubuf, len))
876 goto out_free_meta;
877
878 bip = bio_integrity_alloc(bio, GFP_KERNEL, 1);
879 if (IS_ERR(bip)) {
880 ret = PTR_ERR(bip);
881 goto out_free_meta;
882 }
883
884 bip->bip_iter.bi_size = len;
885 bip->bip_iter.bi_sector = seed;
886 ret = bio_integrity_add_page(bio, virt_to_page(buf), len,
887 offset_in_page(buf));
888 if (ret == len)
889 return buf;
890 ret = -ENOMEM;
891out_free_meta:
892 kfree(buf);
893out:
894 return ERR_PTR(ret);
895}
896
63263d60 897static int nvme_submit_user_cmd(struct request_queue *q,
485783ca
KB		 898 struct nvme_command *cmd, void __user *ubuffer,
899 unsigned bufflen, void __user *meta_buffer, unsigned meta_len,
65e68edc 900 u32 meta_seed, u64 *result, unsigned timeout)
4160982e 901{
7a5abb4b 902 bool write = nvme_is_write(cmd);
0b7f1f26
KB		 903 struct nvme_ns *ns = q->queuedata;
904 struct gendisk *disk = ns ? ns->disk : NULL;
4160982e 905 struct request *req;
0b7f1f26
KB		 906 struct bio *bio = NULL;
907 void *meta = NULL;
4160982e
CH		 908 int ret;
909
eb71f435 910 req = nvme_alloc_request(q, cmd, 0, NVME_QID_ANY);
4160982e
CH		 911 if (IS_ERR(req))
912 return PTR_ERR(req);
913
914 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
bb06ec31 915 nvme_req(req)->flags |= NVME_REQ_USERCMD;
4160982e
CH		 916
917 if (ubuffer && bufflen) {
21d34711
CH		 918 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
919 GFP_KERNEL);
920 if (ret)
921 goto out;
922 bio = req->bio;
74d46992 923 bio->bi_disk = disk;
1cad6562
CH		 924 if (disk && meta_buffer && meta_len) {
925 meta = nvme_add_user_metadata(bio, meta_buffer, meta_len,
926 meta_seed, write);
927 if (IS_ERR(meta)) {
928 ret = PTR_ERR(meta);
0b7f1f26
KB		 929 goto out_unmap;
930 }
f31a2110 931 req->cmd_flags |= REQ_INTEGRITY;
0b7f1f26
KB		 932 }
933 }
1cad6562 934
0b7f1f26 935 blk_execute_rq(req->q, disk, req, 0);
27fa9bc5
CH		 936 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
937 ret = -EINTR;
938 else
939 ret = nvme_req(req)->status;
21d34711 940 if (result)
65e68edc 941 *result = le64_to_cpu(nvme_req(req)->result.u64);
0b7f1f26
KB		 942 if (meta && !ret && !write) {
943 if (copy_to_user(meta_buffer, meta, meta_len))
944 ret = -EFAULT;
945 }
0b7f1f26
KB		 946 kfree(meta);
947 out_unmap:
74d46992 948 if (bio)
0b7f1f26 949 blk_rq_unmap_user(bio);
21d34711
CH		 950 out:
951 blk_mq_free_request(req);
952 return ret;
953}
954
2a842aca 955static void nvme_keep_alive_end_io(struct request *rq, blk_status_t status)
038bd4cb
SG		 956{
957 struct nvme_ctrl *ctrl = rq->end_io_data;
86880d64
JS		 958 unsigned long flags;
959 bool startka = false;
038bd4cb
SG		 960
961 blk_mq_free_request(rq);
962
2a842aca 963 if (status) {
038bd4cb 964 dev_err(ctrl->device,
2a842aca
CH		 965 "failed nvme_keep_alive_end_io error=%d\n",
966 status);
038bd4cb
SG		 967 return;
968 }
969
6e3ca03e 970 ctrl->comp_seen = false;
86880d64
JS		 971 spin_lock_irqsave(&ctrl->lock, flags);
972 if (ctrl->state == NVME_CTRL_LIVE ||
973 ctrl->state == NVME_CTRL_CONNECTING)
974 startka = true;
975 spin_unlock_irqrestore(&ctrl->lock, flags);
976 if (startka)
977 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
038bd4cb
SG		 978}
979
980static int nvme_keep_alive(struct nvme_ctrl *ctrl)
981{
038bd4cb
SG		 982 struct request *rq;
983
0a34e466 984 rq = nvme_alloc_request(ctrl->admin_q, &ctrl->ka_cmd, BLK_MQ_REQ_RESERVED,
038bd4cb
SG		 985 NVME_QID_ANY);
986 if (IS_ERR(rq))
987 return PTR_ERR(rq);
988
989 rq->timeout = ctrl->kato * HZ;
990 rq->end_io_data = ctrl;
991
992 blk_execute_rq_nowait(rq->q, NULL, rq, 0, nvme_keep_alive_end_io);
993
994 return 0;
995}
996
997static void nvme_keep_alive_work(struct work_struct *work)
998{
999 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
1000 struct nvme_ctrl, ka_work);
6e3ca03e
SG		 1001 bool comp_seen = ctrl->comp_seen;
1002
1003 if ((ctrl->ctratt & NVME_CTRL_ATTR_TBKAS) && comp_seen) {
1004 dev_dbg(ctrl->device,
1005 "reschedule traffic based keep-alive timer\n");
1006 ctrl->comp_seen = false;
1007 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
1008 return;
1009 }
038bd4cb
SG		 1010
1011 if (nvme_keep_alive(ctrl)) {
1012 /* allocation failure, reset the controller */
1013 dev_err(ctrl->device, "keep-alive failed\n");
39bdc590 1014 nvme_reset_ctrl(ctrl);
038bd4cb
SG		 1015 return;
1016 }
1017}
1018
00b683db 1019static void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
038bd4cb
SG		 1020{
1021 if (unlikely(ctrl->kato == 0))
1022 return;
1023
038bd4cb
SG		 1024 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
1025}
038bd4cb
SG		 1026
1027void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
1028{
1029 if (unlikely(ctrl->kato == 0))
1030 return;
1031
1032 cancel_delayed_work_sync(&ctrl->ka_work);
1033}
1034EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
1035
3f7f25a9 1036static int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH		 1037{
1038 struct nvme_command c = { };
1039 int error;
1040
1041 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1042 c.identify.opcode = nvme_admin_identify;
986994a2 1043 c.identify.cns = NVME_ID_CNS_CTRL;
21d34711
CH		 1044
1045 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1046 if (!*id)
1047 return -ENOMEM;
1048
1049 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1050 sizeof(struct nvme_id_ctrl));
1051 if (error)
1052 kfree(*id);
1053 return error;
1054}
1055
cdbff4f2 1056static int nvme_identify_ns_descs(struct nvme_ctrl *ctrl, unsigned nsid,
002fab04 1057 struct nvme_ns_ids *ids)
3b22ba26
JT		 1058{
1059 struct nvme_command c = { };
1060 int status;
1061 void *data;
1062 int pos;
1063 int len;
1064
1065 c.identify.opcode = nvme_admin_identify;
1066 c.identify.nsid = cpu_to_le32(nsid);
1067 c.identify.cns = NVME_ID_CNS_NS_DESC_LIST;
1068
1069 data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
1070 if (!data)
1071 return -ENOMEM;
1072
cdbff4f2 1073 status = nvme_submit_sync_cmd(ctrl->admin_q, &c, data,
3b22ba26
JT		 1074 NVME_IDENTIFY_DATA_SIZE);
1075 if (status)
1076 goto free_data;
1077
1078 for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) {
1079 struct nvme_ns_id_desc *cur = data + pos;
1080
1081 if (cur->nidl == 0)
1082 break;
1083
1084 switch (cur->nidt) {
1085 case NVME_NIDT_EUI64:
1086 if (cur->nidl != NVME_NIDT_EUI64_LEN) {
cdbff4f2 1087 dev_warn(ctrl->device,
3b22ba26
JT		 1088 "ctrl returned bogus length: %d for NVME_NIDT_EUI64\n",
1089 cur->nidl);
1090 goto free_data;
1091 }
1092 len = NVME_NIDT_EUI64_LEN;
002fab04 1093 memcpy(ids->eui64, data + pos + sizeof(*cur), len);
3b22ba26
JT		 1094 break;
1095 case NVME_NIDT_NGUID:
1096 if (cur->nidl != NVME_NIDT_NGUID_LEN) {
cdbff4f2 1097 dev_warn(ctrl->device,
3b22ba26
JT		 1098 "ctrl returned bogus length: %d for NVME_NIDT_NGUID\n",
1099 cur->nidl);
1100 goto free_data;
1101 }
1102 len = NVME_NIDT_NGUID_LEN;
002fab04 1103 memcpy(ids->nguid, data + pos + sizeof(*cur), len);
3b22ba26
JT		 1104 break;
1105 case NVME_NIDT_UUID:
1106 if (cur->nidl != NVME_NIDT_UUID_LEN) {
cdbff4f2 1107 dev_warn(ctrl->device,
3b22ba26
JT		 1108 "ctrl returned bogus length: %d for NVME_NIDT_UUID\n",
1109 cur->nidl);
1110 goto free_data;
1111 }
1112 len = NVME_NIDT_UUID_LEN;
002fab04 1113 uuid_copy(&ids->uuid, data + pos + sizeof(*cur));
3b22ba26
JT		 1114 break;
1115 default:
53b3a661 1116 /* Skip unknown types */
3b22ba26
JT		 1117 len = cur->nidl;
1118 break;
1119 }
1120
1121 len += sizeof(*cur);
1122 }
1123free_data:
1124 kfree(data);
1125 return status;
1126}
1127
540c801c
KB		 1128static int nvme_identify_ns_list(struct nvme_ctrl *dev, unsigned nsid, __le32 *ns_list)
1129{
1130 struct nvme_command c = { };
1131
1132 c.identify.opcode = nvme_admin_identify;
986994a2 1133 c.identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST;
540c801c 1134 c.identify.nsid = cpu_to_le32(nsid);
42595eb7
MI		 1135 return nvme_submit_sync_cmd(dev->admin_q, &c, ns_list,
1136 NVME_IDENTIFY_DATA_SIZE);
540c801c
KB		 1137}
1138
331813f6
SG		 1139static int nvme_identify_ns(struct nvme_ctrl *ctrl,
1140 unsigned nsid, struct nvme_id_ns **id)
21d34711
CH		 1141{
1142 struct nvme_command c = { };
1143 int error;
1144
1145 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
778f067c
MG		 1146 c.identify.opcode = nvme_admin_identify;
1147 c.identify.nsid = cpu_to_le32(nsid);
986994a2 1148 c.identify.cns = NVME_ID_CNS_NS;
21d34711 1149
331813f6
SG		 1150 *id = kmalloc(sizeof(**id), GFP_KERNEL);
1151 if (!*id)
1152 return -ENOMEM;
21d34711 1153
331813f6 1154 error = nvme_submit_sync_cmd(ctrl->admin_q, &c, *id, sizeof(**id));
cdbff4f2 1155 if (error) {
d0de579c 1156 dev_warn(ctrl->device, "Identify namespace failed (%d)\n", error);
331813f6 1157 kfree(*id);
cdbff4f2
CH		 1158 }
1159
331813f6 1160 return error;
21d34711
CH		 1161}
1162
1a87ee65
KB		 1163static int nvme_features(struct nvme_ctrl *dev, u8 op, unsigned int fid,
1164 unsigned int dword11, void *buffer, size_t buflen, u32 *result)
21d34711
CH		 1165{
1166 struct nvme_command c;
d49187e9 1167 union nvme_result res;
1cb3cce5 1168 int ret;
21d34711
CH		 1169
1170 memset(&c, 0, sizeof(c));
1a87ee65 1171 c.features.opcode = op;
21d34711
CH		 1172 c.features.fid = cpu_to_le32(fid);
1173 c.features.dword11 = cpu_to_le32(dword11);
1174
d49187e9 1175 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
6287b51c 1176 buffer, buflen, 0, NVME_QID_ANY, 0, 0, false);
9b47f77a 1177 if (ret >= 0 && result)
d49187e9 1178 *result = le32_to_cpu(res.u32);
1cb3cce5 1179 return ret;
21d34711
CH		 1180}
1181
1a87ee65
KB		 1182int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid,
1183 unsigned int dword11, void *buffer, size_t buflen,
1184 u32 *result)
1185{
1186 return nvme_features(dev, nvme_admin_set_features, fid, dword11, buffer,
1187 buflen, result);
1188}
1189EXPORT_SYMBOL_GPL(nvme_set_features);
1190
1191int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid,
1192 unsigned int dword11, void *buffer, size_t buflen,
1193 u32 *result)
1194{
1195 return nvme_features(dev, nvme_admin_get_features, fid, dword11, buffer,
1196 buflen, result);
1197}
1198EXPORT_SYMBOL_GPL(nvme_get_features);
1199
9a0be7ab
CH		 1200int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
1201{
1202 u32 q_count = (*count - 1) | ((*count - 1) << 16);
1203 u32 result;
1204 int status, nr_io_queues;
1205
1a6fe74d 1206 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 1207 &result);
f5fa90dc 1208 if (status < 0)
9a0be7ab
CH		 1209 return status;
1210
f5fa90dc
CH		 1211 /*
1212 * Degraded controllers might return an error when setting the queue
1213 * count. We still want to be able to bring them online and offer
1214 * access to the admin queue, as that might be only way to fix them up.
1215 */
1216 if (status > 0) {
f0425db0 1217 dev_err(ctrl->device, "Could not set queue count (%d)\n", status);
f5fa90dc
CH		 1218 *count = 0;
1219 } else {
1220 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
1221 *count = min(*count, nr_io_queues);
1222 }
1223
9a0be7ab
CH		 1224 return 0;
1225}
576d55d6 1226EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 1227
c0561f82 1228#define NVME_AEN_SUPPORTED \
85f8a435
SG		 1229 (NVME_AEN_CFG_NS_ATTR | NVME_AEN_CFG_FW_ACT | \
1230 NVME_AEN_CFG_ANA_CHANGE | NVME_AEN_CFG_DISC_CHANGE)
c0561f82
HR		 1231
1232static void nvme_enable_aen(struct nvme_ctrl *ctrl)
1233{
fa441b71 1234 u32 result, supported_aens = ctrl->oaes & NVME_AEN_SUPPORTED;
c0561f82
HR		 1235 int status;
1236
fa441b71
WZ		 1237 if (!supported_aens)
1238 return;
1239
1240 status = nvme_set_features(ctrl, NVME_FEAT_ASYNC_EVENT, supported_aens,
1241 NULL, 0, &result);
c0561f82
HR		 1242 if (status)
1243 dev_warn(ctrl->device, "Failed to configure AEN (cfg %x)\n",
fa441b71 1244 supported_aens);
93da4023
SG		 1245
1246 queue_work(nvme_wq, &ctrl->async_event_work);
c0561f82
HR		 1247}
1248
1673f1f0
CH		 1249static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1250{
1251 struct nvme_user_io io;
1252 struct nvme_command c;
1253 unsigned length, meta_len;
1254 void __user *metadata;
1255
1256 if (copy_from_user(&io, uio, sizeof(io)))
1257 return -EFAULT;
63088ec7
KB		 1258 if (io.flags)
1259 return -EINVAL;
1673f1f0
CH		 1260
1261 switch (io.opcode) {
1262 case nvme_cmd_write:
1263 case nvme_cmd_read:
1264 case nvme_cmd_compare:
1265 break;
1266 default:
1267 return -EINVAL;
1268 }
1269
1270 length = (io.nblocks + 1) << ns->lba_shift;
1271 meta_len = (io.nblocks + 1) * ns->ms;
1272 metadata = (void __user *)(uintptr_t)io.metadata;
1273
1274 if (ns->ext) {
1275 length += meta_len;
1276 meta_len = 0;
1277 } else if (meta_len) {
1278 if ((io.metadata & 3) || !io.metadata)
1279 return -EINVAL;
1280 }
1281
1282 memset(&c, 0, sizeof(c));
1283 c.rw.opcode = io.opcode;
1284 c.rw.flags = io.flags;
ed754e5d 1285 c.rw.nsid = cpu_to_le32(ns->head->ns_id);
1673f1f0
CH		 1286 c.rw.slba = cpu_to_le64(io.slba);
1287 c.rw.length = cpu_to_le16(io.nblocks);
1288 c.rw.control = cpu_to_le16(io.control);
1289 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1290 c.rw.reftag = cpu_to_le32(io.reftag);
1291 c.rw.apptag = cpu_to_le16(io.apptag);
1292 c.rw.appmask = cpu_to_le16(io.appmask);
1293
63263d60 1294 return nvme_submit_user_cmd(ns->queue, &c,
1673f1f0 1295 (void __user *)(uintptr_t)io.addr, length,
202359c0 1296 metadata, meta_len, lower_32_bits(io.slba), NULL, 0);
1673f1f0
CH		 1297}
1298
84fef62d
KB		 1299static u32 nvme_known_admin_effects(u8 opcode)
1300{
1301 switch (opcode) {
1302 case nvme_admin_format_nvm:
1303 return NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC |
1304 NVME_CMD_EFFECTS_CSE_MASK;
1305 case nvme_admin_sanitize_nvm:
1306 return NVME_CMD_EFFECTS_CSE_MASK;
1307 default:
1308 break;
1309 }
1310 return 0;
1311}
1312
1313static u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1314 u8 opcode)
1315{
1316 u32 effects = 0;
1317
1318 if (ns) {
1319 if (ctrl->effects)
1320 effects = le32_to_cpu(ctrl->effects->iocs[opcode]);
415df90b 1321 if (effects & ~(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC))
84fef62d
KB		 1322 dev_warn(ctrl->device,
1323 "IO command:%02x has unhandled effects:%08x\n",
1324 opcode, effects);
1325 return 0;
1326 }
1327
1328 if (ctrl->effects)
62843c2e 1329 effects = le32_to_cpu(ctrl->effects->acs[opcode]);
6fa0321a 1330 effects |= nvme_known_admin_effects(opcode);
84fef62d
KB		 1331
1332 /*
1333 * For simplicity, IO to all namespaces is quiesced even if the command
1334 * effects say only one namespace is affected.
1335 */
1336 if (effects & (NVME_CMD_EFFECTS_LBCC | NVME_CMD_EFFECTS_CSE_MASK)) {
e7ad43c3 1337 mutex_lock(&ctrl->scan_lock);
b9156dae
SG		 1338 mutex_lock(&ctrl->subsys->lock);
1339 nvme_mpath_start_freeze(ctrl->subsys);
1340 nvme_mpath_wait_freeze(ctrl->subsys);
84fef62d
KB		 1341 nvme_start_freeze(ctrl);
1342 nvme_wait_freeze(ctrl);
1343 }
1344 return effects;
1345}
1346
1347static void nvme_update_formats(struct nvme_ctrl *ctrl)
1348{
cf39a6bc 1349 struct nvme_ns *ns;
84fef62d 1350
cf39a6bc
SB		 1351 down_read(&ctrl->namespaces_rwsem);
1352 list_for_each_entry(ns, &ctrl->namespaces, list)
1353 if (ns->disk && nvme_revalidate_disk(ns->disk))
1354 nvme_set_queue_dying(ns);
1355 up_read(&ctrl->namespaces_rwsem);
84fef62d
KB		 1356}
1357
1358static void nvme_passthru_end(struct nvme_ctrl *ctrl, u32 effects)
1359{
1360 /*
1361 * Revalidate LBA changes prior to unfreezing. This is necessary to
1362 * prevent memory corruption if a logical block size was changed by
1363 * this command.
1364 */
1365 if (effects & NVME_CMD_EFFECTS_LBCC)
1366 nvme_update_formats(ctrl);
e7ad43c3 1367 if (effects & (NVME_CMD_EFFECTS_LBCC | NVME_CMD_EFFECTS_CSE_MASK)) {
84fef62d 1368 nvme_unfreeze(ctrl);
b9156dae
SG		 1369 nvme_mpath_unfreeze(ctrl->subsys);
1370 mutex_unlock(&ctrl->subsys->lock);
6abff1b9 1371 nvme_remove_invalid_namespaces(ctrl, NVME_NSID_ALL);
e7ad43c3
KB		 1372 mutex_unlock(&ctrl->scan_lock);
1373 }
84fef62d
KB		 1374 if (effects & NVME_CMD_EFFECTS_CCC)
1375 nvme_init_identify(ctrl);
1376 if (effects & (NVME_CMD_EFFECTS_NIC | NVME_CMD_EFFECTS_NCC))
1377 nvme_queue_scan(ctrl);
1378}
1379
f3ca80fc 1380static int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1673f1f0
CH		 1381 struct nvme_passthru_cmd __user *ucmd)
1382{
1383 struct nvme_passthru_cmd cmd;
1384 struct nvme_command c;
1385 unsigned timeout = 0;
84fef62d 1386 u32 effects;
65e68edc
MR		 1387 u64 result;
1388 int status;
1389
1390 if (!capable(CAP_SYS_ADMIN))
1391 return -EACCES;
1392 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1393 return -EFAULT;
1394 if (cmd.flags)
1395 return -EINVAL;
1396
1397 memset(&c, 0, sizeof(c));
1398 c.common.opcode = cmd.opcode;
1399 c.common.flags = cmd.flags;
1400 c.common.nsid = cpu_to_le32(cmd.nsid);
1401 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1402 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1403 c.common.cdw10 = cpu_to_le32(cmd.cdw10);
1404 c.common.cdw11 = cpu_to_le32(cmd.cdw11);
1405 c.common.cdw12 = cpu_to_le32(cmd.cdw12);
1406 c.common.cdw13 = cpu_to_le32(cmd.cdw13);
1407 c.common.cdw14 = cpu_to_le32(cmd.cdw14);
1408 c.common.cdw15 = cpu_to_le32(cmd.cdw15);
1409
1410 if (cmd.timeout_ms)
1411 timeout = msecs_to_jiffies(cmd.timeout_ms);
1412
1413 effects = nvme_passthru_start(ctrl, ns, cmd.opcode);
1414 status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c,
1415 (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
1416 (void __user *)(uintptr_t)cmd.metadata,
1417 cmd.metadata_len, 0, &result, timeout);
1418 nvme_passthru_end(ctrl, effects);
1419
1420 if (status >= 0) {
1421 if (put_user(result, &ucmd->result))
1422 return -EFAULT;
1423 }
1424
1425 return status;
1426}
1427
1428static int nvme_user_cmd64(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1429 struct nvme_passthru_cmd64 __user *ucmd)
1430{
1431 struct nvme_passthru_cmd64 cmd;
1432 struct nvme_command c;
1433 unsigned timeout = 0;
1434 u32 effects;
1673f1f0
CH		 1435 int status;
1436
1437 if (!capable(CAP_SYS_ADMIN))
1438 return -EACCES;
1439 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1440 return -EFAULT;
63088ec7
KB		 1441 if (cmd.flags)
1442 return -EINVAL;
1673f1f0
CH		 1443
1444 memset(&c, 0, sizeof(c));
1445 c.common.opcode = cmd.opcode;
1446 c.common.flags = cmd.flags;
1447 c.common.nsid = cpu_to_le32(cmd.nsid);
1448 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1449 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
b7c8f366
CK		 1450 c.common.cdw10 = cpu_to_le32(cmd.cdw10);
1451 c.common.cdw11 = cpu_to_le32(cmd.cdw11);
1452 c.common.cdw12 = cpu_to_le32(cmd.cdw12);
1453 c.common.cdw13 = cpu_to_le32(cmd.cdw13);
1454 c.common.cdw14 = cpu_to_le32(cmd.cdw14);
1455 c.common.cdw15 = cpu_to_le32(cmd.cdw15);
1673f1f0
CH		 1456
1457 if (cmd.timeout_ms)
1458 timeout = msecs_to_jiffies(cmd.timeout_ms);
1459
84fef62d 1460 effects = nvme_passthru_start(ctrl, ns, cmd.opcode);
1673f1f0 1461 status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c,
d1ea7be5 1462 (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
9b382768 1463 (void __user *)(uintptr_t)cmd.metadata, cmd.metadata_len,
63263d60 1464 0, &cmd.result, timeout);
84fef62d
KB		 1465 nvme_passthru_end(ctrl, effects);
1466
1673f1f0
CH		 1467 if (status >= 0) {
1468 if (put_user(cmd.result, &ucmd->result))
1469 return -EFAULT;
1470 }
1471
1472 return status;
1473}
1474
32acab31
CH		 1475/*
1476 * Issue ioctl requests on the first available path. Note that unlike normal
1477 * block layer requests we will not retry failed request on another controller.
1478 */
1479static struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk,
1480 struct nvme_ns_head **head, int *srcu_idx)
1673f1f0 1481{
32acab31
CH		 1482#ifdef CONFIG_NVME_MULTIPATH
1483 if (disk->fops == &nvme_ns_head_ops) {
100c815c
CH		 1484 struct nvme_ns *ns;
1485
32acab31
CH		 1486 *head = disk->private_data;
1487 *srcu_idx = srcu_read_lock(&(*head)->srcu);
100c815c
CH		 1488 ns = nvme_find_path(*head);
1489 if (!ns)
1490 srcu_read_unlock(&(*head)->srcu, *srcu_idx);
1491 return ns;
32acab31
CH		 1492 }
1493#endif
1494 *head = NULL;
1495 *srcu_idx = -1;
1496 return disk->private_data;
1497}
1673f1f0 1498
32acab31
CH		 1499static void nvme_put_ns_from_disk(struct nvme_ns_head *head, int idx)
1500{
1501 if (head)
1502 srcu_read_unlock(&head->srcu, idx);
1503}
1673f1f0 1504
65e68edc
MR		 1505static bool is_ctrl_ioctl(unsigned int cmd)
1506{
1507 if (cmd == NVME_IOCTL_ADMIN_CMD || cmd == NVME_IOCTL_ADMIN64_CMD)
1508 return true;
1509 if (is_sed_ioctl(cmd))
1510 return true;
1511 return false;
1512}
1513
1514static int nvme_handle_ctrl_ioctl(struct nvme_ns *ns, unsigned int cmd,
1515 void __user *argp,
1516 struct nvme_ns_head *head,
1517 int srcu_idx)
1518{
1519 struct nvme_ctrl *ctrl = ns->ctrl;
1520 int ret;
1521
1522 nvme_get_ctrl(ns->ctrl);
1523 nvme_put_ns_from_disk(head, srcu_idx);
1524
1525 switch (cmd) {
1526 case NVME_IOCTL_ADMIN_CMD:
1527 ret = nvme_user_cmd(ctrl, NULL, argp);
1528 break;
1529 case NVME_IOCTL_ADMIN64_CMD:
1530 ret = nvme_user_cmd64(ctrl, NULL, argp);
1531 break;
1532 default:
1533 ret = sed_ioctl(ctrl->opal_dev, cmd, argp);
1534 break;
1535 }
1536 nvme_put_ctrl(ctrl);
1537 return ret;
1538}
1539
32acab31
CH		 1540static int nvme_ioctl(struct block_device *bdev, fmode_t mode,
1541 unsigned int cmd, unsigned long arg)
1673f1f0 1542{
32acab31 1543 struct nvme_ns_head *head = NULL;
90ec611a 1544 void __user *argp = (void __user *)arg;
32acab31
CH		 1545 struct nvme_ns *ns;
1546 int srcu_idx, ret;
1547
1548 ns = nvme_get_ns_from_disk(bdev->bd_disk, &head, &srcu_idx);
1549 if (unlikely(!ns))
100c815c
CH		 1550 return -EWOULDBLOCK;
1551
5fb4aac7
CH		 1552 /*
1553 * Handle ioctls that apply to the controller instead of the namespace
1554 * seperately and drop the ns SRCU reference early. This avoids a
1555 * deadlock when deleting namespaces using the passthrough interface.
1556 */
65e68edc
MR		 1557 if (is_ctrl_ioctl(cmd))
1558 return nvme_handle_ctrl_ioctl(ns, cmd, argp, head, srcu_idx);
5fb4aac7 1559
90ec611a
CH		 1560 switch (cmd) {
1561 case NVME_IOCTL_ID:
1562 force_successful_syscall_return();
1563 ret = ns->head->ns_id;
1564 break;
90ec611a
CH		 1565 case NVME_IOCTL_IO_CMD:
1566 ret = nvme_user_cmd(ns->ctrl, ns, argp);
1567 break;
1568 case NVME_IOCTL_SUBMIT_IO:
1569 ret = nvme_submit_io(ns, argp);
1570 break;
65e68edc
MR		 1571 case NVME_IOCTL_IO64_CMD:
1572 ret = nvme_user_cmd64(ns->ctrl, ns, argp);
1573 break;
90ec611a
CH		 1574 default:
1575 if (ns->ndev)
1576 ret = nvme_nvm_ioctl(ns, cmd, arg);
90ec611a
CH		 1577 else
1578 ret = -ENOTTY;
1579 }
1580
32acab31
CH		 1581 nvme_put_ns_from_disk(head, srcu_idx);
1582 return ret;
1673f1f0 1583}
1673f1f0
CH		 1584
1585static int nvme_open(struct block_device *bdev, fmode_t mode)
1586{
c6424a90
CH		 1587 struct nvme_ns *ns = bdev->bd_disk->private_data;
1588
32acab31
CH		 1589#ifdef CONFIG_NVME_MULTIPATH
1590 /* should never be called due to GENHD_FL_HIDDEN */
1591 if (WARN_ON_ONCE(ns->head->disk))
85088c4a 1592 goto fail;
32acab31 1593#endif
c6424a90 1594 if (!kref_get_unless_zero(&ns->kref))
85088c4a
NC		 1595 goto fail;
1596 if (!try_module_get(ns->ctrl->ops->module))
1597 goto fail_put_ns;
1598
c6424a90 1599 return 0;
85088c4a
NC		 1600
1601fail_put_ns:
1602 nvme_put_ns(ns);
1603fail:
1604 return -ENXIO;
1673f1f0
CH		 1605}
1606
1607static void nvme_release(struct gendisk *disk, fmode_t mode)
1608{
85088c4a
NC		 1609 struct nvme_ns *ns = disk->private_data;
1610
1611 module_put(ns->ctrl->ops->module);
1612 nvme_put_ns(ns);
1673f1f0
CH		 1613}
1614
1615static int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1616{
1617 /* some standard values */
1618 geo->heads = 1 << 6;
1619 geo->sectors = 1 << 5;
1620 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
1621 return 0;
1622}
1623
1624#ifdef CONFIG_BLK_DEV_INTEGRITY
39b7baa4 1625static void nvme_init_integrity(struct gendisk *disk, u16 ms, u8 pi_type)
1673f1f0
CH		 1626{
1627 struct blk_integrity integrity;
1628
fa9a89fc 1629 memset(&integrity, 0, sizeof(integrity));
39b7baa4 1630 switch (pi_type) {
1673f1f0
CH		 1631 case NVME_NS_DPS_PI_TYPE3:
1632 integrity.profile = &t10_pi_type3_crc;
ba36c21b
NB		 1633 integrity.tag_size = sizeof(u16) + sizeof(u32);
1634 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1635 break;
1636 case NVME_NS_DPS_PI_TYPE1:
1637 case NVME_NS_DPS_PI_TYPE2:
1638 integrity.profile = &t10_pi_type1_crc;
ba36c21b
NB		 1639 integrity.tag_size = sizeof(u16);
1640 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1641 break;
1642 default:
1643 integrity.profile = NULL;
1644 break;
1645 }
39b7baa4
CH		 1646 integrity.tuple_size = ms;
1647 blk_integrity_register(disk, &integrity);
1648 blk_queue_max_integrity_segments(disk->queue, 1);
1673f1f0
CH		 1649}
1650#else
39b7baa4 1651static void nvme_init_integrity(struct gendisk *disk, u16 ms, u8 pi_type)
1673f1f0
CH		 1652{
1653}
1654#endif /* CONFIG_BLK_DEV_INTEGRITY */
1655
6b8190d6
SB		 1656static void nvme_set_chunk_size(struct nvme_ns *ns)
1657{
e08f2ae8 1658 u32 chunk_size = nvme_lba_to_sect(ns, ns->noiob);
6b8190d6
SB		 1659 blk_queue_chunk_sectors(ns->queue, rounddown_pow_of_two(chunk_size));
1660}
1661
26318571 1662static void nvme_config_discard(struct gendisk *disk, struct nvme_ns *ns)
1673f1f0 1663{
3831761e 1664 struct nvme_ctrl *ctrl = ns->ctrl;
26318571 1665 struct request_queue *queue = disk->queue;
30e5e929
CH		 1666 u32 size = queue_logical_block_size(queue);
1667
3831761e
JA		 1668 if (!(ctrl->oncs & NVME_CTRL_ONCS_DSM)) {
1669 blk_queue_flag_clear(QUEUE_FLAG_DISCARD, queue);
1670 return;
1671 }
1672
1673 if (ctrl->nr_streams && ns->sws && ns->sgs)
1674 size *= ns->sws * ns->sgs;
08095e70 1675
b35ba01e
CH		 1676 BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) <
1677 NVME_DSM_MAX_RANGES);
1678
b224f613 1679 queue->limits.discard_alignment = 0;
30e5e929 1680 queue->limits.discard_granularity = size;
f5d11840 1681
3831761e
JA		 1682 /* If discard is already enabled, don't reset queue limits */
1683 if (blk_queue_flag_test_and_set(QUEUE_FLAG_DISCARD, queue))
1684 return;
1685
30e5e929
CH		 1686 blk_queue_max_discard_sectors(queue, UINT_MAX);
1687 blk_queue_max_discard_segments(queue, NVME_DSM_MAX_RANGES);
e850fd16
CH		 1688
1689 if (ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
30e5e929 1690 blk_queue_max_write_zeroes_sectors(queue, UINT_MAX);
1673f1f0
CH		 1691}
1692
9f0916ab 1693static void nvme_config_write_zeroes(struct gendisk *disk, struct nvme_ns *ns)
6e02318e 1694{
e08f2ae8 1695 u64 max_blocks;
6e02318e 1696
7b210e4e
CH		 1697 if (!(ns->ctrl->oncs & NVME_CTRL_ONCS_WRITE_ZEROES) ||
1698 (ns->ctrl->quirks & NVME_QUIRK_DISABLE_WRITE_ZEROES))
6e02318e
CK		 1699 return;
1700 /*
1701 * Even though NVMe spec explicitly states that MDTS is not
1702 * applicable to the write-zeroes:- "The restriction does not apply to
1703 * commands that do not transfer data between the host and the
1704 * controller (e.g., Write Uncorrectable ro Write Zeroes command).".
1705 * In order to be more cautious use controller's max_hw_sectors value
1706 * to configure the maximum sectors for the write-zeroes which is
1707 * configured based on the controller's MDTS field in the
1708 * nvme_init_identify() if available.
1709 */
1710 if (ns->ctrl->max_hw_sectors == UINT_MAX)
e08f2ae8 1711 max_blocks = (u64)USHRT_MAX + 1;
6e02318e 1712 else
e08f2ae8 1713 max_blocks = ns->ctrl->max_hw_sectors + 1;
6e02318e 1714
e08f2ae8
DLM		 1715 blk_queue_max_write_zeroes_sectors(disk->queue,
1716 nvme_lba_to_sect(ns, max_blocks));
6e02318e
CK		 1717}
1718
538af88e 1719static int nvme_report_ns_ids(struct nvme_ctrl *ctrl, unsigned int nsid,
002fab04 1720 struct nvme_id_ns *id, struct nvme_ns_ids *ids)
1673f1f0 1721{
538af88e
SG		 1722 int ret = 0;
1723
002fab04
CH		 1724 memset(ids, 0, sizeof(*ids));
1725
cdbff4f2 1726 if (ctrl->vs >= NVME_VS(1, 1, 0))
002fab04 1727 memcpy(ids->eui64, id->eui64, sizeof(id->eui64));
cdbff4f2 1728 if (ctrl->vs >= NVME_VS(1, 2, 0))
002fab04 1729 memcpy(ids->nguid, id->nguid, sizeof(id->nguid));
cdbff4f2 1730 if (ctrl->vs >= NVME_VS(1, 3, 0)) {
3b22ba26
JT		 1731 /* Don't treat error as fatal we potentially
1732 * already have a NGUID or EUI-64
1733 */
538af88e
SG		 1734 ret = nvme_identify_ns_descs(ctrl, nsid, ids);
1735 if (ret)
cdbff4f2 1736 dev_warn(ctrl->device,
538af88e 1737 "Identify Descriptors failed (%d)\n", ret);
22802bf7
KB		 1738 if (ret > 0)
1739 ret = 0;
3b22ba26 1740 }
538af88e 1741 return ret;
ac81bfa9
MB		 1742}
1743
ed754e5d
CH		 1744static bool nvme_ns_ids_valid(struct nvme_ns_ids *ids)
1745{
1746 return !uuid_is_null(&ids->uuid) ||
1747 memchr_inv(ids->nguid, 0, sizeof(ids->nguid)) ||
1748 memchr_inv(ids->eui64, 0, sizeof(ids->eui64));
1749}
1750
002fab04
CH		 1751static bool nvme_ns_ids_equal(struct nvme_ns_ids *a, struct nvme_ns_ids *b)
1752{
1753 return uuid_equal(&a->uuid, &b->uuid) &&
1754 memcmp(&a->nguid, &b->nguid, sizeof(a->nguid)) == 0 &&
1755 memcmp(&a->eui64, &b->eui64, sizeof(a->eui64)) == 0;
1756}
1757
24b0b58c
CH		 1758static void nvme_update_disk_info(struct gendisk *disk,
1759 struct nvme_ns *ns, struct nvme_id_ns *id)
1760{
e08f2ae8 1761 sector_t capacity = nvme_lba_to_sect(ns, le64_to_cpu(id->nsze));
cee160fd 1762 unsigned short bs = 1 << ns->lba_shift;
81adb863 1763 u32 atomic_bs, phys_bs, io_opt;
24b0b58c 1764
01fa0174
SG		 1765 if (ns->lba_shift > PAGE_SHIFT) {
1766 /* unsupported block size, set capacity to 0 later */
1767 bs = (1 << 9);
1768 }
24b0b58c
CH		 1769 blk_mq_freeze_queue(disk->queue);
1770 blk_integrity_unregister(disk);
1771
81adb863
BVA		 1772 if (id->nabo == 0) {
1773 /*
1774 * Bit 1 indicates whether NAWUPF is defined for this namespace
1775 * and whether it should be used instead of AWUPF. If NAWUPF ==
1776 * 0 then AWUPF must be used instead.
1777 */
1778 if (id->nsfeat & (1 << 1) && id->nawupf)
1779 atomic_bs = (1 + le16_to_cpu(id->nawupf)) * bs;
1780 else
1781 atomic_bs = (1 + ns->ctrl->subsys->awupf) * bs;
1782 } else {
1783 atomic_bs = bs;
1784 }
1785 phys_bs = bs;
1786 io_opt = bs;
1787 if (id->nsfeat & (1 << 4)) {
1788 /* NPWG = Namespace Preferred Write Granularity */
1789 phys_bs *= 1 + le16_to_cpu(id->npwg);
1790 /* NOWS = Namespace Optimal Write Size */
1791 io_opt *= 1 + le16_to_cpu(id->nows);
1792 }
1793
cee160fd 1794 blk_queue_logical_block_size(disk->queue, bs);
81adb863
BVA		 1795 /*
1796 * Linux filesystems assume writing a single physical block is
1797 * an atomic operation. Hence limit the physical block size to the
1798 * value of the Atomic Write Unit Power Fail parameter.
1799 */
1800 blk_queue_physical_block_size(disk->queue, min(phys_bs, atomic_bs));
1801 blk_queue_io_min(disk->queue, phys_bs);
1802 blk_queue_io_opt(disk->queue, io_opt);
cee160fd 1803
24b0b58c
CH		 1804 if (ns->ms && !ns->ext &&
1805 (ns->ctrl->ops->flags & NVME_F_METADATA_SUPPORTED))
1806 nvme_init_integrity(disk, ns->ms, ns->pi_type);
01fa0174
SG		 1807 if ((ns->ms && !nvme_ns_has_pi(ns) && !blk_get_integrity(disk)) ||
1808 ns->lba_shift > PAGE_SHIFT)
24b0b58c 1809 capacity = 0;
24b0b58c 1810
3831761e 1811 set_capacity(disk, capacity);
b1aafb35 1812
26318571 1813 nvme_config_discard(disk, ns);
9f0916ab 1814 nvme_config_write_zeroes(disk, ns);
1293477f
CK		 1815
1816 if (id->nsattr & (1 << 0))
1817 set_disk_ro(disk, true);
1818 else
1819 set_disk_ro(disk, false);
1820
24b0b58c
CH		 1821 blk_mq_unfreeze_queue(disk->queue);
1822}
1823
ac81bfa9
MB		 1824static void __nvme_revalidate_disk(struct gendisk *disk, struct nvme_id_ns *id)
1825{
1826 struct nvme_ns *ns = disk->private_data;
1673f1f0
CH		 1827
1828 /*
1829 * If identify namespace failed, use default 512 byte block size so
1830 * block layer can use before failing read/write for 0 capacity.
1831 */
c81bfba9 1832 ns->lba_shift = id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ds;
1673f1f0
CH		 1833 if (ns->lba_shift == 0)
1834 ns->lba_shift = 9;
6b8190d6 1835 ns->noiob = le16_to_cpu(id->noiob);
b5be3b39 1836 ns->ms = le16_to_cpu(id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ms);
c97f414c 1837 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
b5be3b39
CH		 1838 /* the PI implementation requires metadata equal t10 pi tuple size */
1839 if (ns->ms == sizeof(struct t10_pi_tuple))
1840 ns->pi_type = id->dps & NVME_NS_DPS_PI_MASK;
1841 else
1842 ns->pi_type = 0;
1673f1f0 1843
6b8190d6
SB		 1844 if (ns->noiob)
1845 nvme_set_chunk_size(ns);
24b0b58c 1846 nvme_update_disk_info(disk, ns, id);
32acab31 1847#ifdef CONFIG_NVME_MULTIPATH
8f676b85 1848 if (ns->head->disk) {
32acab31 1849 nvme_update_disk_info(ns->head->disk, ns, id);
8f676b85 1850 blk_queue_stack_limits(ns->head->disk->queue, ns->queue);
fab7772b 1851 revalidate_disk(ns->head->disk);
8f676b85 1852 }
32acab31 1853#endif
ac81bfa9 1854}
1673f1f0 1855
ac81bfa9
MB		 1856static int nvme_revalidate_disk(struct gendisk *disk)
1857{
1858 struct nvme_ns *ns = disk->private_data;
cdbff4f2
CH		 1859 struct nvme_ctrl *ctrl = ns->ctrl;
1860 struct nvme_id_ns *id;
002fab04 1861 struct nvme_ns_ids ids;
cdbff4f2 1862 int ret = 0;
ac81bfa9
MB		 1863
1864 if (test_bit(NVME_NS_DEAD, &ns->flags)) {
1865 set_capacity(disk, 0);
1866 return -ENODEV;
1867 }
1868
331813f6
SG		 1869 ret = nvme_identify_ns(ctrl, ns->head->ns_id, &id);
1870 if (ret)
1871 goto out;
ac81bfa9 1872
cdbff4f2
CH		 1873 if (id->ncap == 0) {
1874 ret = -ENODEV;
331813f6 1875 goto free_id;
cdbff4f2 1876 }
ac81bfa9 1877
5e0fab57 1878 __nvme_revalidate_disk(disk, id);
538af88e
SG		 1879 ret = nvme_report_ns_ids(ctrl, ns->head->ns_id, id, &ids);
1880 if (ret)
1881 goto free_id;
1882
ed754e5d 1883 if (!nvme_ns_ids_equal(&ns->head->ids, &ids)) {
1d5df6af 1884 dev_err(ctrl->device,
ed754e5d 1885 "identifiers changed for nsid %d\n", ns->head->ns_id);
1d5df6af
CH		 1886 ret = -ENODEV;
1887 }
1888
331813f6 1889free_id:
cdbff4f2 1890 kfree(id);
331813f6 1891out:
205da243
SG		 1892 /*
1893 * Only fail the function if we got a fatal error back from the
1894 * device, otherwise ignore the error and just move on.
1895 */
1896 if (ret == -ENOMEM || (ret > 0 && !(ret & NVME_SC_DNR)))
1897 ret = 0;
1898 else if (ret > 0)
331813f6 1899 ret = blk_status_to_errno(nvme_error_status(ret));
cdbff4f2 1900 return ret;
1673f1f0
CH		 1901}
1902
1903static char nvme_pr_type(enum pr_type type)
1904{
1905 switch (type) {
1906 case PR_WRITE_EXCLUSIVE:
1907 return 1;
1908 case PR_EXCLUSIVE_ACCESS:
1909 return 2;
1910 case PR_WRITE_EXCLUSIVE_REG_ONLY:
1911 return 3;
1912 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
1913 return 4;
1914 case PR_WRITE_EXCLUSIVE_ALL_REGS:
1915 return 5;
1916 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
1917 return 6;
1918 default:
1919 return 0;
1920 }
1921};
1922
1923static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
1924 u64 key, u64 sa_key, u8 op)
1925{
32acab31
CH		 1926 struct nvme_ns_head *head = NULL;
1927 struct nvme_ns *ns;
1673f1f0 1928 struct nvme_command c;
32acab31 1929 int srcu_idx, ret;
1673f1f0
CH		 1930 u8 data[16] = { 0, };
1931
b0d61d58
KB		 1932 ns = nvme_get_ns_from_disk(bdev->bd_disk, &head, &srcu_idx);
1933 if (unlikely(!ns))
1934 return -EWOULDBLOCK;
1935
1673f1f0
CH		 1936 put_unaligned_le64(key, &data[0]);
1937 put_unaligned_le64(sa_key, &data[8]);
1938
1939 memset(&c, 0, sizeof(c));
1940 c.common.opcode = op;
b0d61d58 1941 c.common.nsid = cpu_to_le32(ns->head->ns_id);
b7c8f366 1942 c.common.cdw10 = cpu_to_le32(cdw10);
1673f1f0 1943
b0d61d58 1944 ret = nvme_submit_sync_cmd(ns->queue, &c, data, 16);
32acab31
CH		 1945 nvme_put_ns_from_disk(head, srcu_idx);
1946 return ret;
1673f1f0
CH		 1947}
1948
1949static int nvme_pr_register(struct block_device *bdev, u64 old,
1950 u64 new, unsigned flags)
1951{
1952 u32 cdw10;
1953
1954 if (flags & ~PR_FL_IGNORE_KEY)
1955 return -EOPNOTSUPP;
1956
1957 cdw10 = old ? 2 : 0;
1958 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
1959 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
1960 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
1961}
1962
1963static int nvme_pr_reserve(struct block_device *bdev, u64 key,
1964 enum pr_type type, unsigned flags)
1965{
1966 u32 cdw10;
1967
1968 if (flags & ~PR_FL_IGNORE_KEY)
1969 return -EOPNOTSUPP;
1970
1971 cdw10 = nvme_pr_type(type) << 8;
1972 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
1973 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
1974}
1975
1976static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
1977 enum pr_type type, bool abort)
1978{
e9a9853c 1979 u32 cdw10 = nvme_pr_type(type) << 8 | (abort ? 2 : 1);
1673f1f0
CH		 1980 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
1981}
1982
1983static int nvme_pr_clear(struct block_device *bdev, u64 key)
1984{
8c0b3915 1985 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
1673f1f0
CH		 1986 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
1987}
1988
1989static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
1990{
e9a9853c 1991 u32 cdw10 = nvme_pr_type(type) << 8 | (key ? 1 << 3 : 0);
1673f1f0
CH		 1992 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
1993}
1994
1995static const struct pr_ops nvme_pr_ops = {
1996 .pr_register = nvme_pr_register,
1997 .pr_reserve = nvme_pr_reserve,
1998 .pr_release = nvme_pr_release,
1999 .pr_preempt = nvme_pr_preempt,
2000 .pr_clear = nvme_pr_clear,
2001};
2002
a98e58e5 2003#ifdef CONFIG_BLK_SED_OPAL
4f1244c8
CH		 2004int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
2005 bool send)
a98e58e5 2006{
4f1244c8 2007 struct nvme_ctrl *ctrl = data;
a98e58e5 2008 struct nvme_command cmd;
a98e58e5
SB		 2009
2010 memset(&cmd, 0, sizeof(cmd));
2011 if (send)
2012 cmd.common.opcode = nvme_admin_security_send;
2013 else
2014 cmd.common.opcode = nvme_admin_security_recv;
a98e58e5 2015 cmd.common.nsid = 0;
b7c8f366
CK		 2016 cmd.common.cdw10 = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
2017 cmd.common.cdw11 = cpu_to_le32(len);
a98e58e5
SB		 2018
2019 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len,
6287b51c 2020 ADMIN_TIMEOUT, NVME_QID_ANY, 1, 0, false);
a98e58e5
SB		 2021}
2022EXPORT_SYMBOL_GPL(nvme_sec_submit);
2023#endif /* CONFIG_BLK_SED_OPAL */
2024
5bae7f73 2025static const struct block_device_operations nvme_fops = {
1673f1f0
CH		 2026 .owner = THIS_MODULE,
2027 .ioctl = nvme_ioctl,
761f2e1e 2028 .compat_ioctl = nvme_ioctl,
1673f1f0
CH		 2029 .open = nvme_open,
2030 .release = nvme_release,
2031 .getgeo = nvme_getgeo,
2032 .revalidate_disk= nvme_revalidate_disk,
2033 .pr_ops = &nvme_pr_ops,
2034};
2035
32acab31
CH		 2036#ifdef CONFIG_NVME_MULTIPATH
2037static int nvme_ns_head_open(struct block_device *bdev, fmode_t mode)
2038{
2039 struct nvme_ns_head *head = bdev->bd_disk->private_data;
2040
2041 if (!kref_get_unless_zero(&head->ref))
2042 return -ENXIO;
2043 return 0;
2044}
2045
2046static void nvme_ns_head_release(struct gendisk *disk, fmode_t mode)
2047{
2048 nvme_put_ns_head(disk->private_data);
2049}
2050
2051const struct block_device_operations nvme_ns_head_ops = {
2052 .owner = THIS_MODULE,
2053 .open = nvme_ns_head_open,
2054 .release = nvme_ns_head_release,
2055 .ioctl = nvme_ioctl,
2056 .compat_ioctl = nvme_ioctl,
2057 .getgeo = nvme_getgeo,
2058 .pr_ops = &nvme_pr_ops,
2059};
2060#endif /* CONFIG_NVME_MULTIPATH */
2061
5fd4ce1b
CH		 2062static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
2063{
2064 unsigned long timeout =
2065 ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
2066 u32 csts, bit = enabled ? NVME_CSTS_RDY : 0;
2067 int ret;
2068
2069 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB		 2070 if (csts == ~0)
2071 return -ENODEV;
5fd4ce1b
CH		 2072 if ((csts & NVME_CSTS_RDY) == bit)
2073 break;
2074
2075 msleep(100);
2076 if (fatal_signal_pending(current))
2077 return -EINTR;
2078 if (time_after(jiffies, timeout)) {
1b3c47c1 2079 dev_err(ctrl->device,
5fd4ce1b
CH		 2080 "Device not ready; aborting %s\n", enabled ?
2081 "initialisation" : "reset");
2082 return -ENODEV;
2083 }
2084 }
2085
2086 return ret;
2087}
2088
2089/*
2090 * If the device has been passed off to us in an enabled state, just clear
2091 * the enabled bit. The spec says we should set the 'shutdown notification
2092 * bits', but doing so may cause the device to complete commands to the
2093 * admin queue ... and we don't know what memory that might be pointing at!
2094 */
b5b05048 2095int nvme_disable_ctrl(struct nvme_ctrl *ctrl)
5fd4ce1b
CH		 2096{
2097 int ret;
2098
2099 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
2100 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
2101
2102 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2103 if (ret)
2104 return ret;
54adc010 2105
b5a10c5f 2106 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010
GP		 2107 msleep(NVME_QUIRK_DELAY_AMOUNT);
2108
b5b05048 2109 return nvme_wait_ready(ctrl, ctrl->cap, false);
5fd4ce1b 2110}
576d55d6 2111EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b 2112
c0f2f45b 2113int nvme_enable_ctrl(struct nvme_ctrl *ctrl)
5fd4ce1b
CH		 2114{
2115 /*
2116 * Default to a 4K page size, with the intention to update this
2117 * path in the future to accomodate architectures with differing
2118 * kernel and IO page sizes.
2119 */
c0f2f45b 2120 unsigned dev_page_min, page_shift = 12;
5fd4ce1b
CH		 2121 int ret;
2122
c0f2f45b
SG		 2123 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &ctrl->cap);
2124 if (ret) {
2125 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
2126 return ret;
2127 }
2128 dev_page_min = NVME_CAP_MPSMIN(ctrl->cap) + 12;
2129
5fd4ce1b 2130 if (page_shift < dev_page_min) {
1b3c47c1 2131 dev_err(ctrl->device,
5fd4ce1b
CH		 2132 "Minimum device page size %u too large for host (%u)\n",
2133 1 << dev_page_min, 1 << page_shift);
2134 return -ENODEV;
2135 }
2136
2137 ctrl->page_size = 1 << page_shift;
2138
2139 ctrl->ctrl_config = NVME_CC_CSS_NVM;
2140 ctrl->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
60b43f62 2141 ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;
5fd4ce1b
CH		 2142 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
2143 ctrl->ctrl_config |= NVME_CC_ENABLE;
2144
2145 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2146 if (ret)
2147 return ret;
c0f2f45b 2148 return nvme_wait_ready(ctrl, ctrl->cap, true);
5fd4ce1b 2149}
576d55d6 2150EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b
CH		 2151
2152int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl)
2153{
07fbd32a 2154 unsigned long timeout = jiffies + (ctrl->shutdown_timeout * HZ);
5fd4ce1b
CH		 2155 u32 csts;
2156 int ret;
2157
2158 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
2159 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
2160
2161 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2162 if (ret)
2163 return ret;
2164
2165 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
2166 if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_CMPLT)
2167 break;
2168
2169 msleep(100);
2170 if (fatal_signal_pending(current))
2171 return -EINTR;
2172 if (time_after(jiffies, timeout)) {
1b3c47c1 2173 dev_err(ctrl->device,
5fd4ce1b
CH		 2174 "Device shutdown incomplete; abort shutdown\n");
2175 return -ENODEV;
2176 }
2177 }
2178
2179 return ret;
2180}
576d55d6 2181EXPORT_SYMBOL_GPL(nvme_shutdown_ctrl);
5fd4ce1b 2182
da35825d
CH		 2183static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
2184 struct request_queue *q)
2185{
7c88cb00
JA		 2186 bool vwc = false;
2187
da35825d 2188 if (ctrl->max_hw_sectors) {
45686b61
CH		 2189 u32 max_segments =
2190 (ctrl->max_hw_sectors / (ctrl->page_size >> 9)) + 1;
2191
943e942e 2192 max_segments = min_not_zero(max_segments, ctrl->max_segments);
da35825d 2193 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
45686b61 2194 blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
da35825d 2195 }
249159c5
KB		 2196 if ((ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) &&
2197 is_power_of_2(ctrl->max_hw_sectors))
e6282aef 2198 blk_queue_chunk_sectors(q, ctrl->max_hw_sectors);
da35825d 2199 blk_queue_virt_boundary(q, ctrl->page_size - 1);
7c88cb00
JA		 2200 if (ctrl->vwc & NVME_CTRL_VWC_PRESENT)
2201 vwc = true;
2202 blk_queue_write_cache(q, vwc, vwc);
da35825d
CH		 2203}
2204
dbf86b39
JD		 2205static int nvme_configure_timestamp(struct nvme_ctrl *ctrl)
2206{
2207 __le64 ts;
2208 int ret;
2209
2210 if (!(ctrl->oncs & NVME_CTRL_ONCS_TIMESTAMP))
2211 return 0;
2212
2213 ts = cpu_to_le64(ktime_to_ms(ktime_get_real()));
2214 ret = nvme_set_features(ctrl, NVME_FEAT_TIMESTAMP, 0, &ts, sizeof(ts),
2215 NULL);
2216 if (ret)
2217 dev_warn_once(ctrl->device,
2218 "could not set timestamp (%d)\n", ret);
2219 return ret;
2220}
2221
49cd84b6
KB		 2222static int nvme_configure_acre(struct nvme_ctrl *ctrl)
2223{
2224 struct nvme_feat_host_behavior *host;
2225 int ret;
2226
2227 /* Don't bother enabling the feature if retry delay is not reported */
2228 if (!ctrl->crdt[0])
2229 return 0;
2230
2231 host = kzalloc(sizeof(*host), GFP_KERNEL);
2232 if (!host)
2233 return 0;
2234
2235 host->acre = NVME_ENABLE_ACRE;
2236 ret = nvme_set_features(ctrl, NVME_FEAT_HOST_BEHAVIOR, 0,
2237 host, sizeof(*host), NULL);
2238 kfree(host);
2239 return ret;
2240}
2241
634b8325 2242static int nvme_configure_apst(struct nvme_ctrl *ctrl)
c5552fde
AL		 2243{
2244 /*
2245 * APST (Autonomous Power State Transition) lets us program a
2246 * table of power state transitions that the controller will
2247 * perform automatically. We configure it with a simple
2248 * heuristic: we are willing to spend at most 2% of the time
2249 * transitioning between power states. Therefore, when running
2250 * in any given state, we will enter the next lower-power
76e4ad09 2251 * non-operational state after waiting 50 * (enlat + exlat)
da87591b 2252 * microseconds, as long as that state's exit latency is under
c5552fde
AL		 2253 * the requested maximum latency.
2254 *
2255 * We will not autonomously enter any non-operational state for
2256 * which the total latency exceeds ps_max_latency_us. Users
2257 * can set ps_max_latency_us to zero to turn off APST.
2258 */
2259
2260 unsigned apste;
2261 struct nvme_feat_auto_pst *table;
fb0dc399
AL		 2262 u64 max_lat_us = 0;
2263 int max_ps = -1;
c5552fde
AL		 2264 int ret;
2265
2266 /*
2267 * If APST isn't supported or if we haven't been initialized yet,
2268 * then don't do anything.
2269 */
2270 if (!ctrl->apsta)
634b8325 2271 return 0;
c5552fde
AL		 2272
2273 if (ctrl->npss > 31) {
2274 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
634b8325 2275 return 0;
c5552fde
AL		 2276 }
2277
2278 table = kzalloc(sizeof(*table), GFP_KERNEL);
2279 if (!table)
634b8325 2280 return 0;
c5552fde 2281
76a5af84 2282 if (!ctrl->apst_enabled || ctrl->ps_max_latency_us == 0) {
c5552fde
AL		 2283 /* Turn off APST. */
2284 apste = 0;
fb0dc399 2285 dev_dbg(ctrl->device, "APST disabled\n");
c5552fde
AL		 2286 } else {
2287 __le64 target = cpu_to_le64(0);
2288 int state;
2289
2290 /*
2291 * Walk through all states from lowest- to highest-power.
2292 * According to the spec, lower-numbered states use more
2293 * power. NPSS, despite the name, is the index of the
2294 * lowest-power state, not the number of states.
2295 */
2296 for (state = (int)ctrl->npss; state >= 0; state--) {
da87591b 2297 u64 total_latency_us, exit_latency_us, transition_ms;
c5552fde
AL		 2298
2299 if (target)
2300 table->entries[state] = target;
2301
ff5350a8
AL		 2302 /*
2303 * Don't allow transitions to the deepest state
2304 * if it's quirked off.
2305 */
2306 if (state == ctrl->npss &&
2307 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
2308 continue;
2309
c5552fde
AL		 2310 /*
2311 * Is this state a useful non-operational state for
2312 * higher-power states to autonomously transition to?
2313 */
2314 if (!(ctrl->psd[state].flags &
2315 NVME_PS_FLAGS_NON_OP_STATE))
2316 continue;
2317
da87591b
KHF		 2318 exit_latency_us =
2319 (u64)le32_to_cpu(ctrl->psd[state].exit_lat);
2320 if (exit_latency_us > ctrl->ps_max_latency_us)
c5552fde
AL		 2321 continue;
2322
da87591b
KHF		 2323 total_latency_us =
2324 exit_latency_us +
2325 le32_to_cpu(ctrl->psd[state].entry_lat);
2326
c5552fde
AL		 2327 /*
2328 * This state is good. Use it as the APST idle
2329 * target for higher power states.
2330 */
2331 transition_ms = total_latency_us + 19;
2332 do_div(transition_ms, 20);
2333 if (transition_ms > (1 << 24) - 1)
2334 transition_ms = (1 << 24) - 1;
2335
2336 target = cpu_to_le64((state << 3) |
2337 (transition_ms << 8));
fb0dc399
AL		 2338
2339 if (max_ps == -1)
2340 max_ps = state;
2341
2342 if (total_latency_us > max_lat_us)
2343 max_lat_us = total_latency_us;
c5552fde
AL		 2344 }
2345
2346 apste = 1;
fb0dc399
AL		 2347
2348 if (max_ps == -1) {
2349 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n");
2350 } else {
2351 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n",
2352 max_ps, max_lat_us, (int)sizeof(*table), table);
2353 }
c5552fde
AL		 2354 }
2355
2356 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
2357 table, sizeof(*table), NULL);
2358 if (ret)
2359 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
2360
2361 kfree(table);
634b8325 2362 return ret;
c5552fde
AL		 2363}
2364
2365static void nvme_set_latency_tolerance(struct device *dev, s32 val)
2366{
2367 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2368 u64 latency;
2369
2370 switch (val) {
2371 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
2372 case PM_QOS_LATENCY_ANY:
2373 latency = U64_MAX;
2374 break;
2375
2376 default:
2377 latency = val;
2378 }
2379
2380 if (ctrl->ps_max_latency_us != latency) {
2381 ctrl->ps_max_latency_us = latency;
2382 nvme_configure_apst(ctrl);
2383 }
2384}
2385
bd4da3ab
AL		 2386struct nvme_core_quirk_entry {
2387 /*
2388 * NVMe model and firmware strings are padded with spaces. For
2389 * simplicity, strings in the quirk table are padded with NULLs
2390 * instead.
2391 */
2392 u16 vid;
2393 const char *mn;
2394 const char *fr;
2395 unsigned long quirks;
2396};
2397
2398static const struct nvme_core_quirk_entry core_quirks[] = {
c5552fde 2399 {
be56945c
AL		 2400 /*
2401 * This Toshiba device seems to die using any APST states. See:
2402 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
2403 */
2404 .vid = 0x1179,
2405 .mn = "THNSF5256GPUK TOSHIBA",
c5552fde 2406 .quirks = NVME_QUIRK_NO_APST,
cb32de1b
ML		 2407 },
2408 {
2409 /*
2410 * This LiteON CL1-3D*-Q11 firmware version has a race
2411 * condition associated with actions related to suspend to idle
2412 * LiteON has resolved the problem in future firmware
2413 */
2414 .vid = 0x14a4,
2415 .fr = "22301111",
2416 .quirks = NVME_QUIRK_SIMPLE_SUSPEND,
be56945c 2417 }
bd4da3ab
AL		 2418};
2419
2420/* match is null-terminated but idstr is space-padded. */
2421static bool string_matches(const char *idstr, const char *match, size_t len)
2422{
2423 size_t matchlen;
2424
2425 if (!match)
2426 return true;
2427
2428 matchlen = strlen(match);
2429 WARN_ON_ONCE(matchlen > len);
2430
2431 if (memcmp(idstr, match, matchlen))
2432 return false;
2433
2434 for (; matchlen < len; matchlen++)
2435 if (idstr[matchlen] != ' ')
2436 return false;
2437
2438 return true;
2439}
2440
2441static bool quirk_matches(const struct nvme_id_ctrl *id,
2442 const struct nvme_core_quirk_entry *q)
2443{
2444 return q->vid == le16_to_cpu(id->vid) &&
2445 string_matches(id->mn, q->mn, sizeof(id->mn)) &&
2446 string_matches(id->fr, q->fr, sizeof(id->fr));
2447}
2448
ab9e00cc
CH		 2449static void nvme_init_subnqn(struct nvme_subsystem *subsys, struct nvme_ctrl *ctrl,
2450 struct nvme_id_ctrl *id)
180de007
CH		 2451{
2452 size_t nqnlen;
2453 int off;
2454
6299358d
JD		 2455 if(!(ctrl->quirks & NVME_QUIRK_IGNORE_DEV_SUBNQN)) {
2456 nqnlen = strnlen(id->subnqn, NVMF_NQN_SIZE);
2457 if (nqnlen > 0 && nqnlen < NVMF_NQN_SIZE) {
2458 strlcpy(subsys->subnqn, id->subnqn, NVMF_NQN_SIZE);
2459 return;
2460 }
180de007 2461
6299358d
JD		 2462 if (ctrl->vs >= NVME_VS(1, 2, 1))
2463 dev_warn(ctrl->device, "missing or invalid SUBNQN field.\n");
2464 }
180de007
CH		 2465
2466 /* Generate a "fake" NQN per Figure 254 in NVMe 1.3 + ECN 001 */
ab9e00cc 2467 off = snprintf(subsys->subnqn, NVMF_NQN_SIZE,
3da584f5 2468 "nqn.2014.08.org.nvmexpress:%04x%04x",
180de007 2469 le16_to_cpu(id->vid), le16_to_cpu(id->ssvid));
ab9e00cc 2470 memcpy(subsys->subnqn + off, id->sn, sizeof(id->sn));
180de007 2471 off += sizeof(id->sn);
ab9e00cc 2472 memcpy(subsys->subnqn + off, id->mn, sizeof(id->mn));
180de007 2473 off += sizeof(id->mn);
ab9e00cc
CH		 2474 memset(subsys->subnqn + off, 0, sizeof(subsys->subnqn) - off);
2475}
2476
e654dfd3 2477static void nvme_release_subsystem(struct device *dev)
ab9e00cc 2478{
e654dfd3
LG		 2479 struct nvme_subsystem *subsys =
2480 container_of(dev, struct nvme_subsystem, dev);
2481
733e4b69
KB		 2482 if (subsys->instance >= 0)
2483 ida_simple_remove(&nvme_instance_ida, subsys->instance);
ab9e00cc
CH		 2484 kfree(subsys);
2485}
2486
ab9e00cc
CH		 2487static void nvme_destroy_subsystem(struct kref *ref)
2488{
2489 struct nvme_subsystem *subsys =
2490 container_of(ref, struct nvme_subsystem, ref);
2491
2492 mutex_lock(&nvme_subsystems_lock);
2493 list_del(&subsys->entry);
2494 mutex_unlock(&nvme_subsystems_lock);
2495
ed754e5d 2496 ida_destroy(&subsys->ns_ida);
ab9e00cc
CH		 2497 device_del(&subsys->dev);
2498 put_device(&subsys->dev);
2499}
2500
2501static void nvme_put_subsystem(struct nvme_subsystem *subsys)
2502{
2503 kref_put(&subsys->ref, nvme_destroy_subsystem);
2504}
2505
2506static struct nvme_subsystem *__nvme_find_get_subsystem(const char *subsysnqn)
2507{
2508 struct nvme_subsystem *subsys;
2509
2510 lockdep_assert_held(&nvme_subsystems_lock);
2511
c26aa572
JS		 2512 /*
2513 * Fail matches for discovery subsystems. This results
2514 * in each discovery controller bound to a unique subsystem.
2515 * This avoids issues with validating controller values
2516 * that can only be true when there is a single unique subsystem.
2517 * There may be multiple and completely independent entities
2518 * that provide discovery controllers.
2519 */
2520 if (!strcmp(subsysnqn, NVME_DISC_SUBSYS_NAME))
2521 return NULL;
2522
ab9e00cc
CH		 2523 list_for_each_entry(subsys, &nvme_subsystems, entry) {
2524 if (strcmp(subsys->subnqn, subsysnqn))
2525 continue;
2526 if (!kref_get_unless_zero(&subsys->ref))
2527 continue;
2528 return subsys;
2529 }
2530
2531 return NULL;
2532}
2533
1e496938
HR		 2534#define SUBSYS_ATTR_RO(_name, _mode, _show) \
2535 struct device_attribute subsys_attr_##_name = \
2536 __ATTR(_name, _mode, _show, NULL)
2537
2538static ssize_t nvme_subsys_show_nqn(struct device *dev,
2539 struct device_attribute *attr,
2540 char *buf)
2541{
2542 struct nvme_subsystem *subsys =
2543 container_of(dev, struct nvme_subsystem, dev);
2544
2545 return snprintf(buf, PAGE_SIZE, "%s\n", subsys->subnqn);
2546}
2547static SUBSYS_ATTR_RO(subsysnqn, S_IRUGO, nvme_subsys_show_nqn);
2548
2549#define nvme_subsys_show_str_function(field) \
2550static ssize_t subsys_##field##_show(struct device *dev, \
2551 struct device_attribute *attr, char *buf) \
2552{ \
2553 struct nvme_subsystem *subsys = \
2554 container_of(dev, struct nvme_subsystem, dev); \
2555 return sprintf(buf, "%.*s\n", \
2556 (int)sizeof(subsys->field), subsys->field); \
2557} \
2558static SUBSYS_ATTR_RO(field, S_IRUGO, subsys_##field##_show);
2559
2560nvme_subsys_show_str_function(model);
2561nvme_subsys_show_str_function(serial);
2562nvme_subsys_show_str_function(firmware_rev);
2563
2564static struct attribute *nvme_subsys_attrs[] = {
2565 &subsys_attr_model.attr,
2566 &subsys_attr_serial.attr,
2567 &subsys_attr_firmware_rev.attr,
2568 &subsys_attr_subsysnqn.attr,
75c10e73
HR		 2569#ifdef CONFIG_NVME_MULTIPATH
2570 &subsys_attr_iopolicy.attr,
2571#endif
1e496938
HR		 2572 NULL,
2573};
2574
2575static struct attribute_group nvme_subsys_attrs_group = {
2576 .attrs = nvme_subsys_attrs,
2577};
2578
2579static const struct attribute_group *nvme_subsys_attrs_groups[] = {
2580 &nvme_subsys_attrs_group,
2581 NULL,
2582};
2583
1b1031ca
CH		 2584static bool nvme_validate_cntlid(struct nvme_subsystem *subsys,
2585 struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
b837b283 2586{
1b1031ca 2587 struct nvme_ctrl *tmp;
b837b283 2588
32fd90c4
CH		 2589 lockdep_assert_held(&nvme_subsystems_lock);
2590
1b1031ca 2591 list_for_each_entry(tmp, &subsys->ctrls, subsys_entry) {
420dc733
SG		 2592 if (tmp->state == NVME_CTRL_DELETING ||
2593 tmp->state == NVME_CTRL_DEAD)
1b1031ca
CH		 2594 continue;
2595
2596 if (tmp->cntlid == ctrl->cntlid) {
2597 dev_err(ctrl->device,
2598 "Duplicate cntlid %u with %s, rejecting\n",
2599 ctrl->cntlid, dev_name(tmp->device));
2600 return false;
2601 }
b837b283 2602
1b1031ca
CH		 2603 if ((id->cmic & (1 << 1)) ||
2604 (ctrl->opts && ctrl->opts->discovery_nqn))
2605 continue;
2606
2607 dev_err(ctrl->device,
2608 "Subsystem does not support multiple controllers\n");
2609 return false;
b837b283 2610 }
b837b283 2611
1b1031ca 2612 return true;
b837b283
IR		 2613}
2614
ab9e00cc
CH		 2615static int nvme_init_subsystem(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
2616{
2617 struct nvme_subsystem *subsys, *found;
2618 int ret;
2619
2620 subsys = kzalloc(sizeof(*subsys), GFP_KERNEL);
2621 if (!subsys)
2622 return -ENOMEM;
733e4b69
KB		 2623
2624 subsys->instance = -1;
ab9e00cc
CH		 2625 mutex_init(&subsys->lock);
2626 kref_init(&subsys->ref);
2627 INIT_LIST_HEAD(&subsys->ctrls);
ed754e5d 2628 INIT_LIST_HEAD(&subsys->nsheads);
ab9e00cc
CH		 2629 nvme_init_subnqn(subsys, ctrl, id);
2630 memcpy(subsys->serial, id->sn, sizeof(subsys->serial));
2631 memcpy(subsys->model, id->mn, sizeof(subsys->model));
2632 memcpy(subsys->firmware_rev, id->fr, sizeof(subsys->firmware_rev));
2633 subsys->vendor_id = le16_to_cpu(id->vid);
2634 subsys->cmic = id->cmic;
81adb863 2635 subsys->awupf = le16_to_cpu(id->awupf);
75c10e73
HR		 2636#ifdef CONFIG_NVME_MULTIPATH
2637 subsys->iopolicy = NVME_IOPOLICY_NUMA;
2638#endif
ab9e00cc
CH		 2639
2640 subsys->dev.class = nvme_subsys_class;
2641 subsys->dev.release = nvme_release_subsystem;
1e496938 2642 subsys->dev.groups = nvme_subsys_attrs_groups;
733e4b69 2643 dev_set_name(&subsys->dev, "nvme-subsys%d", ctrl->instance);
ab9e00cc
CH		 2644 device_initialize(&subsys->dev);
2645
2646 mutex_lock(&nvme_subsystems_lock);
2647 found = __nvme_find_get_subsystem(subsys->subnqn);
2648 if (found) {
e654dfd3 2649 put_device(&subsys->dev);
ab9e00cc 2650 subsys = found;
32fd90c4 2651
1b1031ca 2652 if (!nvme_validate_cntlid(subsys, ctrl, id)) {
ab9e00cc 2653 ret = -EINVAL;
32fd90c4 2654 goto out_put_subsystem;
ab9e00cc 2655 }
ab9e00cc
CH		 2656 } else {
2657 ret = device_add(&subsys->dev);
2658 if (ret) {
2659 dev_err(ctrl->device,
2660 "failed to register subsystem device.\n");
8c36e66f 2661 put_device(&subsys->dev);
ab9e00cc
CH		 2662 goto out_unlock;
2663 }
ed754e5d 2664 ida_init(&subsys->ns_ida);
ab9e00cc
CH		 2665 list_add_tail(&subsys->entry, &nvme_subsystems);
2666 }
2667
bc4f6e06
DC		 2668 ret = sysfs_create_link(&subsys->dev.kobj, &ctrl->device->kobj,
2669 dev_name(ctrl->device));
2670 if (ret) {
ab9e00cc
CH		 2671 dev_err(ctrl->device,
2672 "failed to create sysfs link from subsystem.\n");
32fd90c4 2673 goto out_put_subsystem;
ab9e00cc
CH		 2674 }
2675
733e4b69
KB		 2676 if (!found)
2677 subsys->instance = ctrl->instance;
32fd90c4 2678 ctrl->subsys = subsys;
ab9e00cc 2679 list_add_tail(&ctrl->subsys_entry, &subsys->ctrls);
32fd90c4 2680 mutex_unlock(&nvme_subsystems_lock);
ab9e00cc
CH		 2681 return 0;
2682
32fd90c4
CH		 2683out_put_subsystem:
2684 nvme_put_subsystem(subsys);
ab9e00cc
CH		 2685out_unlock:
2686 mutex_unlock(&nvme_subsystems_lock);
ab9e00cc 2687 return ret;
180de007
CH		 2688}
2689
0e98719b
CH		 2690int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp,
2691 void *log, size_t size, u64 offset)
c627c487
KB		 2692{
2693 struct nvme_command c = { };
70da6094
MB		 2694 unsigned long dwlen = size / 4 - 1;
2695
2696 c.get_log_page.opcode = nvme_admin_get_log_page;
0e98719b 2697 c.get_log_page.nsid = cpu_to_le32(nsid);
70da6094 2698 c.get_log_page.lid = log_page;
0e98719b 2699 c.get_log_page.lsp = lsp;
70da6094
MB		 2700 c.get_log_page.numdl = cpu_to_le16(dwlen & ((1 << 16) - 1));
2701 c.get_log_page.numdu = cpu_to_le16(dwlen >> 16);
7ec6074f
MB		 2702 c.get_log_page.lpol = cpu_to_le32(lower_32_bits(offset));
2703 c.get_log_page.lpou = cpu_to_le32(upper_32_bits(offset));
c627c487
KB		 2704
2705 return nvme_submit_sync_cmd(ctrl->admin_q, &c, log, size);
2706}
2707
84fef62d
KB		 2708static int nvme_get_effects_log(struct nvme_ctrl *ctrl)
2709{
2710 int ret;
2711
2712 if (!ctrl->effects)
2713 ctrl->effects = kzalloc(sizeof(*ctrl->effects), GFP_KERNEL);
2714
2715 if (!ctrl->effects)
2716 return 0;
2717
0e98719b
CH		 2718 ret = nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_CMD_EFFECTS, 0,
2719 ctrl->effects, sizeof(*ctrl->effects), 0);
84fef62d
KB		 2720 if (ret) {
2721 kfree(ctrl->effects);
2722 ctrl->effects = NULL;
2723 }
2724 return ret;
180de007
CH		 2725}
2726
7fd8930f
CH		 2727/*
2728 * Initialize the cached copies of the Identify data and various controller
2729 * register in our nvme_ctrl structure. This should be called as soon as
2730 * the admin queue is fully up and running.
2731 */
2732int nvme_init_identify(struct nvme_ctrl *ctrl)
2733{
2734 struct nvme_id_ctrl *id;
7fd8930f 2735 int ret, page_shift;
a229dbf6 2736 u32 max_hw_sectors;
76a5af84 2737 bool prev_apst_enabled;
7fd8930f 2738
f3ca80fc
CH		 2739 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
2740 if (ret) {
1b3c47c1 2741 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
f3ca80fc
CH		 2742 return ret;
2743 }
4fba4458 2744 page_shift = NVME_CAP_MPSMIN(ctrl->cap) + 12;
c0f2f45b 2745 ctrl->sqsize = min_t(int, NVME_CAP_MQES(ctrl->cap), ctrl->sqsize);
7fd8930f 2746
8ef2074d 2747 if (ctrl->vs >= NVME_VS(1, 1, 0))
4fba4458 2748 ctrl->subsystem = NVME_CAP_NSSRC(ctrl->cap);
f3ca80fc 2749
7fd8930f
CH		 2750 ret = nvme_identify_ctrl(ctrl, &id);
2751 if (ret) {
1b3c47c1 2752 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH		 2753 return -EIO;
2754 }
2755
84fef62d
KB		 2756 if (id->lpa & NVME_CTRL_LPA_CMD_EFFECTS_LOG) {
2757 ret = nvme_get_effects_log(ctrl);
2758 if (ret < 0)
75c8b19a 2759 goto out_free;
84fef62d 2760 }
180de007 2761
a89fcca8
GP		 2762 if (!(ctrl->ops->flags & NVME_F_FABRICS))
2763 ctrl->cntlid = le16_to_cpu(id->cntlid);
2764
bd4da3ab 2765 if (!ctrl->identified) {
ab9e00cc
CH		 2766 int i;
2767
2768 ret = nvme_init_subsystem(ctrl, id);
2769 if (ret)
2770 goto out_free;
2771
bd4da3ab
AL		 2772 /*
2773 * Check for quirks. Quirk can depend on firmware version,
2774 * so, in principle, the set of quirks present can change
2775 * across a reset. As a possible future enhancement, we
2776 * could re-scan for quirks every time we reinitialize
2777 * the device, but we'd have to make sure that the driver
2778 * behaves intelligently if the quirks change.
2779 */
bd4da3ab
AL		 2780 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
2781 if (quirk_matches(id, &core_quirks[i]))
2782 ctrl->quirks |= core_quirks[i].quirks;
2783 }
2784 }
2785
c35e30b4 2786 if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) {
f0425db0 2787 dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n");
c35e30b4
AL		 2788 ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS;
2789 }
2790
49cd84b6
KB		 2791 ctrl->crdt[0] = le16_to_cpu(id->crdt1);
2792 ctrl->crdt[1] = le16_to_cpu(id->crdt2);
2793 ctrl->crdt[2] = le16_to_cpu(id->crdt3);
2794
8a9ae523 2795 ctrl->oacs = le16_to_cpu(id->oacs);
43e2d08d 2796 ctrl->oncs = le16_to_cpu(id->oncs);
2d466c7a 2797 ctrl->mtfa = le16_to_cpu(id->mtfa);
c0561f82 2798 ctrl->oaes = le32_to_cpu(id->oaes);
400b6a7b
GR		 2799 ctrl->wctemp = le16_to_cpu(id->wctemp);
2800 ctrl->cctemp = le16_to_cpu(id->cctemp);
2801
6bf25d16 2802 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 2803 ctrl->vwc = id->vwc;
7fd8930f 2804 if (id->mdts)
a229dbf6 2805 max_hw_sectors = 1 << (id->mdts + page_shift - 9);
7fd8930f 2806 else
a229dbf6
CH		 2807 max_hw_sectors = UINT_MAX;
2808 ctrl->max_hw_sectors =
2809 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 2810
da35825d 2811 nvme_set_queue_limits(ctrl, ctrl->admin_q);
07bfcd09 2812 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 2813 ctrl->kas = le16_to_cpu(id->kas);
0d0b660f 2814 ctrl->max_namespaces = le32_to_cpu(id->mnan);
3e53ba38 2815 ctrl->ctratt = le32_to_cpu(id->ctratt);
07bfcd09 2816
07fbd32a
MP		 2817 if (id->rtd3e) {
2818 /* us -> s */
2819 u32 transition_time = le32_to_cpu(id->rtd3e) / 1000000;
2820
2821 ctrl->shutdown_timeout = clamp_t(unsigned int, transition_time,
2822 shutdown_timeout, 60);
2823
2824 if (ctrl->shutdown_timeout != shutdown_timeout)
1a3838d7 2825 dev_info(ctrl->device,
07fbd32a
MP		 2826 "Shutdown timeout set to %u seconds\n",
2827 ctrl->shutdown_timeout);
2828 } else
2829 ctrl->shutdown_timeout = shutdown_timeout;
2830
c5552fde 2831 ctrl->npss = id->npss;
76a5af84
KHF		 2832 ctrl->apsta = id->apsta;
2833 prev_apst_enabled = ctrl->apst_enabled;
c35e30b4
AL		 2834 if (ctrl->quirks & NVME_QUIRK_NO_APST) {
2835 if (force_apst && id->apsta) {
f0425db0 2836 dev_warn(ctrl->device, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n");
76a5af84 2837 ctrl->apst_enabled = true;
c35e30b4 2838 } else {
76a5af84 2839 ctrl->apst_enabled = false;
c35e30b4
AL		 2840 }
2841 } else {
76a5af84 2842 ctrl->apst_enabled = id->apsta;
c35e30b4 2843 }
c5552fde
AL		 2844 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
2845
d3d5b87d 2846 if (ctrl->ops->flags & NVME_F_FABRICS) {
07bfcd09
CH		 2847 ctrl->icdoff = le16_to_cpu(id->icdoff);
2848 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
2849 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
2850 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
2851
2852 /*
2853 * In fabrics we need to verify the cntlid matches the
2854 * admin connect
2855 */
634b8325 2856 if (ctrl->cntlid != le16_to_cpu(id->cntlid)) {
a8157ff3
JS		 2857 dev_err(ctrl->device,
2858 "Mismatching cntlid: Connect %u vs Identify "
2859 "%u, rejecting\n",
2860 ctrl->cntlid, le16_to_cpu(id->cntlid));
07bfcd09 2861 ret = -EINVAL;
634b8325
KB		 2862 goto out_free;
2863 }
038bd4cb
SG		 2864
2865 if (!ctrl->opts->discovery_nqn && !ctrl->kas) {
f0425db0 2866 dev_err(ctrl->device,
038bd4cb
SG		 2867 "keep-alive support is mandatory for fabrics\n");
2868 ret = -EINVAL;
634b8325 2869 goto out_free;
038bd4cb 2870 }
07bfcd09 2871 } else {
fe6d53c9
CH		 2872 ctrl->hmpre = le32_to_cpu(id->hmpre);
2873 ctrl->hmmin = le32_to_cpu(id->hmmin);
044a9df1
CH		 2874 ctrl->hmminds = le32_to_cpu(id->hmminds);
2875 ctrl->hmmaxd = le16_to_cpu(id->hmmaxd);
07bfcd09 2876 }
da35825d 2877
0d0b660f 2878 ret = nvme_mpath_init(ctrl, id);
7fd8930f 2879 kfree(id);
bd4da3ab 2880
0d0b660f
CH		 2881 if (ret < 0)
2882 return ret;
2883
76a5af84 2884 if (ctrl->apst_enabled && !prev_apst_enabled)
c5552fde 2885 dev_pm_qos_expose_latency_tolerance(ctrl->device);
76a5af84 2886 else if (!ctrl->apst_enabled && prev_apst_enabled)
c5552fde
AL		 2887 dev_pm_qos_hide_latency_tolerance(ctrl->device);
2888
634b8325
KB		 2889 ret = nvme_configure_apst(ctrl);
2890 if (ret < 0)
2891 return ret;
dbf86b39
JD		 2892
2893 ret = nvme_configure_timestamp(ctrl);
2894 if (ret < 0)
2895 return ret;
634b8325
KB		 2896
2897 ret = nvme_configure_directives(ctrl);
2898 if (ret < 0)
2899 return ret;
c5552fde 2900
49cd84b6
KB		 2901 ret = nvme_configure_acre(ctrl);
2902 if (ret < 0)
2903 return ret;
2904
400b6a7b
GR		 2905 if (!ctrl->identified)
2906 nvme_hwmon_init(ctrl);
2907
bd4da3ab 2908 ctrl->identified = true;
c5552fde 2909
634b8325
KB		 2910 return 0;
2911
2912out_free:
2913 kfree(id);
07bfcd09 2914 return ret;
7fd8930f 2915}
576d55d6 2916EXPORT_SYMBOL_GPL(nvme_init_identify);
7fd8930f 2917
f3ca80fc 2918static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 2919{
a6a5149b
CH		 2920 struct nvme_ctrl *ctrl =
2921 container_of(inode->i_cdev, struct nvme_ctrl, cdev);
1673f1f0 2922
2b1b7e78
JW		 2923 switch (ctrl->state) {
2924 case NVME_CTRL_LIVE:
2b1b7e78
JW		 2925 break;
2926 default:
a6a5149b 2927 return -EWOULDBLOCK;
2b1b7e78
JW		 2928 }
2929
a6a5149b 2930 file->private_data = ctrl;
f3ca80fc
CH		 2931 return 0;
2932}
2933
bfd89471
CH		 2934static int nvme_dev_user_cmd(struct nvme_ctrl *ctrl, void __user *argp)
2935{
2936 struct nvme_ns *ns;
2937 int ret;
2938
765cc031 2939 down_read(&ctrl->namespaces_rwsem);
bfd89471
CH		 2940 if (list_empty(&ctrl->namespaces)) {
2941 ret = -ENOTTY;
2942 goto out_unlock;
2943 }
2944
2945 ns = list_first_entry(&ctrl->namespaces, struct nvme_ns, list);
2946 if (ns != list_last_entry(&ctrl->namespaces, struct nvme_ns, list)) {
1b3c47c1 2947 dev_warn(ctrl->device,
bfd89471
CH		 2948 "NVME_IOCTL_IO_CMD not supported when multiple namespaces present!\n");
2949 ret = -EINVAL;
2950 goto out_unlock;
2951 }
2952
1b3c47c1 2953 dev_warn(ctrl->device,
bfd89471
CH		 2954 "using deprecated NVME_IOCTL_IO_CMD ioctl on the char device!\n");
2955 kref_get(&ns->kref);
765cc031 2956 up_read(&ctrl->namespaces_rwsem);
bfd89471
CH		 2957
2958 ret = nvme_user_cmd(ctrl, ns, argp);
2959 nvme_put_ns(ns);
2960 return ret;
2961
2962out_unlock:
765cc031 2963 up_read(&ctrl->namespaces_rwsem);
bfd89471
CH		 2964 return ret;
2965}
2966
f3ca80fc
CH		 2967static long nvme_dev_ioctl(struct file *file, unsigned int cmd,
2968 unsigned long arg)
2969{
2970 struct nvme_ctrl *ctrl = file->private_data;
2971 void __user *argp = (void __user *)arg;
f3ca80fc
CH		 2972
2973 switch (cmd) {
2974 case NVME_IOCTL_ADMIN_CMD:
2975 return nvme_user_cmd(ctrl, NULL, argp);
65e68edc
MR		 2976 case NVME_IOCTL_ADMIN64_CMD:
2977 return nvme_user_cmd64(ctrl, NULL, argp);
f3ca80fc 2978 case NVME_IOCTL_IO_CMD:
bfd89471 2979 return nvme_dev_user_cmd(ctrl, argp);
f3ca80fc 2980 case NVME_IOCTL_RESET:
1b3c47c1 2981 dev_warn(ctrl->device, "resetting controller\n");
d86c4d8e 2982 return nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 2983 case NVME_IOCTL_SUBSYS_RESET:
2984 return nvme_reset_subsystem(ctrl);
9ec3bb2f
KB		 2985 case NVME_IOCTL_RESCAN:
2986 nvme_queue_scan(ctrl);
2987 return 0;
f3ca80fc
CH		 2988 default:
2989 return -ENOTTY;
2990 }
2991}
2992
2993static const struct file_operations nvme_dev_fops = {
2994 .owner = THIS_MODULE,
2995 .open = nvme_dev_open,
f3ca80fc 2996 .unlocked_ioctl = nvme_dev_ioctl,
1832f2d8 2997 .compat_ioctl = compat_ptr_ioctl,
f3ca80fc
CH		 2998};
2999
3000static ssize_t nvme_sysfs_reset(struct device *dev,
3001 struct device_attribute *attr, const char *buf,
3002 size_t count)
3003{
3004 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3005 int ret;
3006
d86c4d8e 3007 ret = nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 3008 if (ret < 0)
3009 return ret;
3010 return count;
1673f1f0 3011}
f3ca80fc 3012static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
1673f1f0 3013
9ec3bb2f
KB		 3014static ssize_t nvme_sysfs_rescan(struct device *dev,
3015 struct device_attribute *attr, const char *buf,
3016 size_t count)
3017{
3018 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3019
3020 nvme_queue_scan(ctrl);
3021 return count;
3022}
3023static DEVICE_ATTR(rescan_controller, S_IWUSR, NULL, nvme_sysfs_rescan);
3024
5b85b826
CH		 3025static inline struct nvme_ns_head *dev_to_ns_head(struct device *dev)
3026{
3027 struct gendisk *disk = dev_to_disk(dev);
3028
3029 if (disk->fops == &nvme_fops)
3030 return nvme_get_ns_from_dev(dev)->head;
3031 else
3032 return disk->private_data;
3033}
3034
118472ab 3035static ssize_t wwid_show(struct device *dev, struct device_attribute *attr,
5b85b826 3036 char *buf)
118472ab 3037{
5b85b826
CH		 3038 struct nvme_ns_head *head = dev_to_ns_head(dev);
3039 struct nvme_ns_ids *ids = &head->ids;
3040 struct nvme_subsystem *subsys = head->subsys;
ab9e00cc
CH		 3041 int serial_len = sizeof(subsys->serial);
3042 int model_len = sizeof(subsys->model);
118472ab 3043
002fab04
CH		 3044 if (!uuid_is_null(&ids->uuid))
3045 return sprintf(buf, "uuid.%pU\n", &ids->uuid);
6484f5d1 3046
002fab04
CH		 3047 if (memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
3048 return sprintf(buf, "eui.%16phN\n", ids->nguid);
118472ab 3049
002fab04
CH		 3050 if (memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
3051 return sprintf(buf, "eui.%8phN\n", ids->eui64);
118472ab 3052
ab9e00cc
CH		 3053 while (serial_len > 0 && (subsys->serial[serial_len - 1] == ' ' ||
3054 subsys->serial[serial_len - 1] == '\0'))
118472ab 3055 serial_len--;
ab9e00cc
CH		 3056 while (model_len > 0 && (subsys->model[model_len - 1] == ' ' ||
3057 subsys->model[model_len - 1] == '\0'))
118472ab
KB		 3058 model_len--;
3059
ab9e00cc
CH		 3060 return sprintf(buf, "nvme.%04x-%*phN-%*phN-%08x\n", subsys->vendor_id,
3061 serial_len, subsys->serial, model_len, subsys->model,
5b85b826 3062 head->ns_id);
118472ab 3063}
c828a892 3064static DEVICE_ATTR_RO(wwid);
118472ab 3065
d934f984 3066static ssize_t nguid_show(struct device *dev, struct device_attribute *attr,
5b85b826 3067 char *buf)
d934f984 3068{
5b85b826 3069 return sprintf(buf, "%pU\n", dev_to_ns_head(dev)->ids.nguid);
d934f984 3070}
c828a892 3071static DEVICE_ATTR_RO(nguid);
d934f984 3072
2b9b6e86 3073static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,
5b85b826 3074 char *buf)
2b9b6e86 3075{
5b85b826 3076 struct nvme_ns_ids *ids = &dev_to_ns_head(dev)->ids;
d934f984
JT		 3077
3078 /* For backward compatibility expose the NGUID to userspace if
3079 * we have no UUID set
3080 */
002fab04 3081 if (uuid_is_null(&ids->uuid)) {
d934f984
JT		 3082 printk_ratelimited(KERN_WARNING
3083 "No UUID available providing old NGUID\n");
002fab04 3084 return sprintf(buf, "%pU\n", ids->nguid);
d934f984 3085 }
002fab04 3086 return sprintf(buf, "%pU\n", &ids->uuid);
2b9b6e86 3087}
c828a892 3088static DEVICE_ATTR_RO(uuid);
2b9b6e86
KB		 3089
3090static ssize_t eui_show(struct device *dev, struct device_attribute *attr,
5b85b826 3091 char *buf)
2b9b6e86 3092{
5b85b826 3093 return sprintf(buf, "%8ph\n", dev_to_ns_head(dev)->ids.eui64);
2b9b6e86 3094}
c828a892 3095static DEVICE_ATTR_RO(eui);
2b9b6e86
KB		 3096
3097static ssize_t nsid_show(struct device *dev, struct device_attribute *attr,
5b85b826 3098 char *buf)
2b9b6e86 3099{
5b85b826 3100 return sprintf(buf, "%d\n", dev_to_ns_head(dev)->ns_id);
2b9b6e86 3101}
c828a892 3102static DEVICE_ATTR_RO(nsid);
2b9b6e86 3103
5b85b826 3104static struct attribute *nvme_ns_id_attrs[] = {
118472ab 3105 &dev_attr_wwid.attr,
2b9b6e86 3106 &dev_attr_uuid.attr,
d934f984 3107 &dev_attr_nguid.attr,
2b9b6e86
KB		 3108 &dev_attr_eui.attr,
3109 &dev_attr_nsid.attr,
0d0b660f
CH		 3110#ifdef CONFIG_NVME_MULTIPATH
3111 &dev_attr_ana_grpid.attr,
3112 &dev_attr_ana_state.attr,
3113#endif
2b9b6e86
KB		 3114 NULL,
3115};
3116
5b85b826 3117static umode_t nvme_ns_id_attrs_are_visible(struct kobject *kobj,
2b9b6e86
KB		 3118 struct attribute *a, int n)
3119{
3120 struct device *dev = container_of(kobj, struct device, kobj);
5b85b826 3121 struct nvme_ns_ids *ids = &dev_to_ns_head(dev)->ids;
2b9b6e86
KB		 3122
3123 if (a == &dev_attr_uuid.attr) {
a04b5de5 3124 if (uuid_is_null(&ids->uuid) &&
002fab04 3125 !memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
d934f984
JT		 3126 return 0;
3127 }
3128 if (a == &dev_attr_nguid.attr) {
002fab04 3129 if (!memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
2b9b6e86
KB		 3130 return 0;
3131 }
3132 if (a == &dev_attr_eui.attr) {
002fab04 3133 if (!memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
2b9b6e86
KB		 3134 return 0;
3135 }
0d0b660f
CH		 3136#ifdef CONFIG_NVME_MULTIPATH
3137 if (a == &dev_attr_ana_grpid.attr || a == &dev_attr_ana_state.attr) {
3138 if (dev_to_disk(dev)->fops != &nvme_fops) /* per-path attr */
3139 return 0;
3140 if (!nvme_ctrl_use_ana(nvme_get_ns_from_dev(dev)->ctrl))
3141 return 0;
3142 }
3143#endif
2b9b6e86
KB		 3144 return a->mode;
3145}
3146
eb090c4c 3147static const struct attribute_group nvme_ns_id_attr_group = {
5b85b826
CH		 3148 .attrs = nvme_ns_id_attrs,
3149 .is_visible = nvme_ns_id_attrs_are_visible,
2b9b6e86
KB		 3150};
3151
33b14f67
HR		 3152const struct attribute_group *nvme_ns_id_attr_groups[] = {
3153 &nvme_ns_id_attr_group,
3154#ifdef CONFIG_NVM
3155 &nvme_nvm_attr_group,
3156#endif
3157 NULL,
3158};
3159
931e1c22 3160#define nvme_show_str_function(field) \
779ff756
KB		 3161static ssize_t field##_show(struct device *dev, \
3162 struct device_attribute *attr, char *buf) \
3163{ \
3164 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
ab9e00cc
CH		 3165 return sprintf(buf, "%.*s\n", \
3166 (int)sizeof(ctrl->subsys->field), ctrl->subsys->field); \
779ff756
KB		 3167} \
3168static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
3169
ab9e00cc
CH		 3170nvme_show_str_function(model);
3171nvme_show_str_function(serial);
3172nvme_show_str_function(firmware_rev);
3173
931e1c22
ML		 3174#define nvme_show_int_function(field) \
3175static ssize_t field##_show(struct device *dev, \
3176 struct device_attribute *attr, char *buf) \
3177{ \
3178 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
3179 return sprintf(buf, "%d\n", ctrl->field); \
3180} \
3181static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
3182
931e1c22 3183nvme_show_int_function(cntlid);
103e515e 3184nvme_show_int_function(numa_node);
2b1ff255
JS		 3185nvme_show_int_function(queue_count);
3186nvme_show_int_function(sqsize);
779ff756 3187
1a353d85
ML		 3188static ssize_t nvme_sysfs_delete(struct device *dev,
3189 struct device_attribute *attr, const char *buf,
3190 size_t count)
3191{
3192 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3193
3194 if (device_remove_file_self(dev, attr))
c5017e85 3195 nvme_delete_ctrl_sync(ctrl);
1a353d85
ML		 3196 return count;
3197}
3198static DEVICE_ATTR(delete_controller, S_IWUSR, NULL, nvme_sysfs_delete);
3199
3200static ssize_t nvme_sysfs_show_transport(struct device *dev,
3201 struct device_attribute *attr,
3202 char *buf)
3203{
3204 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3205
3206 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->ops->name);
3207}
3208static DEVICE_ATTR(transport, S_IRUGO, nvme_sysfs_show_transport, NULL);
3209
8432bdb2
SG		 3210static ssize_t nvme_sysfs_show_state(struct device *dev,
3211 struct device_attribute *attr,
3212 char *buf)
3213{
3214 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3215 static const char *const state_name[] = {
3216 [NVME_CTRL_NEW] = "new",
3217 [NVME_CTRL_LIVE] = "live",
3218 [NVME_CTRL_RESETTING] = "resetting",
ad6a0a52 3219 [NVME_CTRL_CONNECTING] = "connecting",
8432bdb2
SG		 3220 [NVME_CTRL_DELETING] = "deleting",
3221 [NVME_CTRL_DEAD] = "dead",
3222 };
3223
3224 if ((unsigned)ctrl->state < ARRAY_SIZE(state_name) &&
3225 state_name[ctrl->state])
3226 return sprintf(buf, "%s\n", state_name[ctrl->state]);
3227
3228 return sprintf(buf, "unknown state\n");
3229}
3230
3231static DEVICE_ATTR(state, S_IRUGO, nvme_sysfs_show_state, NULL);
3232
1a353d85
ML		 3233static ssize_t nvme_sysfs_show_subsysnqn(struct device *dev,
3234 struct device_attribute *attr,
3235 char *buf)
3236{
3237 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3238
ab9e00cc 3239 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->subsys->subnqn);
1a353d85
ML		 3240}
3241static DEVICE_ATTR(subsysnqn, S_IRUGO, nvme_sysfs_show_subsysnqn, NULL);
3242
3243static ssize_t nvme_sysfs_show_address(struct device *dev,
3244 struct device_attribute *attr,
3245 char *buf)
3246{
3247 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3248
3249 return ctrl->ops->get_address(ctrl, buf, PAGE_SIZE);
3250}
3251static DEVICE_ATTR(address, S_IRUGO, nvme_sysfs_show_address, NULL);
3252
779ff756
KB		 3253static struct attribute *nvme_dev_attrs[] = {
3254 &dev_attr_reset_controller.attr,
9ec3bb2f 3255 &dev_attr_rescan_controller.attr,
779ff756
KB		 3256 &dev_attr_model.attr,
3257 &dev_attr_serial.attr,
3258 &dev_attr_firmware_rev.attr,
931e1c22 3259 &dev_attr_cntlid.attr,
1a353d85
ML		 3260 &dev_attr_delete_controller.attr,
3261 &dev_attr_transport.attr,
3262 &dev_attr_subsysnqn.attr,
3263 &dev_attr_address.attr,
8432bdb2 3264 &dev_attr_state.attr,
103e515e 3265 &dev_attr_numa_node.attr,
2b1ff255
JS		 3266 &dev_attr_queue_count.attr,
3267 &dev_attr_sqsize.attr,
779ff756
KB		 3268 NULL
3269};
3270
1a353d85
ML		 3271static umode_t nvme_dev_attrs_are_visible(struct kobject *kobj,
3272 struct attribute *a, int n)
3273{
3274 struct device *dev = container_of(kobj, struct device, kobj);
3275 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3276
49d3d50b
CH		 3277 if (a == &dev_attr_delete_controller.attr && !ctrl->ops->delete_ctrl)
3278 return 0;
3279 if (a == &dev_attr_address.attr && !ctrl->ops->get_address)
3280 return 0;
1a353d85
ML		 3281
3282 return a->mode;
3283}
3284
779ff756 3285static struct attribute_group nvme_dev_attrs_group = {
1a353d85
ML		 3286 .attrs = nvme_dev_attrs,
3287 .is_visible = nvme_dev_attrs_are_visible,
779ff756
KB		 3288};
3289
3290static const struct attribute_group *nvme_dev_attr_groups[] = {
3291 &nvme_dev_attrs_group,
3292 NULL,
3293};
3294
ed754e5d
CH		 3295static struct nvme_ns_head *__nvme_find_ns_head(struct nvme_subsystem *subsys,
3296 unsigned nsid)
3297{
3298 struct nvme_ns_head *h;
3299
3300 lockdep_assert_held(&subsys->lock);
3301
3302 list_for_each_entry(h, &subsys->nsheads, entry) {
3303 if (h->ns_id == nsid && kref_get_unless_zero(&h->ref))
3304 return h;
3305 }
3306
3307 return NULL;
3308}
3309
3310static int __nvme_check_ids(struct nvme_subsystem *subsys,
3311 struct nvme_ns_head *new)
3312{
3313 struct nvme_ns_head *h;
3314
3315 lockdep_assert_held(&subsys->lock);
3316
3317 list_for_each_entry(h, &subsys->nsheads, entry) {
3318 if (nvme_ns_ids_valid(&new->ids) &&
2079699c 3319 !list_empty(&h->list) &&
ed754e5d
CH		 3320 nvme_ns_ids_equal(&new->ids, &h->ids))
3321 return -EINVAL;
3322 }
3323
3324 return 0;
3325}
3326
3327static struct nvme_ns_head *nvme_alloc_ns_head(struct nvme_ctrl *ctrl,
3328 unsigned nsid, struct nvme_id_ns *id)
3329{
3330 struct nvme_ns_head *head;
f3334447 3331 size_t size = sizeof(*head);
ed754e5d
CH		 3332 int ret = -ENOMEM;
3333
f3334447
CH		 3334#ifdef CONFIG_NVME_MULTIPATH
3335 size += num_possible_nodes() * sizeof(struct nvme_ns *);
3336#endif
3337
3338 head = kzalloc(size, GFP_KERNEL);
ed754e5d
CH		 3339 if (!head)
3340 goto out;
3341 ret = ida_simple_get(&ctrl->subsys->ns_ida, 1, 0, GFP_KERNEL);
3342 if (ret < 0)
3343 goto out_free_head;
3344 head->instance = ret;
3345 INIT_LIST_HEAD(&head->list);
fd92c77f
MG		 3346 ret = init_srcu_struct(&head->srcu);
3347 if (ret)
3348 goto out_ida_remove;
ed754e5d
CH		 3349 head->subsys = ctrl->subsys;
3350 head->ns_id = nsid;
3351 kref_init(&head->ref);
3352
538af88e
SG		 3353 ret = nvme_report_ns_ids(ctrl, nsid, id, &head->ids);
3354 if (ret)
3355 goto out_cleanup_srcu;
ed754e5d
CH		 3356
3357 ret = __nvme_check_ids(ctrl->subsys, head);
3358 if (ret) {
3359 dev_err(ctrl->device,
3360 "duplicate IDs for nsid %d\n", nsid);
3361 goto out_cleanup_srcu;
3362 }
3363
32acab31
CH		 3364 ret = nvme_mpath_alloc_disk(ctrl, head);
3365 if (ret)
3366 goto out_cleanup_srcu;
3367
ed754e5d 3368 list_add_tail(&head->entry, &ctrl->subsys->nsheads);
12d9f070
JW		 3369
3370 kref_get(&ctrl->subsys->ref);
3371
ed754e5d
CH		 3372 return head;
3373out_cleanup_srcu:
3374 cleanup_srcu_struct(&head->srcu);
fd92c77f 3375out_ida_remove:
ed754e5d
CH		 3376 ida_simple_remove(&ctrl->subsys->ns_ida, head->instance);
3377out_free_head:
3378 kfree(head);
3379out:
538af88e
SG		 3380 if (ret > 0)
3381 ret = blk_status_to_errno(nvme_error_status(ret));
ed754e5d
CH		 3382 return ERR_PTR(ret);
3383}
3384
3385static int nvme_init_ns_head(struct nvme_ns *ns, unsigned nsid,
9bd82b1a 3386 struct nvme_id_ns *id)
ed754e5d
CH		 3387{
3388 struct nvme_ctrl *ctrl = ns->ctrl;
3389 bool is_shared = id->nmic & (1 << 0);
3390 struct nvme_ns_head *head = NULL;
3391 int ret = 0;
3392
3393 mutex_lock(&ctrl->subsys->lock);
3394 if (is_shared)
3395 head = __nvme_find_ns_head(ctrl->subsys, nsid);
3396 if (!head) {
3397 head = nvme_alloc_ns_head(ctrl, nsid, id);
3398 if (IS_ERR(head)) {
3399 ret = PTR_ERR(head);
3400 goto out_unlock;
3401 }
ed754e5d
CH		 3402 } else {
3403 struct nvme_ns_ids ids;
3404
538af88e
SG		 3405 ret = nvme_report_ns_ids(ctrl, nsid, id, &ids);
3406 if (ret)
3407 goto out_unlock;
3408
ed754e5d
CH		 3409 if (!nvme_ns_ids_equal(&head->ids, &ids)) {
3410 dev_err(ctrl->device,
3411 "IDs don't match for shared namespace %d\n",
3412 nsid);
3413 ret = -EINVAL;
3414 goto out_unlock;
3415 }
ed754e5d
CH		 3416 }
3417
3418 list_add_tail(&ns->siblings, &head->list);
3419 ns->head = head;
3420
3421out_unlock:
3422 mutex_unlock(&ctrl->subsys->lock);
538af88e
SG		 3423 if (ret > 0)
3424 ret = blk_status_to_errno(nvme_error_status(ret));
ed754e5d
CH		 3425 return ret;
3426}
3427
5bae7f73
CH		 3428static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
3429{
3430 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
3431 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
3432
ed754e5d 3433 return nsa->head->ns_id - nsb->head->ns_id;
5bae7f73
CH		 3434}
3435
32f0c4af 3436static struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 3437{
32f0c4af 3438 struct nvme_ns *ns, *ret = NULL;
69d3b8ac 3439
765cc031 3440 down_read(&ctrl->namespaces_rwsem);
5bae7f73 3441 list_for_each_entry(ns, &ctrl->namespaces, list) {
ed754e5d 3442 if (ns->head->ns_id == nsid) {
2dd41228
CH		 3443 if (!kref_get_unless_zero(&ns->kref))
3444 continue;
32f0c4af
KB		 3445 ret = ns;
3446 break;
3447 }
ed754e5d 3448 if (ns->head->ns_id > nsid)
5bae7f73
CH		 3449 break;
3450 }
765cc031 3451 up_read(&ctrl->namespaces_rwsem);
32f0c4af 3452 return ret;
5bae7f73
CH		 3453}
3454
f5d11840
JA		 3455static int nvme_setup_streams_ns(struct nvme_ctrl *ctrl, struct nvme_ns *ns)
3456{
3457 struct streams_directive_params s;
3458 int ret;
3459
3460 if (!ctrl->nr_streams)
3461 return 0;
3462
ed754e5d 3463 ret = nvme_get_stream_params(ctrl, &s, ns->head->ns_id);
f5d11840
JA		 3464 if (ret)
3465 return ret;
3466
3467 ns->sws = le32_to_cpu(s.sws);
3468 ns->sgs = le16_to_cpu(s.sgs);
3469
3470 if (ns->sws) {
3471 unsigned int bs = 1 << ns->lba_shift;
3472
3473 blk_queue_io_min(ns->queue, bs * ns->sws);
3474 if (ns->sgs)
3475 blk_queue_io_opt(ns->queue, bs * ns->sws * ns->sgs);
3476 }
3477
3478 return 0;
3479}
3480
ab4ab09c 3481static int nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73
CH		 3482{
3483 struct nvme_ns *ns;
3484 struct gendisk *disk;
ac81bfa9
MB		 3485 struct nvme_id_ns *id;
3486 char disk_name[DISK_NAME_LEN];
ab4ab09c 3487 int node = ctrl->numa_node, flags = GENHD_FL_EXT_DEVT, ret;
5bae7f73
CH		 3488
3489 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
3490 if (!ns)
ab4ab09c 3491 return -ENOMEM;
5bae7f73
CH		 3492
3493 ns->queue = blk_mq_init_queue(ctrl->tagset);
ab4ab09c
HR		 3494 if (IS_ERR(ns->queue)) {
3495 ret = PTR_ERR(ns->queue);
ed754e5d 3496 goto out_free_ns;
ab4ab09c 3497 }
e0596ab2 3498
7d30c81b 3499 if (ctrl->opts && ctrl->opts->data_digest)
958f2a0f
MS		 3500 ns->queue->backing_dev_info->capabilities
3501 |= BDI_CAP_STABLE_WRITES;
3502
8b904b5b 3503 blk_queue_flag_set(QUEUE_FLAG_NONROT, ns->queue);
e0596ab2
LG		 3504 if (ctrl->ops->flags & NVME_F_PCI_P2PDMA)
3505 blk_queue_flag_set(QUEUE_FLAG_PCI_P2PDMA, ns->queue);
3506
5bae7f73
CH		 3507 ns->queue->queuedata = ns;
3508 ns->ctrl = ctrl;
3509
5bae7f73 3510 kref_init(&ns->kref);
5bae7f73 3511 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
5bae7f73
CH		 3512
3513 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
da35825d 3514 nvme_set_queue_limits(ctrl, ns->queue);
5bae7f73 3515
331813f6
SG		 3516 ret = nvme_identify_ns(ctrl, nsid, &id);
3517 if (ret)
ac81bfa9
MB		 3518 goto out_free_queue;
3519
ab4ab09c
HR		 3520 if (id->ncap == 0) {
3521 ret = -EINVAL;
cdbff4f2 3522 goto out_free_id;
ab4ab09c 3523 }
cdbff4f2 3524
ab4ab09c
HR		 3525 ret = nvme_init_ns_head(ns, nsid, id);
3526 if (ret)
ed754e5d 3527 goto out_free_id;
654b4a4a 3528 nvme_setup_streams_ns(ctrl, ns);
a785dbcc 3529 nvme_set_disk_name(disk_name, ns, ctrl, &flags);
cdbff4f2 3530
3dc87dd0 3531 disk = alloc_disk_node(0, node);
ab4ab09c
HR		 3532 if (!disk) {
3533 ret = -ENOMEM;
ed754e5d 3534 goto out_unlink_ns;
ab4ab09c 3535 }
ac81bfa9 3536
3dc87dd0
MB		 3537 disk->fops = &nvme_fops;
3538 disk->private_data = ns;
3539 disk->queue = ns->queue;
32acab31 3540 disk->flags = flags;
3dc87dd0
MB		 3541 memcpy(disk->disk_name, disk_name, DISK_NAME_LEN);
3542 ns->disk = disk;
3543
3544 __nvme_revalidate_disk(disk, id);
5bae7f73 3545
85136c01 3546 if ((ctrl->quirks & NVME_QUIRK_LIGHTNVM) && id->vs[0] == 0x1) {
ab4ab09c
HR		 3547 ret = nvme_nvm_register(ns, disk_name, node);
3548 if (ret) {
85136c01
MB		 3549 dev_warn(ctrl->device, "LightNVM init failure\n");
3550 goto out_put_disk;
3551 }
3552 }
3553
765cc031 3554 down_write(&ctrl->namespaces_rwsem);
32f0c4af 3555 list_add_tail(&ns->list, &ctrl->namespaces);
765cc031 3556 up_write(&ctrl->namespaces_rwsem);
32f0c4af 3557
d22524a4 3558 nvme_get_ctrl(ctrl);
ac81bfa9 3559
33b14f67 3560 device_add_disk(ctrl->device, ns->disk, nvme_ns_id_attr_groups);
32acab31 3561
0d0b660f 3562 nvme_mpath_add_disk(ns, id);
a3646451 3563 nvme_fault_inject_init(&ns->fault_inject, ns->disk->disk_name);
0d0b660f
CH		 3564 kfree(id);
3565
ab4ab09c 3566 return 0;
85136c01
MB		 3567 out_put_disk:
3568 put_disk(ns->disk);
ed754e5d
CH		 3569 out_unlink_ns:
3570 mutex_lock(&ctrl->subsys->lock);
3571 list_del_rcu(&ns->siblings);
3572 mutex_unlock(&ctrl->subsys->lock);
a63b8370 3573 nvme_put_ns_head(ns->head);
ac81bfa9
MB		 3574 out_free_id:
3575 kfree(id);
5bae7f73
CH		 3576 out_free_queue:
3577 blk_cleanup_queue(ns->queue);
3578 out_free_ns:
3579 kfree(ns);
331813f6
SG		 3580 if (ret > 0)
3581 ret = blk_status_to_errno(nvme_error_status(ret));
ab4ab09c 3582 return ret;
5bae7f73
CH		 3583}
3584
3585static void nvme_ns_remove(struct nvme_ns *ns)
3586{
646017a6
KB		 3587 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
3588 return;
69d3b8ac 3589
a3646451 3590 nvme_fault_inject_fini(&ns->fault_inject);
2181e455
AE		 3591
3592 mutex_lock(&ns->ctrl->subsys->lock);
3593 list_del_rcu(&ns->siblings);
3594 mutex_unlock(&ns->ctrl->subsys->lock);
3595 synchronize_rcu(); /* guarantee not available in head->list */
3596 nvme_mpath_clear_current_path(ns);
3597 synchronize_srcu(&ns->head->srcu); /* wait for concurrent submissions */
3598
b0b4e09c 3599 if (ns->disk && ns->disk->flags & GENHD_FL_UP) {
5bae7f73 3600 del_gendisk(ns->disk);
5bae7f73 3601 blk_cleanup_queue(ns->queue);
bd9f5d65
ML		 3602 if (blk_get_integrity(ns->disk))
3603 blk_integrity_unregister(ns->disk);
5bae7f73 3604 }
32f0c4af 3605
765cc031 3606 down_write(&ns->ctrl->namespaces_rwsem);
5bae7f73 3607 list_del_init(&ns->list);
765cc031 3608 up_write(&ns->ctrl->namespaces_rwsem);
32f0c4af 3609
479a322f 3610 nvme_mpath_check_last_path(ns);
5bae7f73
CH		 3611 nvme_put_ns(ns);
3612}
3613
540c801c
KB		 3614static void nvme_validate_ns(struct nvme_ctrl *ctrl, unsigned nsid)
3615{
3616 struct nvme_ns *ns;
3617
32f0c4af 3618 ns = nvme_find_get_ns(ctrl, nsid);
540c801c 3619 if (ns) {
b0b4e09c 3620 if (ns->disk && revalidate_disk(ns->disk))
540c801c 3621 nvme_ns_remove(ns);
32f0c4af 3622 nvme_put_ns(ns);
540c801c
KB		 3623 } else
3624 nvme_alloc_ns(ctrl, nsid);
3625}
3626
47b0e50a
SB		 3627static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
3628 unsigned nsid)
3629{
3630 struct nvme_ns *ns, *next;
6f8e0d78 3631 LIST_HEAD(rm_list);
47b0e50a 3632
765cc031 3633 down_write(&ctrl->namespaces_rwsem);
47b0e50a 3634 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
cf39a6bc 3635 if (ns->head->ns_id > nsid || test_bit(NVME_NS_DEAD, &ns->flags))
6f8e0d78 3636 list_move_tail(&ns->list, &rm_list);
47b0e50a 3637 }
765cc031 3638 up_write(&ctrl->namespaces_rwsem);
6f8e0d78
JW		 3639
3640 list_for_each_entry_safe(ns, next, &rm_list, list)
3641 nvme_ns_remove(ns);
3642
47b0e50a
SB		 3643}
3644
540c801c
KB		 3645static int nvme_scan_ns_list(struct nvme_ctrl *ctrl, unsigned nn)
3646{
3647 struct nvme_ns *ns;
3648 __le32 *ns_list;
c8e8c77b
JL		 3649 unsigned i, j, nsid, prev = 0;
3650 unsigned num_lists = DIV_ROUND_UP_ULL((u64)nn, 1024);
540c801c
KB		 3651 int ret = 0;
3652
42595eb7 3653 ns_list = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
540c801c
KB		 3654 if (!ns_list)
3655 return -ENOMEM;
3656
3657 for (i = 0; i < num_lists; i++) {
3658 ret = nvme_identify_ns_list(ctrl, prev, ns_list);
3659 if (ret)
47b0e50a 3660 goto free;
540c801c
KB		 3661
3662 for (j = 0; j < min(nn, 1024U); j++) {
3663 nsid = le32_to_cpu(ns_list[j]);
3664 if (!nsid)
3665 goto out;
3666
3667 nvme_validate_ns(ctrl, nsid);
3668
3669 while (++prev < nsid) {
32f0c4af
KB		 3670 ns = nvme_find_get_ns(ctrl, prev);
3671 if (ns) {
540c801c 3672 nvme_ns_remove(ns);
32f0c4af
KB		 3673 nvme_put_ns(ns);
3674 }
540c801c
KB		 3675 }
3676 }
3677 nn -= j;
3678 }
3679 out:
47b0e50a
SB		 3680 nvme_remove_invalid_namespaces(ctrl, prev);
3681 free:
540c801c
KB		 3682 kfree(ns_list);
3683 return ret;
3684}
3685
5955be21 3686static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl, unsigned nn)
5bae7f73 3687{
5bae7f73
CH		 3688 unsigned i;
3689
540c801c
KB		 3690 for (i = 1; i <= nn; i++)
3691 nvme_validate_ns(ctrl, i);
3692
47b0e50a 3693 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH		 3694}
3695
f493af37 3696static void nvme_clear_changed_ns_log(struct nvme_ctrl *ctrl)
30d90964
CH		 3697{
3698 size_t log_size = NVME_MAX_CHANGED_NAMESPACES * sizeof(__le32);
3699 __le32 *log;
f493af37 3700 int error;
30d90964
CH		 3701
3702 log = kzalloc(log_size, GFP_KERNEL);
3703 if (!log)
f493af37 3704 return;
30d90964 3705
f493af37
CH		 3706 /*
3707 * We need to read the log to clear the AEN, but we don't want to rely
3708 * on it for the changed namespace information as userspace could have
3709 * raced with us in reading the log page, which could cause us to miss
3710 * updates.
3711 */
0e98719b
CH		 3712 error = nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_CHANGED_NS, 0, log,
3713 log_size, 0);
f493af37 3714 if (error)
30d90964
CH		 3715 dev_warn(ctrl->device,
3716 "reading changed ns log failed: %d\n", error);
30d90964 3717
30d90964 3718 kfree(log);
30d90964
CH		 3719}
3720
5955be21 3721static void nvme_scan_work(struct work_struct *work)
5bae7f73 3722{
5955be21
CH		 3723 struct nvme_ctrl *ctrl =
3724 container_of(work, struct nvme_ctrl, scan_work);
5bae7f73 3725 struct nvme_id_ctrl *id;
540c801c 3726 unsigned nn;
5bae7f73 3727
5d02a5c1
KB		 3728 /* No tagset on a live ctrl means IO queues could not created */
3729 if (ctrl->state != NVME_CTRL_LIVE || !ctrl->tagset)
5955be21
CH		 3730 return;
3731
77016199 3732 if (test_and_clear_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events)) {
30d90964 3733 dev_info(ctrl->device, "rescanning namespaces.\n");
f493af37 3734 nvme_clear_changed_ns_log(ctrl);
30d90964
CH		 3735 }
3736
5bae7f73
CH		 3737 if (nvme_identify_ctrl(ctrl, &id))
3738 return;
540c801c 3739
e7ad43c3 3740 mutex_lock(&ctrl->scan_lock);
540c801c 3741 nn = le32_to_cpu(id->nn);
8ef2074d 3742 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
540c801c
KB		 3743 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
3744 if (!nvme_scan_ns_list(ctrl, nn))
30d90964 3745 goto out_free_id;
540c801c 3746 }
5955be21 3747 nvme_scan_ns_sequential(ctrl, nn);
30d90964 3748out_free_id:
e7ad43c3 3749 mutex_unlock(&ctrl->scan_lock);
30d90964 3750 kfree(id);
765cc031 3751 down_write(&ctrl->namespaces_rwsem);
540c801c 3752 list_sort(NULL, &ctrl->namespaces, ns_cmp);
765cc031 3753 up_write(&ctrl->namespaces_rwsem);
5955be21 3754}
5bae7f73 3755
32f0c4af
KB		 3756/*
3757 * This function iterates the namespace list unlocked to allow recovery from
3758 * controller failure. It is up to the caller to ensure the namespace list is
3759 * not modified by scan work while this function is executing.
3760 */
5bae7f73
CH		 3761void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
3762{
3763 struct nvme_ns *ns, *next;
6f8e0d78 3764 LIST_HEAD(ns_list);
5bae7f73 3765
0157ec8d
SG		 3766 /*
3767 * make sure to requeue I/O to all namespaces as these
3768 * might result from the scan itself and must complete
3769 * for the scan_work to make progress
3770 */
3771 nvme_mpath_clear_ctrl_paths(ctrl);
3772
f6c8e432
SG		 3773 /* prevent racing with ns scanning */
3774 flush_work(&ctrl->scan_work);
3775
0ff9d4e1
KB		 3776 /*
3777 * The dead states indicates the controller was not gracefully
3778 * disconnected. In that case, we won't be able to flush any data while
3779 * removing the namespaces' disks; fail all the queues now to avoid
3780 * potentially having to clean up the failed sync later.
3781 */
3782 if (ctrl->state == NVME_CTRL_DEAD)
3783 nvme_kill_queues(ctrl);
3784
765cc031 3785 down_write(&ctrl->namespaces_rwsem);
6f8e0d78 3786 list_splice_init(&ctrl->namespaces, &ns_list);
765cc031 3787 up_write(&ctrl->namespaces_rwsem);
6f8e0d78
JW		 3788
3789 list_for_each_entry_safe(ns, next, &ns_list, list)
5bae7f73
CH		 3790 nvme_ns_remove(ns);
3791}
576d55d6 3792EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 3793
a42f42e5
SG		 3794static int nvme_class_uevent(struct device *dev, struct kobj_uevent_env *env)
3795{
3796 struct nvme_ctrl *ctrl =
3797 container_of(dev, struct nvme_ctrl, ctrl_device);
3798 struct nvmf_ctrl_options *opts = ctrl->opts;
3799 int ret;
3800
3801 ret = add_uevent_var(env, "NVME_TRTYPE=%s", ctrl->ops->name);
3802 if (ret)
3803 return ret;
3804
3805 if (opts) {
3806 ret = add_uevent_var(env, "NVME_TRADDR=%s", opts->traddr);
3807 if (ret)
3808 return ret;
3809
3810 ret = add_uevent_var(env, "NVME_TRSVCID=%s",
3811 opts->trsvcid ?: "none");
3812 if (ret)
3813 return ret;
3814
3815 ret = add_uevent_var(env, "NVME_HOST_TRADDR=%s",
3816 opts->host_traddr ?: "none");
3817 }
3818 return ret;
3819}
3820
e3d7874d
KB		 3821static void nvme_aen_uevent(struct nvme_ctrl *ctrl)
3822{
3823 char *envp[2] = { NULL, NULL };
3824 u32 aen_result = ctrl->aen_result;
3825
3826 ctrl->aen_result = 0;
3827 if (!aen_result)
3828 return;
3829
3830 envp[0] = kasprintf(GFP_KERNEL, "NVME_AEN=%#08x", aen_result);
3831 if (!envp[0])
3832 return;
3833 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp);
3834 kfree(envp[0]);
3835}
3836
f866fc42
CH		 3837static void nvme_async_event_work(struct work_struct *work)
3838{
3839 struct nvme_ctrl *ctrl =
3840 container_of(work, struct nvme_ctrl, async_event_work);
3841
e3d7874d 3842 nvme_aen_uevent(ctrl);
ad22c355 3843 ctrl->ops->submit_async_event(ctrl);
f866fc42
CH		 3844}
3845
b6dccf7f
AD		 3846static bool nvme_ctrl_pp_status(struct nvme_ctrl *ctrl)
3847{
3848
3849 u32 csts;
3850
3851 if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts))
3852 return false;
3853
3854 if (csts == ~0)
3855 return false;
3856
3857 return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP));
3858}
3859
3860static void nvme_get_fw_slot_info(struct nvme_ctrl *ctrl)
3861{
b6dccf7f
AD		 3862 struct nvme_fw_slot_info_log *log;
3863
3864 log = kmalloc(sizeof(*log), GFP_KERNEL);
3865 if (!log)
3866 return;
3867
0e98719b
CH		 3868 if (nvme_get_log(ctrl, NVME_NSID_ALL, 0, NVME_LOG_FW_SLOT, log,
3869 sizeof(*log), 0))
3870 dev_warn(ctrl->device, "Get FW SLOT INFO log error\n");
b6dccf7f
AD		 3871 kfree(log);
3872}
3873
3874static void nvme_fw_act_work(struct work_struct *work)
3875{
3876 struct nvme_ctrl *ctrl = container_of(work,
3877 struct nvme_ctrl, fw_act_work);
3878 unsigned long fw_act_timeout;
3879
3880 if (ctrl->mtfa)
3881 fw_act_timeout = jiffies +
3882 msecs_to_jiffies(ctrl->mtfa * 100);
3883 else
3884 fw_act_timeout = jiffies +
3885 msecs_to_jiffies(admin_timeout * 1000);
3886
3887 nvme_stop_queues(ctrl);
3888 while (nvme_ctrl_pp_status(ctrl)) {
3889 if (time_after(jiffies, fw_act_timeout)) {
3890 dev_warn(ctrl->device,
3891 "Fw activation timeout, reset controller\n");
4c75f877
KB		 3892 nvme_try_sched_reset(ctrl);
3893 return;
b6dccf7f
AD		 3894 }
3895 msleep(100);
3896 }
3897
4c75f877 3898 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_LIVE))
b6dccf7f
AD		 3899 return;
3900
3901 nvme_start_queues(ctrl);
a806c6c8 3902 /* read FW slot information to clear the AER */
b6dccf7f
AD		 3903 nvme_get_fw_slot_info(ctrl);
3904}
3905
868c2392
CH		 3906static void nvme_handle_aen_notice(struct nvme_ctrl *ctrl, u32 result)
3907{
09bd1ff4
CK		 3908 u32 aer_notice_type = (result & 0xff00) >> 8;
3909
521cfb8e
CK		 3910 trace_nvme_async_event(ctrl, aer_notice_type);
3911
09bd1ff4 3912 switch (aer_notice_type) {
868c2392 3913 case NVME_AER_NOTICE_NS_CHANGED:
77016199 3914 set_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events);
868c2392
CH		 3915 nvme_queue_scan(ctrl);
3916 break;
3917 case NVME_AER_NOTICE_FW_ACT_STARTING:
4c75f877
KB		 3918 /*
3919 * We are (ab)using the RESETTING state to prevent subsequent
3920 * recovery actions from interfering with the controller's
3921 * firmware activation.
3922 */
3923 if (nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
3924 queue_work(nvme_wq, &ctrl->fw_act_work);
868c2392 3925 break;
0d0b660f
CH		 3926#ifdef CONFIG_NVME_MULTIPATH
3927 case NVME_AER_NOTICE_ANA:
3928 if (!ctrl->ana_log_buf)
3929 break;
3930 queue_work(nvme_wq, &ctrl->ana_work);
3931 break;
3932#endif
85f8a435
SG		 3933 case NVME_AER_NOTICE_DISC_CHANGED:
3934 ctrl->aen_result = result;
3935 break;
868c2392
CH		 3936 default:
3937 dev_warn(ctrl->device, "async event result %08x\n", result);
3938 }
3939}
3940
7bf58533 3941void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
287a63eb 3942 volatile union nvme_result *res)
f866fc42 3943{
7bf58533 3944 u32 result = le32_to_cpu(res->u32);
09bd1ff4 3945 u32 aer_type = result & 0x07;
f866fc42 3946
ad22c355 3947 if (le16_to_cpu(status) >> 1 != NVME_SC_SUCCESS)
f866fc42
CH		 3948 return;
3949
09bd1ff4 3950 switch (aer_type) {
868c2392
CH		 3951 case NVME_AER_NOTICE:
3952 nvme_handle_aen_notice(ctrl, result);
3953 break;
e3d7874d
KB		 3954 case NVME_AER_ERROR:
3955 case NVME_AER_SMART:
3956 case NVME_AER_CSS:
3957 case NVME_AER_VS:
09bd1ff4 3958 trace_nvme_async_event(ctrl, aer_type);
e3d7874d 3959 ctrl->aen_result = result;
7bf58533
CH		 3960 break;
3961 default:
3962 break;
f866fc42 3963 }
c669ccdc 3964 queue_work(nvme_wq, &ctrl->async_event_work);
f866fc42 3965}
f866fc42 3966EXPORT_SYMBOL_GPL(nvme_complete_async_event);
f3ca80fc 3967
d09f2b45 3968void nvme_stop_ctrl(struct nvme_ctrl *ctrl)
576d55d6 3969{
0d0b660f 3970 nvme_mpath_stop(ctrl);
d09f2b45 3971 nvme_stop_keep_alive(ctrl);
f866fc42 3972 flush_work(&ctrl->async_event_work);
b6dccf7f 3973 cancel_work_sync(&ctrl->fw_act_work);
d09f2b45
SG		 3974}
3975EXPORT_SYMBOL_GPL(nvme_stop_ctrl);
3976
3977void nvme_start_ctrl(struct nvme_ctrl *ctrl)
3978{
3979 if (ctrl->kato)
3980 nvme_start_keep_alive(ctrl);
3981
93da4023
SG		 3982 nvme_enable_aen(ctrl);
3983
d09f2b45
SG		 3984 if (ctrl->queue_count > 1) {
3985 nvme_queue_scan(ctrl);
d09f2b45
SG		 3986 nvme_start_queues(ctrl);
3987 }
3988}
3989EXPORT_SYMBOL_GPL(nvme_start_ctrl);
5955be21 3990
d09f2b45
SG		 3991void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
3992{
f79d5fda 3993 nvme_fault_inject_fini(&ctrl->fault_inject);
510a405d 3994 dev_pm_qos_hide_latency_tolerance(ctrl->device);
a6a5149b 3995 cdev_device_del(&ctrl->cdev, ctrl->device);
53029b04 3996}
576d55d6 3997EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04 3998
d22524a4 3999static void nvme_free_ctrl(struct device *dev)
53029b04 4000{
d22524a4
CH		 4001 struct nvme_ctrl *ctrl =
4002 container_of(dev, struct nvme_ctrl, ctrl_device);
ab9e00cc 4003 struct nvme_subsystem *subsys = ctrl->subsys;
f3ca80fc 4004
733e4b69
KB		 4005 if (subsys && ctrl->instance != subsys->instance)
4006 ida_simple_remove(&nvme_instance_ida, ctrl->instance);
4007
84fef62d 4008 kfree(ctrl->effects);
0d0b660f 4009 nvme_mpath_uninit(ctrl);
092ff052 4010 __free_page(ctrl->discard_page);
f3ca80fc 4011
ab9e00cc 4012 if (subsys) {
32fd90c4 4013 mutex_lock(&nvme_subsystems_lock);
ab9e00cc 4014 list_del(&ctrl->subsys_entry);
ab9e00cc 4015 sysfs_remove_link(&subsys->dev.kobj, dev_name(ctrl->device));
32fd90c4 4016 mutex_unlock(&nvme_subsystems_lock);
ab9e00cc 4017 }
f3ca80fc
CH		 4018
4019 ctrl->ops->free_ctrl(ctrl);
f3ca80fc 4020
ab9e00cc
CH		 4021 if (subsys)
4022 nvme_put_subsystem(subsys);
f3ca80fc
CH		 4023}
4024
4025/*
4026 * Initialize a NVMe controller structures. This needs to be called during
4027 * earliest initialization so that we have the initialized structured around
4028 * during probing.
4029 */
4030int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
4031 const struct nvme_ctrl_ops *ops, unsigned long quirks)
4032{
4033 int ret;
4034
bb8d261e
CH		 4035 ctrl->state = NVME_CTRL_NEW;
4036 spin_lock_init(&ctrl->lock);
e7ad43c3 4037 mutex_init(&ctrl->scan_lock);
f3ca80fc 4038 INIT_LIST_HEAD(&ctrl->namespaces);
765cc031 4039 init_rwsem(&ctrl->namespaces_rwsem);
f3ca80fc
CH		 4040 ctrl->dev = dev;
4041 ctrl->ops = ops;
4042 ctrl->quirks = quirks;
5955be21 4043 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 4044 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
b6dccf7f 4045 INIT_WORK(&ctrl->fw_act_work, nvme_fw_act_work);
c5017e85 4046 INIT_WORK(&ctrl->delete_work, nvme_delete_ctrl_work);
c1ac9a4b 4047 init_waitqueue_head(&ctrl->state_wq);
f3ca80fc 4048
230f1f9e
JS		 4049 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
4050 memset(&ctrl->ka_cmd, 0, sizeof(ctrl->ka_cmd));
4051 ctrl->ka_cmd.common.opcode = nvme_admin_keep_alive;
4052
cb5b7262
JA		 4053 BUILD_BUG_ON(NVME_DSM_MAX_RANGES * sizeof(struct nvme_dsm_range) >
4054 PAGE_SIZE);
4055 ctrl->discard_page = alloc_page(GFP_KERNEL);
4056 if (!ctrl->discard_page) {
4057 ret = -ENOMEM;
4058 goto out;
4059 }
4060
9843f685
CH		 4061 ret = ida_simple_get(&nvme_instance_ida, 0, 0, GFP_KERNEL);
4062 if (ret < 0)
f3ca80fc 4063 goto out;
9843f685 4064 ctrl->instance = ret;
f3ca80fc 4065
d22524a4
CH		 4066 device_initialize(&ctrl->ctrl_device);
4067 ctrl->device = &ctrl->ctrl_device;
a6a5149b 4068 ctrl->device->devt = MKDEV(MAJOR(nvme_chr_devt), ctrl->instance);
d22524a4
CH		 4069 ctrl->device->class = nvme_class;
4070 ctrl->device->parent = ctrl->dev;
4071 ctrl->device->groups = nvme_dev_attr_groups;
4072 ctrl->device->release = nvme_free_ctrl;
4073 dev_set_drvdata(ctrl->device, ctrl);
4074 ret = dev_set_name(ctrl->device, "nvme%d", ctrl->instance);
4075 if (ret)
f3ca80fc 4076 goto out_release_instance;
f3ca80fc 4077
a6a5149b
CH		 4078 cdev_init(&ctrl->cdev, &nvme_dev_fops);
4079 ctrl->cdev.owner = ops->module;
4080 ret = cdev_device_add(&ctrl->cdev, ctrl->device);
d22524a4
CH		 4081 if (ret)
4082 goto out_free_name;
f3ca80fc 4083
c5552fde
AL		 4084 /*
4085 * Initialize latency tolerance controls. The sysfs files won't
4086 * be visible to userspace unless the device actually supports APST.
4087 */
4088 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
4089 dev_pm_qos_update_user_latency_tolerance(ctrl->device,
4090 min(default_ps_max_latency_us, (unsigned long)S32_MAX));
4091
f79d5fda
AM		 4092 nvme_fault_inject_init(&ctrl->fault_inject, dev_name(ctrl->device));
4093
f3ca80fc 4094 return 0;
d22524a4 4095out_free_name:
d6a2b953 4096 kfree_const(ctrl->device->kobj.name);
f3ca80fc 4097out_release_instance:
9843f685 4098 ida_simple_remove(&nvme_instance_ida, ctrl->instance);
f3ca80fc 4099out:
cb5b7262
JA		 4100 if (ctrl->discard_page)
4101 __free_page(ctrl->discard_page);
f3ca80fc
CH		 4102 return ret;
4103}
576d55d6 4104EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 4105
69d9a99c
KB		 4106/**
4107 * nvme_kill_queues(): Ends all namespace queues
4108 * @ctrl: the dead controller that needs to end
4109 *
4110 * Call this function when the driver determines it is unable to get the
4111 * controller in a state capable of servicing IO.
4112 */
4113void nvme_kill_queues(struct nvme_ctrl *ctrl)
4114{
4115 struct nvme_ns *ns;
4116
765cc031 4117 down_read(&ctrl->namespaces_rwsem);
82654b6b 4118
443bd90f 4119 /* Forcibly unquiesce queues to avoid blocking dispatch */
751a0cc0 4120 if (ctrl->admin_q && !blk_queue_dying(ctrl->admin_q))
7dd1ab16 4121 blk_mq_unquiesce_queue(ctrl->admin_q);
443bd90f 4122
cf39a6bc
SB		 4123 list_for_each_entry(ns, &ctrl->namespaces, list)
4124 nvme_set_queue_dying(ns);
806f026f 4125
765cc031 4126 up_read(&ctrl->namespaces_rwsem);
69d9a99c 4127}
237045fc 4128EXPORT_SYMBOL_GPL(nvme_kill_queues);
69d9a99c 4129
302ad8cc
KB		 4130void nvme_unfreeze(struct nvme_ctrl *ctrl)
4131{
4132 struct nvme_ns *ns;
4133
765cc031 4134 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4135 list_for_each_entry(ns, &ctrl->namespaces, list)
4136 blk_mq_unfreeze_queue(ns->queue);
765cc031 4137 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4138}
4139EXPORT_SYMBOL_GPL(nvme_unfreeze);
4140
4141void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout)
4142{
4143 struct nvme_ns *ns;
4144
765cc031 4145 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4146 list_for_each_entry(ns, &ctrl->namespaces, list) {
4147 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout);
4148 if (timeout <= 0)
4149 break;
4150 }
765cc031 4151 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4152}
4153EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout);
4154
4155void nvme_wait_freeze(struct nvme_ctrl *ctrl)
4156{
4157 struct nvme_ns *ns;
4158
765cc031 4159 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4160 list_for_each_entry(ns, &ctrl->namespaces, list)
4161 blk_mq_freeze_queue_wait(ns->queue);
765cc031 4162 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4163}
4164EXPORT_SYMBOL_GPL(nvme_wait_freeze);
4165
4166void nvme_start_freeze(struct nvme_ctrl *ctrl)
4167{
4168 struct nvme_ns *ns;
4169
765cc031 4170 down_read(&ctrl->namespaces_rwsem);
302ad8cc 4171 list_for_each_entry(ns, &ctrl->namespaces, list)
1671d522 4172 blk_freeze_queue_start(ns->queue);
765cc031 4173 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4174}
4175EXPORT_SYMBOL_GPL(nvme_start_freeze);
4176
25646264 4177void nvme_stop_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 4178{
4179 struct nvme_ns *ns;
4180
765cc031 4181 down_read(&ctrl->namespaces_rwsem);
a6eaa884 4182 list_for_each_entry(ns, &ctrl->namespaces, list)
3174dd33 4183 blk_mq_quiesce_queue(ns->queue);
765cc031 4184 up_read(&ctrl->namespaces_rwsem);
363c9aac 4185}
576d55d6 4186EXPORT_SYMBOL_GPL(nvme_stop_queues);
363c9aac 4187
25646264 4188void nvme_start_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 4189{
4190 struct nvme_ns *ns;
4191
765cc031 4192 down_read(&ctrl->namespaces_rwsem);
8d7b8faf 4193 list_for_each_entry(ns, &ctrl->namespaces, list)
f660174e 4194 blk_mq_unquiesce_queue(ns->queue);
765cc031 4195 up_read(&ctrl->namespaces_rwsem);
363c9aac 4196}
576d55d6 4197EXPORT_SYMBOL_GPL(nvme_start_queues);
363c9aac 4198
d6135c3a
KB		 4199
4200void nvme_sync_queues(struct nvme_ctrl *ctrl)
4201{
4202 struct nvme_ns *ns;
4203
4204 down_read(&ctrl->namespaces_rwsem);
4205 list_for_each_entry(ns, &ctrl->namespaces, list)
4206 blk_sync_queue(ns->queue);
4207 up_read(&ctrl->namespaces_rwsem);
03894b7a
EN		 4208
4209 if (ctrl->admin_q)
4210 blk_sync_queue(ctrl->admin_q);
d6135c3a
KB		 4211}
4212EXPORT_SYMBOL_GPL(nvme_sync_queues);
4213
81101540
CH		 4214/*
4215 * Check we didn't inadvertently grow the command structure sizes:
4216 */
4217static inline void _nvme_check_size(void)
4218{
4219 BUILD_BUG_ON(sizeof(struct nvme_common_command) != 64);
4220 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
4221 BUILD_BUG_ON(sizeof(struct nvme_identify) != 64);
4222 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
4223 BUILD_BUG_ON(sizeof(struct nvme_download_firmware) != 64);
4224 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
4225 BUILD_BUG_ON(sizeof(struct nvme_dsm_cmd) != 64);
4226 BUILD_BUG_ON(sizeof(struct nvme_write_zeroes_cmd) != 64);
4227 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
4228 BUILD_BUG_ON(sizeof(struct nvme_get_log_page_command) != 64);
4229 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
4230 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
4231 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
4232 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
4233 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
4234 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
4235 BUILD_BUG_ON(sizeof(struct nvme_directive_cmd) != 64);
4236}
4237
4238
893a74b7 4239static int __init nvme_core_init(void)
5bae7f73 4240{
b227c59b 4241 int result = -ENOMEM;
5bae7f73 4242
81101540
CH		 4243 _nvme_check_size();
4244
9a6327d2
SG		 4245 nvme_wq = alloc_workqueue("nvme-wq",
4246 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4247 if (!nvme_wq)
b227c59b
RS		 4248 goto out;
4249
4250 nvme_reset_wq = alloc_workqueue("nvme-reset-wq",
4251 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4252 if (!nvme_reset_wq)
4253 goto destroy_wq;
4254
4255 nvme_delete_wq = alloc_workqueue("nvme-delete-wq",
4256 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4257 if (!nvme_delete_wq)
4258 goto destroy_reset_wq;
9a6327d2 4259
a6a5149b 4260 result = alloc_chrdev_region(&nvme_chr_devt, 0, NVME_MINORS, "nvme");
f3ca80fc 4261 if (result < 0)
b227c59b 4262 goto destroy_delete_wq;
f3ca80fc
CH		 4263
4264 nvme_class = class_create(THIS_MODULE, "nvme");
4265 if (IS_ERR(nvme_class)) {
4266 result = PTR_ERR(nvme_class);
4267 goto unregister_chrdev;
4268 }
a42f42e5 4269 nvme_class->dev_uevent = nvme_class_uevent;
f3ca80fc 4270
ab9e00cc
CH		 4271 nvme_subsys_class = class_create(THIS_MODULE, "nvme-subsystem");
4272 if (IS_ERR(nvme_subsys_class)) {
4273 result = PTR_ERR(nvme_subsys_class);
4274 goto destroy_class;
4275 }
5bae7f73 4276 return 0;
f3ca80fc 4277
ab9e00cc
CH		 4278destroy_class:
4279 class_destroy(nvme_class);
9a6327d2 4280unregister_chrdev:
a6a5149b 4281 unregister_chrdev_region(nvme_chr_devt, NVME_MINORS);
b227c59b
RS		 4282destroy_delete_wq:
4283 destroy_workqueue(nvme_delete_wq);
4284destroy_reset_wq:
4285 destroy_workqueue(nvme_reset_wq);
9a6327d2
SG		 4286destroy_wq:
4287 destroy_workqueue(nvme_wq);
b227c59b 4288out:
f3ca80fc 4289 return result;
5bae7f73
CH		 4290}
4291
893a74b7 4292static void __exit nvme_core_exit(void)
5bae7f73 4293{
ab9e00cc 4294 class_destroy(nvme_subsys_class);
f3ca80fc 4295 class_destroy(nvme_class);
a6a5149b 4296 unregister_chrdev_region(nvme_chr_devt, NVME_MINORS);
b227c59b
RS		 4297 destroy_workqueue(nvme_delete_wq);
4298 destroy_workqueue(nvme_reset_wq);
9a6327d2 4299 destroy_workqueue(nvme_wq);
5bae7f73 4300}
576d55d6
ML		 4301
4302MODULE_LICENSE("GPL");
4303MODULE_VERSION("1.0");
4304module_init(nvme_core_init);
4305module_exit(nvme_core_exit);
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