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NVMe: Add device ID's with stripe quirk
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CommitLineData
21d34711
CH
1/*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/blkdev.h>
16#include <linux/blk-mq.h>
5fd4ce1b 17#include <linux/delay.h>
21d34711 18#include <linux/errno.h>
1673f1f0 19#include <linux/hdreg.h>
21d34711 20#include <linux/kernel.h>
5bae7f73
CH
21#include <linux/module.h>
22#include <linux/list_sort.h>
21d34711
CH
23#include <linux/slab.h>
24#include <linux/types.h>
1673f1f0
CH
25#include <linux/pr.h>
26#include <linux/ptrace.h>
27#include <linux/nvme_ioctl.h>
28#include <linux/t10-pi.h>
29#include <scsi/sg.h>
30#include <asm/unaligned.h>
21d34711
CH
31
32#include "nvme.h"
33
f3ca80fc
CH
34#define NVME_MINORS (1U << MINORBITS)
35
ba0ba7d3
ML
36unsigned char admin_timeout = 60;
37module_param(admin_timeout, byte, 0644);
38MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 39EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3
ML
40
41unsigned char nvme_io_timeout = 30;
42module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
43MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 44EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3
ML
45
46unsigned char shutdown_timeout = 5;
47module_param(shutdown_timeout, byte, 0644);
48MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
49
5bae7f73
CH
50static int nvme_major;
51module_param(nvme_major, int, 0);
52
f3ca80fc
CH
53static int nvme_char_major;
54module_param(nvme_char_major, int, 0);
55
56static LIST_HEAD(nvme_ctrl_list);
9f2482b9 57static DEFINE_SPINLOCK(dev_list_lock);
1673f1f0 58
f3ca80fc
CH
59static struct class *nvme_class;
60
bb8d261e
CH
61bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
62 enum nvme_ctrl_state new_state)
63{
64 enum nvme_ctrl_state old_state = ctrl->state;
65 bool changed = false;
66
67 spin_lock_irq(&ctrl->lock);
68 switch (new_state) {
69 case NVME_CTRL_LIVE:
70 switch (old_state) {
71 case NVME_CTRL_RESETTING:
72 changed = true;
73 /* FALLTHRU */
74 default:
75 break;
76 }
77 break;
78 case NVME_CTRL_RESETTING:
79 switch (old_state) {
80 case NVME_CTRL_NEW:
81 case NVME_CTRL_LIVE:
82 changed = true;
83 /* FALLTHRU */
84 default:
85 break;
86 }
87 break;
88 case NVME_CTRL_DELETING:
89 switch (old_state) {
90 case NVME_CTRL_LIVE:
91 case NVME_CTRL_RESETTING:
92 changed = true;
93 /* FALLTHRU */
94 default:
95 break;
96 }
97 break;
0ff9d4e1
KB
98 case NVME_CTRL_DEAD:
99 switch (old_state) {
100 case NVME_CTRL_DELETING:
101 changed = true;
102 /* FALLTHRU */
103 default:
104 break;
105 }
106 break;
bb8d261e
CH
107 default:
108 break;
109 }
110 spin_unlock_irq(&ctrl->lock);
111
112 if (changed)
113 ctrl->state = new_state;
114
115 return changed;
116}
117EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
118
1673f1f0
CH
119static void nvme_free_ns(struct kref *kref)
120{
121 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
122
123 if (ns->type == NVME_NS_LIGHTNVM)
124 nvme_nvm_unregister(ns->queue, ns->disk->disk_name);
125
126 spin_lock(&dev_list_lock);
127 ns->disk->private_data = NULL;
128 spin_unlock(&dev_list_lock);
129
1673f1f0 130 put_disk(ns->disk);
075790eb
KB
131 ida_simple_remove(&ns->ctrl->ns_ida, ns->instance);
132 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH
133 kfree(ns);
134}
135
5bae7f73 136static void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH
137{
138 kref_put(&ns->kref, nvme_free_ns);
139}
140
141static struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk)
142{
143 struct nvme_ns *ns;
144
145 spin_lock(&dev_list_lock);
146 ns = disk->private_data;
e439bb12
SG
147 if (ns) {
148 if (!kref_get_unless_zero(&ns->kref))
149 goto fail;
150 if (!try_module_get(ns->ctrl->ops->module))
151 goto fail_put_ns;
152 }
1673f1f0
CH
153 spin_unlock(&dev_list_lock);
154
155 return ns;
e439bb12
SG
156
157fail_put_ns:
158 kref_put(&ns->kref, nvme_free_ns);
159fail:
160 spin_unlock(&dev_list_lock);
161 return NULL;
1673f1f0
CH
162}
163
7688faa6
CH
164void nvme_requeue_req(struct request *req)
165{
166 unsigned long flags;
167
168 blk_mq_requeue_request(req);
169 spin_lock_irqsave(req->q->queue_lock, flags);
170 if (!blk_queue_stopped(req->q))
171 blk_mq_kick_requeue_list(req->q);
172 spin_unlock_irqrestore(req->q->queue_lock, flags);
173}
576d55d6 174EXPORT_SYMBOL_GPL(nvme_requeue_req);
7688faa6 175
4160982e
CH
176struct request *nvme_alloc_request(struct request_queue *q,
177 struct nvme_command *cmd, unsigned int flags)
21d34711
CH
178{
179 bool write = cmd->common.opcode & 1;
21d34711 180 struct request *req;
21d34711 181
4160982e 182 req = blk_mq_alloc_request(q, write, flags);
21d34711 183 if (IS_ERR(req))
4160982e 184 return req;
21d34711
CH
185
186 req->cmd_type = REQ_TYPE_DRV_PRIV;
187 req->cmd_flags |= REQ_FAILFAST_DRIVER;
188 req->__data_len = 0;
189 req->__sector = (sector_t) -1;
190 req->bio = req->biotail = NULL;
191
21d34711
CH
192 req->cmd = (unsigned char *)cmd;
193 req->cmd_len = sizeof(struct nvme_command);
21d34711 194
4160982e
CH
195 return req;
196}
576d55d6 197EXPORT_SYMBOL_GPL(nvme_alloc_request);
4160982e 198
8093f7ca
ML
199static inline void nvme_setup_flush(struct nvme_ns *ns,
200 struct nvme_command *cmnd)
201{
202 memset(cmnd, 0, sizeof(*cmnd));
203 cmnd->common.opcode = nvme_cmd_flush;
204 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
205}
206
207static inline int nvme_setup_discard(struct nvme_ns *ns, struct request *req,
208 struct nvme_command *cmnd)
209{
210 struct nvme_dsm_range *range;
211 struct page *page;
212 int offset;
213 unsigned int nr_bytes = blk_rq_bytes(req);
214
215 range = kmalloc(sizeof(*range), GFP_ATOMIC);
216 if (!range)
217 return BLK_MQ_RQ_QUEUE_BUSY;
218
219 range->cattr = cpu_to_le32(0);
220 range->nlb = cpu_to_le32(nr_bytes >> ns->lba_shift);
221 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
222
223 memset(cmnd, 0, sizeof(*cmnd));
224 cmnd->dsm.opcode = nvme_cmd_dsm;
225 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
226 cmnd->dsm.nr = 0;
227 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
228
229 req->completion_data = range;
230 page = virt_to_page(range);
231 offset = offset_in_page(range);
232 blk_add_request_payload(req, page, offset, sizeof(*range));
233
234 /*
235 * we set __data_len back to the size of the area to be discarded
236 * on disk. This allows us to report completion on the full amount
237 * of blocks described by the request.
238 */
239 req->__data_len = nr_bytes;
240
241 return 0;
242}
243
244static inline void nvme_setup_rw(struct nvme_ns *ns, struct request *req,
245 struct nvme_command *cmnd)
246{
247 u16 control = 0;
248 u32 dsmgmt = 0;
249
250 if (req->cmd_flags & REQ_FUA)
251 control |= NVME_RW_FUA;
252 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
253 control |= NVME_RW_LR;
254
255 if (req->cmd_flags & REQ_RAHEAD)
256 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
257
258 memset(cmnd, 0, sizeof(*cmnd));
259 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
260 cmnd->rw.command_id = req->tag;
261 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
262 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
263 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
264
265 if (ns->ms) {
266 switch (ns->pi_type) {
267 case NVME_NS_DPS_PI_TYPE3:
268 control |= NVME_RW_PRINFO_PRCHK_GUARD;
269 break;
270 case NVME_NS_DPS_PI_TYPE1:
271 case NVME_NS_DPS_PI_TYPE2:
272 control |= NVME_RW_PRINFO_PRCHK_GUARD |
273 NVME_RW_PRINFO_PRCHK_REF;
274 cmnd->rw.reftag = cpu_to_le32(
275 nvme_block_nr(ns, blk_rq_pos(req)));
276 break;
277 }
278 if (!blk_integrity_rq(req))
279 control |= NVME_RW_PRINFO_PRACT;
280 }
281
282 cmnd->rw.control = cpu_to_le16(control);
283 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
284}
285
286int nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
287 struct nvme_command *cmd)
288{
289 int ret = 0;
290
291 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
292 memcpy(cmd, req->cmd, sizeof(*cmd));
293 else if (req->cmd_flags & REQ_FLUSH)
294 nvme_setup_flush(ns, cmd);
295 else if (req->cmd_flags & REQ_DISCARD)
296 ret = nvme_setup_discard(ns, req, cmd);
297 else
298 nvme_setup_rw(ns, req, cmd);
299
300 return ret;
301}
302EXPORT_SYMBOL_GPL(nvme_setup_cmd);
303
4160982e
CH
304/*
305 * Returns 0 on success. If the result is negative, it's a Linux error code;
306 * if the result is positive, it's an NVM Express status code
307 */
308int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1cb3cce5
CH
309 struct nvme_completion *cqe, void *buffer, unsigned bufflen,
310 unsigned timeout)
4160982e
CH
311{
312 struct request *req;
313 int ret;
314
315 req = nvme_alloc_request(q, cmd, 0);
316 if (IS_ERR(req))
317 return PTR_ERR(req);
318
319 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
1cb3cce5 320 req->special = cqe;
4160982e 321
21d34711
CH
322 if (buffer && bufflen) {
323 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
324 if (ret)
325 goto out;
4160982e
CH
326 }
327
328 blk_execute_rq(req->q, NULL, req, 0);
4160982e
CH
329 ret = req->errors;
330 out:
331 blk_mq_free_request(req);
332 return ret;
333}
334
335int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
336 void *buffer, unsigned bufflen)
337{
1cb3cce5 338 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 0);
4160982e 339}
576d55d6 340EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 341
0b7f1f26
KB
342int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
343 void __user *ubuffer, unsigned bufflen,
344 void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
345 u32 *result, unsigned timeout)
4160982e 346{
0b7f1f26 347 bool write = cmd->common.opcode & 1;
1cb3cce5 348 struct nvme_completion cqe;
0b7f1f26
KB
349 struct nvme_ns *ns = q->queuedata;
350 struct gendisk *disk = ns ? ns->disk : NULL;
4160982e 351 struct request *req;
0b7f1f26
KB
352 struct bio *bio = NULL;
353 void *meta = NULL;
4160982e
CH
354 int ret;
355
356 req = nvme_alloc_request(q, cmd, 0);
357 if (IS_ERR(req))
358 return PTR_ERR(req);
359
360 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
1cb3cce5 361 req->special = &cqe;
4160982e
CH
362
363 if (ubuffer && bufflen) {
21d34711
CH
364 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
365 GFP_KERNEL);
366 if (ret)
367 goto out;
368 bio = req->bio;
21d34711 369
0b7f1f26
KB
370 if (!disk)
371 goto submit;
372 bio->bi_bdev = bdget_disk(disk, 0);
373 if (!bio->bi_bdev) {
374 ret = -ENODEV;
375 goto out_unmap;
376 }
377
e9fc63d6 378 if (meta_buffer && meta_len) {
0b7f1f26
KB
379 struct bio_integrity_payload *bip;
380
381 meta = kmalloc(meta_len, GFP_KERNEL);
382 if (!meta) {
383 ret = -ENOMEM;
384 goto out_unmap;
385 }
386
387 if (write) {
388 if (copy_from_user(meta, meta_buffer,
389 meta_len)) {
390 ret = -EFAULT;
391 goto out_free_meta;
392 }
393 }
394
395 bip = bio_integrity_alloc(bio, GFP_KERNEL, 1);
06c1e390
KB
396 if (IS_ERR(bip)) {
397 ret = PTR_ERR(bip);
0b7f1f26
KB
398 goto out_free_meta;
399 }
400
401 bip->bip_iter.bi_size = meta_len;
402 bip->bip_iter.bi_sector = meta_seed;
403
404 ret = bio_integrity_add_page(bio, virt_to_page(meta),
405 meta_len, offset_in_page(meta));
406 if (ret != meta_len) {
407 ret = -ENOMEM;
408 goto out_free_meta;
409 }
410 }
411 }
412 submit:
413 blk_execute_rq(req->q, disk, req, 0);
414 ret = req->errors;
21d34711 415 if (result)
1cb3cce5 416 *result = le32_to_cpu(cqe.result);
0b7f1f26
KB
417 if (meta && !ret && !write) {
418 if (copy_to_user(meta_buffer, meta, meta_len))
419 ret = -EFAULT;
420 }
421 out_free_meta:
422 kfree(meta);
423 out_unmap:
424 if (bio) {
425 if (disk && bio->bi_bdev)
426 bdput(bio->bi_bdev);
427 blk_rq_unmap_user(bio);
428 }
21d34711
CH
429 out:
430 blk_mq_free_request(req);
431 return ret;
432}
433
0b7f1f26
KB
434int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
435 void __user *ubuffer, unsigned bufflen, u32 *result,
436 unsigned timeout)
437{
438 return __nvme_submit_user_cmd(q, cmd, ubuffer, bufflen, NULL, 0, 0,
439 result, timeout);
440}
441
1c63dc66 442int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH
443{
444 struct nvme_command c = { };
445 int error;
446
447 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
448 c.identify.opcode = nvme_admin_identify;
449 c.identify.cns = cpu_to_le32(1);
450
451 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
452 if (!*id)
453 return -ENOMEM;
454
455 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
456 sizeof(struct nvme_id_ctrl));
457 if (error)
458 kfree(*id);
459 return error;
460}
461
540c801c
KB
462static int nvme_identify_ns_list(struct nvme_ctrl *dev, unsigned nsid, __le32 *ns_list)
463{
464 struct nvme_command c = { };
465
466 c.identify.opcode = nvme_admin_identify;
467 c.identify.cns = cpu_to_le32(2);
468 c.identify.nsid = cpu_to_le32(nsid);
469 return nvme_submit_sync_cmd(dev->admin_q, &c, ns_list, 0x1000);
470}
471
1c63dc66 472int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
21d34711
CH
473 struct nvme_id_ns **id)
474{
475 struct nvme_command c = { };
476 int error;
477
478 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
479 c.identify.opcode = nvme_admin_identify,
480 c.identify.nsid = cpu_to_le32(nsid),
481
482 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
483 if (!*id)
484 return -ENOMEM;
485
486 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
487 sizeof(struct nvme_id_ns));
488 if (error)
489 kfree(*id);
490 return error;
491}
492
1c63dc66 493int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
21d34711
CH
494 dma_addr_t dma_addr, u32 *result)
495{
496 struct nvme_command c;
1cb3cce5
CH
497 struct nvme_completion cqe;
498 int ret;
21d34711
CH
499
500 memset(&c, 0, sizeof(c));
501 c.features.opcode = nvme_admin_get_features;
502 c.features.nsid = cpu_to_le32(nsid);
503 c.features.prp1 = cpu_to_le64(dma_addr);
504 c.features.fid = cpu_to_le32(fid);
505
1cb3cce5
CH
506 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &cqe, NULL, 0, 0);
507 if (ret >= 0)
508 *result = le32_to_cpu(cqe.result);
509 return ret;
21d34711
CH
510}
511
1c63dc66 512int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
21d34711
CH
513 dma_addr_t dma_addr, u32 *result)
514{
515 struct nvme_command c;
1cb3cce5
CH
516 struct nvme_completion cqe;
517 int ret;
21d34711
CH
518
519 memset(&c, 0, sizeof(c));
520 c.features.opcode = nvme_admin_set_features;
521 c.features.prp1 = cpu_to_le64(dma_addr);
522 c.features.fid = cpu_to_le32(fid);
523 c.features.dword11 = cpu_to_le32(dword11);
524
1cb3cce5
CH
525 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &cqe, NULL, 0, 0);
526 if (ret >= 0)
527 *result = le32_to_cpu(cqe.result);
528 return ret;
21d34711
CH
529}
530
1c63dc66 531int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log)
21d34711
CH
532{
533 struct nvme_command c = { };
534 int error;
535
536 c.common.opcode = nvme_admin_get_log_page,
537 c.common.nsid = cpu_to_le32(0xFFFFFFFF),
538 c.common.cdw10[0] = cpu_to_le32(
539 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
540 NVME_LOG_SMART),
541
542 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
543 if (!*log)
544 return -ENOMEM;
545
546 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
547 sizeof(struct nvme_smart_log));
548 if (error)
549 kfree(*log);
550 return error;
551}
1673f1f0 552
9a0be7ab
CH
553int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
554{
555 u32 q_count = (*count - 1) | ((*count - 1) << 16);
556 u32 result;
557 int status, nr_io_queues;
558
559 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, 0,
560 &result);
561 if (status)
562 return status;
563
564 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
565 *count = min(*count, nr_io_queues);
566 return 0;
567}
576d55d6 568EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 569
1673f1f0
CH
570static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
571{
572 struct nvme_user_io io;
573 struct nvme_command c;
574 unsigned length, meta_len;
575 void __user *metadata;
576
577 if (copy_from_user(&io, uio, sizeof(io)))
578 return -EFAULT;
63088ec7
KB
579 if (io.flags)
580 return -EINVAL;
1673f1f0
CH
581
582 switch (io.opcode) {
583 case nvme_cmd_write:
584 case nvme_cmd_read:
585 case nvme_cmd_compare:
586 break;
587 default:
588 return -EINVAL;
589 }
590
591 length = (io.nblocks + 1) << ns->lba_shift;
592 meta_len = (io.nblocks + 1) * ns->ms;
593 metadata = (void __user *)(uintptr_t)io.metadata;
594
595 if (ns->ext) {
596 length += meta_len;
597 meta_len = 0;
598 } else if (meta_len) {
599 if ((io.metadata & 3) || !io.metadata)
600 return -EINVAL;
601 }
602
603 memset(&c, 0, sizeof(c));
604 c.rw.opcode = io.opcode;
605 c.rw.flags = io.flags;
606 c.rw.nsid = cpu_to_le32(ns->ns_id);
607 c.rw.slba = cpu_to_le64(io.slba);
608 c.rw.length = cpu_to_le16(io.nblocks);
609 c.rw.control = cpu_to_le16(io.control);
610 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
611 c.rw.reftag = cpu_to_le32(io.reftag);
612 c.rw.apptag = cpu_to_le16(io.apptag);
613 c.rw.appmask = cpu_to_le16(io.appmask);
614
615 return __nvme_submit_user_cmd(ns->queue, &c,
616 (void __user *)(uintptr_t)io.addr, length,
617 metadata, meta_len, io.slba, NULL, 0);
618}
619
f3ca80fc 620static int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1673f1f0
CH
621 struct nvme_passthru_cmd __user *ucmd)
622{
623 struct nvme_passthru_cmd cmd;
624 struct nvme_command c;
625 unsigned timeout = 0;
626 int status;
627
628 if (!capable(CAP_SYS_ADMIN))
629 return -EACCES;
630 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
631 return -EFAULT;
63088ec7
KB
632 if (cmd.flags)
633 return -EINVAL;
1673f1f0
CH
634
635 memset(&c, 0, sizeof(c));
636 c.common.opcode = cmd.opcode;
637 c.common.flags = cmd.flags;
638 c.common.nsid = cpu_to_le32(cmd.nsid);
639 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
640 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
641 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
642 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
643 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
644 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
645 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
646 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
647
648 if (cmd.timeout_ms)
649 timeout = msecs_to_jiffies(cmd.timeout_ms);
650
651 status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c,
d1ea7be5 652 (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
1673f1f0
CH
653 &cmd.result, timeout);
654 if (status >= 0) {
655 if (put_user(cmd.result, &ucmd->result))
656 return -EFAULT;
657 }
658
659 return status;
660}
661
662static int nvme_ioctl(struct block_device *bdev, fmode_t mode,
663 unsigned int cmd, unsigned long arg)
664{
665 struct nvme_ns *ns = bdev->bd_disk->private_data;
666
667 switch (cmd) {
668 case NVME_IOCTL_ID:
669 force_successful_syscall_return();
670 return ns->ns_id;
671 case NVME_IOCTL_ADMIN_CMD:
672 return nvme_user_cmd(ns->ctrl, NULL, (void __user *)arg);
673 case NVME_IOCTL_IO_CMD:
674 return nvme_user_cmd(ns->ctrl, ns, (void __user *)arg);
675 case NVME_IOCTL_SUBMIT_IO:
676 return nvme_submit_io(ns, (void __user *)arg);
44907332 677#ifdef CONFIG_BLK_DEV_NVME_SCSI
1673f1f0
CH
678 case SG_GET_VERSION_NUM:
679 return nvme_sg_get_version_num((void __user *)arg);
680 case SG_IO:
681 return nvme_sg_io(ns, (void __user *)arg);
44907332 682#endif
1673f1f0
CH
683 default:
684 return -ENOTTY;
685 }
686}
687
688#ifdef CONFIG_COMPAT
689static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
690 unsigned int cmd, unsigned long arg)
691{
692 switch (cmd) {
693 case SG_IO:
694 return -ENOIOCTLCMD;
695 }
696 return nvme_ioctl(bdev, mode, cmd, arg);
697}
698#else
699#define nvme_compat_ioctl NULL
700#endif
701
702static int nvme_open(struct block_device *bdev, fmode_t mode)
703{
704 return nvme_get_ns_from_disk(bdev->bd_disk) ? 0 : -ENXIO;
705}
706
707static void nvme_release(struct gendisk *disk, fmode_t mode)
708{
e439bb12
SG
709 struct nvme_ns *ns = disk->private_data;
710
711 module_put(ns->ctrl->ops->module);
712 nvme_put_ns(ns);
1673f1f0
CH
713}
714
715static int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
716{
717 /* some standard values */
718 geo->heads = 1 << 6;
719 geo->sectors = 1 << 5;
720 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
721 return 0;
722}
723
724#ifdef CONFIG_BLK_DEV_INTEGRITY
725static void nvme_init_integrity(struct nvme_ns *ns)
726{
727 struct blk_integrity integrity;
728
729 switch (ns->pi_type) {
730 case NVME_NS_DPS_PI_TYPE3:
731 integrity.profile = &t10_pi_type3_crc;
732 break;
733 case NVME_NS_DPS_PI_TYPE1:
734 case NVME_NS_DPS_PI_TYPE2:
735 integrity.profile = &t10_pi_type1_crc;
736 break;
737 default:
738 integrity.profile = NULL;
739 break;
740 }
741 integrity.tuple_size = ns->ms;
742 blk_integrity_register(ns->disk, &integrity);
743 blk_queue_max_integrity_segments(ns->queue, 1);
744}
745#else
746static void nvme_init_integrity(struct nvme_ns *ns)
747{
748}
749#endif /* CONFIG_BLK_DEV_INTEGRITY */
750
751static void nvme_config_discard(struct nvme_ns *ns)
752{
08095e70 753 struct nvme_ctrl *ctrl = ns->ctrl;
1673f1f0 754 u32 logical_block_size = queue_logical_block_size(ns->queue);
08095e70
KB
755
756 if (ctrl->quirks & NVME_QUIRK_DISCARD_ZEROES)
757 ns->queue->limits.discard_zeroes_data = 1;
758 else
759 ns->queue->limits.discard_zeroes_data = 0;
760
1673f1f0
CH
761 ns->queue->limits.discard_alignment = logical_block_size;
762 ns->queue->limits.discard_granularity = logical_block_size;
763 blk_queue_max_discard_sectors(ns->queue, 0xffffffff);
764 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
765}
766
5bae7f73 767static int nvme_revalidate_disk(struct gendisk *disk)
1673f1f0
CH
768{
769 struct nvme_ns *ns = disk->private_data;
770 struct nvme_id_ns *id;
771 u8 lbaf, pi_type;
772 u16 old_ms;
773 unsigned short bs;
774
69d9a99c
KB
775 if (test_bit(NVME_NS_DEAD, &ns->flags)) {
776 set_capacity(disk, 0);
777 return -ENODEV;
778 }
1673f1f0 779 if (nvme_identify_ns(ns->ctrl, ns->ns_id, &id)) {
1b3c47c1
SG
780 dev_warn(disk_to_dev(ns->disk), "%s: Identify failure\n",
781 __func__);
1673f1f0
CH
782 return -ENODEV;
783 }
784 if (id->ncap == 0) {
785 kfree(id);
786 return -ENODEV;
787 }
788
789 if (nvme_nvm_ns_supported(ns, id) && ns->type != NVME_NS_LIGHTNVM) {
790 if (nvme_nvm_register(ns->queue, disk->disk_name)) {
1b3c47c1 791 dev_warn(disk_to_dev(ns->disk),
1673f1f0
CH
792 "%s: LightNVM init failure\n", __func__);
793 kfree(id);
794 return -ENODEV;
795 }
796 ns->type = NVME_NS_LIGHTNVM;
797 }
798
2b9b6e86
KB
799 if (ns->ctrl->vs >= NVME_VS(1, 1))
800 memcpy(ns->eui, id->eui64, sizeof(ns->eui));
801 if (ns->ctrl->vs >= NVME_VS(1, 2))
802 memcpy(ns->uuid, id->nguid, sizeof(ns->uuid));
803
1673f1f0
CH
804 old_ms = ns->ms;
805 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
806 ns->lba_shift = id->lbaf[lbaf].ds;
807 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
808 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
809
810 /*
811 * If identify namespace failed, use default 512 byte block size so
812 * block layer can use before failing read/write for 0 capacity.
813 */
814 if (ns->lba_shift == 0)
815 ns->lba_shift = 9;
816 bs = 1 << ns->lba_shift;
1673f1f0
CH
817 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
818 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
819 id->dps & NVME_NS_DPS_PI_MASK : 0;
820
821 blk_mq_freeze_queue(disk->queue);
822 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
823 ns->ms != old_ms ||
824 bs != queue_logical_block_size(disk->queue) ||
825 (ns->ms && ns->ext)))
826 blk_integrity_unregister(disk);
827
828 ns->pi_type = pi_type;
829 blk_queue_logical_block_size(ns->queue, bs);
830
4b9d5b15 831 if (ns->ms && !blk_get_integrity(disk) && !ns->ext)
1673f1f0 832 nvme_init_integrity(ns);
1673f1f0
CH
833 if (ns->ms && !(ns->ms == 8 && ns->pi_type) && !blk_get_integrity(disk))
834 set_capacity(disk, 0);
835 else
836 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
837
838 if (ns->ctrl->oncs & NVME_CTRL_ONCS_DSM)
839 nvme_config_discard(ns);
840 blk_mq_unfreeze_queue(disk->queue);
841
842 kfree(id);
843 return 0;
844}
845
846static char nvme_pr_type(enum pr_type type)
847{
848 switch (type) {
849 case PR_WRITE_EXCLUSIVE:
850 return 1;
851 case PR_EXCLUSIVE_ACCESS:
852 return 2;
853 case PR_WRITE_EXCLUSIVE_REG_ONLY:
854 return 3;
855 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
856 return 4;
857 case PR_WRITE_EXCLUSIVE_ALL_REGS:
858 return 5;
859 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
860 return 6;
861 default:
862 return 0;
863 }
864};
865
866static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
867 u64 key, u64 sa_key, u8 op)
868{
869 struct nvme_ns *ns = bdev->bd_disk->private_data;
870 struct nvme_command c;
871 u8 data[16] = { 0, };
872
873 put_unaligned_le64(key, &data[0]);
874 put_unaligned_le64(sa_key, &data[8]);
875
876 memset(&c, 0, sizeof(c));
877 c.common.opcode = op;
878 c.common.nsid = cpu_to_le32(ns->ns_id);
879 c.common.cdw10[0] = cpu_to_le32(cdw10);
880
881 return nvme_submit_sync_cmd(ns->queue, &c, data, 16);
882}
883
884static int nvme_pr_register(struct block_device *bdev, u64 old,
885 u64 new, unsigned flags)
886{
887 u32 cdw10;
888
889 if (flags & ~PR_FL_IGNORE_KEY)
890 return -EOPNOTSUPP;
891
892 cdw10 = old ? 2 : 0;
893 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
894 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
895 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
896}
897
898static int nvme_pr_reserve(struct block_device *bdev, u64 key,
899 enum pr_type type, unsigned flags)
900{
901 u32 cdw10;
902
903 if (flags & ~PR_FL_IGNORE_KEY)
904 return -EOPNOTSUPP;
905
906 cdw10 = nvme_pr_type(type) << 8;
907 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
908 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
909}
910
911static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
912 enum pr_type type, bool abort)
913{
914 u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
915 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
916}
917
918static int nvme_pr_clear(struct block_device *bdev, u64 key)
919{
8c0b3915 920 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
1673f1f0
CH
921 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
922}
923
924static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
925{
926 u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
927 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
928}
929
930static const struct pr_ops nvme_pr_ops = {
931 .pr_register = nvme_pr_register,
932 .pr_reserve = nvme_pr_reserve,
933 .pr_release = nvme_pr_release,
934 .pr_preempt = nvme_pr_preempt,
935 .pr_clear = nvme_pr_clear,
936};
937
5bae7f73 938static const struct block_device_operations nvme_fops = {
1673f1f0
CH
939 .owner = THIS_MODULE,
940 .ioctl = nvme_ioctl,
941 .compat_ioctl = nvme_compat_ioctl,
942 .open = nvme_open,
943 .release = nvme_release,
944 .getgeo = nvme_getgeo,
945 .revalidate_disk= nvme_revalidate_disk,
946 .pr_ops = &nvme_pr_ops,
947};
948
5fd4ce1b
CH
949static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
950{
951 unsigned long timeout =
952 ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
953 u32 csts, bit = enabled ? NVME_CSTS_RDY : 0;
954 int ret;
955
956 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
957 if ((csts & NVME_CSTS_RDY) == bit)
958 break;
959
960 msleep(100);
961 if (fatal_signal_pending(current))
962 return -EINTR;
963 if (time_after(jiffies, timeout)) {
1b3c47c1 964 dev_err(ctrl->device,
5fd4ce1b
CH
965 "Device not ready; aborting %s\n", enabled ?
966 "initialisation" : "reset");
967 return -ENODEV;
968 }
969 }
970
971 return ret;
972}
973
974/*
975 * If the device has been passed off to us in an enabled state, just clear
976 * the enabled bit. The spec says we should set the 'shutdown notification
977 * bits', but doing so may cause the device to complete commands to the
978 * admin queue ... and we don't know what memory that might be pointing at!
979 */
980int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
981{
982 int ret;
983
984 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
985 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
986
987 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
988 if (ret)
989 return ret;
990 return nvme_wait_ready(ctrl, cap, false);
991}
576d55d6 992EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b
CH
993
994int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
995{
996 /*
997 * Default to a 4K page size, with the intention to update this
998 * path in the future to accomodate architectures with differing
999 * kernel and IO page sizes.
1000 */
1001 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12, page_shift = 12;
1002 int ret;
1003
1004 if (page_shift < dev_page_min) {
1b3c47c1 1005 dev_err(ctrl->device,
5fd4ce1b
CH
1006 "Minimum device page size %u too large for host (%u)\n",
1007 1 << dev_page_min, 1 << page_shift);
1008 return -ENODEV;
1009 }
1010
1011 ctrl->page_size = 1 << page_shift;
1012
1013 ctrl->ctrl_config = NVME_CC_CSS_NVM;
1014 ctrl->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1015 ctrl->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1016 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1017 ctrl->ctrl_config |= NVME_CC_ENABLE;
1018
1019 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1020 if (ret)
1021 return ret;
1022 return nvme_wait_ready(ctrl, cap, true);
1023}
576d55d6 1024EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b
CH
1025
1026int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl)
1027{
1028 unsigned long timeout = SHUTDOWN_TIMEOUT + jiffies;
1029 u32 csts;
1030 int ret;
1031
1032 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1033 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
1034
1035 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1036 if (ret)
1037 return ret;
1038
1039 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
1040 if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_CMPLT)
1041 break;
1042
1043 msleep(100);
1044 if (fatal_signal_pending(current))
1045 return -EINTR;
1046 if (time_after(jiffies, timeout)) {
1b3c47c1 1047 dev_err(ctrl->device,
5fd4ce1b
CH
1048 "Device shutdown incomplete; abort shutdown\n");
1049 return -ENODEV;
1050 }
1051 }
1052
1053 return ret;
1054}
576d55d6 1055EXPORT_SYMBOL_GPL(nvme_shutdown_ctrl);
5fd4ce1b 1056
da35825d
CH
1057static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
1058 struct request_queue *q)
1059{
7c88cb00
JA
1060 bool vwc = false;
1061
da35825d 1062 if (ctrl->max_hw_sectors) {
45686b61
CH
1063 u32 max_segments =
1064 (ctrl->max_hw_sectors / (ctrl->page_size >> 9)) + 1;
1065
da35825d 1066 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
45686b61 1067 blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
da35825d
CH
1068 }
1069 if (ctrl->stripe_size)
1070 blk_queue_chunk_sectors(q, ctrl->stripe_size >> 9);
da35825d 1071 blk_queue_virt_boundary(q, ctrl->page_size - 1);
7c88cb00
JA
1072 if (ctrl->vwc & NVME_CTRL_VWC_PRESENT)
1073 vwc = true;
1074 blk_queue_write_cache(q, vwc, vwc);
da35825d
CH
1075}
1076
7fd8930f
CH
1077/*
1078 * Initialize the cached copies of the Identify data and various controller
1079 * register in our nvme_ctrl structure. This should be called as soon as
1080 * the admin queue is fully up and running.
1081 */
1082int nvme_init_identify(struct nvme_ctrl *ctrl)
1083{
1084 struct nvme_id_ctrl *id;
1085 u64 cap;
1086 int ret, page_shift;
1087
f3ca80fc
CH
1088 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
1089 if (ret) {
1b3c47c1 1090 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
f3ca80fc
CH
1091 return ret;
1092 }
1093
7fd8930f
CH
1094 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &cap);
1095 if (ret) {
1b3c47c1 1096 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
7fd8930f
CH
1097 return ret;
1098 }
1099 page_shift = NVME_CAP_MPSMIN(cap) + 12;
1100
f3ca80fc
CH
1101 if (ctrl->vs >= NVME_VS(1, 1))
1102 ctrl->subsystem = NVME_CAP_NSSRC(cap);
1103
7fd8930f
CH
1104 ret = nvme_identify_ctrl(ctrl, &id);
1105 if (ret) {
1b3c47c1 1106 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH
1107 return -EIO;
1108 }
1109
118472ab 1110 ctrl->vid = le16_to_cpu(id->vid);
7fd8930f 1111 ctrl->oncs = le16_to_cpup(&id->oncs);
6bf25d16 1112 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 1113 ctrl->vwc = id->vwc;
931e1c22 1114 ctrl->cntlid = le16_to_cpup(&id->cntlid);
7fd8930f
CH
1115 memcpy(ctrl->serial, id->sn, sizeof(id->sn));
1116 memcpy(ctrl->model, id->mn, sizeof(id->mn));
1117 memcpy(ctrl->firmware_rev, id->fr, sizeof(id->fr));
1118 if (id->mdts)
1119 ctrl->max_hw_sectors = 1 << (id->mdts + page_shift - 9);
1120 else
1121 ctrl->max_hw_sectors = UINT_MAX;
1122
1123 if ((ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) && id->vs[3]) {
1124 unsigned int max_hw_sectors;
1125
1126 ctrl->stripe_size = 1 << (id->vs[3] + page_shift);
1127 max_hw_sectors = ctrl->stripe_size >> (page_shift - 9);
1128 if (ctrl->max_hw_sectors) {
1129 ctrl->max_hw_sectors = min(max_hw_sectors,
1130 ctrl->max_hw_sectors);
1131 } else {
1132 ctrl->max_hw_sectors = max_hw_sectors;
1133 }
1134 }
1135
da35825d
CH
1136 nvme_set_queue_limits(ctrl, ctrl->admin_q);
1137
7fd8930f
CH
1138 kfree(id);
1139 return 0;
1140}
576d55d6 1141EXPORT_SYMBOL_GPL(nvme_init_identify);
7fd8930f 1142
f3ca80fc 1143static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 1144{
f3ca80fc
CH
1145 struct nvme_ctrl *ctrl;
1146 int instance = iminor(inode);
1147 int ret = -ENODEV;
1673f1f0 1148
f3ca80fc
CH
1149 spin_lock(&dev_list_lock);
1150 list_for_each_entry(ctrl, &nvme_ctrl_list, node) {
1151 if (ctrl->instance != instance)
1152 continue;
1153
1154 if (!ctrl->admin_q) {
1155 ret = -EWOULDBLOCK;
1156 break;
1157 }
1158 if (!kref_get_unless_zero(&ctrl->kref))
1159 break;
1160 file->private_data = ctrl;
1161 ret = 0;
1162 break;
1163 }
1164 spin_unlock(&dev_list_lock);
1165
1166 return ret;
1673f1f0
CH
1167}
1168
f3ca80fc 1169static int nvme_dev_release(struct inode *inode, struct file *file)
1673f1f0 1170{
f3ca80fc
CH
1171 nvme_put_ctrl(file->private_data);
1172 return 0;
1173}
1174
bfd89471
CH
1175static int nvme_dev_user_cmd(struct nvme_ctrl *ctrl, void __user *argp)
1176{
1177 struct nvme_ns *ns;
1178 int ret;
1179
1180 mutex_lock(&ctrl->namespaces_mutex);
1181 if (list_empty(&ctrl->namespaces)) {
1182 ret = -ENOTTY;
1183 goto out_unlock;
1184 }
1185
1186 ns = list_first_entry(&ctrl->namespaces, struct nvme_ns, list);
1187 if (ns != list_last_entry(&ctrl->namespaces, struct nvme_ns, list)) {
1b3c47c1 1188 dev_warn(ctrl->device,
bfd89471
CH
1189 "NVME_IOCTL_IO_CMD not supported when multiple namespaces present!\n");
1190 ret = -EINVAL;
1191 goto out_unlock;
1192 }
1193
1b3c47c1 1194 dev_warn(ctrl->device,
bfd89471
CH
1195 "using deprecated NVME_IOCTL_IO_CMD ioctl on the char device!\n");
1196 kref_get(&ns->kref);
1197 mutex_unlock(&ctrl->namespaces_mutex);
1198
1199 ret = nvme_user_cmd(ctrl, ns, argp);
1200 nvme_put_ns(ns);
1201 return ret;
1202
1203out_unlock:
1204 mutex_unlock(&ctrl->namespaces_mutex);
1205 return ret;
1206}
1207
f3ca80fc
CH
1208static long nvme_dev_ioctl(struct file *file, unsigned int cmd,
1209 unsigned long arg)
1210{
1211 struct nvme_ctrl *ctrl = file->private_data;
1212 void __user *argp = (void __user *)arg;
f3ca80fc
CH
1213
1214 switch (cmd) {
1215 case NVME_IOCTL_ADMIN_CMD:
1216 return nvme_user_cmd(ctrl, NULL, argp);
1217 case NVME_IOCTL_IO_CMD:
bfd89471 1218 return nvme_dev_user_cmd(ctrl, argp);
f3ca80fc 1219 case NVME_IOCTL_RESET:
1b3c47c1 1220 dev_warn(ctrl->device, "resetting controller\n");
f3ca80fc
CH
1221 return ctrl->ops->reset_ctrl(ctrl);
1222 case NVME_IOCTL_SUBSYS_RESET:
1223 return nvme_reset_subsystem(ctrl);
9ec3bb2f
KB
1224 case NVME_IOCTL_RESCAN:
1225 nvme_queue_scan(ctrl);
1226 return 0;
f3ca80fc
CH
1227 default:
1228 return -ENOTTY;
1229 }
1230}
1231
1232static const struct file_operations nvme_dev_fops = {
1233 .owner = THIS_MODULE,
1234 .open = nvme_dev_open,
1235 .release = nvme_dev_release,
1236 .unlocked_ioctl = nvme_dev_ioctl,
1237 .compat_ioctl = nvme_dev_ioctl,
1238};
1239
1240static ssize_t nvme_sysfs_reset(struct device *dev,
1241 struct device_attribute *attr, const char *buf,
1242 size_t count)
1243{
1244 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1245 int ret;
1246
1247 ret = ctrl->ops->reset_ctrl(ctrl);
1248 if (ret < 0)
1249 return ret;
1250 return count;
1673f1f0 1251}
f3ca80fc 1252static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
1673f1f0 1253
9ec3bb2f
KB
1254static ssize_t nvme_sysfs_rescan(struct device *dev,
1255 struct device_attribute *attr, const char *buf,
1256 size_t count)
1257{
1258 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1259
1260 nvme_queue_scan(ctrl);
1261 return count;
1262}
1263static DEVICE_ATTR(rescan_controller, S_IWUSR, NULL, nvme_sysfs_rescan);
1264
118472ab
KB
1265static ssize_t wwid_show(struct device *dev, struct device_attribute *attr,
1266 char *buf)
1267{
1268 struct nvme_ns *ns = dev_to_disk(dev)->private_data;
1269 struct nvme_ctrl *ctrl = ns->ctrl;
1270 int serial_len = sizeof(ctrl->serial);
1271 int model_len = sizeof(ctrl->model);
1272
1273 if (memchr_inv(ns->uuid, 0, sizeof(ns->uuid)))
1274 return sprintf(buf, "eui.%16phN\n", ns->uuid);
1275
1276 if (memchr_inv(ns->eui, 0, sizeof(ns->eui)))
1277 return sprintf(buf, "eui.%8phN\n", ns->eui);
1278
1279 while (ctrl->serial[serial_len - 1] == ' ')
1280 serial_len--;
1281 while (ctrl->model[model_len - 1] == ' ')
1282 model_len--;
1283
1284 return sprintf(buf, "nvme.%04x-%*phN-%*phN-%08x\n", ctrl->vid,
1285 serial_len, ctrl->serial, model_len, ctrl->model, ns->ns_id);
1286}
1287static DEVICE_ATTR(wwid, S_IRUGO, wwid_show, NULL);
1288
2b9b6e86
KB
1289static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,
1290 char *buf)
1291{
1292 struct nvme_ns *ns = dev_to_disk(dev)->private_data;
1293 return sprintf(buf, "%pU\n", ns->uuid);
1294}
1295static DEVICE_ATTR(uuid, S_IRUGO, uuid_show, NULL);
1296
1297static ssize_t eui_show(struct device *dev, struct device_attribute *attr,
1298 char *buf)
1299{
1300 struct nvme_ns *ns = dev_to_disk(dev)->private_data;
1301 return sprintf(buf, "%8phd\n", ns->eui);
1302}
1303static DEVICE_ATTR(eui, S_IRUGO, eui_show, NULL);
1304
1305static ssize_t nsid_show(struct device *dev, struct device_attribute *attr,
1306 char *buf)
1307{
1308 struct nvme_ns *ns = dev_to_disk(dev)->private_data;
1309 return sprintf(buf, "%d\n", ns->ns_id);
1310}
1311static DEVICE_ATTR(nsid, S_IRUGO, nsid_show, NULL);
1312
1313static struct attribute *nvme_ns_attrs[] = {
118472ab 1314 &dev_attr_wwid.attr,
2b9b6e86
KB
1315 &dev_attr_uuid.attr,
1316 &dev_attr_eui.attr,
1317 &dev_attr_nsid.attr,
1318 NULL,
1319};
1320
1321static umode_t nvme_attrs_are_visible(struct kobject *kobj,
1322 struct attribute *a, int n)
1323{
1324 struct device *dev = container_of(kobj, struct device, kobj);
1325 struct nvme_ns *ns = dev_to_disk(dev)->private_data;
1326
1327 if (a == &dev_attr_uuid.attr) {
1328 if (!memchr_inv(ns->uuid, 0, sizeof(ns->uuid)))
1329 return 0;
1330 }
1331 if (a == &dev_attr_eui.attr) {
1332 if (!memchr_inv(ns->eui, 0, sizeof(ns->eui)))
1333 return 0;
1334 }
1335 return a->mode;
1336}
1337
1338static const struct attribute_group nvme_ns_attr_group = {
1339 .attrs = nvme_ns_attrs,
1340 .is_visible = nvme_attrs_are_visible,
1341};
1342
931e1c22 1343#define nvme_show_str_function(field) \
779ff756
KB
1344static ssize_t field##_show(struct device *dev, \
1345 struct device_attribute *attr, char *buf) \
1346{ \
1347 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
1348 return sprintf(buf, "%.*s\n", (int)sizeof(ctrl->field), ctrl->field); \
1349} \
1350static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
1351
931e1c22
ML
1352#define nvme_show_int_function(field) \
1353static ssize_t field##_show(struct device *dev, \
1354 struct device_attribute *attr, char *buf) \
1355{ \
1356 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
1357 return sprintf(buf, "%d\n", ctrl->field); \
1358} \
1359static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
1360
1361nvme_show_str_function(model);
1362nvme_show_str_function(serial);
1363nvme_show_str_function(firmware_rev);
1364nvme_show_int_function(cntlid);
779ff756
KB
1365
1366static struct attribute *nvme_dev_attrs[] = {
1367 &dev_attr_reset_controller.attr,
9ec3bb2f 1368 &dev_attr_rescan_controller.attr,
779ff756
KB
1369 &dev_attr_model.attr,
1370 &dev_attr_serial.attr,
1371 &dev_attr_firmware_rev.attr,
931e1c22 1372 &dev_attr_cntlid.attr,
779ff756
KB
1373 NULL
1374};
1375
1376static struct attribute_group nvme_dev_attrs_group = {
1377 .attrs = nvme_dev_attrs,
1378};
1379
1380static const struct attribute_group *nvme_dev_attr_groups[] = {
1381 &nvme_dev_attrs_group,
1382 NULL,
1383};
1384
5bae7f73
CH
1385static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
1386{
1387 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
1388 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
1389
1390 return nsa->ns_id - nsb->ns_id;
1391}
1392
1393static struct nvme_ns *nvme_find_ns(struct nvme_ctrl *ctrl, unsigned nsid)
1394{
1395 struct nvme_ns *ns;
1396
69d3b8ac
CH
1397 lockdep_assert_held(&ctrl->namespaces_mutex);
1398
5bae7f73
CH
1399 list_for_each_entry(ns, &ctrl->namespaces, list) {
1400 if (ns->ns_id == nsid)
1401 return ns;
1402 if (ns->ns_id > nsid)
1403 break;
1404 }
1405 return NULL;
1406}
1407
1408static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
1409{
1410 struct nvme_ns *ns;
1411 struct gendisk *disk;
1412 int node = dev_to_node(ctrl->dev);
1413
69d3b8ac
CH
1414 lockdep_assert_held(&ctrl->namespaces_mutex);
1415
5bae7f73
CH
1416 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
1417 if (!ns)
1418 return;
1419
075790eb
KB
1420 ns->instance = ida_simple_get(&ctrl->ns_ida, 1, 0, GFP_KERNEL);
1421 if (ns->instance < 0)
1422 goto out_free_ns;
1423
5bae7f73
CH
1424 ns->queue = blk_mq_init_queue(ctrl->tagset);
1425 if (IS_ERR(ns->queue))
075790eb 1426 goto out_release_instance;
5bae7f73
CH
1427 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
1428 ns->queue->queuedata = ns;
1429 ns->ctrl = ctrl;
1430
1431 disk = alloc_disk_node(0, node);
1432 if (!disk)
1433 goto out_free_queue;
1434
1435 kref_init(&ns->kref);
1436 ns->ns_id = nsid;
1437 ns->disk = disk;
1438 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
5bae7f73 1439
da35825d 1440
5bae7f73 1441 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
da35825d 1442 nvme_set_queue_limits(ctrl, ns->queue);
5bae7f73
CH
1443
1444 disk->major = nvme_major;
1445 disk->first_minor = 0;
1446 disk->fops = &nvme_fops;
1447 disk->private_data = ns;
1448 disk->queue = ns->queue;
1449 disk->driverfs_dev = ctrl->device;
1450 disk->flags = GENHD_FL_EXT_DEVT;
075790eb 1451 sprintf(disk->disk_name, "nvme%dn%d", ctrl->instance, ns->instance);
5bae7f73 1452
5bae7f73
CH
1453 if (nvme_revalidate_disk(ns->disk))
1454 goto out_free_disk;
1455
0bf77e9d 1456 list_add_tail_rcu(&ns->list, &ctrl->namespaces);
5bae7f73 1457 kref_get(&ctrl->kref);
2b9b6e86
KB
1458 if (ns->type == NVME_NS_LIGHTNVM)
1459 return;
5bae7f73 1460
2b9b6e86
KB
1461 add_disk(ns->disk);
1462 if (sysfs_create_group(&disk_to_dev(ns->disk)->kobj,
1463 &nvme_ns_attr_group))
1464 pr_warn("%s: failed to create sysfs group for identification\n",
1465 ns->disk->disk_name);
5bae7f73
CH
1466 return;
1467 out_free_disk:
1468 kfree(disk);
5bae7f73
CH
1469 out_free_queue:
1470 blk_cleanup_queue(ns->queue);
075790eb
KB
1471 out_release_instance:
1472 ida_simple_remove(&ctrl->ns_ida, ns->instance);
5bae7f73
CH
1473 out_free_ns:
1474 kfree(ns);
1475}
1476
1477static void nvme_ns_remove(struct nvme_ns *ns)
1478{
b7b9c227
ML
1479 lockdep_assert_held(&ns->ctrl->namespaces_mutex);
1480
646017a6
KB
1481 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
1482 return;
69d3b8ac 1483
5bae7f73
CH
1484 if (ns->disk->flags & GENHD_FL_UP) {
1485 if (blk_get_integrity(ns->disk))
1486 blk_integrity_unregister(ns->disk);
2b9b6e86
KB
1487 sysfs_remove_group(&disk_to_dev(ns->disk)->kobj,
1488 &nvme_ns_attr_group);
5bae7f73 1489 del_gendisk(ns->disk);
5bae7f73
CH
1490 blk_mq_abort_requeue_list(ns->queue);
1491 blk_cleanup_queue(ns->queue);
1492 }
1493 list_del_init(&ns->list);
0bf77e9d 1494 synchronize_rcu();
5bae7f73
CH
1495 nvme_put_ns(ns);
1496}
1497
540c801c
KB
1498static void nvme_validate_ns(struct nvme_ctrl *ctrl, unsigned nsid)
1499{
1500 struct nvme_ns *ns;
1501
1502 ns = nvme_find_ns(ctrl, nsid);
1503 if (ns) {
1504 if (revalidate_disk(ns->disk))
1505 nvme_ns_remove(ns);
1506 } else
1507 nvme_alloc_ns(ctrl, nsid);
1508}
1509
1510static int nvme_scan_ns_list(struct nvme_ctrl *ctrl, unsigned nn)
1511{
1512 struct nvme_ns *ns;
1513 __le32 *ns_list;
1514 unsigned i, j, nsid, prev = 0, num_lists = DIV_ROUND_UP(nn, 1024);
1515 int ret = 0;
1516
1517 ns_list = kzalloc(0x1000, GFP_KERNEL);
1518 if (!ns_list)
1519 return -ENOMEM;
1520
1521 for (i = 0; i < num_lists; i++) {
1522 ret = nvme_identify_ns_list(ctrl, prev, ns_list);
1523 if (ret)
1524 goto out;
1525
1526 for (j = 0; j < min(nn, 1024U); j++) {
1527 nsid = le32_to_cpu(ns_list[j]);
1528 if (!nsid)
1529 goto out;
1530
1531 nvme_validate_ns(ctrl, nsid);
1532
1533 while (++prev < nsid) {
1534 ns = nvme_find_ns(ctrl, prev);
1535 if (ns)
1536 nvme_ns_remove(ns);
1537 }
1538 }
1539 nn -= j;
1540 }
1541 out:
1542 kfree(ns_list);
1543 return ret;
1544}
1545
5955be21 1546static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl, unsigned nn)
5bae7f73
CH
1547{
1548 struct nvme_ns *ns, *next;
1549 unsigned i;
1550
69d3b8ac
CH
1551 lockdep_assert_held(&ctrl->namespaces_mutex);
1552
540c801c
KB
1553 for (i = 1; i <= nn; i++)
1554 nvme_validate_ns(ctrl, i);
1555
5bae7f73
CH
1556 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
1557 if (ns->ns_id > nn)
1558 nvme_ns_remove(ns);
1559 }
5bae7f73
CH
1560}
1561
5955be21 1562static void nvme_scan_work(struct work_struct *work)
5bae7f73 1563{
5955be21
CH
1564 struct nvme_ctrl *ctrl =
1565 container_of(work, struct nvme_ctrl, scan_work);
5bae7f73 1566 struct nvme_id_ctrl *id;
540c801c 1567 unsigned nn;
5bae7f73 1568
5955be21
CH
1569 if (ctrl->state != NVME_CTRL_LIVE)
1570 return;
1571
5bae7f73
CH
1572 if (nvme_identify_ctrl(ctrl, &id))
1573 return;
540c801c 1574
69d3b8ac 1575 mutex_lock(&ctrl->namespaces_mutex);
540c801c
KB
1576 nn = le32_to_cpu(id->nn);
1577 if (ctrl->vs >= NVME_VS(1, 1) &&
1578 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
1579 if (!nvme_scan_ns_list(ctrl, nn))
1580 goto done;
1581 }
5955be21 1582 nvme_scan_ns_sequential(ctrl, nn);
540c801c
KB
1583 done:
1584 list_sort(NULL, &ctrl->namespaces, ns_cmp);
69d3b8ac 1585 mutex_unlock(&ctrl->namespaces_mutex);
5bae7f73 1586 kfree(id);
5955be21
CH
1587
1588 if (ctrl->ops->post_scan)
1589 ctrl->ops->post_scan(ctrl);
5bae7f73 1590}
5955be21
CH
1591
1592void nvme_queue_scan(struct nvme_ctrl *ctrl)
1593{
1594 /*
1595 * Do not queue new scan work when a controller is reset during
1596 * removal.
1597 */
1598 if (ctrl->state == NVME_CTRL_LIVE)
1599 schedule_work(&ctrl->scan_work);
1600}
1601EXPORT_SYMBOL_GPL(nvme_queue_scan);
5bae7f73
CH
1602
1603void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
1604{
1605 struct nvme_ns *ns, *next;
1606
0ff9d4e1
KB
1607 /*
1608 * The dead states indicates the controller was not gracefully
1609 * disconnected. In that case, we won't be able to flush any data while
1610 * removing the namespaces' disks; fail all the queues now to avoid
1611 * potentially having to clean up the failed sync later.
1612 */
1613 if (ctrl->state == NVME_CTRL_DEAD)
1614 nvme_kill_queues(ctrl);
1615
b7b9c227 1616 mutex_lock(&ctrl->namespaces_mutex);
5bae7f73
CH
1617 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list)
1618 nvme_ns_remove(ns);
b7b9c227 1619 mutex_unlock(&ctrl->namespaces_mutex);
5bae7f73 1620}
576d55d6 1621EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 1622
f866fc42
CH
1623static void nvme_async_event_work(struct work_struct *work)
1624{
1625 struct nvme_ctrl *ctrl =
1626 container_of(work, struct nvme_ctrl, async_event_work);
1627
1628 spin_lock_irq(&ctrl->lock);
1629 while (ctrl->event_limit > 0) {
1630 int aer_idx = --ctrl->event_limit;
1631
1632 spin_unlock_irq(&ctrl->lock);
1633 ctrl->ops->submit_async_event(ctrl, aer_idx);
1634 spin_lock_irq(&ctrl->lock);
1635 }
1636 spin_unlock_irq(&ctrl->lock);
1637}
1638
1639void nvme_complete_async_event(struct nvme_ctrl *ctrl,
1640 struct nvme_completion *cqe)
1641{
1642 u16 status = le16_to_cpu(cqe->status) >> 1;
1643 u32 result = le32_to_cpu(cqe->result);
1644
1645 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) {
1646 ++ctrl->event_limit;
1647 schedule_work(&ctrl->async_event_work);
1648 }
1649
1650 if (status != NVME_SC_SUCCESS)
1651 return;
1652
1653 switch (result & 0xff07) {
1654 case NVME_AER_NOTICE_NS_CHANGED:
1655 dev_info(ctrl->device, "rescanning\n");
1656 nvme_queue_scan(ctrl);
1657 break;
1658 default:
1659 dev_warn(ctrl->device, "async event result %08x\n", result);
1660 }
1661}
1662EXPORT_SYMBOL_GPL(nvme_complete_async_event);
1663
1664void nvme_queue_async_events(struct nvme_ctrl *ctrl)
1665{
1666 ctrl->event_limit = NVME_NR_AERS;
1667 schedule_work(&ctrl->async_event_work);
1668}
1669EXPORT_SYMBOL_GPL(nvme_queue_async_events);
1670
f3ca80fc
CH
1671static DEFINE_IDA(nvme_instance_ida);
1672
1673static int nvme_set_instance(struct nvme_ctrl *ctrl)
1674{
1675 int instance, error;
1676
1677 do {
1678 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
1679 return -ENODEV;
1680
1681 spin_lock(&dev_list_lock);
1682 error = ida_get_new(&nvme_instance_ida, &instance);
1683 spin_unlock(&dev_list_lock);
1684 } while (error == -EAGAIN);
1685
1686 if (error)
1687 return -ENODEV;
1688
1689 ctrl->instance = instance;
1690 return 0;
1691}
1692
1693static void nvme_release_instance(struct nvme_ctrl *ctrl)
1694{
1695 spin_lock(&dev_list_lock);
1696 ida_remove(&nvme_instance_ida, ctrl->instance);
1697 spin_unlock(&dev_list_lock);
1698}
1699
53029b04 1700void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
576d55d6 1701{
f866fc42 1702 flush_work(&ctrl->async_event_work);
5955be21
CH
1703 flush_work(&ctrl->scan_work);
1704 nvme_remove_namespaces(ctrl);
1705
53029b04 1706 device_destroy(nvme_class, MKDEV(nvme_char_major, ctrl->instance));
f3ca80fc
CH
1707
1708 spin_lock(&dev_list_lock);
1709 list_del(&ctrl->node);
1710 spin_unlock(&dev_list_lock);
53029b04 1711}
576d55d6 1712EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04
KB
1713
1714static void nvme_free_ctrl(struct kref *kref)
1715{
1716 struct nvme_ctrl *ctrl = container_of(kref, struct nvme_ctrl, kref);
f3ca80fc
CH
1717
1718 put_device(ctrl->device);
1719 nvme_release_instance(ctrl);
075790eb 1720 ida_destroy(&ctrl->ns_ida);
f3ca80fc
CH
1721
1722 ctrl->ops->free_ctrl(ctrl);
1723}
1724
1725void nvme_put_ctrl(struct nvme_ctrl *ctrl)
1726{
1727 kref_put(&ctrl->kref, nvme_free_ctrl);
1728}
576d55d6 1729EXPORT_SYMBOL_GPL(nvme_put_ctrl);
f3ca80fc
CH
1730
1731/*
1732 * Initialize a NVMe controller structures. This needs to be called during
1733 * earliest initialization so that we have the initialized structured around
1734 * during probing.
1735 */
1736int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
1737 const struct nvme_ctrl_ops *ops, unsigned long quirks)
1738{
1739 int ret;
1740
bb8d261e
CH
1741 ctrl->state = NVME_CTRL_NEW;
1742 spin_lock_init(&ctrl->lock);
f3ca80fc 1743 INIT_LIST_HEAD(&ctrl->namespaces);
69d3b8ac 1744 mutex_init(&ctrl->namespaces_mutex);
f3ca80fc
CH
1745 kref_init(&ctrl->kref);
1746 ctrl->dev = dev;
1747 ctrl->ops = ops;
1748 ctrl->quirks = quirks;
5955be21 1749 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 1750 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
f3ca80fc
CH
1751
1752 ret = nvme_set_instance(ctrl);
1753 if (ret)
1754 goto out;
1755
779ff756 1756 ctrl->device = device_create_with_groups(nvme_class, ctrl->dev,
f3ca80fc 1757 MKDEV(nvme_char_major, ctrl->instance),
f4f0f63e 1758 ctrl, nvme_dev_attr_groups,
779ff756 1759 "nvme%d", ctrl->instance);
f3ca80fc
CH
1760 if (IS_ERR(ctrl->device)) {
1761 ret = PTR_ERR(ctrl->device);
1762 goto out_release_instance;
1763 }
1764 get_device(ctrl->device);
075790eb 1765 ida_init(&ctrl->ns_ida);
f3ca80fc 1766
f3ca80fc
CH
1767 spin_lock(&dev_list_lock);
1768 list_add_tail(&ctrl->node, &nvme_ctrl_list);
1769 spin_unlock(&dev_list_lock);
1770
1771 return 0;
f3ca80fc
CH
1772out_release_instance:
1773 nvme_release_instance(ctrl);
1774out:
1775 return ret;
1776}
576d55d6 1777EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 1778
69d9a99c
KB
1779/**
1780 * nvme_kill_queues(): Ends all namespace queues
1781 * @ctrl: the dead controller that needs to end
1782 *
1783 * Call this function when the driver determines it is unable to get the
1784 * controller in a state capable of servicing IO.
1785 */
1786void nvme_kill_queues(struct nvme_ctrl *ctrl)
1787{
1788 struct nvme_ns *ns;
1789
0bf77e9d
ML
1790 rcu_read_lock();
1791 list_for_each_entry_rcu(ns, &ctrl->namespaces, list) {
69d9a99c
KB
1792 if (!kref_get_unless_zero(&ns->kref))
1793 continue;
1794
1795 /*
1796 * Revalidating a dead namespace sets capacity to 0. This will
1797 * end buffered writers dirtying pages that can't be synced.
1798 */
1799 if (!test_and_set_bit(NVME_NS_DEAD, &ns->flags))
1800 revalidate_disk(ns->disk);
1801
1802 blk_set_queue_dying(ns->queue);
1803 blk_mq_abort_requeue_list(ns->queue);
1804 blk_mq_start_stopped_hw_queues(ns->queue, true);
1805
1806 nvme_put_ns(ns);
1807 }
0bf77e9d 1808 rcu_read_unlock();
69d9a99c 1809}
237045fc 1810EXPORT_SYMBOL_GPL(nvme_kill_queues);
69d9a99c 1811
25646264 1812void nvme_stop_queues(struct nvme_ctrl *ctrl)
363c9aac
SG
1813{
1814 struct nvme_ns *ns;
1815
0bf77e9d
ML
1816 rcu_read_lock();
1817 list_for_each_entry_rcu(ns, &ctrl->namespaces, list) {
363c9aac
SG
1818 spin_lock_irq(ns->queue->queue_lock);
1819 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
1820 spin_unlock_irq(ns->queue->queue_lock);
1821
1822 blk_mq_cancel_requeue_work(ns->queue);
1823 blk_mq_stop_hw_queues(ns->queue);
1824 }
0bf77e9d 1825 rcu_read_unlock();
363c9aac 1826}
576d55d6 1827EXPORT_SYMBOL_GPL(nvme_stop_queues);
363c9aac 1828
25646264 1829void nvme_start_queues(struct nvme_ctrl *ctrl)
363c9aac
SG
1830{
1831 struct nvme_ns *ns;
1832
0bf77e9d
ML
1833 rcu_read_lock();
1834 list_for_each_entry_rcu(ns, &ctrl->namespaces, list) {
363c9aac 1835 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
363c9aac
SG
1836 blk_mq_start_stopped_hw_queues(ns->queue, true);
1837 blk_mq_kick_requeue_list(ns->queue);
1838 }
0bf77e9d 1839 rcu_read_unlock();
363c9aac 1840}
576d55d6 1841EXPORT_SYMBOL_GPL(nvme_start_queues);
363c9aac 1842
5bae7f73
CH
1843int __init nvme_core_init(void)
1844{
1845 int result;
1846
1847 result = register_blkdev(nvme_major, "nvme");
1848 if (result < 0)
1849 return result;
1850 else if (result > 0)
1851 nvme_major = result;
1852
f3ca80fc
CH
1853 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
1854 &nvme_dev_fops);
1855 if (result < 0)
1856 goto unregister_blkdev;
1857 else if (result > 0)
1858 nvme_char_major = result;
1859
1860 nvme_class = class_create(THIS_MODULE, "nvme");
1861 if (IS_ERR(nvme_class)) {
1862 result = PTR_ERR(nvme_class);
1863 goto unregister_chrdev;
1864 }
1865
5bae7f73 1866 return 0;
f3ca80fc
CH
1867
1868 unregister_chrdev:
1869 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
1870 unregister_blkdev:
1871 unregister_blkdev(nvme_major, "nvme");
1872 return result;
5bae7f73
CH
1873}
1874
1875void nvme_core_exit(void)
1876{
f3ca80fc
CH
1877 class_destroy(nvme_class);
1878 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
23bd63ce 1879 unregister_blkdev(nvme_major, "nvme");
5bae7f73 1880}
576d55d6
ML
1881
1882MODULE_LICENSE("GPL");
1883MODULE_VERSION("1.0");
1884module_init(nvme_core_init);
1885module_exit(nvme_core_exit);