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nvme: add symbolic constants for CC identifiers
[mirror_ubuntu-bionic-kernel.git] / drivers / nvme / host / core.c
CommitLineData
21d34711
CH		 1/*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/blkdev.h>
16#include <linux/blk-mq.h>
5fd4ce1b 17#include <linux/delay.h>
21d34711 18#include <linux/errno.h>
1673f1f0 19#include <linux/hdreg.h>
21d34711 20#include <linux/kernel.h>
5bae7f73
CH		 21#include <linux/module.h>
22#include <linux/list_sort.h>
21d34711
CH		 23#include <linux/slab.h>
24#include <linux/types.h>
1673f1f0
CH		 25#include <linux/pr.h>
26#include <linux/ptrace.h>
27#include <linux/nvme_ioctl.h>
28#include <linux/t10-pi.h>
c5552fde 29#include <linux/pm_qos.h>
1673f1f0 30#include <asm/unaligned.h>
21d34711
CH		 31
32#include "nvme.h"
038bd4cb 33#include "fabrics.h"
21d34711 34
f3ca80fc
CH		 35#define NVME_MINORS (1U << MINORBITS)
36
ba0ba7d3
ML		 37unsigned char admin_timeout = 60;
38module_param(admin_timeout, byte, 0644);
39MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 40EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3
ML		 41
42unsigned char nvme_io_timeout = 30;
43module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
44MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 45EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3 46
b3b1b0b0 47static unsigned char shutdown_timeout = 5;
ba0ba7d3
ML		 48module_param(shutdown_timeout, byte, 0644);
49MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
50
44e44b29
CH		 51static u8 nvme_max_retries = 5;
52module_param_named(max_retries, nvme_max_retries, byte, 0644);
f80ec966 53MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
5bae7f73 54
f3ca80fc
CH		 55static int nvme_char_major;
56module_param(nvme_char_major, int, 0);
57
9947d6a0 58static unsigned long default_ps_max_latency_us = 100000;
c5552fde
AL		 59module_param(default_ps_max_latency_us, ulong, 0644);
60MODULE_PARM_DESC(default_ps_max_latency_us,
61 "max power saving latency for new devices; use PM QOS to change per device");
62
c35e30b4
AL		 63static bool force_apst;
64module_param(force_apst, bool, 0644);
65MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off");
66
f5d11840
JA		 67static bool streams;
68module_param(streams, bool, 0644);
69MODULE_PARM_DESC(streams, "turn on support for Streams write directives");
70
9a6327d2
SG		 71struct workqueue_struct *nvme_wq;
72EXPORT_SYMBOL_GPL(nvme_wq);
73
f3ca80fc 74static LIST_HEAD(nvme_ctrl_list);
9f2482b9 75static DEFINE_SPINLOCK(dev_list_lock);
1673f1f0 76
f3ca80fc
CH		 77static struct class *nvme_class;
78
b6dccf7f
AD		 79static __le32 nvme_get_log_dw10(u8 lid, size_t size)
80{
81 return cpu_to_le32((((size / 4) - 1) << 16) | lid);
82}
83
d86c4d8e
CH		 84int nvme_reset_ctrl(struct nvme_ctrl *ctrl)
85{
86 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
87 return -EBUSY;
88 if (!queue_work(nvme_wq, &ctrl->reset_work))
89 return -EBUSY;
90 return 0;
91}
92EXPORT_SYMBOL_GPL(nvme_reset_ctrl);
93
94static int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
95{
96 int ret;
97
98 ret = nvme_reset_ctrl(ctrl);
99 if (!ret)
100 flush_work(&ctrl->reset_work);
101 return ret;
102}
103
2a842aca 104static blk_status_t nvme_error_status(struct request *req)
27fa9bc5
CH		 105{
106 switch (nvme_req(req)->status & 0x7ff) {
107 case NVME_SC_SUCCESS:
2a842aca 108 return BLK_STS_OK;
27fa9bc5 109 case NVME_SC_CAP_EXCEEDED:
2a842aca 110 return BLK_STS_NOSPC;
e02ab023 111 case NVME_SC_ONCS_NOT_SUPPORTED:
2a842aca 112 return BLK_STS_NOTSUPP;
e02ab023
JG		 113 case NVME_SC_WRITE_FAULT:
114 case NVME_SC_READ_ERROR:
115 case NVME_SC_UNWRITTEN_BLOCK:
2a842aca
CH		 116 return BLK_STS_MEDIUM;
117 default:
118 return BLK_STS_IOERR;
27fa9bc5
CH		 119 }
120}
27fa9bc5 121
f6324b1b 122static inline bool nvme_req_needs_retry(struct request *req)
77f02a7a 123{
f6324b1b
CH		 124 if (blk_noretry_request(req))
125 return false;
27fa9bc5 126 if (nvme_req(req)->status & NVME_SC_DNR)
f6324b1b
CH		 127 return false;
128 if (jiffies - req->start_time >= req->timeout)
129 return false;
44e44b29 130 if (nvme_req(req)->retries >= nvme_max_retries)
f6324b1b
CH		 131 return false;
132 return true;
77f02a7a
CH		 133}
134
135void nvme_complete_rq(struct request *req)
136{
27fa9bc5
CH		 137 if (unlikely(nvme_req(req)->status && nvme_req_needs_retry(req))) {
138 nvme_req(req)->retries++;
8d7b8faf 139 blk_mq_requeue_request(req, true);
27fa9bc5 140 return;
77f02a7a
CH		 141 }
142
27fa9bc5 143 blk_mq_end_request(req, nvme_error_status(req));
77f02a7a
CH		 144}
145EXPORT_SYMBOL_GPL(nvme_complete_rq);
146
c55a2fd4
ML		 147void nvme_cancel_request(struct request *req, void *data, bool reserved)
148{
149 int status;
150
151 if (!blk_mq_request_started(req))
152 return;
153
154 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
155 "Cancelling I/O %d", req->tag);
156
157 status = NVME_SC_ABORT_REQ;
158 if (blk_queue_dying(req->q))
159 status |= NVME_SC_DNR;
27fa9bc5 160 nvme_req(req)->status = status;
08e0029a 161 blk_mq_complete_request(req);
27fa9bc5 162
c55a2fd4
ML		 163}
164EXPORT_SYMBOL_GPL(nvme_cancel_request);
165
bb8d261e
CH		 166bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
167 enum nvme_ctrl_state new_state)
168{
f6b6a28e 169 enum nvme_ctrl_state old_state;
bb8d261e
CH		 170 bool changed = false;
171
172 spin_lock_irq(&ctrl->lock);
f6b6a28e
GKB		 173
174 old_state = ctrl->state;
bb8d261e
CH		 175 switch (new_state) {
176 case NVME_CTRL_LIVE:
177 switch (old_state) {
7d2e8008 178 case NVME_CTRL_NEW:
bb8d261e 179 case NVME_CTRL_RESETTING:
def61eca 180 case NVME_CTRL_RECONNECTING:
bb8d261e
CH		 181 changed = true;
182 /* FALLTHRU */
183 default:
184 break;
185 }
186 break;
187 case NVME_CTRL_RESETTING:
188 switch (old_state) {
189 case NVME_CTRL_NEW:
def61eca 190 case NVME_CTRL_LIVE:
def61eca
CH		 191 changed = true;
192 /* FALLTHRU */
193 default:
194 break;
195 }
196 break;
197 case NVME_CTRL_RECONNECTING:
198 switch (old_state) {
bb8d261e
CH		 199 case NVME_CTRL_LIVE:
200 changed = true;
201 /* FALLTHRU */
202 default:
203 break;
204 }
205 break;
206 case NVME_CTRL_DELETING:
207 switch (old_state) {
208 case NVME_CTRL_LIVE:
209 case NVME_CTRL_RESETTING:
def61eca 210 case NVME_CTRL_RECONNECTING:
bb8d261e
CH		 211 changed = true;
212 /* FALLTHRU */
213 default:
214 break;
215 }
216 break;
0ff9d4e1
KB		 217 case NVME_CTRL_DEAD:
218 switch (old_state) {
219 case NVME_CTRL_DELETING:
220 changed = true;
221 /* FALLTHRU */
222 default:
223 break;
224 }
225 break;
bb8d261e
CH		 226 default:
227 break;
228 }
bb8d261e
CH		 229
230 if (changed)
231 ctrl->state = new_state;
232
f6b6a28e
GKB		 233 spin_unlock_irq(&ctrl->lock);
234
bb8d261e
CH		 235 return changed;
236}
237EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
238
1673f1f0
CH		 239static void nvme_free_ns(struct kref *kref)
240{
241 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
242
b0b4e09c
MB		 243 if (ns->ndev)
244 nvme_nvm_unregister(ns);
1673f1f0 245
b0b4e09c
MB		 246 if (ns->disk) {
247 spin_lock(&dev_list_lock);
248 ns->disk->private_data = NULL;
249 spin_unlock(&dev_list_lock);
250 }
1673f1f0 251
1673f1f0 252 put_disk(ns->disk);
075790eb
KB		 253 ida_simple_remove(&ns->ctrl->ns_ida, ns->instance);
254 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH		 255 kfree(ns);
256}
257
5bae7f73 258static void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH		 259{
260 kref_put(&ns->kref, nvme_free_ns);
261}
262
263static struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk)
264{
265 struct nvme_ns *ns;
266
267 spin_lock(&dev_list_lock);
268 ns = disk->private_data;
e439bb12
SG		 269 if (ns) {
270 if (!kref_get_unless_zero(&ns->kref))
271 goto fail;
272 if (!try_module_get(ns->ctrl->ops->module))
273 goto fail_put_ns;
274 }
1673f1f0
CH		 275 spin_unlock(&dev_list_lock);
276
277 return ns;
e439bb12
SG		 278
279fail_put_ns:
280 kref_put(&ns->kref, nvme_free_ns);
281fail:
282 spin_unlock(&dev_list_lock);
283 return NULL;
1673f1f0
CH		 284}
285
4160982e 286struct request *nvme_alloc_request(struct request_queue *q,
eb71f435 287 struct nvme_command *cmd, unsigned int flags, int qid)
21d34711 288{
aebf526b 289 unsigned op = nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN;
21d34711 290 struct request *req;
21d34711 291
eb71f435 292 if (qid == NVME_QID_ANY) {
aebf526b 293 req = blk_mq_alloc_request(q, op, flags);
eb71f435 294 } else {
aebf526b 295 req = blk_mq_alloc_request_hctx(q, op, flags,
eb71f435
CH		 296 qid ? qid - 1 : 0);
297 }
21d34711 298 if (IS_ERR(req))
4160982e 299 return req;
21d34711 300
21d34711 301 req->cmd_flags |= REQ_FAILFAST_DRIVER;
d49187e9 302 nvme_req(req)->cmd = cmd;
21d34711 303
4160982e
CH		 304 return req;
305}
576d55d6 306EXPORT_SYMBOL_GPL(nvme_alloc_request);
4160982e 307
f5d11840
JA		 308static int nvme_toggle_streams(struct nvme_ctrl *ctrl, bool enable)
309{
310 struct nvme_command c;
311
312 memset(&c, 0, sizeof(c));
313
314 c.directive.opcode = nvme_admin_directive_send;
62346eae 315 c.directive.nsid = cpu_to_le32(NVME_NSID_ALL);
f5d11840
JA		 316 c.directive.doper = NVME_DIR_SND_ID_OP_ENABLE;
317 c.directive.dtype = NVME_DIR_IDENTIFY;
318 c.directive.tdtype = NVME_DIR_STREAMS;
319 c.directive.endir = enable ? NVME_DIR_ENDIR : 0;
320
321 return nvme_submit_sync_cmd(ctrl->admin_q, &c, NULL, 0);
322}
323
324static int nvme_disable_streams(struct nvme_ctrl *ctrl)
325{
326 return nvme_toggle_streams(ctrl, false);
327}
328
329static int nvme_enable_streams(struct nvme_ctrl *ctrl)
330{
331 return nvme_toggle_streams(ctrl, true);
332}
333
334static int nvme_get_stream_params(struct nvme_ctrl *ctrl,
335 struct streams_directive_params *s, u32 nsid)
336{
337 struct nvme_command c;
338
339 memset(&c, 0, sizeof(c));
340 memset(s, 0, sizeof(*s));
341
342 c.directive.opcode = nvme_admin_directive_recv;
343 c.directive.nsid = cpu_to_le32(nsid);
a082b426 344 c.directive.numd = cpu_to_le32((sizeof(*s) >> 2) - 1);
f5d11840
JA		 345 c.directive.doper = NVME_DIR_RCV_ST_OP_PARAM;
346 c.directive.dtype = NVME_DIR_STREAMS;
347
348 return nvme_submit_sync_cmd(ctrl->admin_q, &c, s, sizeof(*s));
349}
350
351static int nvme_configure_directives(struct nvme_ctrl *ctrl)
352{
353 struct streams_directive_params s;
354 int ret;
355
356 if (!(ctrl->oacs & NVME_CTRL_OACS_DIRECTIVES))
357 return 0;
358 if (!streams)
359 return 0;
360
361 ret = nvme_enable_streams(ctrl);
362 if (ret)
363 return ret;
364
62346eae 365 ret = nvme_get_stream_params(ctrl, &s, NVME_NSID_ALL);
f5d11840
JA		 366 if (ret)
367 return ret;
368
369 ctrl->nssa = le16_to_cpu(s.nssa);
370 if (ctrl->nssa < BLK_MAX_WRITE_HINTS - 1) {
371 dev_info(ctrl->device, "too few streams (%u) available\n",
372 ctrl->nssa);
373 nvme_disable_streams(ctrl);
374 return 0;
375 }
376
377 ctrl->nr_streams = min_t(unsigned, ctrl->nssa, BLK_MAX_WRITE_HINTS - 1);
378 dev_info(ctrl->device, "Using %u streams\n", ctrl->nr_streams);
379 return 0;
380}
381
382/*
383 * Check if 'req' has a write hint associated with it. If it does, assign
384 * a valid namespace stream to the write.
385 */
386static void nvme_assign_write_stream(struct nvme_ctrl *ctrl,
387 struct request *req, u16 *control,
388 u32 *dsmgmt)
389{
390 enum rw_hint streamid = req->write_hint;
391
392 if (streamid == WRITE_LIFE_NOT_SET || streamid == WRITE_LIFE_NONE)
393 streamid = 0;
394 else {
395 streamid--;
396 if (WARN_ON_ONCE(streamid > ctrl->nr_streams))
397 return;
398
399 *control |= NVME_RW_DTYPE_STREAMS;
400 *dsmgmt |= streamid << 16;
401 }
402
403 if (streamid < ARRAY_SIZE(req->q->write_hints))
404 req->q->write_hints[streamid] += blk_rq_bytes(req) >> 9;
405}
406
8093f7ca
ML		 407static inline void nvme_setup_flush(struct nvme_ns *ns,
408 struct nvme_command *cmnd)
409{
410 memset(cmnd, 0, sizeof(*cmnd));
411 cmnd->common.opcode = nvme_cmd_flush;
412 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
413}
414
fc17b653 415static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 416 struct nvme_command *cmnd)
417{
b35ba01e 418 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
8093f7ca 419 struct nvme_dsm_range *range;
b35ba01e 420 struct bio *bio;
8093f7ca 421
b35ba01e 422 range = kmalloc_array(segments, sizeof(*range), GFP_ATOMIC);
8093f7ca 423 if (!range)
fc17b653 424 return BLK_STS_RESOURCE;
8093f7ca 425
b35ba01e
CH		 426 __rq_for_each_bio(bio, req) {
427 u64 slba = nvme_block_nr(ns, bio->bi_iter.bi_sector);
428 u32 nlb = bio->bi_iter.bi_size >> ns->lba_shift;
429
430 range[n].cattr = cpu_to_le32(0);
431 range[n].nlb = cpu_to_le32(nlb);
432 range[n].slba = cpu_to_le64(slba);
433 n++;
434 }
435
436 if (WARN_ON_ONCE(n != segments)) {
437 kfree(range);
fc17b653 438 return BLK_STS_IOERR;
b35ba01e 439 }
8093f7ca
ML		 440
441 memset(cmnd, 0, sizeof(*cmnd));
442 cmnd->dsm.opcode = nvme_cmd_dsm;
443 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
f1dd03a8 444 cmnd->dsm.nr = cpu_to_le32(segments - 1);
8093f7ca
ML		 445 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
446
f9d03f96
CH		 447 req->special_vec.bv_page = virt_to_page(range);
448 req->special_vec.bv_offset = offset_in_page(range);
b35ba01e 449 req->special_vec.bv_len = sizeof(*range) * segments;
f9d03f96 450 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 451
fc17b653 452 return BLK_STS_OK;
8093f7ca 453}
8093f7ca 454
ebe6d874
CH		 455static inline blk_status_t nvme_setup_rw(struct nvme_ns *ns,
456 struct request *req, struct nvme_command *cmnd)
8093f7ca 457{
f5d11840 458 struct nvme_ctrl *ctrl = ns->ctrl;
8093f7ca
ML		 459 u16 control = 0;
460 u32 dsmgmt = 0;
461
ebe6d874
CH		 462 /*
463 * If formated with metadata, require the block layer provide a buffer
464 * unless this namespace is formated such that the metadata can be
465 * stripped/generated by the controller with PRACT=1.
466 */
8fa61121
SG		 467 if (ns && ns->ms &&
468 (!ns->pi_type || ns->ms != sizeof(struct t10_pi_tuple)) &&
ebe6d874
CH		 469 !blk_integrity_rq(req) && !blk_rq_is_passthrough(req))
470 return BLK_STS_NOTSUPP;
471
8093f7ca
ML		 472 if (req->cmd_flags & REQ_FUA)
473 control |= NVME_RW_FUA;
474 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
475 control |= NVME_RW_LR;
476
477 if (req->cmd_flags & REQ_RAHEAD)
478 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
479
480 memset(cmnd, 0, sizeof(*cmnd));
481 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
8093f7ca
ML		 482 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
483 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
484 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
485
f5d11840
JA		 486 if (req_op(req) == REQ_OP_WRITE && ctrl->nr_streams)
487 nvme_assign_write_stream(ctrl, req, &control, &dsmgmt);
488
8093f7ca
ML		 489 if (ns->ms) {
490 switch (ns->pi_type) {
491 case NVME_NS_DPS_PI_TYPE3:
492 control |= NVME_RW_PRINFO_PRCHK_GUARD;
493 break;
494 case NVME_NS_DPS_PI_TYPE1:
495 case NVME_NS_DPS_PI_TYPE2:
496 control |= NVME_RW_PRINFO_PRCHK_GUARD |
497 NVME_RW_PRINFO_PRCHK_REF;
498 cmnd->rw.reftag = cpu_to_le32(
499 nvme_block_nr(ns, blk_rq_pos(req)));
500 break;
501 }
502 if (!blk_integrity_rq(req))
503 control |= NVME_RW_PRINFO_PRACT;
504 }
505
506 cmnd->rw.control = cpu_to_le16(control);
507 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
ebe6d874 508 return 0;
8093f7ca
ML		 509}
510
fc17b653 511blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 512 struct nvme_command *cmd)
513{
fc17b653 514 blk_status_t ret = BLK_STS_OK;
8093f7ca 515
987f699a 516 if (!(req->rq_flags & RQF_DONTPREP)) {
44e44b29 517 nvme_req(req)->retries = 0;
27fa9bc5 518 nvme_req(req)->flags = 0;
987f699a
CH		 519 req->rq_flags |= RQF_DONTPREP;
520 }
521
aebf526b
CH		 522 switch (req_op(req)) {
523 case REQ_OP_DRV_IN:
524 case REQ_OP_DRV_OUT:
d49187e9 525 memcpy(cmd, nvme_req(req)->cmd, sizeof(*cmd));
aebf526b
CH		 526 break;
527 case REQ_OP_FLUSH:
8093f7ca 528 nvme_setup_flush(ns, cmd);
aebf526b 529 break;
e850fd16
CH		 530 case REQ_OP_WRITE_ZEROES:
531 /* currently only aliased to deallocate for a few ctrls: */
aebf526b 532 case REQ_OP_DISCARD:
8093f7ca 533 ret = nvme_setup_discard(ns, req, cmd);
aebf526b
CH		 534 break;
535 case REQ_OP_READ:
536 case REQ_OP_WRITE:
ebe6d874 537 ret = nvme_setup_rw(ns, req, cmd);
aebf526b
CH		 538 break;
539 default:
540 WARN_ON_ONCE(1);
fc17b653 541 return BLK_STS_IOERR;
aebf526b 542 }
8093f7ca 543
721b3917 544 cmd->common.command_id = req->tag;
8093f7ca
ML		 545 return ret;
546}
547EXPORT_SYMBOL_GPL(nvme_setup_cmd);
548
4160982e
CH		 549/*
550 * Returns 0 on success. If the result is negative, it's a Linux error code;
551 * if the result is positive, it's an NVM Express status code
552 */
553int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 554 union nvme_result *result, void *buffer, unsigned bufflen,
eb71f435 555 unsigned timeout, int qid, int at_head, int flags)
4160982e
CH		 556{
557 struct request *req;
558 int ret;
559
eb71f435 560 req = nvme_alloc_request(q, cmd, flags, qid);
4160982e
CH		 561 if (IS_ERR(req))
562 return PTR_ERR(req);
563
564 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
565
21d34711
CH		 566 if (buffer && bufflen) {
567 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
568 if (ret)
569 goto out;
4160982e
CH		 570 }
571
eb71f435 572 blk_execute_rq(req->q, NULL, req, at_head);
d49187e9
CH		 573 if (result)
574 *result = nvme_req(req)->result;
27fa9bc5
CH		 575 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
576 ret = -EINTR;
577 else
578 ret = nvme_req(req)->status;
4160982e
CH		 579 out:
580 blk_mq_free_request(req);
581 return ret;
582}
eb71f435 583EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH		 584
585int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
586 void *buffer, unsigned bufflen)
587{
eb71f435
CH		 588 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 0,
589 NVME_QID_ANY, 0, 0);
4160982e 590}
576d55d6 591EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 592
0b7f1f26
KB		 593int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
594 void __user *ubuffer, unsigned bufflen,
595 void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
596 u32 *result, unsigned timeout)
4160982e 597{
7a5abb4b 598 bool write = nvme_is_write(cmd);
0b7f1f26
KB		 599 struct nvme_ns *ns = q->queuedata;
600 struct gendisk *disk = ns ? ns->disk : NULL;
4160982e 601 struct request *req;
0b7f1f26
KB		 602 struct bio *bio = NULL;
603 void *meta = NULL;
4160982e
CH		 604 int ret;
605
eb71f435 606 req = nvme_alloc_request(q, cmd, 0, NVME_QID_ANY);
4160982e
CH		 607 if (IS_ERR(req))
608 return PTR_ERR(req);
609
610 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
611
612 if (ubuffer && bufflen) {
21d34711
CH		 613 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
614 GFP_KERNEL);
615 if (ret)
616 goto out;
617 bio = req->bio;
21d34711 618
0b7f1f26
KB		 619 if (!disk)
620 goto submit;
74d46992 621 bio->bi_disk = disk;
0b7f1f26 622
e9fc63d6 623 if (meta_buffer && meta_len) {
0b7f1f26
KB		 624 struct bio_integrity_payload *bip;
625
626 meta = kmalloc(meta_len, GFP_KERNEL);
627 if (!meta) {
628 ret = -ENOMEM;
629 goto out_unmap;
630 }
631
632 if (write) {
633 if (copy_from_user(meta, meta_buffer,
634 meta_len)) {
635 ret = -EFAULT;
636 goto out_free_meta;
637 }
638 }
639
640 bip = bio_integrity_alloc(bio, GFP_KERNEL, 1);
06c1e390
KB		 641 if (IS_ERR(bip)) {
642 ret = PTR_ERR(bip);
0b7f1f26
KB		 643 goto out_free_meta;
644 }
645
646 bip->bip_iter.bi_size = meta_len;
647 bip->bip_iter.bi_sector = meta_seed;
648
649 ret = bio_integrity_add_page(bio, virt_to_page(meta),
650 meta_len, offset_in_page(meta));
651 if (ret != meta_len) {
652 ret = -ENOMEM;
653 goto out_free_meta;
654 }
655 }
656 }
657 submit:
658 blk_execute_rq(req->q, disk, req, 0);
27fa9bc5
CH		 659 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
660 ret = -EINTR;
661 else
662 ret = nvme_req(req)->status;
21d34711 663 if (result)
d49187e9 664 *result = le32_to_cpu(nvme_req(req)->result.u32);
0b7f1f26
KB		 665 if (meta && !ret && !write) {
666 if (copy_to_user(meta_buffer, meta, meta_len))
667 ret = -EFAULT;
668 }
669 out_free_meta:
670 kfree(meta);
671 out_unmap:
74d46992 672 if (bio)
0b7f1f26 673 blk_rq_unmap_user(bio);
21d34711
CH		 674 out:
675 blk_mq_free_request(req);
676 return ret;
677}
678
0b7f1f26
KB		 679int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
680 void __user *ubuffer, unsigned bufflen, u32 *result,
681 unsigned timeout)
682{
683 return __nvme_submit_user_cmd(q, cmd, ubuffer, bufflen, NULL, 0, 0,
684 result, timeout);
685}
686
2a842aca 687static void nvme_keep_alive_end_io(struct request *rq, blk_status_t status)
038bd4cb
SG		 688{
689 struct nvme_ctrl *ctrl = rq->end_io_data;
690
691 blk_mq_free_request(rq);
692
2a842aca 693 if (status) {
038bd4cb 694 dev_err(ctrl->device,
2a842aca
CH		 695 "failed nvme_keep_alive_end_io error=%d\n",
696 status);
038bd4cb
SG		 697 return;
698 }
699
700 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
701}
702
703static int nvme_keep_alive(struct nvme_ctrl *ctrl)
704{
705 struct nvme_command c;
706 struct request *rq;
707
708 memset(&c, 0, sizeof(c));
709 c.common.opcode = nvme_admin_keep_alive;
710
711 rq = nvme_alloc_request(ctrl->admin_q, &c, BLK_MQ_REQ_RESERVED,
712 NVME_QID_ANY);
713 if (IS_ERR(rq))
714 return PTR_ERR(rq);
715
716 rq->timeout = ctrl->kato * HZ;
717 rq->end_io_data = ctrl;
718
719 blk_execute_rq_nowait(rq->q, NULL, rq, 0, nvme_keep_alive_end_io);
720
721 return 0;
722}
723
724static void nvme_keep_alive_work(struct work_struct *work)
725{
726 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
727 struct nvme_ctrl, ka_work);
728
729 if (nvme_keep_alive(ctrl)) {
730 /* allocation failure, reset the controller */
731 dev_err(ctrl->device, "keep-alive failed\n");
39bdc590 732 nvme_reset_ctrl(ctrl);
038bd4cb
SG		 733 return;
734 }
735}
736
737void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
738{
739 if (unlikely(ctrl->kato == 0))
740 return;
741
742 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
743 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
744}
745EXPORT_SYMBOL_GPL(nvme_start_keep_alive);
746
747void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
748{
749 if (unlikely(ctrl->kato == 0))
750 return;
751
752 cancel_delayed_work_sync(&ctrl->ka_work);
753}
754EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
755
3f7f25a9 756static int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH		 757{
758 struct nvme_command c = { };
759 int error;
760
761 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
762 c.identify.opcode = nvme_admin_identify;
986994a2 763 c.identify.cns = NVME_ID_CNS_CTRL;
21d34711
CH		 764
765 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
766 if (!*id)
767 return -ENOMEM;
768
769 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
770 sizeof(struct nvme_id_ctrl));
771 if (error)
772 kfree(*id);
773 return error;
774}
775
3b22ba26
JT		 776static int nvme_identify_ns_descs(struct nvme_ns *ns, unsigned nsid)
777{
778 struct nvme_command c = { };
779 int status;
780 void *data;
781 int pos;
782 int len;
783
784 c.identify.opcode = nvme_admin_identify;
785 c.identify.nsid = cpu_to_le32(nsid);
786 c.identify.cns = NVME_ID_CNS_NS_DESC_LIST;
787
788 data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
789 if (!data)
790 return -ENOMEM;
791
792 status = nvme_submit_sync_cmd(ns->ctrl->admin_q, &c, data,
793 NVME_IDENTIFY_DATA_SIZE);
794 if (status)
795 goto free_data;
796
797 for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) {
798 struct nvme_ns_id_desc *cur = data + pos;
799
800 if (cur->nidl == 0)
801 break;
802
803 switch (cur->nidt) {
804 case NVME_NIDT_EUI64:
805 if (cur->nidl != NVME_NIDT_EUI64_LEN) {
806 dev_warn(ns->ctrl->device,
807 "ctrl returned bogus length: %d for NVME_NIDT_EUI64\n",
808 cur->nidl);
809 goto free_data;
810 }
811 len = NVME_NIDT_EUI64_LEN;
812 memcpy(ns->eui, data + pos + sizeof(*cur), len);
813 break;
814 case NVME_NIDT_NGUID:
815 if (cur->nidl != NVME_NIDT_NGUID_LEN) {
816 dev_warn(ns->ctrl->device,
817 "ctrl returned bogus length: %d for NVME_NIDT_NGUID\n",
818 cur->nidl);
819 goto free_data;
820 }
821 len = NVME_NIDT_NGUID_LEN;
822 memcpy(ns->nguid, data + pos + sizeof(*cur), len);
823 break;
824 case NVME_NIDT_UUID:
825 if (cur->nidl != NVME_NIDT_UUID_LEN) {
826 dev_warn(ns->ctrl->device,
827 "ctrl returned bogus length: %d for NVME_NIDT_UUID\n",
828 cur->nidl);
829 goto free_data;
830 }
831 len = NVME_NIDT_UUID_LEN;
832 uuid_copy(&ns->uuid, data + pos + sizeof(*cur));
833 break;
834 default:
835 /* Skip unnkown types */
836 len = cur->nidl;
837 break;
838 }
839
840 len += sizeof(*cur);
841 }
842free_data:
843 kfree(data);
844 return status;
845}
846
540c801c
KB		 847static int nvme_identify_ns_list(struct nvme_ctrl *dev, unsigned nsid, __le32 *ns_list)
848{
849 struct nvme_command c = { };
850
851 c.identify.opcode = nvme_admin_identify;
986994a2 852 c.identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST;
540c801c
KB		 853 c.identify.nsid = cpu_to_le32(nsid);
854 return nvme_submit_sync_cmd(dev->admin_q, &c, ns_list, 0x1000);
855}
856
3f7f25a9 857static int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
21d34711
CH		 858 struct nvme_id_ns **id)
859{
860 struct nvme_command c = { };
861 int error;
862
863 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
778f067c
MG		 864 c.identify.opcode = nvme_admin_identify;
865 c.identify.nsid = cpu_to_le32(nsid);
986994a2 866 c.identify.cns = NVME_ID_CNS_NS;
21d34711
CH		 867
868 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
869 if (!*id)
870 return -ENOMEM;
871
872 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
873 sizeof(struct nvme_id_ns));
874 if (error)
875 kfree(*id);
876 return error;
877}
878
3f7f25a9 879static int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
1a6fe74d 880 void *buffer, size_t buflen, u32 *result)
21d34711
CH		 881{
882 struct nvme_command c;
d49187e9 883 union nvme_result res;
1cb3cce5 884 int ret;
21d34711
CH		 885
886 memset(&c, 0, sizeof(c));
887 c.features.opcode = nvme_admin_set_features;
21d34711
CH		 888 c.features.fid = cpu_to_le32(fid);
889 c.features.dword11 = cpu_to_le32(dword11);
890
d49187e9 891 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
1a6fe74d 892 buffer, buflen, 0, NVME_QID_ANY, 0, 0);
9b47f77a 893 if (ret >= 0 && result)
d49187e9 894 *result = le32_to_cpu(res.u32);
1cb3cce5 895 return ret;
21d34711
CH		 896}
897
9a0be7ab
CH		 898int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
899{
900 u32 q_count = (*count - 1) | ((*count - 1) << 16);
901 u32 result;
902 int status, nr_io_queues;
903
1a6fe74d 904 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 905 &result);
f5fa90dc 906 if (status < 0)
9a0be7ab
CH		 907 return status;
908
f5fa90dc
CH		 909 /*
910 * Degraded controllers might return an error when setting the queue
911 * count. We still want to be able to bring them online and offer
912 * access to the admin queue, as that might be only way to fix them up.
913 */
914 if (status > 0) {
f0425db0 915 dev_err(ctrl->device, "Could not set queue count (%d)\n", status);
f5fa90dc
CH		 916 *count = 0;
917 } else {
918 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
919 *count = min(*count, nr_io_queues);
920 }
921
9a0be7ab
CH		 922 return 0;
923}
576d55d6 924EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 925
1673f1f0
CH		 926static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
927{
928 struct nvme_user_io io;
929 struct nvme_command c;
930 unsigned length, meta_len;
931 void __user *metadata;
932
933 if (copy_from_user(&io, uio, sizeof(io)))
934 return -EFAULT;
63088ec7
KB		 935 if (io.flags)
936 return -EINVAL;
1673f1f0
CH		 937
938 switch (io.opcode) {
939 case nvme_cmd_write:
940 case nvme_cmd_read:
941 case nvme_cmd_compare:
942 break;
943 default:
944 return -EINVAL;
945 }
946
947 length = (io.nblocks + 1) << ns->lba_shift;
948 meta_len = (io.nblocks + 1) * ns->ms;
949 metadata = (void __user *)(uintptr_t)io.metadata;
950
951 if (ns->ext) {
952 length += meta_len;
953 meta_len = 0;
954 } else if (meta_len) {
955 if ((io.metadata & 3) || !io.metadata)
956 return -EINVAL;
957 }
958
959 memset(&c, 0, sizeof(c));
960 c.rw.opcode = io.opcode;
961 c.rw.flags = io.flags;
962 c.rw.nsid = cpu_to_le32(ns->ns_id);
963 c.rw.slba = cpu_to_le64(io.slba);
964 c.rw.length = cpu_to_le16(io.nblocks);
965 c.rw.control = cpu_to_le16(io.control);
966 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
967 c.rw.reftag = cpu_to_le32(io.reftag);
968 c.rw.apptag = cpu_to_le16(io.apptag);
969 c.rw.appmask = cpu_to_le16(io.appmask);
970
971 return __nvme_submit_user_cmd(ns->queue, &c,
972 (void __user *)(uintptr_t)io.addr, length,
973 metadata, meta_len, io.slba, NULL, 0);
974}
975
f3ca80fc 976static int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1673f1f0
CH		 977 struct nvme_passthru_cmd __user *ucmd)
978{
979 struct nvme_passthru_cmd cmd;
980 struct nvme_command c;
981 unsigned timeout = 0;
982 int status;
983
984 if (!capable(CAP_SYS_ADMIN))
985 return -EACCES;
986 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
987 return -EFAULT;
63088ec7
KB		 988 if (cmd.flags)
989 return -EINVAL;
1673f1f0
CH		 990
991 memset(&c, 0, sizeof(c));
992 c.common.opcode = cmd.opcode;
993 c.common.flags = cmd.flags;
994 c.common.nsid = cpu_to_le32(cmd.nsid);
995 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
996 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
997 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
998 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
999 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1000 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1001 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1002 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1003
1004 if (cmd.timeout_ms)
1005 timeout = msecs_to_jiffies(cmd.timeout_ms);
1006
1007 status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c,
d1ea7be5 1008 (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
1673f1f0
CH		 1009 &cmd.result, timeout);
1010 if (status >= 0) {
1011 if (put_user(cmd.result, &ucmd->result))
1012 return -EFAULT;
1013 }
1014
1015 return status;
1016}
1017
1018static int nvme_ioctl(struct block_device *bdev, fmode_t mode,
1019 unsigned int cmd, unsigned long arg)
1020{
1021 struct nvme_ns *ns = bdev->bd_disk->private_data;
1022
1023 switch (cmd) {
1024 case NVME_IOCTL_ID:
1025 force_successful_syscall_return();
1026 return ns->ns_id;
1027 case NVME_IOCTL_ADMIN_CMD:
1028 return nvme_user_cmd(ns->ctrl, NULL, (void __user *)arg);
1029 case NVME_IOCTL_IO_CMD:
1030 return nvme_user_cmd(ns->ctrl, ns, (void __user *)arg);
1031 case NVME_IOCTL_SUBMIT_IO:
1032 return nvme_submit_io(ns, (void __user *)arg);
1673f1f0 1033 default:
84d4add7
MB		 1034#ifdef CONFIG_NVM
1035 if (ns->ndev)
1036 return nvme_nvm_ioctl(ns, cmd, arg);
1037#endif
a98e58e5 1038 if (is_sed_ioctl(cmd))
4f1244c8 1039 return sed_ioctl(ns->ctrl->opal_dev, cmd,
e225c20e 1040 (void __user *) arg);
1673f1f0
CH		 1041 return -ENOTTY;
1042 }
1043}
1044
1045#ifdef CONFIG_COMPAT
1046static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1047 unsigned int cmd, unsigned long arg)
1048{
1673f1f0
CH		 1049 return nvme_ioctl(bdev, mode, cmd, arg);
1050}
1051#else
1052#define nvme_compat_ioctl NULL
1053#endif
1054
1055static int nvme_open(struct block_device *bdev, fmode_t mode)
1056{
1057 return nvme_get_ns_from_disk(bdev->bd_disk) ? 0 : -ENXIO;
1058}
1059
1060static void nvme_release(struct gendisk *disk, fmode_t mode)
1061{
e439bb12
SG		 1062 struct nvme_ns *ns = disk->private_data;
1063
1064 module_put(ns->ctrl->ops->module);
1065 nvme_put_ns(ns);
1673f1f0
CH		 1066}
1067
1068static int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1069{
1070 /* some standard values */
1071 geo->heads = 1 << 6;
1072 geo->sectors = 1 << 5;
1073 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
1074 return 0;
1075}
1076
1077#ifdef CONFIG_BLK_DEV_INTEGRITY
c81bfba9
CH		 1078static void nvme_prep_integrity(struct gendisk *disk, struct nvme_id_ns *id,
1079 u16 bs)
1080{
1081 struct nvme_ns *ns = disk->private_data;
1082 u16 old_ms = ns->ms;
1083 u8 pi_type = 0;
1084
1085 ns->ms = le16_to_cpu(id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ms);
1086 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
1087
1088 /* PI implementation requires metadata equal t10 pi tuple size */
1089 if (ns->ms == sizeof(struct t10_pi_tuple))
1090 pi_type = id->dps & NVME_NS_DPS_PI_MASK;
1091
1092 if (blk_get_integrity(disk) &&
1093 (ns->pi_type != pi_type || ns->ms != old_ms ||
1094 bs != queue_logical_block_size(disk->queue) ||
1095 (ns->ms && ns->ext)))
1096 blk_integrity_unregister(disk);
1097
1098 ns->pi_type = pi_type;
1099}
1100
1673f1f0
CH		 1101static void nvme_init_integrity(struct nvme_ns *ns)
1102{
1103 struct blk_integrity integrity;
1104
fa9a89fc 1105 memset(&integrity, 0, sizeof(integrity));
1673f1f0
CH		 1106 switch (ns->pi_type) {
1107 case NVME_NS_DPS_PI_TYPE3:
1108 integrity.profile = &t10_pi_type3_crc;
ba36c21b
NB		 1109 integrity.tag_size = sizeof(u16) + sizeof(u32);
1110 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1111 break;
1112 case NVME_NS_DPS_PI_TYPE1:
1113 case NVME_NS_DPS_PI_TYPE2:
1114 integrity.profile = &t10_pi_type1_crc;
ba36c21b
NB		 1115 integrity.tag_size = sizeof(u16);
1116 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1117 break;
1118 default:
1119 integrity.profile = NULL;
1120 break;
1121 }
1122 integrity.tuple_size = ns->ms;
1123 blk_integrity_register(ns->disk, &integrity);
1124 blk_queue_max_integrity_segments(ns->queue, 1);
1125}
1126#else
c81bfba9
CH		 1127static void nvme_prep_integrity(struct gendisk *disk, struct nvme_id_ns *id,
1128 u16 bs)
1129{
1130}
1673f1f0
CH		 1131static void nvme_init_integrity(struct nvme_ns *ns)
1132{
1133}
1134#endif /* CONFIG_BLK_DEV_INTEGRITY */
1135
6b8190d6
SB		 1136static void nvme_set_chunk_size(struct nvme_ns *ns)
1137{
1138 u32 chunk_size = (((u32)ns->noiob) << (ns->lba_shift - 9));
1139 blk_queue_chunk_sectors(ns->queue, rounddown_pow_of_two(chunk_size));
1140}
1141
1673f1f0
CH		 1142static void nvme_config_discard(struct nvme_ns *ns)
1143{
08095e70 1144 struct nvme_ctrl *ctrl = ns->ctrl;
1673f1f0 1145 u32 logical_block_size = queue_logical_block_size(ns->queue);
08095e70 1146
b35ba01e
CH		 1147 BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) <
1148 NVME_DSM_MAX_RANGES);
1149
f5d11840
JA		 1150 if (ctrl->nr_streams && ns->sws && ns->sgs) {
1151 unsigned int sz = logical_block_size * ns->sws * ns->sgs;
1152
1153 ns->queue->limits.discard_alignment = sz;
1154 ns->queue->limits.discard_granularity = sz;
1155 } else {
1156 ns->queue->limits.discard_alignment = logical_block_size;
1157 ns->queue->limits.discard_granularity = logical_block_size;
1158 }
bd0fc288 1159 blk_queue_max_discard_sectors(ns->queue, UINT_MAX);
b35ba01e 1160 blk_queue_max_discard_segments(ns->queue, NVME_DSM_MAX_RANGES);
1673f1f0 1161 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
e850fd16
CH		 1162
1163 if (ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
1164 blk_queue_max_write_zeroes_sectors(ns->queue, UINT_MAX);
1673f1f0
CH		 1165}
1166
ac81bfa9 1167static int nvme_revalidate_ns(struct nvme_ns *ns, struct nvme_id_ns **id)
1673f1f0 1168{
ac81bfa9 1169 if (nvme_identify_ns(ns->ctrl, ns->ns_id, id)) {
caaa15c5 1170 dev_warn(ns->ctrl->device, "Identify namespace failed\n");
1673f1f0
CH		 1171 return -ENODEV;
1172 }
1673f1f0 1173
ac81bfa9
MB		 1174 if ((*id)->ncap == 0) {
1175 kfree(*id);
1176 return -ENODEV;
1673f1f0
CH		 1177 }
1178
8ef2074d 1179 if (ns->ctrl->vs >= NVME_VS(1, 1, 0))
ac81bfa9 1180 memcpy(ns->eui, (*id)->eui64, sizeof(ns->eui));
8ef2074d 1181 if (ns->ctrl->vs >= NVME_VS(1, 2, 0))
90985b84 1182 memcpy(ns->nguid, (*id)->nguid, sizeof(ns->nguid));
3b22ba26
JT		 1183 if (ns->ctrl->vs >= NVME_VS(1, 3, 0)) {
1184 /* Don't treat error as fatal we potentially
1185 * already have a NGUID or EUI-64
1186 */
1187 if (nvme_identify_ns_descs(ns, ns->ns_id))
1188 dev_warn(ns->ctrl->device,
1189 "%s: Identify Descriptors failed\n", __func__);
1190 }
ac81bfa9
MB		 1191
1192 return 0;
1193}
1194
1195static void __nvme_revalidate_disk(struct gendisk *disk, struct nvme_id_ns *id)
1196{
1197 struct nvme_ns *ns = disk->private_data;
f5d11840 1198 struct nvme_ctrl *ctrl = ns->ctrl;
c81bfba9 1199 u16 bs;
1673f1f0
CH		 1200
1201 /*
1202 * If identify namespace failed, use default 512 byte block size so
1203 * block layer can use before failing read/write for 0 capacity.
1204 */
c81bfba9 1205 ns->lba_shift = id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ds;
1673f1f0
CH		 1206 if (ns->lba_shift == 0)
1207 ns->lba_shift = 9;
1208 bs = 1 << ns->lba_shift;
6b8190d6 1209 ns->noiob = le16_to_cpu(id->noiob);
1673f1f0
CH		 1210
1211 blk_mq_freeze_queue(disk->queue);
1673f1f0 1212
f5d11840 1213 if (ctrl->ops->flags & NVME_F_METADATA_SUPPORTED)
c81bfba9 1214 nvme_prep_integrity(disk, id, bs);
1673f1f0 1215 blk_queue_logical_block_size(ns->queue, bs);
6b8190d6
SB		 1216 if (ns->noiob)
1217 nvme_set_chunk_size(ns);
4b9d5b15 1218 if (ns->ms && !blk_get_integrity(disk) && !ns->ext)
1673f1f0 1219 nvme_init_integrity(ns);
1673f1f0
CH		 1220 if (ns->ms && !(ns->ms == 8 && ns->pi_type) && !blk_get_integrity(disk))
1221 set_capacity(disk, 0);
1222 else
1223 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1224
f5d11840 1225 if (ctrl->oncs & NVME_CTRL_ONCS_DSM)
1673f1f0
CH		 1226 nvme_config_discard(ns);
1227 blk_mq_unfreeze_queue(disk->queue);
ac81bfa9 1228}
1673f1f0 1229
ac81bfa9
MB		 1230static int nvme_revalidate_disk(struct gendisk *disk)
1231{
1232 struct nvme_ns *ns = disk->private_data;
1233 struct nvme_id_ns *id = NULL;
1234 int ret;
1235
1236 if (test_bit(NVME_NS_DEAD, &ns->flags)) {
1237 set_capacity(disk, 0);
1238 return -ENODEV;
1239 }
1240
1241 ret = nvme_revalidate_ns(ns, &id);
1242 if (ret)
1243 return ret;
1244
1245 __nvme_revalidate_disk(disk, id);
1673f1f0 1246 kfree(id);
ac81bfa9 1247
1673f1f0
CH		 1248 return 0;
1249}
1250
1251static char nvme_pr_type(enum pr_type type)
1252{
1253 switch (type) {
1254 case PR_WRITE_EXCLUSIVE:
1255 return 1;
1256 case PR_EXCLUSIVE_ACCESS:
1257 return 2;
1258 case PR_WRITE_EXCLUSIVE_REG_ONLY:
1259 return 3;
1260 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
1261 return 4;
1262 case PR_WRITE_EXCLUSIVE_ALL_REGS:
1263 return 5;
1264 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
1265 return 6;
1266 default:
1267 return 0;
1268 }
1269};
1270
1271static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
1272 u64 key, u64 sa_key, u8 op)
1273{
1274 struct nvme_ns *ns = bdev->bd_disk->private_data;
1275 struct nvme_command c;
1276 u8 data[16] = { 0, };
1277
1278 put_unaligned_le64(key, &data[0]);
1279 put_unaligned_le64(sa_key, &data[8]);
1280
1281 memset(&c, 0, sizeof(c));
1282 c.common.opcode = op;
1283 c.common.nsid = cpu_to_le32(ns->ns_id);
1284 c.common.cdw10[0] = cpu_to_le32(cdw10);
1285
1286 return nvme_submit_sync_cmd(ns->queue, &c, data, 16);
1287}
1288
1289static int nvme_pr_register(struct block_device *bdev, u64 old,
1290 u64 new, unsigned flags)
1291{
1292 u32 cdw10;
1293
1294 if (flags & ~PR_FL_IGNORE_KEY)
1295 return -EOPNOTSUPP;
1296
1297 cdw10 = old ? 2 : 0;
1298 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
1299 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
1300 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
1301}
1302
1303static int nvme_pr_reserve(struct block_device *bdev, u64 key,
1304 enum pr_type type, unsigned flags)
1305{
1306 u32 cdw10;
1307
1308 if (flags & ~PR_FL_IGNORE_KEY)
1309 return -EOPNOTSUPP;
1310
1311 cdw10 = nvme_pr_type(type) << 8;
1312 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
1313 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
1314}
1315
1316static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
1317 enum pr_type type, bool abort)
1318{
1319 u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
1320 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
1321}
1322
1323static int nvme_pr_clear(struct block_device *bdev, u64 key)
1324{
8c0b3915 1325 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
1673f1f0
CH		 1326 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
1327}
1328
1329static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
1330{
1331 u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
1332 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
1333}
1334
1335static const struct pr_ops nvme_pr_ops = {
1336 .pr_register = nvme_pr_register,
1337 .pr_reserve = nvme_pr_reserve,
1338 .pr_release = nvme_pr_release,
1339 .pr_preempt = nvme_pr_preempt,
1340 .pr_clear = nvme_pr_clear,
1341};
1342
a98e58e5 1343#ifdef CONFIG_BLK_SED_OPAL
4f1244c8
CH		 1344int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
1345 bool send)
a98e58e5 1346{
4f1244c8 1347 struct nvme_ctrl *ctrl = data;
a98e58e5 1348 struct nvme_command cmd;
a98e58e5
SB		 1349
1350 memset(&cmd, 0, sizeof(cmd));
1351 if (send)
1352 cmd.common.opcode = nvme_admin_security_send;
1353 else
1354 cmd.common.opcode = nvme_admin_security_recv;
a98e58e5
SB		 1355 cmd.common.nsid = 0;
1356 cmd.common.cdw10[0] = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
1357 cmd.common.cdw10[1] = cpu_to_le32(len);
1358
1359 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len,
1360 ADMIN_TIMEOUT, NVME_QID_ANY, 1, 0);
1361}
1362EXPORT_SYMBOL_GPL(nvme_sec_submit);
1363#endif /* CONFIG_BLK_SED_OPAL */
1364
5bae7f73 1365static const struct block_device_operations nvme_fops = {
1673f1f0
CH		 1366 .owner = THIS_MODULE,
1367 .ioctl = nvme_ioctl,
1368 .compat_ioctl = nvme_compat_ioctl,
1369 .open = nvme_open,
1370 .release = nvme_release,
1371 .getgeo = nvme_getgeo,
1372 .revalidate_disk= nvme_revalidate_disk,
1373 .pr_ops = &nvme_pr_ops,
1374};
1375
5fd4ce1b
CH		 1376static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
1377{
1378 unsigned long timeout =
1379 ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1380 u32 csts, bit = enabled ? NVME_CSTS_RDY : 0;
1381 int ret;
1382
1383 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB		 1384 if (csts == ~0)
1385 return -ENODEV;
5fd4ce1b
CH		 1386 if ((csts & NVME_CSTS_RDY) == bit)
1387 break;
1388
1389 msleep(100);
1390 if (fatal_signal_pending(current))
1391 return -EINTR;
1392 if (time_after(jiffies, timeout)) {
1b3c47c1 1393 dev_err(ctrl->device,
5fd4ce1b
CH		 1394 "Device not ready; aborting %s\n", enabled ?
1395 "initialisation" : "reset");
1396 return -ENODEV;
1397 }
1398 }
1399
1400 return ret;
1401}
1402
1403/*
1404 * If the device has been passed off to us in an enabled state, just clear
1405 * the enabled bit. The spec says we should set the 'shutdown notification
1406 * bits', but doing so may cause the device to complete commands to the
1407 * admin queue ... and we don't know what memory that might be pointing at!
1408 */
1409int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1410{
1411 int ret;
1412
1413 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1414 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
1415
1416 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1417 if (ret)
1418 return ret;
54adc010 1419
b5a10c5f 1420 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010
GP		 1421 msleep(NVME_QUIRK_DELAY_AMOUNT);
1422
5fd4ce1b
CH		 1423 return nvme_wait_ready(ctrl, cap, false);
1424}
576d55d6 1425EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b
CH		 1426
1427int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1428{
1429 /*
1430 * Default to a 4K page size, with the intention to update this
1431 * path in the future to accomodate architectures with differing
1432 * kernel and IO page sizes.
1433 */
1434 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12, page_shift = 12;
1435 int ret;
1436
1437 if (page_shift < dev_page_min) {
1b3c47c1 1438 dev_err(ctrl->device,
5fd4ce1b
CH		 1439 "Minimum device page size %u too large for host (%u)\n",
1440 1 << dev_page_min, 1 << page_shift);
1441 return -ENODEV;
1442 }
1443
1444 ctrl->page_size = 1 << page_shift;
1445
1446 ctrl->ctrl_config = NVME_CC_CSS_NVM;
1447 ctrl->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1448 ctrl->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1449 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1450 ctrl->ctrl_config |= NVME_CC_ENABLE;
1451
1452 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1453 if (ret)
1454 return ret;
1455 return nvme_wait_ready(ctrl, cap, true);
1456}
576d55d6 1457EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b
CH		 1458
1459int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl)
1460{
b3b1b0b0 1461 unsigned long timeout = jiffies + (shutdown_timeout * HZ);
5fd4ce1b
CH		 1462 u32 csts;
1463 int ret;
1464
1465 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1466 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
1467
1468 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1469 if (ret)
1470 return ret;
1471
1472 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
1473 if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_CMPLT)
1474 break;
1475
1476 msleep(100);
1477 if (fatal_signal_pending(current))
1478 return -EINTR;
1479 if (time_after(jiffies, timeout)) {
1b3c47c1 1480 dev_err(ctrl->device,
5fd4ce1b
CH		 1481 "Device shutdown incomplete; abort shutdown\n");
1482 return -ENODEV;
1483 }
1484 }
1485
1486 return ret;
1487}
576d55d6 1488EXPORT_SYMBOL_GPL(nvme_shutdown_ctrl);
5fd4ce1b 1489
da35825d
CH		 1490static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
1491 struct request_queue *q)
1492{
7c88cb00
JA		 1493 bool vwc = false;
1494
da35825d 1495 if (ctrl->max_hw_sectors) {
45686b61
CH		 1496 u32 max_segments =
1497 (ctrl->max_hw_sectors / (ctrl->page_size >> 9)) + 1;
1498
da35825d 1499 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
45686b61 1500 blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
da35825d 1501 }
e6282aef
KB		 1502 if (ctrl->quirks & NVME_QUIRK_STRIPE_SIZE)
1503 blk_queue_chunk_sectors(q, ctrl->max_hw_sectors);
da35825d 1504 blk_queue_virt_boundary(q, ctrl->page_size - 1);
7c88cb00
JA		 1505 if (ctrl->vwc & NVME_CTRL_VWC_PRESENT)
1506 vwc = true;
1507 blk_queue_write_cache(q, vwc, vwc);
da35825d
CH		 1508}
1509
dbf86b39
JD		 1510static int nvme_configure_timestamp(struct nvme_ctrl *ctrl)
1511{
1512 __le64 ts;
1513 int ret;
1514
1515 if (!(ctrl->oncs & NVME_CTRL_ONCS_TIMESTAMP))
1516 return 0;
1517
1518 ts = cpu_to_le64(ktime_to_ms(ktime_get_real()));
1519 ret = nvme_set_features(ctrl, NVME_FEAT_TIMESTAMP, 0, &ts, sizeof(ts),
1520 NULL);
1521 if (ret)
1522 dev_warn_once(ctrl->device,
1523 "could not set timestamp (%d)\n", ret);
1524 return ret;
1525}
1526
634b8325 1527static int nvme_configure_apst(struct nvme_ctrl *ctrl)
c5552fde
AL		 1528{
1529 /*
1530 * APST (Autonomous Power State Transition) lets us program a
1531 * table of power state transitions that the controller will
1532 * perform automatically. We configure it with a simple
1533 * heuristic: we are willing to spend at most 2% of the time
1534 * transitioning between power states. Therefore, when running
1535 * in any given state, we will enter the next lower-power
76e4ad09 1536 * non-operational state after waiting 50 * (enlat + exlat)
da87591b 1537 * microseconds, as long as that state's exit latency is under
c5552fde
AL		 1538 * the requested maximum latency.
1539 *
1540 * We will not autonomously enter any non-operational state for
1541 * which the total latency exceeds ps_max_latency_us. Users
1542 * can set ps_max_latency_us to zero to turn off APST.
1543 */
1544
1545 unsigned apste;
1546 struct nvme_feat_auto_pst *table;
fb0dc399
AL		 1547 u64 max_lat_us = 0;
1548 int max_ps = -1;
c5552fde
AL		 1549 int ret;
1550
1551 /*
1552 * If APST isn't supported or if we haven't been initialized yet,
1553 * then don't do anything.
1554 */
1555 if (!ctrl->apsta)
634b8325 1556 return 0;
c5552fde
AL		 1557
1558 if (ctrl->npss > 31) {
1559 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
634b8325 1560 return 0;
c5552fde
AL		 1561 }
1562
1563 table = kzalloc(sizeof(*table), GFP_KERNEL);
1564 if (!table)
634b8325 1565 return 0;
c5552fde 1566
76a5af84 1567 if (!ctrl->apst_enabled || ctrl->ps_max_latency_us == 0) {
c5552fde
AL		 1568 /* Turn off APST. */
1569 apste = 0;
fb0dc399 1570 dev_dbg(ctrl->device, "APST disabled\n");
c5552fde
AL		 1571 } else {
1572 __le64 target = cpu_to_le64(0);
1573 int state;
1574
1575 /*
1576 * Walk through all states from lowest- to highest-power.
1577 * According to the spec, lower-numbered states use more
1578 * power. NPSS, despite the name, is the index of the
1579 * lowest-power state, not the number of states.
1580 */
1581 for (state = (int)ctrl->npss; state >= 0; state--) {
da87591b 1582 u64 total_latency_us, exit_latency_us, transition_ms;
c5552fde
AL		 1583
1584 if (target)
1585 table->entries[state] = target;
1586
ff5350a8
AL		 1587 /*
1588 * Don't allow transitions to the deepest state
1589 * if it's quirked off.
1590 */
1591 if (state == ctrl->npss &&
1592 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
1593 continue;
1594
c5552fde
AL		 1595 /*
1596 * Is this state a useful non-operational state for
1597 * higher-power states to autonomously transition to?
1598 */
1599 if (!(ctrl->psd[state].flags &
1600 NVME_PS_FLAGS_NON_OP_STATE))
1601 continue;
1602
da87591b
KHF		 1603 exit_latency_us =
1604 (u64)le32_to_cpu(ctrl->psd[state].exit_lat);
1605 if (exit_latency_us > ctrl->ps_max_latency_us)
c5552fde
AL		 1606 continue;
1607
da87591b
KHF		 1608 total_latency_us =
1609 exit_latency_us +
1610 le32_to_cpu(ctrl->psd[state].entry_lat);
1611
c5552fde
AL		 1612 /*
1613 * This state is good. Use it as the APST idle
1614 * target for higher power states.
1615 */
1616 transition_ms = total_latency_us + 19;
1617 do_div(transition_ms, 20);
1618 if (transition_ms > (1 << 24) - 1)
1619 transition_ms = (1 << 24) - 1;
1620
1621 target = cpu_to_le64((state << 3) |
1622 (transition_ms << 8));
fb0dc399
AL		 1623
1624 if (max_ps == -1)
1625 max_ps = state;
1626
1627 if (total_latency_us > max_lat_us)
1628 max_lat_us = total_latency_us;
c5552fde
AL		 1629 }
1630
1631 apste = 1;
fb0dc399
AL		 1632
1633 if (max_ps == -1) {
1634 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n");
1635 } else {
1636 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n",
1637 max_ps, max_lat_us, (int)sizeof(*table), table);
1638 }
c5552fde
AL		 1639 }
1640
1641 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
1642 table, sizeof(*table), NULL);
1643 if (ret)
1644 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
1645
1646 kfree(table);
634b8325 1647 return ret;
c5552fde
AL		 1648}
1649
1650static void nvme_set_latency_tolerance(struct device *dev, s32 val)
1651{
1652 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1653 u64 latency;
1654
1655 switch (val) {
1656 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
1657 case PM_QOS_LATENCY_ANY:
1658 latency = U64_MAX;
1659 break;
1660
1661 default:
1662 latency = val;
1663 }
1664
1665 if (ctrl->ps_max_latency_us != latency) {
1666 ctrl->ps_max_latency_us = latency;
1667 nvme_configure_apst(ctrl);
1668 }
1669}
1670
bd4da3ab
AL		 1671struct nvme_core_quirk_entry {
1672 /*
1673 * NVMe model and firmware strings are padded with spaces. For
1674 * simplicity, strings in the quirk table are padded with NULLs
1675 * instead.
1676 */
1677 u16 vid;
1678 const char *mn;
1679 const char *fr;
1680 unsigned long quirks;
1681};
1682
1683static const struct nvme_core_quirk_entry core_quirks[] = {
c5552fde 1684 {
be56945c
AL		 1685 /*
1686 * This Toshiba device seems to die using any APST states. See:
1687 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
1688 */
1689 .vid = 0x1179,
1690 .mn = "THNSF5256GPUK TOSHIBA",
c5552fde 1691 .quirks = NVME_QUIRK_NO_APST,
be56945c 1692 }
bd4da3ab
AL		 1693};
1694
1695/* match is null-terminated but idstr is space-padded. */
1696static bool string_matches(const char *idstr, const char *match, size_t len)
1697{
1698 size_t matchlen;
1699
1700 if (!match)
1701 return true;
1702
1703 matchlen = strlen(match);
1704 WARN_ON_ONCE(matchlen > len);
1705
1706 if (memcmp(idstr, match, matchlen))
1707 return false;
1708
1709 for (; matchlen < len; matchlen++)
1710 if (idstr[matchlen] != ' ')
1711 return false;
1712
1713 return true;
1714}
1715
1716static bool quirk_matches(const struct nvme_id_ctrl *id,
1717 const struct nvme_core_quirk_entry *q)
1718{
1719 return q->vid == le16_to_cpu(id->vid) &&
1720 string_matches(id->mn, q->mn, sizeof(id->mn)) &&
1721 string_matches(id->fr, q->fr, sizeof(id->fr));
1722}
1723
180de007
CH		 1724static void nvme_init_subnqn(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
1725{
1726 size_t nqnlen;
1727 int off;
1728
1729 nqnlen = strnlen(id->subnqn, NVMF_NQN_SIZE);
1730 if (nqnlen > 0 && nqnlen < NVMF_NQN_SIZE) {
1731 strcpy(ctrl->subnqn, id->subnqn);
1732 return;
1733 }
1734
1735 if (ctrl->vs >= NVME_VS(1, 2, 1))
1736 dev_warn(ctrl->device, "missing or invalid SUBNQN field.\n");
1737
1738 /* Generate a "fake" NQN per Figure 254 in NVMe 1.3 + ECN 001 */
1739 off = snprintf(ctrl->subnqn, NVMF_NQN_SIZE,
1740 "nqn.2014.08.org.nvmexpress:%4x%4x",
1741 le16_to_cpu(id->vid), le16_to_cpu(id->ssvid));
1742 memcpy(ctrl->subnqn + off, id->sn, sizeof(id->sn));
1743 off += sizeof(id->sn);
1744 memcpy(ctrl->subnqn + off, id->mn, sizeof(id->mn));
1745 off += sizeof(id->mn);
1746 memset(ctrl->subnqn + off, 0, sizeof(ctrl->subnqn) - off);
1747}
1748
7fd8930f
CH		 1749/*
1750 * Initialize the cached copies of the Identify data and various controller
1751 * register in our nvme_ctrl structure. This should be called as soon as
1752 * the admin queue is fully up and running.
1753 */
1754int nvme_init_identify(struct nvme_ctrl *ctrl)
1755{
1756 struct nvme_id_ctrl *id;
1757 u64 cap;
1758 int ret, page_shift;
a229dbf6 1759 u32 max_hw_sectors;
76a5af84 1760 bool prev_apst_enabled;
7fd8930f 1761
f3ca80fc
CH		 1762 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
1763 if (ret) {
1b3c47c1 1764 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
f3ca80fc
CH		 1765 return ret;
1766 }
1767
7fd8930f
CH		 1768 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &cap);
1769 if (ret) {
1b3c47c1 1770 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
7fd8930f
CH		 1771 return ret;
1772 }
1773 page_shift = NVME_CAP_MPSMIN(cap) + 12;
1774
8ef2074d 1775 if (ctrl->vs >= NVME_VS(1, 1, 0))
f3ca80fc
CH		 1776 ctrl->subsystem = NVME_CAP_NSSRC(cap);
1777
7fd8930f
CH		 1778 ret = nvme_identify_ctrl(ctrl, &id);
1779 if (ret) {
1b3c47c1 1780 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH		 1781 return -EIO;
1782 }
1783
180de007
CH		 1784 nvme_init_subnqn(ctrl, id);
1785
bd4da3ab
AL		 1786 if (!ctrl->identified) {
1787 /*
1788 * Check for quirks. Quirk can depend on firmware version,
1789 * so, in principle, the set of quirks present can change
1790 * across a reset. As a possible future enhancement, we
1791 * could re-scan for quirks every time we reinitialize
1792 * the device, but we'd have to make sure that the driver
1793 * behaves intelligently if the quirks change.
1794 */
1795
1796 int i;
1797
1798 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
1799 if (quirk_matches(id, &core_quirks[i]))
1800 ctrl->quirks |= core_quirks[i].quirks;
1801 }
1802 }
1803
c35e30b4 1804 if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) {
f0425db0 1805 dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n");
c35e30b4
AL		 1806 ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS;
1807 }
1808
8a9ae523 1809 ctrl->oacs = le16_to_cpu(id->oacs);
118472ab 1810 ctrl->vid = le16_to_cpu(id->vid);
7fd8930f 1811 ctrl->oncs = le16_to_cpup(&id->oncs);
6bf25d16 1812 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 1813 ctrl->vwc = id->vwc;
931e1c22 1814 ctrl->cntlid = le16_to_cpup(&id->cntlid);
7fd8930f
CH		 1815 memcpy(ctrl->serial, id->sn, sizeof(id->sn));
1816 memcpy(ctrl->model, id->mn, sizeof(id->mn));
1817 memcpy(ctrl->firmware_rev, id->fr, sizeof(id->fr));
1818 if (id->mdts)
a229dbf6 1819 max_hw_sectors = 1 << (id->mdts + page_shift - 9);
7fd8930f 1820 else
a229dbf6
CH		 1821 max_hw_sectors = UINT_MAX;
1822 ctrl->max_hw_sectors =
1823 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 1824
da35825d 1825 nvme_set_queue_limits(ctrl, ctrl->admin_q);
07bfcd09 1826 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 1827 ctrl->kas = le16_to_cpu(id->kas);
07bfcd09 1828
c5552fde 1829 ctrl->npss = id->npss;
76a5af84
KHF		 1830 ctrl->apsta = id->apsta;
1831 prev_apst_enabled = ctrl->apst_enabled;
c35e30b4
AL		 1832 if (ctrl->quirks & NVME_QUIRK_NO_APST) {
1833 if (force_apst && id->apsta) {
f0425db0 1834 dev_warn(ctrl->device, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n");
76a5af84 1835 ctrl->apst_enabled = true;
c35e30b4 1836 } else {
76a5af84 1837 ctrl->apst_enabled = false;
c35e30b4
AL		 1838 }
1839 } else {
76a5af84 1840 ctrl->apst_enabled = id->apsta;
c35e30b4 1841 }
c5552fde
AL		 1842 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
1843
d3d5b87d 1844 if (ctrl->ops->flags & NVME_F_FABRICS) {
07bfcd09
CH		 1845 ctrl->icdoff = le16_to_cpu(id->icdoff);
1846 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
1847 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
1848 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
1849
1850 /*
1851 * In fabrics we need to verify the cntlid matches the
1852 * admin connect
1853 */
634b8325 1854 if (ctrl->cntlid != le16_to_cpu(id->cntlid)) {
07bfcd09 1855 ret = -EINVAL;
634b8325
KB		 1856 goto out_free;
1857 }
038bd4cb
SG		 1858
1859 if (!ctrl->opts->discovery_nqn && !ctrl->kas) {
f0425db0 1860 dev_err(ctrl->device,
038bd4cb
SG		 1861 "keep-alive support is mandatory for fabrics\n");
1862 ret = -EINVAL;
634b8325 1863 goto out_free;
038bd4cb 1864 }
07bfcd09
CH		 1865 } else {
1866 ctrl->cntlid = le16_to_cpu(id->cntlid);
fe6d53c9
CH		 1867 ctrl->hmpre = le32_to_cpu(id->hmpre);
1868 ctrl->hmmin = le32_to_cpu(id->hmmin);
07bfcd09 1869 }
da35825d 1870
7fd8930f 1871 kfree(id);
bd4da3ab 1872
76a5af84 1873 if (ctrl->apst_enabled && !prev_apst_enabled)
c5552fde 1874 dev_pm_qos_expose_latency_tolerance(ctrl->device);
76a5af84 1875 else if (!ctrl->apst_enabled && prev_apst_enabled)
c5552fde
AL		 1876 dev_pm_qos_hide_latency_tolerance(ctrl->device);
1877
634b8325
KB		 1878 ret = nvme_configure_apst(ctrl);
1879 if (ret < 0)
1880 return ret;
dbf86b39
JD		 1881
1882 ret = nvme_configure_timestamp(ctrl);
1883 if (ret < 0)
1884 return ret;
634b8325
KB		 1885
1886 ret = nvme_configure_directives(ctrl);
1887 if (ret < 0)
1888 return ret;
c5552fde 1889
bd4da3ab 1890 ctrl->identified = true;
c5552fde 1891
634b8325
KB		 1892 return 0;
1893
1894out_free:
1895 kfree(id);
07bfcd09 1896 return ret;
7fd8930f 1897}
576d55d6 1898EXPORT_SYMBOL_GPL(nvme_init_identify);
7fd8930f 1899
f3ca80fc 1900static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 1901{
f3ca80fc
CH		 1902 struct nvme_ctrl *ctrl;
1903 int instance = iminor(inode);
1904 int ret = -ENODEV;
1673f1f0 1905
f3ca80fc
CH		 1906 spin_lock(&dev_list_lock);
1907 list_for_each_entry(ctrl, &nvme_ctrl_list, node) {
1908 if (ctrl->instance != instance)
1909 continue;
1910
1911 if (!ctrl->admin_q) {
1912 ret = -EWOULDBLOCK;
1913 break;
1914 }
1915 if (!kref_get_unless_zero(&ctrl->kref))
1916 break;
1917 file->private_data = ctrl;
1918 ret = 0;
1919 break;
1920 }
1921 spin_unlock(&dev_list_lock);
1922
1923 return ret;
1673f1f0
CH		 1924}
1925
f3ca80fc 1926static int nvme_dev_release(struct inode *inode, struct file *file)
1673f1f0 1927{
f3ca80fc
CH		 1928 nvme_put_ctrl(file->private_data);
1929 return 0;
1930}
1931
bfd89471
CH		 1932static int nvme_dev_user_cmd(struct nvme_ctrl *ctrl, void __user *argp)
1933{
1934 struct nvme_ns *ns;
1935 int ret;
1936
1937 mutex_lock(&ctrl->namespaces_mutex);
1938 if (list_empty(&ctrl->namespaces)) {
1939 ret = -ENOTTY;
1940 goto out_unlock;
1941 }
1942
1943 ns = list_first_entry(&ctrl->namespaces, struct nvme_ns, list);
1944 if (ns != list_last_entry(&ctrl->namespaces, struct nvme_ns, list)) {
1b3c47c1 1945 dev_warn(ctrl->device,
bfd89471
CH		 1946 "NVME_IOCTL_IO_CMD not supported when multiple namespaces present!\n");
1947 ret = -EINVAL;
1948 goto out_unlock;
1949 }
1950
1b3c47c1 1951 dev_warn(ctrl->device,
bfd89471
CH		 1952 "using deprecated NVME_IOCTL_IO_CMD ioctl on the char device!\n");
1953 kref_get(&ns->kref);
1954 mutex_unlock(&ctrl->namespaces_mutex);
1955
1956 ret = nvme_user_cmd(ctrl, ns, argp);
1957 nvme_put_ns(ns);
1958 return ret;
1959
1960out_unlock:
1961 mutex_unlock(&ctrl->namespaces_mutex);
1962 return ret;
1963}
1964
f3ca80fc
CH		 1965static long nvme_dev_ioctl(struct file *file, unsigned int cmd,
1966 unsigned long arg)
1967{
1968 struct nvme_ctrl *ctrl = file->private_data;
1969 void __user *argp = (void __user *)arg;
f3ca80fc
CH		 1970
1971 switch (cmd) {
1972 case NVME_IOCTL_ADMIN_CMD:
1973 return nvme_user_cmd(ctrl, NULL, argp);
1974 case NVME_IOCTL_IO_CMD:
bfd89471 1975 return nvme_dev_user_cmd(ctrl, argp);
f3ca80fc 1976 case NVME_IOCTL_RESET:
1b3c47c1 1977 dev_warn(ctrl->device, "resetting controller\n");
d86c4d8e 1978 return nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 1979 case NVME_IOCTL_SUBSYS_RESET:
1980 return nvme_reset_subsystem(ctrl);
9ec3bb2f
KB		 1981 case NVME_IOCTL_RESCAN:
1982 nvme_queue_scan(ctrl);
1983 return 0;
f3ca80fc
CH		 1984 default:
1985 return -ENOTTY;
1986 }
1987}
1988
1989static const struct file_operations nvme_dev_fops = {
1990 .owner = THIS_MODULE,
1991 .open = nvme_dev_open,
1992 .release = nvme_dev_release,
1993 .unlocked_ioctl = nvme_dev_ioctl,
1994 .compat_ioctl = nvme_dev_ioctl,
1995};
1996
1997static ssize_t nvme_sysfs_reset(struct device *dev,
1998 struct device_attribute *attr, const char *buf,
1999 size_t count)
2000{
2001 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2002 int ret;
2003
d86c4d8e 2004 ret = nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 2005 if (ret < 0)
2006 return ret;
2007 return count;
1673f1f0 2008}
f3ca80fc 2009static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
1673f1f0 2010
9ec3bb2f
KB		 2011static ssize_t nvme_sysfs_rescan(struct device *dev,
2012 struct device_attribute *attr, const char *buf,
2013 size_t count)
2014{
2015 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2016
2017 nvme_queue_scan(ctrl);
2018 return count;
2019}
2020static DEVICE_ATTR(rescan_controller, S_IWUSR, NULL, nvme_sysfs_rescan);
2021
118472ab
KB		 2022static ssize_t wwid_show(struct device *dev, struct device_attribute *attr,
2023 char *buf)
2024{
40267efd 2025 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
118472ab
KB		 2026 struct nvme_ctrl *ctrl = ns->ctrl;
2027 int serial_len = sizeof(ctrl->serial);
2028 int model_len = sizeof(ctrl->model);
2029
6484f5d1
JT		 2030 if (!uuid_is_null(&ns->uuid))
2031 return sprintf(buf, "uuid.%pU\n", &ns->uuid);
2032
90985b84
JT		 2033 if (memchr_inv(ns->nguid, 0, sizeof(ns->nguid)))
2034 return sprintf(buf, "eui.%16phN\n", ns->nguid);
118472ab
KB		 2035
2036 if (memchr_inv(ns->eui, 0, sizeof(ns->eui)))
2037 return sprintf(buf, "eui.%8phN\n", ns->eui);
2038
758f3735
MW		 2039 while (serial_len > 0 && (ctrl->serial[serial_len - 1] == ' ' ||
2040 ctrl->serial[serial_len - 1] == '\0'))
118472ab 2041 serial_len--;
758f3735
MW		 2042 while (model_len > 0 && (ctrl->model[model_len - 1] == ' ' ||
2043 ctrl->model[model_len - 1] == '\0'))
118472ab
KB		 2044 model_len--;
2045
2046 return sprintf(buf, "nvme.%04x-%*phN-%*phN-%08x\n", ctrl->vid,
2047 serial_len, ctrl->serial, model_len, ctrl->model, ns->ns_id);
2048}
2049static DEVICE_ATTR(wwid, S_IRUGO, wwid_show, NULL);
2050
d934f984
JT		 2051static ssize_t nguid_show(struct device *dev, struct device_attribute *attr,
2052 char *buf)
2053{
2054 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2055 return sprintf(buf, "%pU\n", ns->nguid);
2056}
2057static DEVICE_ATTR(nguid, S_IRUGO, nguid_show, NULL);
2058
2b9b6e86
KB		 2059static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,
2060 char *buf)
2061{
40267efd 2062 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
d934f984
JT		 2063
2064 /* For backward compatibility expose the NGUID to userspace if
2065 * we have no UUID set
2066 */
2067 if (uuid_is_null(&ns->uuid)) {
2068 printk_ratelimited(KERN_WARNING
2069 "No UUID available providing old NGUID\n");
2070 return sprintf(buf, "%pU\n", ns->nguid);
2071 }
2072 return sprintf(buf, "%pU\n", &ns->uuid);
2b9b6e86
KB		 2073}
2074static DEVICE_ATTR(uuid, S_IRUGO, uuid_show, NULL);
2075
2076static ssize_t eui_show(struct device *dev, struct device_attribute *attr,
2077 char *buf)
2078{
40267efd 2079 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 2080 return sprintf(buf, "%8phd\n", ns->eui);
2081}
2082static DEVICE_ATTR(eui, S_IRUGO, eui_show, NULL);
2083
2084static ssize_t nsid_show(struct device *dev, struct device_attribute *attr,
2085 char *buf)
2086{
40267efd 2087 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 2088 return sprintf(buf, "%d\n", ns->ns_id);
2089}
2090static DEVICE_ATTR(nsid, S_IRUGO, nsid_show, NULL);
2091
2092static struct attribute *nvme_ns_attrs[] = {
118472ab 2093 &dev_attr_wwid.attr,
2b9b6e86 2094 &dev_attr_uuid.attr,
d934f984 2095 &dev_attr_nguid.attr,
2b9b6e86
KB		 2096 &dev_attr_eui.attr,
2097 &dev_attr_nsid.attr,
2098 NULL,
2099};
2100
1a353d85 2101static umode_t nvme_ns_attrs_are_visible(struct kobject *kobj,
2b9b6e86
KB		 2102 struct attribute *a, int n)
2103{
2104 struct device *dev = container_of(kobj, struct device, kobj);
40267efd 2105 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB		 2106
2107 if (a == &dev_attr_uuid.attr) {
d934f984
JT		 2108 if (uuid_is_null(&ns->uuid) ||
2109 !memchr_inv(ns->nguid, 0, sizeof(ns->nguid)))
2110 return 0;
2111 }
2112 if (a == &dev_attr_nguid.attr) {
90985b84 2113 if (!memchr_inv(ns->nguid, 0, sizeof(ns->nguid)))
2b9b6e86
KB		 2114 return 0;
2115 }
2116 if (a == &dev_attr_eui.attr) {
2117 if (!memchr_inv(ns->eui, 0, sizeof(ns->eui)))
2118 return 0;
2119 }
2120 return a->mode;
2121}
2122
2123static const struct attribute_group nvme_ns_attr_group = {
2124 .attrs = nvme_ns_attrs,
1a353d85 2125 .is_visible = nvme_ns_attrs_are_visible,
2b9b6e86
KB		 2126};
2127
931e1c22 2128#define nvme_show_str_function(field) \
779ff756
KB		 2129static ssize_t field##_show(struct device *dev, \
2130 struct device_attribute *attr, char *buf) \
2131{ \
2132 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
2133 return sprintf(buf, "%.*s\n", (int)sizeof(ctrl->field), ctrl->field); \
2134} \
2135static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
2136
931e1c22
ML		 2137#define nvme_show_int_function(field) \
2138static ssize_t field##_show(struct device *dev, \
2139 struct device_attribute *attr, char *buf) \
2140{ \
2141 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
2142 return sprintf(buf, "%d\n", ctrl->field); \
2143} \
2144static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
2145
2146nvme_show_str_function(model);
2147nvme_show_str_function(serial);
2148nvme_show_str_function(firmware_rev);
2149nvme_show_int_function(cntlid);
779ff756 2150
1a353d85
ML		 2151static ssize_t nvme_sysfs_delete(struct device *dev,
2152 struct device_attribute *attr, const char *buf,
2153 size_t count)
2154{
2155 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2156
2157 if (device_remove_file_self(dev, attr))
2158 ctrl->ops->delete_ctrl(ctrl);
2159 return count;
2160}
2161static DEVICE_ATTR(delete_controller, S_IWUSR, NULL, nvme_sysfs_delete);
2162
2163static ssize_t nvme_sysfs_show_transport(struct device *dev,
2164 struct device_attribute *attr,
2165 char *buf)
2166{
2167 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2168
2169 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->ops->name);
2170}
2171static DEVICE_ATTR(transport, S_IRUGO, nvme_sysfs_show_transport, NULL);
2172
8432bdb2
SG		 2173static ssize_t nvme_sysfs_show_state(struct device *dev,
2174 struct device_attribute *attr,
2175 char *buf)
2176{
2177 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2178 static const char *const state_name[] = {
2179 [NVME_CTRL_NEW] = "new",
2180 [NVME_CTRL_LIVE] = "live",
2181 [NVME_CTRL_RESETTING] = "resetting",
2182 [NVME_CTRL_RECONNECTING]= "reconnecting",
2183 [NVME_CTRL_DELETING] = "deleting",
2184 [NVME_CTRL_DEAD] = "dead",
2185 };
2186
2187 if ((unsigned)ctrl->state < ARRAY_SIZE(state_name) &&
2188 state_name[ctrl->state])
2189 return sprintf(buf, "%s\n", state_name[ctrl->state]);
2190
2191 return sprintf(buf, "unknown state\n");
2192}
2193
2194static DEVICE_ATTR(state, S_IRUGO, nvme_sysfs_show_state, NULL);
2195
1a353d85
ML		 2196static ssize_t nvme_sysfs_show_subsysnqn(struct device *dev,
2197 struct device_attribute *attr,
2198 char *buf)
2199{
2200 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2201
180de007 2202 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->subnqn);
1a353d85
ML		 2203}
2204static DEVICE_ATTR(subsysnqn, S_IRUGO, nvme_sysfs_show_subsysnqn, NULL);
2205
2206static ssize_t nvme_sysfs_show_address(struct device *dev,
2207 struct device_attribute *attr,
2208 char *buf)
2209{
2210 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2211
2212 return ctrl->ops->get_address(ctrl, buf, PAGE_SIZE);
2213}
2214static DEVICE_ATTR(address, S_IRUGO, nvme_sysfs_show_address, NULL);
2215
779ff756
KB		 2216static struct attribute *nvme_dev_attrs[] = {
2217 &dev_attr_reset_controller.attr,
9ec3bb2f 2218 &dev_attr_rescan_controller.attr,
779ff756
KB		 2219 &dev_attr_model.attr,
2220 &dev_attr_serial.attr,
2221 &dev_attr_firmware_rev.attr,
931e1c22 2222 &dev_attr_cntlid.attr,
1a353d85
ML		 2223 &dev_attr_delete_controller.attr,
2224 &dev_attr_transport.attr,
2225 &dev_attr_subsysnqn.attr,
2226 &dev_attr_address.attr,
8432bdb2 2227 &dev_attr_state.attr,
779ff756
KB		 2228 NULL
2229};
2230
1a353d85
ML		 2231static umode_t nvme_dev_attrs_are_visible(struct kobject *kobj,
2232 struct attribute *a, int n)
2233{
2234 struct device *dev = container_of(kobj, struct device, kobj);
2235 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2236
49d3d50b
CH		 2237 if (a == &dev_attr_delete_controller.attr && !ctrl->ops->delete_ctrl)
2238 return 0;
2239 if (a == &dev_attr_address.attr && !ctrl->ops->get_address)
2240 return 0;
1a353d85
ML		 2241
2242 return a->mode;
2243}
2244
779ff756 2245static struct attribute_group nvme_dev_attrs_group = {
1a353d85
ML		 2246 .attrs = nvme_dev_attrs,
2247 .is_visible = nvme_dev_attrs_are_visible,
779ff756
KB		 2248};
2249
2250static const struct attribute_group *nvme_dev_attr_groups[] = {
2251 &nvme_dev_attrs_group,
2252 NULL,
2253};
2254
5bae7f73
CH		 2255static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2256{
2257 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2258 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2259
2260 return nsa->ns_id - nsb->ns_id;
2261}
2262
32f0c4af 2263static struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 2264{
32f0c4af 2265 struct nvme_ns *ns, *ret = NULL;
69d3b8ac 2266
32f0c4af 2267 mutex_lock(&ctrl->namespaces_mutex);
5bae7f73 2268 list_for_each_entry(ns, &ctrl->namespaces, list) {
32f0c4af
KB		 2269 if (ns->ns_id == nsid) {
2270 kref_get(&ns->kref);
2271 ret = ns;
2272 break;
2273 }
5bae7f73
CH		 2274 if (ns->ns_id > nsid)
2275 break;
2276 }
32f0c4af
KB		 2277 mutex_unlock(&ctrl->namespaces_mutex);
2278 return ret;
5bae7f73
CH		 2279}
2280
f5d11840
JA		 2281static int nvme_setup_streams_ns(struct nvme_ctrl *ctrl, struct nvme_ns *ns)
2282{
2283 struct streams_directive_params s;
2284 int ret;
2285
2286 if (!ctrl->nr_streams)
2287 return 0;
2288
2289 ret = nvme_get_stream_params(ctrl, &s, ns->ns_id);
2290 if (ret)
2291 return ret;
2292
2293 ns->sws = le32_to_cpu(s.sws);
2294 ns->sgs = le16_to_cpu(s.sgs);
2295
2296 if (ns->sws) {
2297 unsigned int bs = 1 << ns->lba_shift;
2298
2299 blk_queue_io_min(ns->queue, bs * ns->sws);
2300 if (ns->sgs)
2301 blk_queue_io_opt(ns->queue, bs * ns->sws * ns->sgs);
2302 }
2303
2304 return 0;
2305}
2306
5bae7f73
CH		 2307static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
2308{
2309 struct nvme_ns *ns;
2310 struct gendisk *disk;
ac81bfa9
MB		 2311 struct nvme_id_ns *id;
2312 char disk_name[DISK_NAME_LEN];
5bae7f73
CH		 2313 int node = dev_to_node(ctrl->dev);
2314
2315 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
2316 if (!ns)
2317 return;
2318
075790eb
KB		 2319 ns->instance = ida_simple_get(&ctrl->ns_ida, 1, 0, GFP_KERNEL);
2320 if (ns->instance < 0)
2321 goto out_free_ns;
2322
5bae7f73
CH		 2323 ns->queue = blk_mq_init_queue(ctrl->tagset);
2324 if (IS_ERR(ns->queue))
075790eb 2325 goto out_release_instance;
5bae7f73
CH		 2326 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
2327 ns->queue->queuedata = ns;
2328 ns->ctrl = ctrl;
2329
5bae7f73
CH		 2330 kref_init(&ns->kref);
2331 ns->ns_id = nsid;
5bae7f73 2332 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
5bae7f73
CH		 2333
2334 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
da35825d 2335 nvme_set_queue_limits(ctrl, ns->queue);
f5d11840 2336 nvme_setup_streams_ns(ctrl, ns);
5bae7f73 2337
ac81bfa9 2338 sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->instance);
5bae7f73 2339
ac81bfa9
MB		 2340 if (nvme_revalidate_ns(ns, &id))
2341 goto out_free_queue;
2342
3dc87dd0
MB		 2343 if (nvme_nvm_ns_supported(ns, id) &&
2344 nvme_nvm_register(ns, disk_name, node)) {
f0425db0 2345 dev_warn(ctrl->device, "%s: LightNVM init failure\n", __func__);
3dc87dd0
MB		 2346 goto out_free_id;
2347 }
ac81bfa9 2348
3dc87dd0
MB		 2349 disk = alloc_disk_node(0, node);
2350 if (!disk)
2351 goto out_free_id;
ac81bfa9 2352
3dc87dd0
MB		 2353 disk->fops = &nvme_fops;
2354 disk->private_data = ns;
2355 disk->queue = ns->queue;
2356 disk->flags = GENHD_FL_EXT_DEVT;
2357 memcpy(disk->disk_name, disk_name, DISK_NAME_LEN);
2358 ns->disk = disk;
2359
2360 __nvme_revalidate_disk(disk, id);
5bae7f73 2361
32f0c4af
KB		 2362 mutex_lock(&ctrl->namespaces_mutex);
2363 list_add_tail(&ns->list, &ctrl->namespaces);
2364 mutex_unlock(&ctrl->namespaces_mutex);
2365
5bae7f73 2366 kref_get(&ctrl->kref);
ac81bfa9
MB		 2367
2368 kfree(id);
2369
0d52c756 2370 device_add_disk(ctrl->device, ns->disk);
2b9b6e86
KB		 2371 if (sysfs_create_group(&disk_to_dev(ns->disk)->kobj,
2372 &nvme_ns_attr_group))
2373 pr_warn("%s: failed to create sysfs group for identification\n",
2374 ns->disk->disk_name);
3dc87dd0
MB		 2375 if (ns->ndev && nvme_nvm_register_sysfs(ns))
2376 pr_warn("%s: failed to register lightnvm sysfs group for identification\n",
2377 ns->disk->disk_name);
5bae7f73 2378 return;
ac81bfa9
MB		 2379 out_free_id:
2380 kfree(id);
5bae7f73
CH		 2381 out_free_queue:
2382 blk_cleanup_queue(ns->queue);
075790eb
KB		 2383 out_release_instance:
2384 ida_simple_remove(&ctrl->ns_ida, ns->instance);
5bae7f73
CH		 2385 out_free_ns:
2386 kfree(ns);
2387}
2388
2389static void nvme_ns_remove(struct nvme_ns *ns)
2390{
646017a6
KB		 2391 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
2392 return;
69d3b8ac 2393
b0b4e09c 2394 if (ns->disk && ns->disk->flags & GENHD_FL_UP) {
5bae7f73
CH		 2395 if (blk_get_integrity(ns->disk))
2396 blk_integrity_unregister(ns->disk);
2b9b6e86
KB		 2397 sysfs_remove_group(&disk_to_dev(ns->disk)->kobj,
2398 &nvme_ns_attr_group);
3dc87dd0
MB		 2399 if (ns->ndev)
2400 nvme_nvm_unregister_sysfs(ns);
5bae7f73 2401 del_gendisk(ns->disk);
5bae7f73
CH		 2402 blk_cleanup_queue(ns->queue);
2403 }
32f0c4af
KB		 2404
2405 mutex_lock(&ns->ctrl->namespaces_mutex);
5bae7f73 2406 list_del_init(&ns->list);
32f0c4af
KB		 2407 mutex_unlock(&ns->ctrl->namespaces_mutex);
2408
5bae7f73
CH		 2409 nvme_put_ns(ns);
2410}
2411
540c801c
KB		 2412static void nvme_validate_ns(struct nvme_ctrl *ctrl, unsigned nsid)
2413{
2414 struct nvme_ns *ns;
2415
32f0c4af 2416 ns = nvme_find_get_ns(ctrl, nsid);
540c801c 2417 if (ns) {
b0b4e09c 2418 if (ns->disk && revalidate_disk(ns->disk))
540c801c 2419 nvme_ns_remove(ns);
32f0c4af 2420 nvme_put_ns(ns);
540c801c
KB		 2421 } else
2422 nvme_alloc_ns(ctrl, nsid);
2423}
2424
47b0e50a
SB		 2425static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
2426 unsigned nsid)
2427{
2428 struct nvme_ns *ns, *next;
2429
2430 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
2431 if (ns->ns_id > nsid)
2432 nvme_ns_remove(ns);
2433 }
2434}
2435
540c801c
KB		 2436static int nvme_scan_ns_list(struct nvme_ctrl *ctrl, unsigned nn)
2437{
2438 struct nvme_ns *ns;
2439 __le32 *ns_list;
2440 unsigned i, j, nsid, prev = 0, num_lists = DIV_ROUND_UP(nn, 1024);
2441 int ret = 0;
2442
2443 ns_list = kzalloc(0x1000, GFP_KERNEL);
2444 if (!ns_list)
2445 return -ENOMEM;
2446
2447 for (i = 0; i < num_lists; i++) {
2448 ret = nvme_identify_ns_list(ctrl, prev, ns_list);
2449 if (ret)
47b0e50a 2450 goto free;
540c801c
KB		 2451
2452 for (j = 0; j < min(nn, 1024U); j++) {
2453 nsid = le32_to_cpu(ns_list[j]);
2454 if (!nsid)
2455 goto out;
2456
2457 nvme_validate_ns(ctrl, nsid);
2458
2459 while (++prev < nsid) {
32f0c4af
KB		 2460 ns = nvme_find_get_ns(ctrl, prev);
2461 if (ns) {
540c801c 2462 nvme_ns_remove(ns);
32f0c4af
KB		 2463 nvme_put_ns(ns);
2464 }
540c801c
KB		 2465 }
2466 }
2467 nn -= j;
2468 }
2469 out:
47b0e50a
SB		 2470 nvme_remove_invalid_namespaces(ctrl, prev);
2471 free:
540c801c
KB		 2472 kfree(ns_list);
2473 return ret;
2474}
2475
5955be21 2476static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl, unsigned nn)
5bae7f73 2477{
5bae7f73
CH		 2478 unsigned i;
2479
540c801c
KB		 2480 for (i = 1; i <= nn; i++)
2481 nvme_validate_ns(ctrl, i);
2482
47b0e50a 2483 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH		 2484}
2485
5955be21 2486static void nvme_scan_work(struct work_struct *work)
5bae7f73 2487{
5955be21
CH		 2488 struct nvme_ctrl *ctrl =
2489 container_of(work, struct nvme_ctrl, scan_work);
5bae7f73 2490 struct nvme_id_ctrl *id;
540c801c 2491 unsigned nn;
5bae7f73 2492
5955be21
CH		 2493 if (ctrl->state != NVME_CTRL_LIVE)
2494 return;
2495
5bae7f73
CH		 2496 if (nvme_identify_ctrl(ctrl, &id))
2497 return;
540c801c
KB		 2498
2499 nn = le32_to_cpu(id->nn);
8ef2074d 2500 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
540c801c
KB		 2501 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
2502 if (!nvme_scan_ns_list(ctrl, nn))
2503 goto done;
2504 }
5955be21 2505 nvme_scan_ns_sequential(ctrl, nn);
540c801c 2506 done:
32f0c4af 2507 mutex_lock(&ctrl->namespaces_mutex);
540c801c 2508 list_sort(NULL, &ctrl->namespaces, ns_cmp);
69d3b8ac 2509 mutex_unlock(&ctrl->namespaces_mutex);
5bae7f73
CH		 2510 kfree(id);
2511}
5955be21
CH		 2512
2513void nvme_queue_scan(struct nvme_ctrl *ctrl)
2514{
2515 /*
2516 * Do not queue new scan work when a controller is reset during
2517 * removal.
2518 */
2519 if (ctrl->state == NVME_CTRL_LIVE)
c669ccdc 2520 queue_work(nvme_wq, &ctrl->scan_work);
5955be21
CH		 2521}
2522EXPORT_SYMBOL_GPL(nvme_queue_scan);
5bae7f73 2523
32f0c4af
KB		 2524/*
2525 * This function iterates the namespace list unlocked to allow recovery from
2526 * controller failure. It is up to the caller to ensure the namespace list is
2527 * not modified by scan work while this function is executing.
2528 */
5bae7f73
CH		 2529void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
2530{
2531 struct nvme_ns *ns, *next;
2532
0ff9d4e1
KB		 2533 /*
2534 * The dead states indicates the controller was not gracefully
2535 * disconnected. In that case, we won't be able to flush any data while
2536 * removing the namespaces' disks; fail all the queues now to avoid
2537 * potentially having to clean up the failed sync later.
2538 */
2539 if (ctrl->state == NVME_CTRL_DEAD)
2540 nvme_kill_queues(ctrl);
2541
5bae7f73
CH		 2542 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list)
2543 nvme_ns_remove(ns);
2544}
576d55d6 2545EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 2546
f866fc42
CH		 2547static void nvme_async_event_work(struct work_struct *work)
2548{
2549 struct nvme_ctrl *ctrl =
2550 container_of(work, struct nvme_ctrl, async_event_work);
2551
2552 spin_lock_irq(&ctrl->lock);
2553 while (ctrl->event_limit > 0) {
2554 int aer_idx = --ctrl->event_limit;
2555
2556 spin_unlock_irq(&ctrl->lock);
2557 ctrl->ops->submit_async_event(ctrl, aer_idx);
2558 spin_lock_irq(&ctrl->lock);
2559 }
2560 spin_unlock_irq(&ctrl->lock);
2561}
2562
b6dccf7f
AD		 2563static bool nvme_ctrl_pp_status(struct nvme_ctrl *ctrl)
2564{
2565
2566 u32 csts;
2567
2568 if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts))
2569 return false;
2570
2571 if (csts == ~0)
2572 return false;
2573
2574 return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP));
2575}
2576
2577static void nvme_get_fw_slot_info(struct nvme_ctrl *ctrl)
2578{
2579 struct nvme_command c = { };
2580 struct nvme_fw_slot_info_log *log;
2581
2582 log = kmalloc(sizeof(*log), GFP_KERNEL);
2583 if (!log)
2584 return;
2585
2586 c.common.opcode = nvme_admin_get_log_page;
62346eae 2587 c.common.nsid = cpu_to_le32(NVME_NSID_ALL);
b6dccf7f
AD		 2588 c.common.cdw10[0] = nvme_get_log_dw10(NVME_LOG_FW_SLOT, sizeof(*log));
2589
2590 if (!nvme_submit_sync_cmd(ctrl->admin_q, &c, log, sizeof(*log)))
2591 dev_warn(ctrl->device,
2592 "Get FW SLOT INFO log error\n");
2593 kfree(log);
2594}
2595
2596static void nvme_fw_act_work(struct work_struct *work)
2597{
2598 struct nvme_ctrl *ctrl = container_of(work,
2599 struct nvme_ctrl, fw_act_work);
2600 unsigned long fw_act_timeout;
2601
2602 if (ctrl->mtfa)
2603 fw_act_timeout = jiffies +
2604 msecs_to_jiffies(ctrl->mtfa * 100);
2605 else
2606 fw_act_timeout = jiffies +
2607 msecs_to_jiffies(admin_timeout * 1000);
2608
2609 nvme_stop_queues(ctrl);
2610 while (nvme_ctrl_pp_status(ctrl)) {
2611 if (time_after(jiffies, fw_act_timeout)) {
2612 dev_warn(ctrl->device,
2613 "Fw activation timeout, reset controller\n");
2614 nvme_reset_ctrl(ctrl);
2615 break;
2616 }
2617 msleep(100);
2618 }
2619
2620 if (ctrl->state != NVME_CTRL_LIVE)
2621 return;
2622
2623 nvme_start_queues(ctrl);
2624 /* read FW slot informationi to clear the AER*/
2625 nvme_get_fw_slot_info(ctrl);
2626}
2627
7bf58533
CH		 2628void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
2629 union nvme_result *res)
f866fc42 2630{
7bf58533
CH		 2631 u32 result = le32_to_cpu(res->u32);
2632 bool done = true;
f866fc42 2633
7bf58533
CH		 2634 switch (le16_to_cpu(status) >> 1) {
2635 case NVME_SC_SUCCESS:
2636 done = false;
2637 /*FALLTHRU*/
2638 case NVME_SC_ABORT_REQ:
f866fc42 2639 ++ctrl->event_limit;
c669ccdc 2640 queue_work(nvme_wq, &ctrl->async_event_work);
7bf58533
CH		 2641 break;
2642 default:
2643 break;
f866fc42
CH		 2644 }
2645
7bf58533 2646 if (done)
f866fc42
CH		 2647 return;
2648
2649 switch (result & 0xff07) {
2650 case NVME_AER_NOTICE_NS_CHANGED:
2651 dev_info(ctrl->device, "rescanning\n");
2652 nvme_queue_scan(ctrl);
2653 break;
b6dccf7f
AD		 2654 case NVME_AER_NOTICE_FW_ACT_STARTING:
2655 schedule_work(&ctrl->fw_act_work);
2656 break;
f866fc42
CH		 2657 default:
2658 dev_warn(ctrl->device, "async event result %08x\n", result);
2659 }
2660}
2661EXPORT_SYMBOL_GPL(nvme_complete_async_event);
2662
2663void nvme_queue_async_events(struct nvme_ctrl *ctrl)
2664{
2665 ctrl->event_limit = NVME_NR_AERS;
c669ccdc 2666 queue_work(nvme_wq, &ctrl->async_event_work);
f866fc42
CH		 2667}
2668EXPORT_SYMBOL_GPL(nvme_queue_async_events);
2669
f3ca80fc
CH		 2670static DEFINE_IDA(nvme_instance_ida);
2671
2672static int nvme_set_instance(struct nvme_ctrl *ctrl)
2673{
2674 int instance, error;
2675
2676 do {
2677 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2678 return -ENODEV;
2679
2680 spin_lock(&dev_list_lock);
2681 error = ida_get_new(&nvme_instance_ida, &instance);
2682 spin_unlock(&dev_list_lock);
2683 } while (error == -EAGAIN);
2684
2685 if (error)
2686 return -ENODEV;
2687
2688 ctrl->instance = instance;
2689 return 0;
2690}
2691
2692static void nvme_release_instance(struct nvme_ctrl *ctrl)
2693{
2694 spin_lock(&dev_list_lock);
2695 ida_remove(&nvme_instance_ida, ctrl->instance);
2696 spin_unlock(&dev_list_lock);
2697}
2698
d09f2b45 2699void nvme_stop_ctrl(struct nvme_ctrl *ctrl)
576d55d6 2700{
d09f2b45 2701 nvme_stop_keep_alive(ctrl);
f866fc42 2702 flush_work(&ctrl->async_event_work);
5955be21 2703 flush_work(&ctrl->scan_work);
b6dccf7f 2704 cancel_work_sync(&ctrl->fw_act_work);
d09f2b45
SG		 2705}
2706EXPORT_SYMBOL_GPL(nvme_stop_ctrl);
2707
2708void nvme_start_ctrl(struct nvme_ctrl *ctrl)
2709{
2710 if (ctrl->kato)
2711 nvme_start_keep_alive(ctrl);
2712
2713 if (ctrl->queue_count > 1) {
2714 nvme_queue_scan(ctrl);
2715 nvme_queue_async_events(ctrl);
2716 nvme_start_queues(ctrl);
2717 }
2718}
2719EXPORT_SYMBOL_GPL(nvme_start_ctrl);
5955be21 2720
d09f2b45
SG		 2721void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
2722{
53029b04 2723 device_destroy(nvme_class, MKDEV(nvme_char_major, ctrl->instance));
f3ca80fc
CH		 2724
2725 spin_lock(&dev_list_lock);
2726 list_del(&ctrl->node);
2727 spin_unlock(&dev_list_lock);
53029b04 2728}
576d55d6 2729EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04
KB		 2730
2731static void nvme_free_ctrl(struct kref *kref)
2732{
2733 struct nvme_ctrl *ctrl = container_of(kref, struct nvme_ctrl, kref);
f3ca80fc
CH		 2734
2735 put_device(ctrl->device);
2736 nvme_release_instance(ctrl);
075790eb 2737 ida_destroy(&ctrl->ns_ida);
f3ca80fc
CH		 2738
2739 ctrl->ops->free_ctrl(ctrl);
2740}
2741
2742void nvme_put_ctrl(struct nvme_ctrl *ctrl)
2743{
2744 kref_put(&ctrl->kref, nvme_free_ctrl);
2745}
576d55d6 2746EXPORT_SYMBOL_GPL(nvme_put_ctrl);
f3ca80fc
CH		 2747
2748/*
2749 * Initialize a NVMe controller structures. This needs to be called during
2750 * earliest initialization so that we have the initialized structured around
2751 * during probing.
2752 */
2753int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
2754 const struct nvme_ctrl_ops *ops, unsigned long quirks)
2755{
2756 int ret;
2757
bb8d261e
CH		 2758 ctrl->state = NVME_CTRL_NEW;
2759 spin_lock_init(&ctrl->lock);
f3ca80fc 2760 INIT_LIST_HEAD(&ctrl->namespaces);
69d3b8ac 2761 mutex_init(&ctrl->namespaces_mutex);
f3ca80fc
CH		 2762 kref_init(&ctrl->kref);
2763 ctrl->dev = dev;
2764 ctrl->ops = ops;
2765 ctrl->quirks = quirks;
5955be21 2766 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 2767 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
b6dccf7f 2768 INIT_WORK(&ctrl->fw_act_work, nvme_fw_act_work);
f3ca80fc
CH		 2769
2770 ret = nvme_set_instance(ctrl);
2771 if (ret)
2772 goto out;
2773
779ff756 2774 ctrl->device = device_create_with_groups(nvme_class, ctrl->dev,
f3ca80fc 2775 MKDEV(nvme_char_major, ctrl->instance),
f4f0f63e 2776 ctrl, nvme_dev_attr_groups,
779ff756 2777 "nvme%d", ctrl->instance);
f3ca80fc
CH		 2778 if (IS_ERR(ctrl->device)) {
2779 ret = PTR_ERR(ctrl->device);
2780 goto out_release_instance;
2781 }
2782 get_device(ctrl->device);
075790eb 2783 ida_init(&ctrl->ns_ida);
f3ca80fc 2784
f3ca80fc
CH		 2785 spin_lock(&dev_list_lock);
2786 list_add_tail(&ctrl->node, &nvme_ctrl_list);
2787 spin_unlock(&dev_list_lock);
2788
c5552fde
AL		 2789 /*
2790 * Initialize latency tolerance controls. The sysfs files won't
2791 * be visible to userspace unless the device actually supports APST.
2792 */
2793 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
2794 dev_pm_qos_update_user_latency_tolerance(ctrl->device,
2795 min(default_ps_max_latency_us, (unsigned long)S32_MAX));
2796
f3ca80fc 2797 return 0;
f3ca80fc
CH		 2798out_release_instance:
2799 nvme_release_instance(ctrl);
2800out:
2801 return ret;
2802}
576d55d6 2803EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 2804
69d9a99c
KB		 2805/**
2806 * nvme_kill_queues(): Ends all namespace queues
2807 * @ctrl: the dead controller that needs to end
2808 *
2809 * Call this function when the driver determines it is unable to get the
2810 * controller in a state capable of servicing IO.
2811 */
2812void nvme_kill_queues(struct nvme_ctrl *ctrl)
2813{
2814 struct nvme_ns *ns;
2815
32f0c4af 2816 mutex_lock(&ctrl->namespaces_mutex);
82654b6b 2817
443bd90f 2818 /* Forcibly unquiesce queues to avoid blocking dispatch */
7dd1ab16
SB		 2819 if (ctrl->admin_q)
2820 blk_mq_unquiesce_queue(ctrl->admin_q);
443bd90f 2821
32f0c4af 2822 list_for_each_entry(ns, &ctrl->namespaces, list) {
69d9a99c
KB		 2823 /*
2824 * Revalidating a dead namespace sets capacity to 0. This will
2825 * end buffered writers dirtying pages that can't be synced.
2826 */
f33447b9
KB		 2827 if (!ns->disk || test_and_set_bit(NVME_NS_DEAD, &ns->flags))
2828 continue;
2829 revalidate_disk(ns->disk);
69d9a99c 2830 blk_set_queue_dying(ns->queue);
806f026f 2831
443bd90f
ML		 2832 /* Forcibly unquiesce queues to avoid blocking dispatch */
2833 blk_mq_unquiesce_queue(ns->queue);
69d9a99c 2834 }
32f0c4af 2835 mutex_unlock(&ctrl->namespaces_mutex);
69d9a99c 2836}
237045fc 2837EXPORT_SYMBOL_GPL(nvme_kill_queues);
69d9a99c 2838
302ad8cc
KB		 2839void nvme_unfreeze(struct nvme_ctrl *ctrl)
2840{
2841 struct nvme_ns *ns;
2842
2843 mutex_lock(&ctrl->namespaces_mutex);
2844 list_for_each_entry(ns, &ctrl->namespaces, list)
2845 blk_mq_unfreeze_queue(ns->queue);
2846 mutex_unlock(&ctrl->namespaces_mutex);
2847}
2848EXPORT_SYMBOL_GPL(nvme_unfreeze);
2849
2850void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout)
2851{
2852 struct nvme_ns *ns;
2853
2854 mutex_lock(&ctrl->namespaces_mutex);
2855 list_for_each_entry(ns, &ctrl->namespaces, list) {
2856 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout);
2857 if (timeout <= 0)
2858 break;
2859 }
2860 mutex_unlock(&ctrl->namespaces_mutex);
2861}
2862EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout);
2863
2864void nvme_wait_freeze(struct nvme_ctrl *ctrl)
2865{
2866 struct nvme_ns *ns;
2867
2868 mutex_lock(&ctrl->namespaces_mutex);
2869 list_for_each_entry(ns, &ctrl->namespaces, list)
2870 blk_mq_freeze_queue_wait(ns->queue);
2871 mutex_unlock(&ctrl->namespaces_mutex);
2872}
2873EXPORT_SYMBOL_GPL(nvme_wait_freeze);
2874
2875void nvme_start_freeze(struct nvme_ctrl *ctrl)
2876{
2877 struct nvme_ns *ns;
2878
2879 mutex_lock(&ctrl->namespaces_mutex);
2880 list_for_each_entry(ns, &ctrl->namespaces, list)
1671d522 2881 blk_freeze_queue_start(ns->queue);
302ad8cc
KB		 2882 mutex_unlock(&ctrl->namespaces_mutex);
2883}
2884EXPORT_SYMBOL_GPL(nvme_start_freeze);
2885
25646264 2886void nvme_stop_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 2887{
2888 struct nvme_ns *ns;
2889
32f0c4af 2890 mutex_lock(&ctrl->namespaces_mutex);
a6eaa884 2891 list_for_each_entry(ns, &ctrl->namespaces, list)
3174dd33 2892 blk_mq_quiesce_queue(ns->queue);
32f0c4af 2893 mutex_unlock(&ctrl->namespaces_mutex);
363c9aac 2894}
576d55d6 2895EXPORT_SYMBOL_GPL(nvme_stop_queues);
363c9aac 2896
25646264 2897void nvme_start_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 2898{
2899 struct nvme_ns *ns;
2900
32f0c4af 2901 mutex_lock(&ctrl->namespaces_mutex);
8d7b8faf 2902 list_for_each_entry(ns, &ctrl->namespaces, list)
f660174e 2903 blk_mq_unquiesce_queue(ns->queue);
32f0c4af 2904 mutex_unlock(&ctrl->namespaces_mutex);
363c9aac 2905}
576d55d6 2906EXPORT_SYMBOL_GPL(nvme_start_queues);
363c9aac 2907
5bae7f73
CH		 2908int __init nvme_core_init(void)
2909{
2910 int result;
2911
9a6327d2
SG		 2912 nvme_wq = alloc_workqueue("nvme-wq",
2913 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
2914 if (!nvme_wq)
2915 return -ENOMEM;
2916
f3ca80fc
CH		 2917 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
2918 &nvme_dev_fops);
2919 if (result < 0)
9a6327d2 2920 goto destroy_wq;
f3ca80fc
CH		 2921 else if (result > 0)
2922 nvme_char_major = result;
2923
2924 nvme_class = class_create(THIS_MODULE, "nvme");
2925 if (IS_ERR(nvme_class)) {
2926 result = PTR_ERR(nvme_class);
2927 goto unregister_chrdev;
2928 }
2929
5bae7f73 2930 return 0;
f3ca80fc 2931
9a6327d2 2932unregister_chrdev:
f3ca80fc 2933 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
9a6327d2
SG		 2934destroy_wq:
2935 destroy_workqueue(nvme_wq);
f3ca80fc 2936 return result;
5bae7f73
CH		 2937}
2938
2939void nvme_core_exit(void)
2940{
f3ca80fc
CH		 2941 class_destroy(nvme_class);
2942 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
9a6327d2 2943 destroy_workqueue(nvme_wq);
5bae7f73 2944}
576d55d6
ML		 2945
2946MODULE_LICENSE("GPL");
2947MODULE_VERSION("1.0");
2948module_init(nvme_core_init);
2949module_exit(nvme_core_exit);
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