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Merge tag 'drm/tegra/for-4.11-rc1' of git://anongit.freedesktop.org/tegra/linux into...
[mirror_ubuntu-artful-kernel.git] / drivers / nvme / host / lightnvm.c
CommitLineData
ca064085
MB		 1/*
2 * nvme-lightnvm.c - LightNVM NVMe device
3 *
4 * Copyright (C) 2014-2015 IT University of Copenhagen
5 * Initial release: Matias Bjorling <mb@lightnvm.io>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License version
9 * 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; see the file COPYING. If not, write to
18 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139,
19 * USA.
20 *
21 */
22
23#include "nvme.h"
24
ca064085
MB		 25#include <linux/nvme.h>
26#include <linux/bitops.h>
27#include <linux/lightnvm.h>
28#include <linux/vmalloc.h>
29
30enum nvme_nvm_admin_opcode {
31 nvme_nvm_admin_identity = 0xe2,
32 nvme_nvm_admin_get_l2p_tbl = 0xea,
33 nvme_nvm_admin_get_bb_tbl = 0xf2,
34 nvme_nvm_admin_set_bb_tbl = 0xf1,
35};
36
37struct nvme_nvm_hb_rw {
38 __u8 opcode;
39 __u8 flags;
40 __u16 command_id;
41 __le32 nsid;
42 __u64 rsvd2;
43 __le64 metadata;
44 __le64 prp1;
45 __le64 prp2;
46 __le64 spba;
47 __le16 length;
48 __le16 control;
49 __le32 dsmgmt;
50 __le64 slba;
51};
52
53struct nvme_nvm_ph_rw {
54 __u8 opcode;
55 __u8 flags;
56 __u16 command_id;
57 __le32 nsid;
58 __u64 rsvd2;
59 __le64 metadata;
60 __le64 prp1;
61 __le64 prp2;
62 __le64 spba;
63 __le16 length;
64 __le16 control;
65 __le32 dsmgmt;
66 __le64 resv;
67};
68
69struct nvme_nvm_identity {
70 __u8 opcode;
71 __u8 flags;
72 __u16 command_id;
73 __le32 nsid;
74 __u64 rsvd[2];
75 __le64 prp1;
76 __le64 prp2;
77 __le32 chnl_off;
78 __u32 rsvd11[5];
79};
80
81struct nvme_nvm_l2ptbl {
82 __u8 opcode;
83 __u8 flags;
84 __u16 command_id;
85 __le32 nsid;
86 __le32 cdw2[4];
87 __le64 prp1;
88 __le64 prp2;
89 __le64 slba;
90 __le32 nlb;
91 __le16 cdw14[6];
92};
93
11450469 94struct nvme_nvm_getbbtbl {
ca064085
MB		 95 __u8 opcode;
96 __u8 flags;
97 __u16 command_id;
98 __le32 nsid;
99 __u64 rsvd[2];
100 __le64 prp1;
101 __le64 prp2;
11450469
MB		 102 __le64 spba;
103 __u32 rsvd4[4];
104};
105
106struct nvme_nvm_setbbtbl {
107 __u8 opcode;
108 __u8 flags;
109 __u16 command_id;
110 __le32 nsid;
111 __le64 rsvd[2];
112 __le64 prp1;
113 __le64 prp2;
114 __le64 spba;
115 __le16 nlb;
116 __u8 value;
117 __u8 rsvd3;
118 __u32 rsvd4[3];
ca064085
MB		 119};
120
121struct nvme_nvm_erase_blk {
122 __u8 opcode;
123 __u8 flags;
124 __u16 command_id;
125 __le32 nsid;
126 __u64 rsvd[2];
127 __le64 prp1;
128 __le64 prp2;
129 __le64 spba;
130 __le16 length;
131 __le16 control;
132 __le32 dsmgmt;
133 __le64 resv;
134};
135
136struct nvme_nvm_command {
137 union {
138 struct nvme_common_command common;
139 struct nvme_nvm_identity identity;
140 struct nvme_nvm_hb_rw hb_rw;
141 struct nvme_nvm_ph_rw ph_rw;
142 struct nvme_nvm_l2ptbl l2p;
11450469
MB		 143 struct nvme_nvm_getbbtbl get_bb;
144 struct nvme_nvm_setbbtbl set_bb;
ca064085
MB		 145 struct nvme_nvm_erase_blk erase;
146 };
147};
148
6dde1d6c 149#define NVME_NVM_LP_MLC_PAIRS 886
ca5927e7 150struct nvme_nvm_lp_mlc {
6f929702 151 __le16 num_pairs;
6dde1d6c 152 __u8 pairs[NVME_NVM_LP_MLC_PAIRS];
ca5927e7
MB		 153};
154
155struct nvme_nvm_lp_tbl {
156 __u8 id[8];
157 struct nvme_nvm_lp_mlc mlc;
158};
159
ca064085
MB		 160struct nvme_nvm_id_group {
161 __u8 mtype;
162 __u8 fmtype;
163 __le16 res16;
164 __u8 num_ch;
165 __u8 num_lun;
166 __u8 num_pln;
36d5dbc6 167 __u8 rsvd1;
ca064085
MB		 168 __le16 num_blk;
169 __le16 num_pg;
170 __le16 fpg_sz;
171 __le16 csecs;
172 __le16 sos;
36d5dbc6 173 __le16 rsvd2;
ca064085
MB		 174 __le32 trdt;
175 __le32 trdm;
176 __le32 tprt;
177 __le32 tprm;
178 __le32 tbet;
179 __le32 tbem;
180 __le32 mpos;
12be5edf 181 __le32 mccap;
ca064085 182 __le16 cpar;
ca5927e7
MB		 183 __u8 reserved[10];
184 struct nvme_nvm_lp_tbl lptbl;
ca064085
MB		 185} __packed;
186
187struct nvme_nvm_addr_format {
188 __u8 ch_offset;
189 __u8 ch_len;
190 __u8 lun_offset;
191 __u8 lun_len;
192 __u8 pln_offset;
193 __u8 pln_len;
194 __u8 blk_offset;
195 __u8 blk_len;
196 __u8 pg_offset;
197 __u8 pg_len;
198 __u8 sect_offset;
199 __u8 sect_len;
200 __u8 res[4];
201} __packed;
202
203struct nvme_nvm_id {
204 __u8 ver_id;
205 __u8 vmnt;
206 __u8 cgrps;
dad1b009 207 __u8 res;
ca064085
MB		 208 __le32 cap;
209 __le32 dom;
210 struct nvme_nvm_addr_format ppaf;
dad1b009 211 __u8 resv[228];
ca064085
MB		 212 struct nvme_nvm_id_group groups[4];
213} __packed;
214
11450469
MB		 215struct nvme_nvm_bb_tbl {
216 __u8 tblid[4];
217 __le16 verid;
218 __le16 revid;
219 __le32 rvsd1;
220 __le32 tblks;
221 __le32 tfact;
222 __le32 tgrown;
223 __le32 tdresv;
224 __le32 thresv;
225 __le32 rsvd2[8];
226 __u8 blk[0];
227};
228
ca064085
MB		 229/*
230 * Check we didn't inadvertently grow the command struct
231 */
232static inline void _nvme_nvm_check_size(void)
233{
234 BUILD_BUG_ON(sizeof(struct nvme_nvm_identity) != 64);
235 BUILD_BUG_ON(sizeof(struct nvme_nvm_hb_rw) != 64);
236 BUILD_BUG_ON(sizeof(struct nvme_nvm_ph_rw) != 64);
11450469
MB		 237 BUILD_BUG_ON(sizeof(struct nvme_nvm_getbbtbl) != 64);
238 BUILD_BUG_ON(sizeof(struct nvme_nvm_setbbtbl) != 64);
ca064085
MB		 239 BUILD_BUG_ON(sizeof(struct nvme_nvm_l2ptbl) != 64);
240 BUILD_BUG_ON(sizeof(struct nvme_nvm_erase_blk) != 64);
241 BUILD_BUG_ON(sizeof(struct nvme_nvm_id_group) != 960);
242 BUILD_BUG_ON(sizeof(struct nvme_nvm_addr_format) != 128);
243 BUILD_BUG_ON(sizeof(struct nvme_nvm_id) != 4096);
11450469 244 BUILD_BUG_ON(sizeof(struct nvme_nvm_bb_tbl) != 512);
ca064085
MB		 245}
246
247static int init_grps(struct nvm_id *nvm_id, struct nvme_nvm_id *nvme_nvm_id)
248{
249 struct nvme_nvm_id_group *src;
250 struct nvm_id_group *dst;
251 int i, end;
252
253 end = min_t(u32, 4, nvm_id->cgrps);
254
255 for (i = 0; i < end; i++) {
256 src = &nvme_nvm_id->groups[i];
257 dst = &nvm_id->groups[i];
258
259 dst->mtype = src->mtype;
260 dst->fmtype = src->fmtype;
261 dst->num_ch = src->num_ch;
262 dst->num_lun = src->num_lun;
263 dst->num_pln = src->num_pln;
264
265 dst->num_pg = le16_to_cpu(src->num_pg);
266 dst->num_blk = le16_to_cpu(src->num_blk);
267 dst->fpg_sz = le16_to_cpu(src->fpg_sz);
268 dst->csecs = le16_to_cpu(src->csecs);
269 dst->sos = le16_to_cpu(src->sos);
270
271 dst->trdt = le32_to_cpu(src->trdt);
272 dst->trdm = le32_to_cpu(src->trdm);
273 dst->tprt = le32_to_cpu(src->tprt);
274 dst->tprm = le32_to_cpu(src->tprm);
275 dst->tbet = le32_to_cpu(src->tbet);
276 dst->tbem = le32_to_cpu(src->tbem);
277 dst->mpos = le32_to_cpu(src->mpos);
12be5edf 278 dst->mccap = le32_to_cpu(src->mccap);
ca064085
MB		 279
280 dst->cpar = le16_to_cpu(src->cpar);
ca5927e7
MB		 281
282 if (dst->fmtype == NVM_ID_FMTYPE_MLC) {
283 memcpy(dst->lptbl.id, src->lptbl.id, 8);
284 dst->lptbl.mlc.num_pairs =
285 le16_to_cpu(src->lptbl.mlc.num_pairs);
6dde1d6c
MB		 286
287 if (dst->lptbl.mlc.num_pairs > NVME_NVM_LP_MLC_PAIRS) {
288 pr_err("nvm: number of MLC pairs not supported\n");
289 return -EINVAL;
290 }
291
ca5927e7 292 memcpy(dst->lptbl.mlc.pairs, src->lptbl.mlc.pairs,
6dde1d6c 293 dst->lptbl.mlc.num_pairs);
ca5927e7 294 }
ca064085
MB		 295 }
296
297 return 0;
298}
299
16f26c3a 300static int nvme_nvm_identity(struct nvm_dev *nvmdev, struct nvm_id *nvm_id)
ca064085 301{
16f26c3a 302 struct nvme_ns *ns = nvmdev->q->queuedata;
ca064085
MB		 303 struct nvme_nvm_id *nvme_nvm_id;
304 struct nvme_nvm_command c = {};
305 int ret;
306
307 c.identity.opcode = nvme_nvm_admin_identity;
308 c.identity.nsid = cpu_to_le32(ns->ns_id);
309 c.identity.chnl_off = 0;
310
311 nvme_nvm_id = kmalloc(sizeof(struct nvme_nvm_id), GFP_KERNEL);
312 if (!nvme_nvm_id)
313 return -ENOMEM;
314
ac02ddde 315 ret = nvme_submit_sync_cmd(ns->ctrl->admin_q, (struct nvme_command *)&c,
47b3115a 316 nvme_nvm_id, sizeof(struct nvme_nvm_id));
ca064085
MB		 317 if (ret) {
318 ret = -EIO;
319 goto out;
320 }
321
322 nvm_id->ver_id = nvme_nvm_id->ver_id;
323 nvm_id->vmnt = nvme_nvm_id->vmnt;
324 nvm_id->cgrps = nvme_nvm_id->cgrps;
325 nvm_id->cap = le32_to_cpu(nvme_nvm_id->cap);
326 nvm_id->dom = le32_to_cpu(nvme_nvm_id->dom);
2393bd39
MB		 327 memcpy(&nvm_id->ppaf, &nvme_nvm_id->ppaf,
328 sizeof(struct nvme_nvm_addr_format));
ca064085
MB		 329
330 ret = init_grps(nvm_id, nvme_nvm_id);
331out:
332 kfree(nvme_nvm_id);
333 return ret;
334}
335
16f26c3a 336static int nvme_nvm_get_l2p_tbl(struct nvm_dev *nvmdev, u64 slba, u32 nlb,
ca064085
MB		 337 nvm_l2p_update_fn *update_l2p, void *priv)
338{
16f26c3a 339 struct nvme_ns *ns = nvmdev->q->queuedata;
ca064085 340 struct nvme_nvm_command c = {};
ac02ddde 341 u32 len = queue_max_hw_sectors(ns->ctrl->admin_q) << 9;
5f436e5e 342 u32 nlb_pr_rq = len / sizeof(u64);
ca064085
MB		 343 u64 cmd_slba = slba;
344 void *entries;
345 int ret = 0;
346
347 c.l2p.opcode = nvme_nvm_admin_get_l2p_tbl;
348 c.l2p.nsid = cpu_to_le32(ns->ns_id);
349 entries = kmalloc(len, GFP_KERNEL);
350 if (!entries)
351 return -ENOMEM;
352
353 while (nlb) {
5f436e5e 354 u32 cmd_nlb = min(nlb_pr_rq, nlb);
8e79b5cb 355 u64 elba = slba + cmd_nlb;
ca064085
MB		 356
357 c.l2p.slba = cpu_to_le64(cmd_slba);
358 c.l2p.nlb = cpu_to_le32(cmd_nlb);
359
ac02ddde 360 ret = nvme_submit_sync_cmd(ns->ctrl->admin_q,
47b3115a 361 (struct nvme_command *)&c, entries, len);
ca064085 362 if (ret) {
b86d8d36
SG		 363 dev_err(ns->ctrl->device,
364 "L2P table transfer failed (%d)\n", ret);
ca064085
MB		 365 ret = -EIO;
366 goto out;
367 }
368
8e79b5cb
JG		 369 if (unlikely(elba > nvmdev->total_secs)) {
370 pr_err("nvm: L2P data from device is out of bounds!\n");
371 return -EINVAL;
372 }
373
8e53624d
JG		 374 /* Transform physical address to target address space */
375 nvmdev->mt->part_to_tgt(nvmdev, entries, cmd_nlb);
376
ca064085
MB		 377 if (update_l2p(cmd_slba, cmd_nlb, entries, priv)) {
378 ret = -EINTR;
379 goto out;
380 }
381
382 cmd_slba += cmd_nlb;
383 nlb -= cmd_nlb;
384 }
385
386out:
387 kfree(entries);
388 return ret;
389}
390
08236c6b 391static int nvme_nvm_get_bb_tbl(struct nvm_dev *nvmdev, struct ppa_addr ppa,
e11903f5 392 u8 *blks)
ca064085 393{
08236c6b 394 struct request_queue *q = nvmdev->q;
8e79b5cb 395 struct nvm_geo *geo = &nvmdev->geo;
ca064085 396 struct nvme_ns *ns = q->queuedata;
ac02ddde 397 struct nvme_ctrl *ctrl = ns->ctrl;
ca064085 398 struct nvme_nvm_command c = {};
11450469 399 struct nvme_nvm_bb_tbl *bb_tbl;
8e79b5cb 400 int nr_blks = geo->blks_per_lun * geo->plane_mode;
22e8c976 401 int tblsz = sizeof(struct nvme_nvm_bb_tbl) + nr_blks;
ca064085
MB		 402 int ret = 0;
403
404 c.get_bb.opcode = nvme_nvm_admin_get_bb_tbl;
405 c.get_bb.nsid = cpu_to_le32(ns->ns_id);
11450469 406 c.get_bb.spba = cpu_to_le64(ppa.ppa);
ca064085 407
11450469
MB		 408 bb_tbl = kzalloc(tblsz, GFP_KERNEL);
409 if (!bb_tbl)
410 return -ENOMEM;
ca064085 411
ac02ddde 412 ret = nvme_submit_sync_cmd(ctrl->admin_q, (struct nvme_command *)&c,
47b3115a 413 bb_tbl, tblsz);
ca064085 414 if (ret) {
b86d8d36 415 dev_err(ctrl->device, "get bad block table failed (%d)\n", ret);
ca064085
MB		 416 ret = -EIO;
417 goto out;
418 }
419
11450469
MB		 420 if (bb_tbl->tblid[0] != 'B' || bb_tbl->tblid[1] != 'B' ||
421 bb_tbl->tblid[2] != 'L' || bb_tbl->tblid[3] != 'T') {
b86d8d36 422 dev_err(ctrl->device, "bbt format mismatch\n");
11450469
MB		 423 ret = -EINVAL;
424 goto out;
425 }
426
427 if (le16_to_cpu(bb_tbl->verid) != 1) {
428 ret = -EINVAL;
b86d8d36 429 dev_err(ctrl->device, "bbt version not supported\n");
11450469
MB		 430 goto out;
431 }
432
22e8c976 433 if (le32_to_cpu(bb_tbl->tblks) != nr_blks) {
11450469 434 ret = -EINVAL;
b86d8d36
SG		 435 dev_err(ctrl->device,
436 "bbt unsuspected blocks returned (%u!=%u)",
22e8c976 437 le32_to_cpu(bb_tbl->tblks), nr_blks);
11450469
MB		 438 goto out;
439 }
440
8e79b5cb 441 memcpy(blks, bb_tbl->blk, geo->blks_per_lun * geo->plane_mode);
ca064085 442out:
11450469
MB		 443 kfree(bb_tbl);
444 return ret;
445}
446
00ee6cc3
MB		 447static int nvme_nvm_set_bb_tbl(struct nvm_dev *nvmdev, struct ppa_addr *ppas,
448 int nr_ppas, int type)
11450469 449{
16f26c3a 450 struct nvme_ns *ns = nvmdev->q->queuedata;
11450469
MB		 451 struct nvme_nvm_command c = {};
452 int ret = 0;
453
454 c.set_bb.opcode = nvme_nvm_admin_set_bb_tbl;
455 c.set_bb.nsid = cpu_to_le32(ns->ns_id);
00ee6cc3
MB		 456 c.set_bb.spba = cpu_to_le64(ppas->ppa);
457 c.set_bb.nlb = cpu_to_le16(nr_ppas - 1);
11450469
MB		 458 c.set_bb.value = type;
459
ac02ddde 460 ret = nvme_submit_sync_cmd(ns->ctrl->admin_q, (struct nvme_command *)&c,
47b3115a 461 NULL, 0);
11450469 462 if (ret)
b86d8d36
SG		 463 dev_err(ns->ctrl->device, "set bad block table failed (%d)\n",
464 ret);
ca064085
MB		 465 return ret;
466}
467
468static inline void nvme_nvm_rqtocmd(struct request *rq, struct nvm_rq *rqd,
469 struct nvme_ns *ns, struct nvme_nvm_command *c)
470{
471 c->ph_rw.opcode = rqd->opcode;
472 c->ph_rw.nsid = cpu_to_le32(ns->ns_id);
473 c->ph_rw.spba = cpu_to_le64(rqd->ppa_addr.ppa);
45bbd052 474 c->ph_rw.metadata = cpu_to_le64(rqd->dma_meta_list);
ca064085 475 c->ph_rw.control = cpu_to_le16(rqd->flags);
6d5be959 476 c->ph_rw.length = cpu_to_le16(rqd->nr_ppas - 1);
ca064085
MB		 477
478 if (rqd->opcode == NVM_OP_HBWRITE || rqd->opcode == NVM_OP_HBREAD)
b0b4e09c
MB		 479 c->hb_rw.slba = cpu_to_le64(nvme_block_nr(ns,
480 rqd->bio->bi_iter.bi_sector));
ca064085
MB		 481}
482
483static void nvme_nvm_end_io(struct request *rq, int error)
484{
485 struct nvm_rq *rqd = rq->end_io_data;
ca064085 486
d49187e9 487 rqd->ppa_status = nvme_req(rq)->result.u64;
91276162 488 nvm_end_io(rqd, error);
ca064085 489
7498e99f 490 kfree(nvme_req(rq)->cmd);
ca064085
MB		 491 blk_mq_free_request(rq);
492}
493
16f26c3a 494static int nvme_nvm_submit_io(struct nvm_dev *dev, struct nvm_rq *rqd)
ca064085 495{
16f26c3a 496 struct request_queue *q = dev->q;
ca064085
MB		 497 struct nvme_ns *ns = q->queuedata;
498 struct request *rq;
499 struct bio *bio = rqd->bio;
500 struct nvme_nvm_command *cmd;
501
d49187e9
CH		 502 cmd = kzalloc(sizeof(struct nvme_nvm_command), GFP_KERNEL);
503 if (!cmd)
ca064085
MB		 504 return -ENOMEM;
505
d49187e9
CH		 506 rq = nvme_alloc_request(q, (struct nvme_command *)cmd, 0, NVME_QID_ANY);
507 if (IS_ERR(rq)) {
508 kfree(cmd);
ca064085
MB		 509 return -ENOMEM;
510 }
d49187e9 511 rq->cmd_flags &= ~REQ_FAILFAST_DRIVER;
ca064085 512
ca064085 513 rq->ioprio = bio_prio(bio);
ca064085
MB		 514 if (bio_has_data(bio))
515 rq->nr_phys_segments = bio_phys_segments(q, bio);
516
517 rq->__data_len = bio->bi_iter.bi_size;
518 rq->bio = rq->biotail = bio;
519
520 nvme_nvm_rqtocmd(rq, rqd, ns, cmd);
521
ca064085
MB		 522 rq->end_io_data = rqd;
523
524 blk_execute_rq_nowait(q, NULL, rq, 0, nvme_nvm_end_io);
525
526 return 0;
527}
528
16f26c3a 529static int nvme_nvm_erase_block(struct nvm_dev *dev, struct nvm_rq *rqd)
ca064085 530{
16f26c3a 531 struct request_queue *q = dev->q;
ca064085
MB		 532 struct nvme_ns *ns = q->queuedata;
533 struct nvme_nvm_command c = {};
534
535 c.erase.opcode = NVM_OP_ERASE;
536 c.erase.nsid = cpu_to_le32(ns->ns_id);
537 c.erase.spba = cpu_to_le64(rqd->ppa_addr.ppa);
6d5be959 538 c.erase.length = cpu_to_le16(rqd->nr_ppas - 1);
bb314979 539 c.erase.control = cpu_to_le16(rqd->flags);
ca064085
MB		 540
541 return nvme_submit_sync_cmd(q, (struct nvme_command *)&c, NULL, 0);
542}
543
16f26c3a 544static void *nvme_nvm_create_dma_pool(struct nvm_dev *nvmdev, char *name)
ca064085 545{
16f26c3a 546 struct nvme_ns *ns = nvmdev->q->queuedata;
ca064085 547
ac02ddde 548 return dma_pool_create(name, ns->ctrl->dev, PAGE_SIZE, PAGE_SIZE, 0);
ca064085
MB		 549}
550
551static void nvme_nvm_destroy_dma_pool(void *pool)
552{
553 struct dma_pool *dma_pool = pool;
554
555 dma_pool_destroy(dma_pool);
556}
557
16f26c3a 558static void *nvme_nvm_dev_dma_alloc(struct nvm_dev *dev, void *pool,
ca064085
MB		 559 gfp_t mem_flags, dma_addr_t *dma_handler)
560{
561 return dma_pool_alloc(pool, mem_flags, dma_handler);
562}
563
75b85649 564static void nvme_nvm_dev_dma_free(void *pool, void *addr,
ca064085
MB		 565 dma_addr_t dma_handler)
566{
75b85649 567 dma_pool_free(pool, addr, dma_handler);
ca064085
MB		 568}
569
570static struct nvm_dev_ops nvme_nvm_dev_ops = {
571 .identity = nvme_nvm_identity,
572
573 .get_l2p_tbl = nvme_nvm_get_l2p_tbl,
574
575 .get_bb_tbl = nvme_nvm_get_bb_tbl,
11450469 576 .set_bb_tbl = nvme_nvm_set_bb_tbl,
ca064085
MB		 577
578 .submit_io = nvme_nvm_submit_io,
579 .erase_block = nvme_nvm_erase_block,
580
581 .create_dma_pool = nvme_nvm_create_dma_pool,
582 .destroy_dma_pool = nvme_nvm_destroy_dma_pool,
583 .dev_dma_alloc = nvme_nvm_dev_dma_alloc,
584 .dev_dma_free = nvme_nvm_dev_dma_free,
585
586 .max_phys_sect = 64,
587};
588
3dc87dd0 589int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node)
ca064085 590{
b0b4e09c
MB		 591 struct request_queue *q = ns->queue;
592 struct nvm_dev *dev;
b0b4e09c
MB		 593
594 dev = nvm_alloc_dev(node);
595 if (!dev)
596 return -ENOMEM;
597
598 dev->q = q;
599 memcpy(dev->name, disk_name, DISK_NAME_LEN);
600 dev->ops = &nvme_nvm_dev_ops;
40267efd 601 dev->private_data = ns;
b0b4e09c
MB		 602 ns->ndev = dev;
603
3dc87dd0 604 return nvm_register(dev);
ca064085
MB		 605}
606
b0b4e09c 607void nvme_nvm_unregister(struct nvme_ns *ns)
ca064085 608{
b0b4e09c 609 nvm_unregister(ns->ndev);
ca064085
MB		 610}
611
3dc87dd0
MB		 612static ssize_t nvm_dev_attr_show(struct device *dev,
613 struct device_attribute *dattr, char *page)
614{
615 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
616 struct nvm_dev *ndev = ns->ndev;
617 struct nvm_id *id;
618 struct nvm_id_group *grp;
619 struct attribute *attr;
620
621 if (!ndev)
622 return 0;
623
624 id = &ndev->identity;
625 grp = &id->groups[0];
626 attr = &dattr->attr;
627
628 if (strcmp(attr->name, "version") == 0) {
629 return scnprintf(page, PAGE_SIZE, "%u\n", id->ver_id);
630 } else if (strcmp(attr->name, "vendor_opcode") == 0) {
631 return scnprintf(page, PAGE_SIZE, "%u\n", id->vmnt);
632 } else if (strcmp(attr->name, "capabilities") == 0) {
633 return scnprintf(page, PAGE_SIZE, "%u\n", id->cap);
634 } else if (strcmp(attr->name, "device_mode") == 0) {
635 return scnprintf(page, PAGE_SIZE, "%u\n", id->dom);
636 } else if (strcmp(attr->name, "media_manager") == 0) {
637 if (!ndev->mt)
638 return scnprintf(page, PAGE_SIZE, "%s\n", "none");
639 return scnprintf(page, PAGE_SIZE, "%s\n", ndev->mt->name);
640 } else if (strcmp(attr->name, "ppa_format") == 0) {
641 return scnprintf(page, PAGE_SIZE,
642 "0x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
643 id->ppaf.ch_offset, id->ppaf.ch_len,
644 id->ppaf.lun_offset, id->ppaf.lun_len,
645 id->ppaf.pln_offset, id->ppaf.pln_len,
646 id->ppaf.blk_offset, id->ppaf.blk_len,
647 id->ppaf.pg_offset, id->ppaf.pg_len,
648 id->ppaf.sect_offset, id->ppaf.sect_len);
649 } else if (strcmp(attr->name, "media_type") == 0) { /* u8 */
650 return scnprintf(page, PAGE_SIZE, "%u\n", grp->mtype);
651 } else if (strcmp(attr->name, "flash_media_type") == 0) {
652 return scnprintf(page, PAGE_SIZE, "%u\n", grp->fmtype);
653 } else if (strcmp(attr->name, "num_channels") == 0) {
654 return scnprintf(page, PAGE_SIZE, "%u\n", grp->num_ch);
655 } else if (strcmp(attr->name, "num_luns") == 0) {
656 return scnprintf(page, PAGE_SIZE, "%u\n", grp->num_lun);
657 } else if (strcmp(attr->name, "num_planes") == 0) {
658 return scnprintf(page, PAGE_SIZE, "%u\n", grp->num_pln);
659 } else if (strcmp(attr->name, "num_blocks") == 0) { /* u16 */
660 return scnprintf(page, PAGE_SIZE, "%u\n", grp->num_blk);
661 } else if (strcmp(attr->name, "num_pages") == 0) {
662 return scnprintf(page, PAGE_SIZE, "%u\n", grp->num_pg);
663 } else if (strcmp(attr->name, "page_size") == 0) {
664 return scnprintf(page, PAGE_SIZE, "%u\n", grp->fpg_sz);
665 } else if (strcmp(attr->name, "hw_sector_size") == 0) {
666 return scnprintf(page, PAGE_SIZE, "%u\n", grp->csecs);
667 } else if (strcmp(attr->name, "oob_sector_size") == 0) {/* u32 */
668 return scnprintf(page, PAGE_SIZE, "%u\n", grp->sos);
669 } else if (strcmp(attr->name, "read_typ") == 0) {
670 return scnprintf(page, PAGE_SIZE, "%u\n", grp->trdt);
671 } else if (strcmp(attr->name, "read_max") == 0) {
672 return scnprintf(page, PAGE_SIZE, "%u\n", grp->trdm);
673 } else if (strcmp(attr->name, "prog_typ") == 0) {
674 return scnprintf(page, PAGE_SIZE, "%u\n", grp->tprt);
675 } else if (strcmp(attr->name, "prog_max") == 0) {
676 return scnprintf(page, PAGE_SIZE, "%u\n", grp->tprm);
677 } else if (strcmp(attr->name, "erase_typ") == 0) {
678 return scnprintf(page, PAGE_SIZE, "%u\n", grp->tbet);
679 } else if (strcmp(attr->name, "erase_max") == 0) {
680 return scnprintf(page, PAGE_SIZE, "%u\n", grp->tbem);
681 } else if (strcmp(attr->name, "multiplane_modes") == 0) {
682 return scnprintf(page, PAGE_SIZE, "0x%08x\n", grp->mpos);
683 } else if (strcmp(attr->name, "media_capabilities") == 0) {
684 return scnprintf(page, PAGE_SIZE, "0x%08x\n", grp->mccap);
685 } else if (strcmp(attr->name, "max_phys_secs") == 0) {
686 return scnprintf(page, PAGE_SIZE, "%u\n",
687 ndev->ops->max_phys_sect);
688 } else {
689 return scnprintf(page,
690 PAGE_SIZE,
691 "Unhandled attr(%s) in `nvm_dev_attr_show`\n",
692 attr->name);
693 }
694}
695
696#define NVM_DEV_ATTR_RO(_name) \
697 DEVICE_ATTR(_name, S_IRUGO, nvm_dev_attr_show, NULL)
698
699static NVM_DEV_ATTR_RO(version);
700static NVM_DEV_ATTR_RO(vendor_opcode);
701static NVM_DEV_ATTR_RO(capabilities);
702static NVM_DEV_ATTR_RO(device_mode);
703static NVM_DEV_ATTR_RO(ppa_format);
704static NVM_DEV_ATTR_RO(media_manager);
705
706static NVM_DEV_ATTR_RO(media_type);
707static NVM_DEV_ATTR_RO(flash_media_type);
708static NVM_DEV_ATTR_RO(num_channels);
709static NVM_DEV_ATTR_RO(num_luns);
710static NVM_DEV_ATTR_RO(num_planes);
711static NVM_DEV_ATTR_RO(num_blocks);
712static NVM_DEV_ATTR_RO(num_pages);
713static NVM_DEV_ATTR_RO(page_size);
714static NVM_DEV_ATTR_RO(hw_sector_size);
715static NVM_DEV_ATTR_RO(oob_sector_size);
716static NVM_DEV_ATTR_RO(read_typ);
717static NVM_DEV_ATTR_RO(read_max);
718static NVM_DEV_ATTR_RO(prog_typ);
719static NVM_DEV_ATTR_RO(prog_max);
720static NVM_DEV_ATTR_RO(erase_typ);
721static NVM_DEV_ATTR_RO(erase_max);
722static NVM_DEV_ATTR_RO(multiplane_modes);
723static NVM_DEV_ATTR_RO(media_capabilities);
724static NVM_DEV_ATTR_RO(max_phys_secs);
725
726static struct attribute *nvm_dev_attrs[] = {
727 &dev_attr_version.attr,
728 &dev_attr_vendor_opcode.attr,
729 &dev_attr_capabilities.attr,
730 &dev_attr_device_mode.attr,
731 &dev_attr_media_manager.attr,
732
733 &dev_attr_ppa_format.attr,
734 &dev_attr_media_type.attr,
735 &dev_attr_flash_media_type.attr,
736 &dev_attr_num_channels.attr,
737 &dev_attr_num_luns.attr,
738 &dev_attr_num_planes.attr,
739 &dev_attr_num_blocks.attr,
740 &dev_attr_num_pages.attr,
741 &dev_attr_page_size.attr,
742 &dev_attr_hw_sector_size.attr,
743 &dev_attr_oob_sector_size.attr,
744 &dev_attr_read_typ.attr,
745 &dev_attr_read_max.attr,
746 &dev_attr_prog_typ.attr,
747 &dev_attr_prog_max.attr,
748 &dev_attr_erase_typ.attr,
749 &dev_attr_erase_max.attr,
750 &dev_attr_multiplane_modes.attr,
751 &dev_attr_media_capabilities.attr,
752 &dev_attr_max_phys_secs.attr,
753 NULL,
754};
755
756static const struct attribute_group nvm_dev_attr_group = {
757 .name = "lightnvm",
758 .attrs = nvm_dev_attrs,
759};
760
761int nvme_nvm_register_sysfs(struct nvme_ns *ns)
762{
763 return sysfs_create_group(&disk_to_dev(ns->disk)->kobj,
764 &nvm_dev_attr_group);
765}
766
767void nvme_nvm_unregister_sysfs(struct nvme_ns *ns)
768{
769 sysfs_remove_group(&disk_to_dev(ns->disk)->kobj,
770 &nvm_dev_attr_group);
771}
772
09f2e716
MB		 773/* move to shared place when used in multiple places. */
774#define PCI_VENDOR_ID_CNEX 0x1d1d
775#define PCI_DEVICE_ID_CNEX_WL 0x2807
776#define PCI_DEVICE_ID_CNEX_QEMU 0x1f1f
777
ca064085
MB		 778int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id)
779{
ac02ddde
CH		 780 struct nvme_ctrl *ctrl = ns->ctrl;
781 /* XXX: this is poking into PCI structures from generic code! */
782 struct pci_dev *pdev = to_pci_dev(ctrl->dev);
ca064085
MB		 783
784 /* QEMU NVMe simulator - PCI ID + Vendor specific bit */
09f2e716
MB		 785 if (pdev->vendor == PCI_VENDOR_ID_CNEX &&
786 pdev->device == PCI_DEVICE_ID_CNEX_QEMU &&
ca064085
MB		 787 id->vs[0] == 0x1)
788 return 1;
789
790 /* CNEX Labs - PCI ID + Vendor specific bit */
09f2e716
MB		 791 if (pdev->vendor == PCI_VENDOR_ID_CNEX &&
792 pdev->device == PCI_DEVICE_ID_CNEX_WL &&
ca064085
MB		 793 id->vs[0] == 0x1)
794 return 1;
795
796 return 0;
797}
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