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f11bb3e2 CH |
1 | /* |
2 | * Copyright (c) 2011-2014, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | */ | |
13 | ||
14 | #ifndef _NVME_H | |
15 | #define _NVME_H | |
16 | ||
17 | #include <linux/nvme.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/kref.h> | |
20 | #include <linux/blk-mq.h> | |
b0b4e09c | 21 | #include <linux/lightnvm.h> |
f11bb3e2 | 22 | |
297465c8 CH |
23 | enum { |
24 | /* | |
25 | * Driver internal status code for commands that were cancelled due | |
26 | * to timeouts or controller shutdown. The value is negative so | |
27 | * that it a) doesn't overlap with the unsigned hardware error codes, | |
28 | * and b) can easily be tested for. | |
29 | */ | |
30 | NVME_SC_CANCELLED = -EINTR, | |
31 | }; | |
32 | ||
f11bb3e2 CH |
33 | extern unsigned char nvme_io_timeout; |
34 | #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) | |
35 | ||
21d34711 CH |
36 | extern unsigned char admin_timeout; |
37 | #define ADMIN_TIMEOUT (admin_timeout * HZ) | |
38 | ||
5fd4ce1b CH |
39 | extern unsigned char shutdown_timeout; |
40 | #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ) | |
41 | ||
038bd4cb SG |
42 | #define NVME_DEFAULT_KATO 5 |
43 | #define NVME_KATO_GRACE 10 | |
44 | ||
f80ec966 KB |
45 | extern unsigned int nvme_max_retries; |
46 | ||
ca064085 MB |
47 | enum { |
48 | NVME_NS_LBA = 0, | |
49 | NVME_NS_LIGHTNVM = 1, | |
50 | }; | |
51 | ||
f11bb3e2 | 52 | /* |
106198ed CH |
53 | * List of workarounds for devices that required behavior not specified in |
54 | * the standard. | |
f11bb3e2 | 55 | */ |
106198ed CH |
56 | enum nvme_quirks { |
57 | /* | |
58 | * Prefers I/O aligned to a stripe size specified in a vendor | |
59 | * specific Identify field. | |
60 | */ | |
61 | NVME_QUIRK_STRIPE_SIZE = (1 << 0), | |
540c801c KB |
62 | |
63 | /* | |
64 | * The controller doesn't handle Identify value others than 0 or 1 | |
65 | * correctly. | |
66 | */ | |
67 | NVME_QUIRK_IDENTIFY_CNS = (1 << 1), | |
08095e70 KB |
68 | |
69 | /* | |
70 | * The controller deterministically returns O's on reads to discarded | |
71 | * logical blocks. | |
72 | */ | |
73 | NVME_QUIRK_DISCARD_ZEROES = (1 << 2), | |
54adc010 GP |
74 | |
75 | /* | |
76 | * The controller needs a delay before starts checking the device | |
77 | * readiness, which is done by reading the NVME_CSTS_RDY bit. | |
78 | */ | |
79 | NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), | |
106198ed CH |
80 | }; |
81 | ||
d49187e9 CH |
82 | /* |
83 | * Common request structure for NVMe passthrough. All drivers must have | |
84 | * this structure as the first member of their request-private data. | |
85 | */ | |
86 | struct nvme_request { | |
87 | struct nvme_command *cmd; | |
88 | union nvme_result result; | |
89 | }; | |
90 | ||
91 | static inline struct nvme_request *nvme_req(struct request *req) | |
92 | { | |
93 | return blk_mq_rq_to_pdu(req); | |
94 | } | |
95 | ||
54adc010 GP |
96 | /* The below value is the specific amount of delay needed before checking |
97 | * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the | |
98 | * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was | |
99 | * found empirically. | |
100 | */ | |
101 | #define NVME_QUIRK_DELAY_AMOUNT 2000 | |
102 | ||
bb8d261e CH |
103 | enum nvme_ctrl_state { |
104 | NVME_CTRL_NEW, | |
105 | NVME_CTRL_LIVE, | |
106 | NVME_CTRL_RESETTING, | |
def61eca | 107 | NVME_CTRL_RECONNECTING, |
bb8d261e | 108 | NVME_CTRL_DELETING, |
0ff9d4e1 | 109 | NVME_CTRL_DEAD, |
bb8d261e CH |
110 | }; |
111 | ||
1c63dc66 | 112 | struct nvme_ctrl { |
bb8d261e CH |
113 | enum nvme_ctrl_state state; |
114 | spinlock_t lock; | |
1c63dc66 | 115 | const struct nvme_ctrl_ops *ops; |
f11bb3e2 | 116 | struct request_queue *admin_q; |
07bfcd09 | 117 | struct request_queue *connect_q; |
f11bb3e2 | 118 | struct device *dev; |
1673f1f0 | 119 | struct kref kref; |
f11bb3e2 | 120 | int instance; |
5bae7f73 | 121 | struct blk_mq_tag_set *tagset; |
f11bb3e2 | 122 | struct list_head namespaces; |
69d3b8ac | 123 | struct mutex namespaces_mutex; |
5bae7f73 | 124 | struct device *device; /* char device */ |
f3ca80fc | 125 | struct list_head node; |
075790eb | 126 | struct ida ns_ida; |
1c63dc66 | 127 | |
f11bb3e2 CH |
128 | char name[12]; |
129 | char serial[20]; | |
130 | char model[40]; | |
131 | char firmware_rev[8]; | |
76e3914a | 132 | u16 cntlid; |
5fd4ce1b CH |
133 | |
134 | u32 ctrl_config; | |
135 | ||
136 | u32 page_size; | |
f11bb3e2 | 137 | u32 max_hw_sectors; |
f11bb3e2 | 138 | u16 oncs; |
118472ab | 139 | u16 vid; |
6bf25d16 | 140 | atomic_t abort_limit; |
f11bb3e2 CH |
141 | u8 event_limit; |
142 | u8 vwc; | |
f3ca80fc | 143 | u32 vs; |
07bfcd09 | 144 | u32 sgls; |
038bd4cb SG |
145 | u16 kas; |
146 | unsigned int kato; | |
f3ca80fc | 147 | bool subsystem; |
106198ed | 148 | unsigned long quirks; |
5955be21 | 149 | struct work_struct scan_work; |
f866fc42 | 150 | struct work_struct async_event_work; |
038bd4cb | 151 | struct delayed_work ka_work; |
07bfcd09 CH |
152 | |
153 | /* Fabrics only */ | |
154 | u16 sqsize; | |
155 | u32 ioccsz; | |
156 | u32 iorcsz; | |
157 | u16 icdoff; | |
158 | u16 maxcmd; | |
159 | struct nvmf_ctrl_options *opts; | |
f11bb3e2 CH |
160 | }; |
161 | ||
162 | /* | |
163 | * An NVM Express namespace is equivalent to a SCSI LUN | |
164 | */ | |
165 | struct nvme_ns { | |
166 | struct list_head list; | |
167 | ||
1c63dc66 | 168 | struct nvme_ctrl *ctrl; |
f11bb3e2 CH |
169 | struct request_queue *queue; |
170 | struct gendisk *disk; | |
b0b4e09c | 171 | struct nvm_dev *ndev; |
f11bb3e2 | 172 | struct kref kref; |
075790eb | 173 | int instance; |
f11bb3e2 | 174 | |
2b9b6e86 KB |
175 | u8 eui[8]; |
176 | u8 uuid[16]; | |
177 | ||
f11bb3e2 CH |
178 | unsigned ns_id; |
179 | int lba_shift; | |
180 | u16 ms; | |
181 | bool ext; | |
182 | u8 pi_type; | |
646017a6 KB |
183 | unsigned long flags; |
184 | ||
185 | #define NVME_NS_REMOVING 0 | |
69d9a99c | 186 | #define NVME_NS_DEAD 1 |
646017a6 | 187 | |
f11bb3e2 CH |
188 | u64 mode_select_num_blocks; |
189 | u32 mode_select_block_len; | |
190 | }; | |
191 | ||
1c63dc66 | 192 | struct nvme_ctrl_ops { |
1a353d85 | 193 | const char *name; |
e439bb12 | 194 | struct module *module; |
07bfcd09 | 195 | bool is_fabrics; |
1c63dc66 | 196 | int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); |
5fd4ce1b | 197 | int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); |
7fd8930f | 198 | int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); |
f3ca80fc | 199 | int (*reset_ctrl)(struct nvme_ctrl *ctrl); |
1673f1f0 | 200 | void (*free_ctrl)(struct nvme_ctrl *ctrl); |
f866fc42 | 201 | void (*submit_async_event)(struct nvme_ctrl *ctrl, int aer_idx); |
1a353d85 ML |
202 | int (*delete_ctrl)(struct nvme_ctrl *ctrl); |
203 | const char *(*get_subsysnqn)(struct nvme_ctrl *ctrl); | |
204 | int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); | |
f11bb3e2 CH |
205 | }; |
206 | ||
1c63dc66 CH |
207 | static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl) |
208 | { | |
209 | u32 val = 0; | |
210 | ||
211 | if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val)) | |
212 | return false; | |
213 | return val & NVME_CSTS_RDY; | |
214 | } | |
215 | ||
f3ca80fc CH |
216 | static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) |
217 | { | |
218 | if (!ctrl->subsystem) | |
219 | return -ENOTTY; | |
220 | return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); | |
221 | } | |
222 | ||
f11bb3e2 CH |
223 | static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector) |
224 | { | |
225 | return (sector >> (ns->lba_shift - 9)); | |
226 | } | |
227 | ||
6904242d ML |
228 | static inline void nvme_cleanup_cmd(struct request *req) |
229 | { | |
f9d03f96 CH |
230 | if (req->rq_flags & RQF_SPECIAL_PAYLOAD) { |
231 | kfree(page_address(req->special_vec.bv_page) + | |
232 | req->special_vec.bv_offset); | |
233 | } | |
6904242d ML |
234 | } |
235 | ||
15a190f7 CH |
236 | static inline int nvme_error_status(u16 status) |
237 | { | |
238 | switch (status & 0x7ff) { | |
239 | case NVME_SC_SUCCESS: | |
240 | return 0; | |
241 | case NVME_SC_CAP_EXCEEDED: | |
242 | return -ENOSPC; | |
243 | default: | |
244 | return -EIO; | |
245 | } | |
246 | } | |
247 | ||
7688faa6 CH |
248 | static inline bool nvme_req_needs_retry(struct request *req, u16 status) |
249 | { | |
250 | return !(status & NVME_SC_DNR || blk_noretry_request(req)) && | |
f80ec966 KB |
251 | (jiffies - req->start_time) < req->timeout && |
252 | req->retries < nvme_max_retries; | |
7688faa6 CH |
253 | } |
254 | ||
c55a2fd4 | 255 | void nvme_cancel_request(struct request *req, void *data, bool reserved); |
bb8d261e CH |
256 | bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, |
257 | enum nvme_ctrl_state new_state); | |
5fd4ce1b CH |
258 | int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap); |
259 | int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap); | |
260 | int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl); | |
f3ca80fc CH |
261 | int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, |
262 | const struct nvme_ctrl_ops *ops, unsigned long quirks); | |
53029b04 | 263 | void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); |
1673f1f0 | 264 | void nvme_put_ctrl(struct nvme_ctrl *ctrl); |
7fd8930f | 265 | int nvme_init_identify(struct nvme_ctrl *ctrl); |
5bae7f73 | 266 | |
5955be21 | 267 | void nvme_queue_scan(struct nvme_ctrl *ctrl); |
5bae7f73 | 268 | void nvme_remove_namespaces(struct nvme_ctrl *ctrl); |
1673f1f0 | 269 | |
f866fc42 | 270 | #define NVME_NR_AERS 1 |
7bf58533 CH |
271 | void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, |
272 | union nvme_result *res); | |
f866fc42 CH |
273 | void nvme_queue_async_events(struct nvme_ctrl *ctrl); |
274 | ||
25646264 KB |
275 | void nvme_stop_queues(struct nvme_ctrl *ctrl); |
276 | void nvme_start_queues(struct nvme_ctrl *ctrl); | |
69d9a99c | 277 | void nvme_kill_queues(struct nvme_ctrl *ctrl); |
363c9aac | 278 | |
eb71f435 | 279 | #define NVME_QID_ANY -1 |
4160982e | 280 | struct request *nvme_alloc_request(struct request_queue *q, |
eb71f435 | 281 | struct nvme_command *cmd, unsigned int flags, int qid); |
7688faa6 | 282 | void nvme_requeue_req(struct request *req); |
8093f7ca ML |
283 | int nvme_setup_cmd(struct nvme_ns *ns, struct request *req, |
284 | struct nvme_command *cmd); | |
f11bb3e2 CH |
285 | int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
286 | void *buf, unsigned bufflen); | |
287 | int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, | |
d49187e9 | 288 | union nvme_result *result, void *buffer, unsigned bufflen, |
eb71f435 | 289 | unsigned timeout, int qid, int at_head, int flags); |
4160982e CH |
290 | int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd, |
291 | void __user *ubuffer, unsigned bufflen, u32 *result, | |
292 | unsigned timeout); | |
0b7f1f26 KB |
293 | int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd, |
294 | void __user *ubuffer, unsigned bufflen, | |
295 | void __user *meta_buffer, unsigned meta_len, u32 meta_seed, | |
f11bb3e2 | 296 | u32 *result, unsigned timeout); |
1c63dc66 CH |
297 | int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id); |
298 | int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid, | |
f11bb3e2 | 299 | struct nvme_id_ns **id); |
1c63dc66 CH |
300 | int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log); |
301 | int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid, | |
1a6fe74d | 302 | void *buffer, size_t buflen, u32 *result); |
1c63dc66 | 303 | int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11, |
1a6fe74d | 304 | void *buffer, size_t buflen, u32 *result); |
9a0be7ab | 305 | int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); |
038bd4cb SG |
306 | void nvme_start_keep_alive(struct nvme_ctrl *ctrl); |
307 | void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); | |
f11bb3e2 CH |
308 | |
309 | struct sg_io_hdr; | |
310 | ||
311 | int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr); | |
312 | int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg); | |
313 | int nvme_sg_get_version_num(int __user *ip); | |
314 | ||
c4699e70 | 315 | #ifdef CONFIG_NVM |
ca064085 | 316 | int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id); |
3dc87dd0 | 317 | int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node); |
b0b4e09c | 318 | void nvme_nvm_unregister(struct nvme_ns *ns); |
3dc87dd0 MB |
319 | int nvme_nvm_register_sysfs(struct nvme_ns *ns); |
320 | void nvme_nvm_unregister_sysfs(struct nvme_ns *ns); | |
c4699e70 | 321 | #else |
b0b4e09c | 322 | static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, |
3dc87dd0 | 323 | int node) |
c4699e70 KB |
324 | { |
325 | return 0; | |
326 | } | |
327 | ||
b0b4e09c | 328 | static inline void nvme_nvm_unregister(struct nvme_ns *ns) {}; |
3dc87dd0 MB |
329 | static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns) |
330 | { | |
331 | return 0; | |
332 | } | |
333 | static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {}; | |
c4699e70 KB |
334 | static inline int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id) |
335 | { | |
336 | return 0; | |
337 | } | |
3dc87dd0 MB |
338 | #endif /* CONFIG_NVM */ |
339 | ||
40267efd SL |
340 | static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev) |
341 | { | |
342 | return dev_to_disk(dev)->private_data; | |
343 | } | |
ca064085 | 344 | |
5bae7f73 CH |
345 | int __init nvme_core_init(void); |
346 | void nvme_core_exit(void); | |
347 | ||
f11bb3e2 | 348 | #endif /* _NVME_H */ |