[mirror_ubuntu-bionic-kernel.git] / drivers / nvme / host / nvme.h

/*
 * Copyright (c) 2011-2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef _NVME_H
#define _NVME_H

#include <linux/nvme.h>
#include <linux/pci.h>
#include <linux/kref.h>
#include <linux/blk-mq.h>

enum {
	/*
	 * Driver internal status code for commands that were cancelled due
	 * to timeouts or controller shutdown.  The value is negative so
	 * that it a) doesn't overlap with the unsigned hardware error codes,
	 * and b) can easily be tested for.
	 */
	NVME_SC_CANCELLED		= -EINTR,
};

extern unsigned char nvme_io_timeout;
#define NVME_IO_TIMEOUT	(nvme_io_timeout * HZ)

extern unsigned char admin_timeout;
#define ADMIN_TIMEOUT	(admin_timeout * HZ)

extern unsigned char shutdown_timeout;
#define SHUTDOWN_TIMEOUT	(shutdown_timeout * HZ)

enum {
	NVME_NS_LBA		= 0,
	NVME_NS_LIGHTNVM	= 1,
};

/*
 * List of workarounds for devices that required behavior not specified in
 * the standard.
 */
enum nvme_quirks {
	/*
	 * Prefers I/O aligned to a stripe size specified in a vendor
	 * specific Identify field.
	 */
	NVME_QUIRK_STRIPE_SIZE			= (1 << 0),

	/*
	 * The controller doesn't handle Identify value others than 0 or 1
	 * correctly.
	 */
	NVME_QUIRK_IDENTIFY_CNS			= (1 << 1),

	/*
	 * The controller deterministically returns O's on reads to discarded
	 * logical blocks.
	 */
	NVME_QUIRK_DISCARD_ZEROES		= (1 << 2),
};

struct nvme_ctrl {
	const struct nvme_ctrl_ops *ops;
	struct request_queue *admin_q;
	struct device *dev;
	struct kref kref;
	int instance;
	struct blk_mq_tag_set *tagset;
	struct list_head namespaces;
	struct mutex namespaces_mutex;
	struct device *device;	/* char device */
	struct list_head node;
	struct ida ns_ida;

	char name[12];
	char serial[20];
	char model[40];
	char firmware_rev[8];
	int cntlid;

	u32 ctrl_config;

	u32 page_size;
	u32 max_hw_sectors;
	u32 stripe_size;
	u16 oncs;
	u16 vid;
	atomic_t abort_limit;
	u8 event_limit;
	u8 vwc;
	u32 vs;
	bool subsystem;
	unsigned long quirks;
};

/*
 * An NVM Express namespace is equivalent to a SCSI LUN
 */
struct nvme_ns {
	struct list_head list;

	struct nvme_ctrl *ctrl;
	struct request_queue *queue;
	struct gendisk *disk;
	struct kref kref;
	int instance;

	u8 eui[8];
	u8 uuid[16];

	unsigned ns_id;
	int lba_shift;
	u16 ms;
	bool ext;
	u8 pi_type;
	int type;
	unsigned long flags;

#define NVME_NS_REMOVING 0
#define NVME_NS_DEAD     1

	u64 mode_select_num_blocks;
	u32 mode_select_block_len;
};

struct nvme_ctrl_ops {
	struct module *module;
	int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val);
	int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val);
	int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val);
	bool (*io_incapable)(struct nvme_ctrl *ctrl);
	int (*reset_ctrl)(struct nvme_ctrl *ctrl);
	void (*free_ctrl)(struct nvme_ctrl *ctrl);
};

static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
{
	u32 val = 0;

	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
		return false;
	return val & NVME_CSTS_RDY;
}

static inline bool nvme_io_incapable(struct nvme_ctrl *ctrl)
{
	u32 val = 0;

	if (ctrl->ops->io_incapable(ctrl))
		return true;
	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
		return true;
	return val & NVME_CSTS_CFS;
}

static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
{
	if (!ctrl->subsystem)
		return -ENOTTY;
	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
}

static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
{
	return (sector >> (ns->lba_shift - 9));
}

static inline unsigned nvme_map_len(struct request *rq)
{
	if (rq->cmd_flags & REQ_DISCARD)
		return sizeof(struct nvme_dsm_range);
	else
		return blk_rq_bytes(rq);
}

static inline void nvme_setup_flush(struct nvme_ns *ns,
		struct nvme_command *cmnd)
{
	memset(cmnd, 0, sizeof(*cmnd));
	cmnd->common.opcode = nvme_cmd_flush;
	cmnd->common.nsid = cpu_to_le32(ns->ns_id);
}

static inline void nvme_setup_rw(struct nvme_ns *ns, struct request *req,
		struct nvme_command *cmnd)
{
	u16 control = 0;
	u32 dsmgmt = 0;

	if (req->cmd_flags & REQ_FUA)
		control |= NVME_RW_FUA;
	if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
		control |= NVME_RW_LR;

	if (req->cmd_flags & REQ_RAHEAD)
		dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;

	memset(cmnd, 0, sizeof(*cmnd));
	cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
	cmnd->rw.command_id = req->tag;
	cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
	cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
	cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);

	if (ns->ms) {
		switch (ns->pi_type) {
		case NVME_NS_DPS_PI_TYPE3:
			control |= NVME_RW_PRINFO_PRCHK_GUARD;
			break;
		case NVME_NS_DPS_PI_TYPE1:
		case NVME_NS_DPS_PI_TYPE2:
			control |= NVME_RW_PRINFO_PRCHK_GUARD |
					NVME_RW_PRINFO_PRCHK_REF;
			cmnd->rw.reftag = cpu_to_le32(
					nvme_block_nr(ns, blk_rq_pos(req)));
			break;
		}
		if (!blk_integrity_rq(req))
			control |= NVME_RW_PRINFO_PRACT;
	}

	cmnd->rw.control = cpu_to_le16(control);
	cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
}


static inline int nvme_error_status(u16 status)
{
	switch (status & 0x7ff) {
	case NVME_SC_SUCCESS:
		return 0;
	case NVME_SC_CAP_EXCEEDED:
		return -ENOSPC;
	default:
		return -EIO;
	}
}

static inline bool nvme_req_needs_retry(struct request *req, u16 status)
{
	return !(status & NVME_SC_DNR || blk_noretry_request(req)) &&
		(jiffies - req->start_time) < req->timeout;
}

int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
		const struct nvme_ctrl_ops *ops, unsigned long quirks);
void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
void nvme_put_ctrl(struct nvme_ctrl *ctrl);
int nvme_init_identify(struct nvme_ctrl *ctrl);

void nvme_scan_namespaces(struct nvme_ctrl *ctrl);
void nvme_remove_namespaces(struct nvme_ctrl *ctrl);

void nvme_stop_queues(struct nvme_ctrl *ctrl);
void nvme_start_queues(struct nvme_ctrl *ctrl);
void nvme_kill_queues(struct nvme_ctrl *ctrl);

struct request *nvme_alloc_request(struct request_queue *q,
		struct nvme_command *cmd, unsigned int flags);
void nvme_requeue_req(struct request *req);
int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		void *buf, unsigned bufflen);
int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		struct nvme_completion *cqe, void *buffer, unsigned bufflen,
		unsigned timeout);
int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
		void __user *ubuffer, unsigned bufflen, u32 *result,
		unsigned timeout);
int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
		void __user *ubuffer, unsigned bufflen,
		void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
		u32 *result, unsigned timeout);
int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id);
int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
		struct nvme_id_ns **id);
int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log);
int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
			dma_addr_t dma_addr, u32 *result);
int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
			dma_addr_t dma_addr, u32 *result);
int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);

struct sg_io_hdr;

int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr);
int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
int nvme_sg_get_version_num(int __user *ip);

#ifdef CONFIG_NVM
int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id);
int nvme_nvm_register(struct request_queue *q, char *disk_name);
void nvme_nvm_unregister(struct request_queue *q, char *disk_name);
#else
static inline int nvme_nvm_register(struct request_queue *q, char *disk_name)
{
	return 0;
}

static inline void nvme_nvm_unregister(struct request_queue *q, char *disk_name) {};

static inline int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id)
{
	return 0;
}
#endif /* CONFIG_NVM */

int __init nvme_core_init(void);
void nvme_core_exit(void);

#endif /* _NVME_H */
Commit	Line	Data
f11bb3e2 CH	1	/*
	2	* Copyright (c) 2011-2014, Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*/
	13
	14	#ifndef _NVME_H
	15	#define _NVME_H
	16
	17	#include <linux/nvme.h>
	18	#include <linux/pci.h>
	19	#include <linux/kref.h>
	20	#include <linux/blk-mq.h>
	21
297465c8 CH	22	enum {
	23	/*
	24	* Driver internal status code for commands that were cancelled due
	25	* to timeouts or controller shutdown. The value is negative so
	26	* that it a) doesn't overlap with the unsigned hardware error codes,
	27	* and b) can easily be tested for.
	28	*/
	29	NVME_SC_CANCELLED = -EINTR,
	30	};
	31
f11bb3e2 CH	32	extern unsigned char nvme_io_timeout;
	33	#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
	34
21d34711 CH	35	extern unsigned char admin_timeout;
	36	#define ADMIN_TIMEOUT (admin_timeout * HZ)
	37
5fd4ce1b CH	38	extern unsigned char shutdown_timeout;
	39	#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
	40
ca064085 MB	41	enum {
	42	NVME_NS_LBA = 0,
	43	NVME_NS_LIGHTNVM = 1,
	44	};
	45
f11bb3e2	46	/*
106198ed CH	47	* List of workarounds for devices that required behavior not specified in
106198ed CH	48	* the standard.
f11bb3e2	49	*/
106198ed CH	50	enum nvme_quirks {
	51	/*
	52	* Prefers I/O aligned to a stripe size specified in a vendor
	53	* specific Identify field.
	54	*/
	55	NVME_QUIRK_STRIPE_SIZE = (1 << 0),
540c801c KB	56
	57	/*
	58	* The controller doesn't handle Identify value others than 0 or 1
	59	* correctly.
	60	*/
	61	NVME_QUIRK_IDENTIFY_CNS = (1 << 1),
08095e70 KB	62
	63	/*
	64	* The controller deterministically returns O's on reads to discarded
	65	* logical blocks.
	66	*/
	67	NVME_QUIRK_DISCARD_ZEROES = (1 << 2),
106198ed CH	68	};
106198ed CH	69
1c63dc66 CH	70	struct nvme_ctrl {
1c63dc66 CH	71	const struct nvme_ctrl_ops *ops;
f11bb3e2	72	struct request_queue *admin_q;
f11bb3e2	73	struct device *dev;
1673f1f0	74	struct kref kref;
f11bb3e2	75	int instance;
5bae7f73	76	struct blk_mq_tag_set *tagset;
f11bb3e2	77	struct list_head namespaces;
69d3b8ac	78	struct mutex namespaces_mutex;
5bae7f73	79	struct device device; / char device */
f3ca80fc	80	struct list_head node;
075790eb	81	struct ida ns_ida;
1c63dc66	82
f11bb3e2 CH	83	char name[12];
	84	char serial[20];
	85	char model[40];
	86	char firmware_rev[8];
931e1c22	87	int cntlid;
5fd4ce1b CH	88
	89	u32 ctrl_config;
	90
	91	u32 page_size;
f11bb3e2 CH	92	u32 max_hw_sectors;
f11bb3e2 CH	93	u32 stripe_size;
f11bb3e2	94	u16 oncs;
118472ab	95	u16 vid;
6bf25d16	96	atomic_t abort_limit;
f11bb3e2 CH	97	u8 event_limit;
f11bb3e2 CH	98	u8 vwc;
f3ca80fc CH	99	u32 vs;
f3ca80fc CH	100	bool subsystem;
106198ed	101	unsigned long quirks;
f11bb3e2 CH	102	};
	103
	104	/*
	105	* An NVM Express namespace is equivalent to a SCSI LUN
	106	*/
	107	struct nvme_ns {
	108	struct list_head list;
	109
1c63dc66	110	struct nvme_ctrl *ctrl;
f11bb3e2 CH	111	struct request_queue *queue;
	112	struct gendisk *disk;
	113	struct kref kref;
075790eb	114	int instance;
f11bb3e2	115
2b9b6e86 KB	116	u8 eui[8];
	117	u8 uuid[16];
	118
f11bb3e2 CH	119	unsigned ns_id;
	120	int lba_shift;
	121	u16 ms;
	122	bool ext;
	123	u8 pi_type;
ca064085	124	int type;
646017a6 KB	125	unsigned long flags;
	126
	127	#define NVME_NS_REMOVING 0
69d9a99c	128	#define NVME_NS_DEAD 1
646017a6	129
f11bb3e2 CH	130	u64 mode_select_num_blocks;
	131	u32 mode_select_block_len;
	132	};
	133
1c63dc66	134	struct nvme_ctrl_ops {
e439bb12	135	struct module *module;
1c63dc66	136	int (reg_read32)(struct nvme_ctrl ctrl, u32 off, u32 *val);
5fd4ce1b	137	int (reg_write32)(struct nvme_ctrl ctrl, u32 off, u32 val);
7fd8930f	138	int (reg_read64)(struct nvme_ctrl ctrl, u32 off, u64 *val);
5bae7f73	139	bool (io_incapable)(struct nvme_ctrl ctrl);
f3ca80fc	140	int (reset_ctrl)(struct nvme_ctrl ctrl);
1673f1f0	141	void (free_ctrl)(struct nvme_ctrl ctrl);
f11bb3e2 CH	142	};
f11bb3e2 CH	143
1c63dc66 CH	144	static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
	145	{
	146	u32 val = 0;
	147
	148	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
	149	return false;
	150	return val & NVME_CSTS_RDY;
	151	}
	152
5bae7f73 CH	153	static inline bool nvme_io_incapable(struct nvme_ctrl *ctrl)
	154	{
	155	u32 val = 0;
	156
	157	if (ctrl->ops->io_incapable(ctrl))
4f76d0e4	158	return true;
5bae7f73	159	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
4f76d0e4	160	return true;
5bae7f73 CH	161	return val & NVME_CSTS_CFS;
	162	}
	163
f3ca80fc CH	164	static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
	165	{
	166	if (!ctrl->subsystem)
	167	return -ENOTTY;
	168	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
	169	}
	170
f11bb3e2 CH	171	static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
	172	{
	173	return (sector >> (ns->lba_shift - 9));
	174	}
	175
58b45602 ML	176	static inline unsigned nvme_map_len(struct request *rq)
	177	{
	178	if (rq->cmd_flags & REQ_DISCARD)
	179	return sizeof(struct nvme_dsm_range);
	180	else
	181	return blk_rq_bytes(rq);
	182	}
	183
22944e99 CH	184	static inline void nvme_setup_flush(struct nvme_ns *ns,
	185	struct nvme_command *cmnd)
	186	{
	187	memset(cmnd, 0, sizeof(*cmnd));
	188	cmnd->common.opcode = nvme_cmd_flush;
	189	cmnd->common.nsid = cpu_to_le32(ns->ns_id);
	190	}
	191
	192	static inline void nvme_setup_rw(struct nvme_ns ns, struct request req,
	193	struct nvme_command *cmnd)
	194	{
	195	u16 control = 0;
	196	u32 dsmgmt = 0;
	197
	198	if (req->cmd_flags & REQ_FUA)
	199	control \|= NVME_RW_FUA;
	200	if (req->cmd_flags & (REQ_FAILFAST_DEV \| REQ_RAHEAD))
	201	control \|= NVME_RW_LR;
	202
	203	if (req->cmd_flags & REQ_RAHEAD)
	204	dsmgmt \|= NVME_RW_DSM_FREQ_PREFETCH;
	205
	206	memset(cmnd, 0, sizeof(*cmnd));
	207	cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
	208	cmnd->rw.command_id = req->tag;
	209	cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
	210	cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
	211	cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
	212
	213	if (ns->ms) {
	214	switch (ns->pi_type) {
	215	case NVME_NS_DPS_PI_TYPE3:
	216	control \|= NVME_RW_PRINFO_PRCHK_GUARD;
	217	break;
	218	case NVME_NS_DPS_PI_TYPE1:
	219	case NVME_NS_DPS_PI_TYPE2:
	220	control \|= NVME_RW_PRINFO_PRCHK_GUARD \|
	221	NVME_RW_PRINFO_PRCHK_REF;
	222	cmnd->rw.reftag = cpu_to_le32(
	223	nvme_block_nr(ns, blk_rq_pos(req)));
	224	break;
	225	}
	226	if (!blk_integrity_rq(req))
	227	control \|= NVME_RW_PRINFO_PRACT;
	228	}
	229
	230	cmnd->rw.control = cpu_to_le16(control);
	231	cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
	232	}
	233
	234
15a190f7 CH	235	static inline int nvme_error_status(u16 status)
	236	{
	237	switch (status & 0x7ff) {
	238	case NVME_SC_SUCCESS:
	239	return 0;
	240	case NVME_SC_CAP_EXCEEDED:
	241	return -ENOSPC;
	242	default:
	243	return -EIO;
	244	}
	245	}
	246
7688faa6 CH	247	static inline bool nvme_req_needs_retry(struct request *req, u16 status)
	248	{
	249	return !(status & NVME_SC_DNR \|\| blk_noretry_request(req)) &&
	250	(jiffies - req->start_time) < req->timeout;
	251	}
	252
5fd4ce1b CH	253	int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	254	int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	255	int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
f3ca80fc CH	256	int nvme_init_ctrl(struct nvme_ctrl ctrl, struct device dev,
f3ca80fc CH	257	const struct nvme_ctrl_ops *ops, unsigned long quirks);
53029b04	258	void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
1673f1f0	259	void nvme_put_ctrl(struct nvme_ctrl *ctrl);
7fd8930f	260	int nvme_init_identify(struct nvme_ctrl *ctrl);
5bae7f73 CH	261
	262	void nvme_scan_namespaces(struct nvme_ctrl *ctrl);
	263	void nvme_remove_namespaces(struct nvme_ctrl *ctrl);
1673f1f0	264
25646264 KB	265	void nvme_stop_queues(struct nvme_ctrl *ctrl);
25646264 KB	266	void nvme_start_queues(struct nvme_ctrl *ctrl);
69d9a99c	267	void nvme_kill_queues(struct nvme_ctrl *ctrl);
363c9aac	268
4160982e CH	269	struct request nvme_alloc_request(struct request_queue q,
4160982e CH	270	struct nvme_command *cmd, unsigned int flags);
7688faa6	271	void nvme_requeue_req(struct request *req);
f11bb3e2 CH	272	int nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
	273	void *buf, unsigned bufflen);
	274	int __nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
1cb3cce5 CH	275	struct nvme_completion cqe, void buffer, unsigned bufflen,
1cb3cce5 CH	276	unsigned timeout);
4160982e CH	277	int nvme_submit_user_cmd(struct request_queue q, struct nvme_command cmd,
	278	void __user ubuffer, unsigned bufflen, u32 result,
	279	unsigned timeout);
0b7f1f26 KB	280	int __nvme_submit_user_cmd(struct request_queue q, struct nvme_command cmd,
	281	void __user *ubuffer, unsigned bufflen,
	282	void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
f11bb3e2	283	u32 *result, unsigned timeout);
1c63dc66 CH	284	int nvme_identify_ctrl(struct nvme_ctrl dev, struct nvme_id_ctrl *id);
1c63dc66 CH	285	int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
f11bb3e2	286	struct nvme_id_ns **id);
1c63dc66 CH	287	int nvme_get_log_page(struct nvme_ctrl dev, struct nvme_smart_log *log);
1c63dc66 CH	288	int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
f11bb3e2	289	dma_addr_t dma_addr, u32 *result);
1c63dc66	290	int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
f11bb3e2	291	dma_addr_t dma_addr, u32 *result);
9a0be7ab	292	int nvme_set_queue_count(struct nvme_ctrl ctrl, int count);
f11bb3e2 CH	293
	294	struct sg_io_hdr;
	295
	296	int nvme_sg_io(struct nvme_ns ns, struct sg_io_hdr __user u_hdr);
	297	int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
	298	int nvme_sg_get_version_num(int __user *ip);
	299
c4699e70	300	#ifdef CONFIG_NVM
ca064085 MB	301	int nvme_nvm_ns_supported(struct nvme_ns ns, struct nvme_id_ns id);
	302	int nvme_nvm_register(struct request_queue q, char disk_name);
	303	void nvme_nvm_unregister(struct request_queue q, char disk_name);
c4699e70 KB	304	#else
	305	static inline int nvme_nvm_register(struct request_queue q, char disk_name)
	306	{
	307	return 0;
	308	}
	309
	310	static inline void nvme_nvm_unregister(struct request_queue q, char disk_name) {};
	311
	312	static inline int nvme_nvm_ns_supported(struct nvme_ns ns, struct nvme_id_ns id)
	313	{
	314	return 0;
	315	}
	316	#endif /* CONFIG_NVM */
ca064085	317
5bae7f73 CH	318	int __init nvme_core_init(void);
	319	void nvme_core_exit(void);
	320
f11bb3e2	321	#endif /* _NVME_H */