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f11bb3e2 CH |
1 | /* |
2 | * Copyright (c) 2011-2014, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | */ | |
13 | ||
14 | #ifndef _NVME_H | |
15 | #define _NVME_H | |
16 | ||
17 | #include <linux/nvme.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/kref.h> | |
20 | #include <linux/blk-mq.h> | |
21 | ||
297465c8 CH |
22 | enum { |
23 | /* | |
24 | * Driver internal status code for commands that were cancelled due | |
25 | * to timeouts or controller shutdown. The value is negative so | |
26 | * that it a) doesn't overlap with the unsigned hardware error codes, | |
27 | * and b) can easily be tested for. | |
28 | */ | |
29 | NVME_SC_CANCELLED = -EINTR, | |
30 | }; | |
31 | ||
f11bb3e2 CH |
32 | extern unsigned char nvme_io_timeout; |
33 | #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) | |
34 | ||
21d34711 CH |
35 | extern unsigned char admin_timeout; |
36 | #define ADMIN_TIMEOUT (admin_timeout * HZ) | |
37 | ||
5fd4ce1b CH |
38 | extern unsigned char shutdown_timeout; |
39 | #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ) | |
40 | ||
ca064085 MB |
41 | enum { |
42 | NVME_NS_LBA = 0, | |
43 | NVME_NS_LIGHTNVM = 1, | |
44 | }; | |
45 | ||
f11bb3e2 | 46 | /* |
106198ed CH |
47 | * List of workarounds for devices that required behavior not specified in |
48 | * the standard. | |
f11bb3e2 | 49 | */ |
106198ed CH |
50 | enum nvme_quirks { |
51 | /* | |
52 | * Prefers I/O aligned to a stripe size specified in a vendor | |
53 | * specific Identify field. | |
54 | */ | |
55 | NVME_QUIRK_STRIPE_SIZE = (1 << 0), | |
540c801c KB |
56 | |
57 | /* | |
58 | * The controller doesn't handle Identify value others than 0 or 1 | |
59 | * correctly. | |
60 | */ | |
61 | NVME_QUIRK_IDENTIFY_CNS = (1 << 1), | |
106198ed CH |
62 | }; |
63 | ||
1c63dc66 CH |
64 | struct nvme_ctrl { |
65 | const struct nvme_ctrl_ops *ops; | |
f11bb3e2 | 66 | struct request_queue *admin_q; |
f11bb3e2 | 67 | struct device *dev; |
1673f1f0 | 68 | struct kref kref; |
f11bb3e2 | 69 | int instance; |
5bae7f73 | 70 | struct blk_mq_tag_set *tagset; |
f11bb3e2 | 71 | struct list_head namespaces; |
69d3b8ac | 72 | struct mutex namespaces_mutex; |
5bae7f73 | 73 | struct device *device; /* char device */ |
f3ca80fc | 74 | struct list_head node; |
075790eb | 75 | struct ida ns_ida; |
1c63dc66 | 76 | |
f11bb3e2 CH |
77 | char name[12]; |
78 | char serial[20]; | |
79 | char model[40]; | |
80 | char firmware_rev[8]; | |
5fd4ce1b CH |
81 | |
82 | u32 ctrl_config; | |
83 | ||
84 | u32 page_size; | |
f11bb3e2 CH |
85 | u32 max_hw_sectors; |
86 | u32 stripe_size; | |
f11bb3e2 | 87 | u16 oncs; |
6bf25d16 | 88 | atomic_t abort_limit; |
f11bb3e2 CH |
89 | u8 event_limit; |
90 | u8 vwc; | |
f3ca80fc CH |
91 | u32 vs; |
92 | bool subsystem; | |
106198ed | 93 | unsigned long quirks; |
f11bb3e2 CH |
94 | }; |
95 | ||
96 | /* | |
97 | * An NVM Express namespace is equivalent to a SCSI LUN | |
98 | */ | |
99 | struct nvme_ns { | |
100 | struct list_head list; | |
101 | ||
1c63dc66 | 102 | struct nvme_ctrl *ctrl; |
f11bb3e2 CH |
103 | struct request_queue *queue; |
104 | struct gendisk *disk; | |
105 | struct kref kref; | |
075790eb | 106 | int instance; |
f11bb3e2 | 107 | |
2b9b6e86 KB |
108 | u8 eui[8]; |
109 | u8 uuid[16]; | |
110 | ||
f11bb3e2 CH |
111 | unsigned ns_id; |
112 | int lba_shift; | |
113 | u16 ms; | |
114 | bool ext; | |
115 | u8 pi_type; | |
ca064085 | 116 | int type; |
f11bb3e2 CH |
117 | u64 mode_select_num_blocks; |
118 | u32 mode_select_block_len; | |
119 | }; | |
120 | ||
1c63dc66 CH |
121 | struct nvme_ctrl_ops { |
122 | int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); | |
5fd4ce1b | 123 | int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); |
7fd8930f | 124 | int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); |
5bae7f73 | 125 | bool (*io_incapable)(struct nvme_ctrl *ctrl); |
f3ca80fc | 126 | int (*reset_ctrl)(struct nvme_ctrl *ctrl); |
1673f1f0 | 127 | void (*free_ctrl)(struct nvme_ctrl *ctrl); |
f11bb3e2 CH |
128 | }; |
129 | ||
1c63dc66 CH |
130 | static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl) |
131 | { | |
132 | u32 val = 0; | |
133 | ||
134 | if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val)) | |
135 | return false; | |
136 | return val & NVME_CSTS_RDY; | |
137 | } | |
138 | ||
5bae7f73 CH |
139 | static inline bool nvme_io_incapable(struct nvme_ctrl *ctrl) |
140 | { | |
141 | u32 val = 0; | |
142 | ||
143 | if (ctrl->ops->io_incapable(ctrl)) | |
4f76d0e4 | 144 | return true; |
5bae7f73 | 145 | if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val)) |
4f76d0e4 | 146 | return true; |
5bae7f73 CH |
147 | return val & NVME_CSTS_CFS; |
148 | } | |
149 | ||
f3ca80fc CH |
150 | static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) |
151 | { | |
152 | if (!ctrl->subsystem) | |
153 | return -ENOTTY; | |
154 | return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); | |
155 | } | |
156 | ||
f11bb3e2 CH |
157 | static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector) |
158 | { | |
159 | return (sector >> (ns->lba_shift - 9)); | |
160 | } | |
161 | ||
22944e99 CH |
162 | static inline void nvme_setup_flush(struct nvme_ns *ns, |
163 | struct nvme_command *cmnd) | |
164 | { | |
165 | memset(cmnd, 0, sizeof(*cmnd)); | |
166 | cmnd->common.opcode = nvme_cmd_flush; | |
167 | cmnd->common.nsid = cpu_to_le32(ns->ns_id); | |
168 | } | |
169 | ||
170 | static inline void nvme_setup_rw(struct nvme_ns *ns, struct request *req, | |
171 | struct nvme_command *cmnd) | |
172 | { | |
173 | u16 control = 0; | |
174 | u32 dsmgmt = 0; | |
175 | ||
176 | if (req->cmd_flags & REQ_FUA) | |
177 | control |= NVME_RW_FUA; | |
178 | if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD)) | |
179 | control |= NVME_RW_LR; | |
180 | ||
181 | if (req->cmd_flags & REQ_RAHEAD) | |
182 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; | |
183 | ||
184 | memset(cmnd, 0, sizeof(*cmnd)); | |
185 | cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read); | |
186 | cmnd->rw.command_id = req->tag; | |
187 | cmnd->rw.nsid = cpu_to_le32(ns->ns_id); | |
188 | cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
189 | cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1); | |
190 | ||
191 | if (ns->ms) { | |
192 | switch (ns->pi_type) { | |
193 | case NVME_NS_DPS_PI_TYPE3: | |
194 | control |= NVME_RW_PRINFO_PRCHK_GUARD; | |
195 | break; | |
196 | case NVME_NS_DPS_PI_TYPE1: | |
197 | case NVME_NS_DPS_PI_TYPE2: | |
198 | control |= NVME_RW_PRINFO_PRCHK_GUARD | | |
199 | NVME_RW_PRINFO_PRCHK_REF; | |
200 | cmnd->rw.reftag = cpu_to_le32( | |
201 | nvme_block_nr(ns, blk_rq_pos(req))); | |
202 | break; | |
203 | } | |
204 | if (!blk_integrity_rq(req)) | |
205 | control |= NVME_RW_PRINFO_PRACT; | |
206 | } | |
207 | ||
208 | cmnd->rw.control = cpu_to_le16(control); | |
209 | cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); | |
210 | } | |
211 | ||
212 | ||
15a190f7 CH |
213 | static inline int nvme_error_status(u16 status) |
214 | { | |
215 | switch (status & 0x7ff) { | |
216 | case NVME_SC_SUCCESS: | |
217 | return 0; | |
218 | case NVME_SC_CAP_EXCEEDED: | |
219 | return -ENOSPC; | |
220 | default: | |
221 | return -EIO; | |
222 | } | |
223 | } | |
224 | ||
7688faa6 CH |
225 | static inline bool nvme_req_needs_retry(struct request *req, u16 status) |
226 | { | |
227 | return !(status & NVME_SC_DNR || blk_noretry_request(req)) && | |
228 | (jiffies - req->start_time) < req->timeout; | |
229 | } | |
230 | ||
5fd4ce1b CH |
231 | int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap); |
232 | int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap); | |
233 | int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl); | |
f3ca80fc CH |
234 | int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, |
235 | const struct nvme_ctrl_ops *ops, unsigned long quirks); | |
53029b04 | 236 | void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); |
1673f1f0 | 237 | void nvme_put_ctrl(struct nvme_ctrl *ctrl); |
7fd8930f | 238 | int nvme_init_identify(struct nvme_ctrl *ctrl); |
5bae7f73 CH |
239 | |
240 | void nvme_scan_namespaces(struct nvme_ctrl *ctrl); | |
241 | void nvme_remove_namespaces(struct nvme_ctrl *ctrl); | |
1673f1f0 | 242 | |
25646264 KB |
243 | void nvme_stop_queues(struct nvme_ctrl *ctrl); |
244 | void nvme_start_queues(struct nvme_ctrl *ctrl); | |
363c9aac | 245 | |
4160982e CH |
246 | struct request *nvme_alloc_request(struct request_queue *q, |
247 | struct nvme_command *cmd, unsigned int flags); | |
7688faa6 | 248 | void nvme_requeue_req(struct request *req); |
f11bb3e2 CH |
249 | int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
250 | void *buf, unsigned bufflen); | |
251 | int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, | |
4160982e CH |
252 | void *buffer, unsigned bufflen, u32 *result, unsigned timeout); |
253 | int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd, | |
254 | void __user *ubuffer, unsigned bufflen, u32 *result, | |
255 | unsigned timeout); | |
0b7f1f26 KB |
256 | int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd, |
257 | void __user *ubuffer, unsigned bufflen, | |
258 | void __user *meta_buffer, unsigned meta_len, u32 meta_seed, | |
f11bb3e2 | 259 | u32 *result, unsigned timeout); |
1c63dc66 CH |
260 | int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id); |
261 | int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid, | |
f11bb3e2 | 262 | struct nvme_id_ns **id); |
1c63dc66 CH |
263 | int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log); |
264 | int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid, | |
f11bb3e2 | 265 | dma_addr_t dma_addr, u32 *result); |
1c63dc66 | 266 | int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11, |
f11bb3e2 | 267 | dma_addr_t dma_addr, u32 *result); |
9a0be7ab | 268 | int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); |
f11bb3e2 | 269 | |
1673f1f0 | 270 | extern spinlock_t dev_list_lock; |
f11bb3e2 CH |
271 | |
272 | struct sg_io_hdr; | |
273 | ||
274 | int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr); | |
275 | int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg); | |
276 | int nvme_sg_get_version_num(int __user *ip); | |
277 | ||
c4699e70 | 278 | #ifdef CONFIG_NVM |
ca064085 MB |
279 | int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id); |
280 | int nvme_nvm_register(struct request_queue *q, char *disk_name); | |
281 | void nvme_nvm_unregister(struct request_queue *q, char *disk_name); | |
c4699e70 KB |
282 | #else |
283 | static inline int nvme_nvm_register(struct request_queue *q, char *disk_name) | |
284 | { | |
285 | return 0; | |
286 | } | |
287 | ||
288 | static inline void nvme_nvm_unregister(struct request_queue *q, char *disk_name) {}; | |
289 | ||
290 | static inline int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id) | |
291 | { | |
292 | return 0; | |
293 | } | |
294 | #endif /* CONFIG_NVM */ | |
ca064085 | 295 | |
5bae7f73 CH |
296 | int __init nvme_core_init(void); |
297 | void nvme_core_exit(void); | |
298 | ||
f11bb3e2 | 299 | #endif /* _NVME_H */ |