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f11bb3e2 CH |
1 | /* |
2 | * Copyright (c) 2011-2014, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | */ | |
13 | ||
14 | #ifndef _NVME_H | |
15 | #define _NVME_H | |
16 | ||
17 | #include <linux/nvme.h> | |
a6a5149b | 18 | #include <linux/cdev.h> |
f11bb3e2 CH |
19 | #include <linux/pci.h> |
20 | #include <linux/kref.h> | |
21 | #include <linux/blk-mq.h> | |
b0b4e09c | 22 | #include <linux/lightnvm.h> |
a98e58e5 | 23 | #include <linux/sed-opal.h> |
f11bb3e2 | 24 | |
8ae4e447 | 25 | extern unsigned int nvme_io_timeout; |
f11bb3e2 CH |
26 | #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) |
27 | ||
8ae4e447 | 28 | extern unsigned int admin_timeout; |
21d34711 CH |
29 | #define ADMIN_TIMEOUT (admin_timeout * HZ) |
30 | ||
038bd4cb SG |
31 | #define NVME_DEFAULT_KATO 5 |
32 | #define NVME_KATO_GRACE 10 | |
33 | ||
9a6327d2 SG |
34 | extern struct workqueue_struct *nvme_wq; |
35 | ||
ca064085 MB |
36 | enum { |
37 | NVME_NS_LBA = 0, | |
38 | NVME_NS_LIGHTNVM = 1, | |
39 | }; | |
40 | ||
f11bb3e2 | 41 | /* |
106198ed CH |
42 | * List of workarounds for devices that required behavior not specified in |
43 | * the standard. | |
f11bb3e2 | 44 | */ |
106198ed CH |
45 | enum nvme_quirks { |
46 | /* | |
47 | * Prefers I/O aligned to a stripe size specified in a vendor | |
48 | * specific Identify field. | |
49 | */ | |
50 | NVME_QUIRK_STRIPE_SIZE = (1 << 0), | |
540c801c KB |
51 | |
52 | /* | |
53 | * The controller doesn't handle Identify value others than 0 or 1 | |
54 | * correctly. | |
55 | */ | |
56 | NVME_QUIRK_IDENTIFY_CNS = (1 << 1), | |
08095e70 KB |
57 | |
58 | /* | |
e850fd16 CH |
59 | * The controller deterministically returns O's on reads to |
60 | * logical blocks that deallocate was called on. | |
08095e70 | 61 | */ |
e850fd16 | 62 | NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2), |
54adc010 GP |
63 | |
64 | /* | |
65 | * The controller needs a delay before starts checking the device | |
66 | * readiness, which is done by reading the NVME_CSTS_RDY bit. | |
67 | */ | |
68 | NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), | |
c5552fde AL |
69 | |
70 | /* | |
71 | * APST should not be used. | |
72 | */ | |
73 | NVME_QUIRK_NO_APST = (1 << 4), | |
ff5350a8 AL |
74 | |
75 | /* | |
76 | * The deepest sleep state should not be used. | |
77 | */ | |
78 | NVME_QUIRK_NO_DEEPEST_PS = (1 << 5), | |
608cc4b1 CH |
79 | |
80 | /* | |
81 | * Supports the LighNVM command set if indicated in vs[1]. | |
82 | */ | |
83 | NVME_QUIRK_LIGHTNVM = (1 << 6), | |
106198ed CH |
84 | }; |
85 | ||
d49187e9 CH |
86 | /* |
87 | * Common request structure for NVMe passthrough. All drivers must have | |
88 | * this structure as the first member of their request-private data. | |
89 | */ | |
90 | struct nvme_request { | |
91 | struct nvme_command *cmd; | |
92 | union nvme_result result; | |
44e44b29 | 93 | u8 retries; |
27fa9bc5 CH |
94 | u8 flags; |
95 | u16 status; | |
96 | }; | |
97 | ||
98 | enum { | |
99 | NVME_REQ_CANCELLED = (1 << 0), | |
d49187e9 CH |
100 | }; |
101 | ||
102 | static inline struct nvme_request *nvme_req(struct request *req) | |
103 | { | |
104 | return blk_mq_rq_to_pdu(req); | |
105 | } | |
106 | ||
54adc010 GP |
107 | /* The below value is the specific amount of delay needed before checking |
108 | * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the | |
109 | * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was | |
110 | * found empirically. | |
111 | */ | |
112 | #define NVME_QUIRK_DELAY_AMOUNT 2000 | |
113 | ||
bb8d261e CH |
114 | enum nvme_ctrl_state { |
115 | NVME_CTRL_NEW, | |
116 | NVME_CTRL_LIVE, | |
117 | NVME_CTRL_RESETTING, | |
def61eca | 118 | NVME_CTRL_RECONNECTING, |
bb8d261e | 119 | NVME_CTRL_DELETING, |
0ff9d4e1 | 120 | NVME_CTRL_DEAD, |
bb8d261e CH |
121 | }; |
122 | ||
1c63dc66 | 123 | struct nvme_ctrl { |
bb8d261e | 124 | enum nvme_ctrl_state state; |
bd4da3ab | 125 | bool identified; |
bb8d261e | 126 | spinlock_t lock; |
1c63dc66 | 127 | const struct nvme_ctrl_ops *ops; |
f11bb3e2 | 128 | struct request_queue *admin_q; |
07bfcd09 | 129 | struct request_queue *connect_q; |
f11bb3e2 | 130 | struct device *dev; |
f11bb3e2 | 131 | int instance; |
5bae7f73 | 132 | struct blk_mq_tag_set *tagset; |
34b6c231 | 133 | struct blk_mq_tag_set *admin_tagset; |
f11bb3e2 | 134 | struct list_head namespaces; |
69d3b8ac | 135 | struct mutex namespaces_mutex; |
d22524a4 | 136 | struct device ctrl_device; |
5bae7f73 | 137 | struct device *device; /* char device */ |
a6a5149b | 138 | struct cdev cdev; |
075790eb | 139 | struct ida ns_ida; |
d86c4d8e | 140 | struct work_struct reset_work; |
c5017e85 | 141 | struct work_struct delete_work; |
1c63dc66 | 142 | |
4f1244c8 | 143 | struct opal_dev *opal_dev; |
a98e58e5 | 144 | |
f11bb3e2 CH |
145 | char name[12]; |
146 | char serial[20]; | |
147 | char model[40]; | |
148 | char firmware_rev[8]; | |
180de007 | 149 | char subnqn[NVMF_NQN_SIZE]; |
76e3914a | 150 | u16 cntlid; |
5fd4ce1b CH |
151 | |
152 | u32 ctrl_config; | |
b6dccf7f | 153 | u16 mtfa; |
d858e5f0 | 154 | u32 queue_count; |
5fd4ce1b | 155 | |
20d0dfe6 | 156 | u64 cap; |
5fd4ce1b | 157 | u32 page_size; |
f11bb3e2 | 158 | u32 max_hw_sectors; |
f11bb3e2 | 159 | u16 oncs; |
118472ab | 160 | u16 vid; |
8a9ae523 | 161 | u16 oacs; |
f5d11840 JA |
162 | u16 nssa; |
163 | u16 nr_streams; | |
6bf25d16 | 164 | atomic_t abort_limit; |
f11bb3e2 CH |
165 | u8 event_limit; |
166 | u8 vwc; | |
f3ca80fc | 167 | u32 vs; |
07bfcd09 | 168 | u32 sgls; |
038bd4cb | 169 | u16 kas; |
c5552fde AL |
170 | u8 npss; |
171 | u8 apsta; | |
07fbd32a | 172 | unsigned int shutdown_timeout; |
038bd4cb | 173 | unsigned int kato; |
f3ca80fc | 174 | bool subsystem; |
106198ed | 175 | unsigned long quirks; |
c5552fde | 176 | struct nvme_id_power_state psd[32]; |
84fef62d | 177 | struct nvme_effects_log *effects; |
5955be21 | 178 | struct work_struct scan_work; |
f866fc42 | 179 | struct work_struct async_event_work; |
038bd4cb | 180 | struct delayed_work ka_work; |
b6dccf7f | 181 | struct work_struct fw_act_work; |
07bfcd09 | 182 | |
c5552fde AL |
183 | /* Power saving configuration */ |
184 | u64 ps_max_latency_us; | |
76a5af84 | 185 | bool apst_enabled; |
c5552fde | 186 | |
044a9df1 | 187 | /* PCIe only: */ |
fe6d53c9 CH |
188 | u32 hmpre; |
189 | u32 hmmin; | |
044a9df1 CH |
190 | u32 hmminds; |
191 | u16 hmmaxd; | |
fe6d53c9 | 192 | |
07bfcd09 CH |
193 | /* Fabrics only */ |
194 | u16 sqsize; | |
195 | u32 ioccsz; | |
196 | u32 iorcsz; | |
197 | u16 icdoff; | |
198 | u16 maxcmd; | |
fdf9dfa8 | 199 | int nr_reconnects; |
07bfcd09 | 200 | struct nvmf_ctrl_options *opts; |
f11bb3e2 CH |
201 | }; |
202 | ||
f11bb3e2 CH |
203 | struct nvme_ns { |
204 | struct list_head list; | |
205 | ||
1c63dc66 | 206 | struct nvme_ctrl *ctrl; |
f11bb3e2 CH |
207 | struct request_queue *queue; |
208 | struct gendisk *disk; | |
b0b4e09c | 209 | struct nvm_dev *ndev; |
f11bb3e2 | 210 | struct kref kref; |
075790eb | 211 | int instance; |
f11bb3e2 | 212 | |
2b9b6e86 | 213 | u8 eui[8]; |
90985b84 | 214 | u8 nguid[16]; |
3b22ba26 | 215 | uuid_t uuid; |
2b9b6e86 | 216 | |
f11bb3e2 CH |
217 | unsigned ns_id; |
218 | int lba_shift; | |
219 | u16 ms; | |
f5d11840 JA |
220 | u16 sgs; |
221 | u32 sws; | |
f11bb3e2 CH |
222 | bool ext; |
223 | u8 pi_type; | |
646017a6 | 224 | unsigned long flags; |
646017a6 | 225 | #define NVME_NS_REMOVING 0 |
69d9a99c | 226 | #define NVME_NS_DEAD 1 |
57eeaf8e | 227 | u16 noiob; |
f11bb3e2 CH |
228 | }; |
229 | ||
1c63dc66 | 230 | struct nvme_ctrl_ops { |
1a353d85 | 231 | const char *name; |
e439bb12 | 232 | struct module *module; |
d3d5b87d CH |
233 | unsigned int flags; |
234 | #define NVME_F_FABRICS (1 << 0) | |
c81bfba9 | 235 | #define NVME_F_METADATA_SUPPORTED (1 << 1) |
1c63dc66 | 236 | int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); |
5fd4ce1b | 237 | int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); |
7fd8930f | 238 | int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); |
1673f1f0 | 239 | void (*free_ctrl)(struct nvme_ctrl *ctrl); |
f866fc42 | 240 | void (*submit_async_event)(struct nvme_ctrl *ctrl, int aer_idx); |
c5017e85 | 241 | void (*delete_ctrl)(struct nvme_ctrl *ctrl); |
1a353d85 | 242 | int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); |
31b84460 | 243 | int (*reinit_request)(void *data, struct request *rq); |
f11bb3e2 CH |
244 | }; |
245 | ||
1c63dc66 CH |
246 | static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl) |
247 | { | |
248 | u32 val = 0; | |
249 | ||
250 | if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val)) | |
251 | return false; | |
252 | return val & NVME_CSTS_RDY; | |
253 | } | |
254 | ||
f3ca80fc CH |
255 | static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) |
256 | { | |
257 | if (!ctrl->subsystem) | |
258 | return -ENOTTY; | |
259 | return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); | |
260 | } | |
261 | ||
f11bb3e2 CH |
262 | static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector) |
263 | { | |
264 | return (sector >> (ns->lba_shift - 9)); | |
265 | } | |
266 | ||
6904242d ML |
267 | static inline void nvme_cleanup_cmd(struct request *req) |
268 | { | |
f9d03f96 CH |
269 | if (req->rq_flags & RQF_SPECIAL_PAYLOAD) { |
270 | kfree(page_address(req->special_vec.bv_page) + | |
271 | req->special_vec.bv_offset); | |
272 | } | |
6904242d ML |
273 | } |
274 | ||
27fa9bc5 CH |
275 | static inline void nvme_end_request(struct request *req, __le16 status, |
276 | union nvme_result result) | |
15a190f7 | 277 | { |
27fa9bc5 | 278 | struct nvme_request *rq = nvme_req(req); |
15a190f7 | 279 | |
27fa9bc5 CH |
280 | rq->status = le16_to_cpu(status) >> 1; |
281 | rq->result = result; | |
08e0029a | 282 | blk_mq_complete_request(req); |
7688faa6 CH |
283 | } |
284 | ||
d22524a4 CH |
285 | static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl) |
286 | { | |
287 | get_device(ctrl->device); | |
288 | } | |
289 | ||
290 | static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl) | |
291 | { | |
292 | put_device(ctrl->device); | |
293 | } | |
294 | ||
77f02a7a | 295 | void nvme_complete_rq(struct request *req); |
c55a2fd4 | 296 | void nvme_cancel_request(struct request *req, void *data, bool reserved); |
bb8d261e CH |
297 | bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, |
298 | enum nvme_ctrl_state new_state); | |
5fd4ce1b CH |
299 | int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap); |
300 | int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap); | |
301 | int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl); | |
f3ca80fc CH |
302 | int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, |
303 | const struct nvme_ctrl_ops *ops, unsigned long quirks); | |
53029b04 | 304 | void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); |
d09f2b45 SG |
305 | void nvme_start_ctrl(struct nvme_ctrl *ctrl); |
306 | void nvme_stop_ctrl(struct nvme_ctrl *ctrl); | |
1673f1f0 | 307 | void nvme_put_ctrl(struct nvme_ctrl *ctrl); |
7fd8930f | 308 | int nvme_init_identify(struct nvme_ctrl *ctrl); |
5bae7f73 | 309 | |
5955be21 | 310 | void nvme_queue_scan(struct nvme_ctrl *ctrl); |
5bae7f73 | 311 | void nvme_remove_namespaces(struct nvme_ctrl *ctrl); |
1673f1f0 | 312 | |
4f1244c8 CH |
313 | int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len, |
314 | bool send); | |
a98e58e5 | 315 | |
7bf58533 CH |
316 | void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, |
317 | union nvme_result *res); | |
f866fc42 CH |
318 | void nvme_queue_async_events(struct nvme_ctrl *ctrl); |
319 | ||
25646264 KB |
320 | void nvme_stop_queues(struct nvme_ctrl *ctrl); |
321 | void nvme_start_queues(struct nvme_ctrl *ctrl); | |
69d9a99c | 322 | void nvme_kill_queues(struct nvme_ctrl *ctrl); |
302ad8cc KB |
323 | void nvme_unfreeze(struct nvme_ctrl *ctrl); |
324 | void nvme_wait_freeze(struct nvme_ctrl *ctrl); | |
325 | void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout); | |
326 | void nvme_start_freeze(struct nvme_ctrl *ctrl); | |
31b84460 | 327 | int nvme_reinit_tagset(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set); |
363c9aac | 328 | |
eb71f435 | 329 | #define NVME_QID_ANY -1 |
4160982e | 330 | struct request *nvme_alloc_request(struct request_queue *q, |
eb71f435 | 331 | struct nvme_command *cmd, unsigned int flags, int qid); |
fc17b653 | 332 | blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req, |
8093f7ca | 333 | struct nvme_command *cmd); |
f11bb3e2 CH |
334 | int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
335 | void *buf, unsigned bufflen); | |
336 | int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, | |
d49187e9 | 337 | union nvme_result *result, void *buffer, unsigned bufflen, |
eb71f435 | 338 | unsigned timeout, int qid, int at_head, int flags); |
9a0be7ab | 339 | int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); |
038bd4cb SG |
340 | void nvme_start_keep_alive(struct nvme_ctrl *ctrl); |
341 | void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); | |
d86c4d8e | 342 | int nvme_reset_ctrl(struct nvme_ctrl *ctrl); |
c5017e85 CH |
343 | int nvme_delete_ctrl(struct nvme_ctrl *ctrl); |
344 | int nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl); | |
f11bb3e2 | 345 | |
c4699e70 | 346 | #ifdef CONFIG_NVM |
3dc87dd0 | 347 | int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node); |
b0b4e09c | 348 | void nvme_nvm_unregister(struct nvme_ns *ns); |
3dc87dd0 MB |
349 | int nvme_nvm_register_sysfs(struct nvme_ns *ns); |
350 | void nvme_nvm_unregister_sysfs(struct nvme_ns *ns); | |
84d4add7 | 351 | int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg); |
c4699e70 | 352 | #else |
b0b4e09c | 353 | static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, |
3dc87dd0 | 354 | int node) |
c4699e70 KB |
355 | { |
356 | return 0; | |
357 | } | |
358 | ||
b0b4e09c | 359 | static inline void nvme_nvm_unregister(struct nvme_ns *ns) {}; |
3dc87dd0 MB |
360 | static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns) |
361 | { | |
362 | return 0; | |
363 | } | |
364 | static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {}; | |
84d4add7 MB |
365 | static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, |
366 | unsigned long arg) | |
367 | { | |
368 | return -ENOTTY; | |
369 | } | |
3dc87dd0 MB |
370 | #endif /* CONFIG_NVM */ |
371 | ||
40267efd SL |
372 | static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev) |
373 | { | |
374 | return dev_to_disk(dev)->private_data; | |
375 | } | |
ca064085 | 376 | |
5bae7f73 CH |
377 | int __init nvme_core_init(void); |
378 | void nvme_core_exit(void); | |
379 | ||
f11bb3e2 | 380 | #endif /* _NVME_H */ |