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f11bb3e2 CH |
1 | /* |
2 | * Copyright (c) 2011-2014, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | */ | |
13 | ||
14 | #ifndef _NVME_H | |
15 | #define _NVME_H | |
16 | ||
17 | #include <linux/nvme.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/kref.h> | |
20 | #include <linux/blk-mq.h> | |
21 | ||
22 | extern unsigned char nvme_io_timeout; | |
23 | #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) | |
24 | ||
21d34711 CH |
25 | extern unsigned char admin_timeout; |
26 | #define ADMIN_TIMEOUT (admin_timeout * HZ) | |
27 | ||
ca064085 MB |
28 | enum { |
29 | NVME_NS_LBA = 0, | |
30 | NVME_NS_LIGHTNVM = 1, | |
31 | }; | |
32 | ||
1c63dc66 CH |
33 | struct nvme_ctrl { |
34 | const struct nvme_ctrl_ops *ops; | |
f11bb3e2 | 35 | struct request_queue *admin_q; |
f11bb3e2 | 36 | struct device *dev; |
f11bb3e2 | 37 | int instance; |
1c63dc66 | 38 | |
f11bb3e2 CH |
39 | char name[12]; |
40 | char serial[20]; | |
41 | char model[40]; | |
42 | char firmware_rev[8]; | |
f11bb3e2 CH |
43 | u16 oncs; |
44 | u16 abort_limit; | |
45 | u8 event_limit; | |
46 | u8 vwc; | |
47 | }; | |
48 | ||
49 | /* | |
50 | * An NVM Express namespace is equivalent to a SCSI LUN | |
51 | */ | |
52 | struct nvme_ns { | |
53 | struct list_head list; | |
54 | ||
1c63dc66 | 55 | struct nvme_ctrl *ctrl; |
f11bb3e2 CH |
56 | struct request_queue *queue; |
57 | struct gendisk *disk; | |
58 | struct kref kref; | |
59 | ||
60 | unsigned ns_id; | |
61 | int lba_shift; | |
62 | u16 ms; | |
63 | bool ext; | |
64 | u8 pi_type; | |
ca064085 | 65 | int type; |
f11bb3e2 CH |
66 | u64 mode_select_num_blocks; |
67 | u32 mode_select_block_len; | |
68 | }; | |
69 | ||
1c63dc66 CH |
70 | struct nvme_ctrl_ops { |
71 | int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); | |
72 | }; | |
73 | ||
74 | static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl) | |
75 | { | |
76 | u32 val = 0; | |
77 | ||
78 | if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val)) | |
79 | return false; | |
80 | return val & NVME_CSTS_RDY; | |
81 | } | |
82 | ||
f11bb3e2 CH |
83 | static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector) |
84 | { | |
85 | return (sector >> (ns->lba_shift - 9)); | |
86 | } | |
87 | ||
22944e99 CH |
88 | static inline void nvme_setup_flush(struct nvme_ns *ns, |
89 | struct nvme_command *cmnd) | |
90 | { | |
91 | memset(cmnd, 0, sizeof(*cmnd)); | |
92 | cmnd->common.opcode = nvme_cmd_flush; | |
93 | cmnd->common.nsid = cpu_to_le32(ns->ns_id); | |
94 | } | |
95 | ||
96 | static inline void nvme_setup_rw(struct nvme_ns *ns, struct request *req, | |
97 | struct nvme_command *cmnd) | |
98 | { | |
99 | u16 control = 0; | |
100 | u32 dsmgmt = 0; | |
101 | ||
102 | if (req->cmd_flags & REQ_FUA) | |
103 | control |= NVME_RW_FUA; | |
104 | if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD)) | |
105 | control |= NVME_RW_LR; | |
106 | ||
107 | if (req->cmd_flags & REQ_RAHEAD) | |
108 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; | |
109 | ||
110 | memset(cmnd, 0, sizeof(*cmnd)); | |
111 | cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read); | |
112 | cmnd->rw.command_id = req->tag; | |
113 | cmnd->rw.nsid = cpu_to_le32(ns->ns_id); | |
114 | cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
115 | cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1); | |
116 | ||
117 | if (ns->ms) { | |
118 | switch (ns->pi_type) { | |
119 | case NVME_NS_DPS_PI_TYPE3: | |
120 | control |= NVME_RW_PRINFO_PRCHK_GUARD; | |
121 | break; | |
122 | case NVME_NS_DPS_PI_TYPE1: | |
123 | case NVME_NS_DPS_PI_TYPE2: | |
124 | control |= NVME_RW_PRINFO_PRCHK_GUARD | | |
125 | NVME_RW_PRINFO_PRCHK_REF; | |
126 | cmnd->rw.reftag = cpu_to_le32( | |
127 | nvme_block_nr(ns, blk_rq_pos(req))); | |
128 | break; | |
129 | } | |
130 | if (!blk_integrity_rq(req)) | |
131 | control |= NVME_RW_PRINFO_PRACT; | |
132 | } | |
133 | ||
134 | cmnd->rw.control = cpu_to_le16(control); | |
135 | cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); | |
136 | } | |
137 | ||
138 | ||
15a190f7 CH |
139 | static inline int nvme_error_status(u16 status) |
140 | { | |
141 | switch (status & 0x7ff) { | |
142 | case NVME_SC_SUCCESS: | |
143 | return 0; | |
144 | case NVME_SC_CAP_EXCEEDED: | |
145 | return -ENOSPC; | |
146 | default: | |
147 | return -EIO; | |
148 | } | |
149 | } | |
150 | ||
4160982e CH |
151 | struct request *nvme_alloc_request(struct request_queue *q, |
152 | struct nvme_command *cmd, unsigned int flags); | |
f11bb3e2 CH |
153 | int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
154 | void *buf, unsigned bufflen); | |
155 | int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, | |
4160982e CH |
156 | void *buffer, unsigned bufflen, u32 *result, unsigned timeout); |
157 | int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd, | |
158 | void __user *ubuffer, unsigned bufflen, u32 *result, | |
159 | unsigned timeout); | |
0b7f1f26 KB |
160 | int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd, |
161 | void __user *ubuffer, unsigned bufflen, | |
162 | void __user *meta_buffer, unsigned meta_len, u32 meta_seed, | |
163 | u32 *result, unsigned timeout); | |
1c63dc66 CH |
164 | int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id); |
165 | int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid, | |
f11bb3e2 | 166 | struct nvme_id_ns **id); |
1c63dc66 CH |
167 | int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log); |
168 | int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid, | |
f11bb3e2 | 169 | dma_addr_t dma_addr, u32 *result); |
1c63dc66 | 170 | int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11, |
f11bb3e2 CH |
171 | dma_addr_t dma_addr, u32 *result); |
172 | ||
173 | struct sg_io_hdr; | |
174 | ||
175 | int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr); | |
176 | int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg); | |
177 | int nvme_sg_get_version_num(int __user *ip); | |
178 | ||
ca064085 MB |
179 | int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id); |
180 | int nvme_nvm_register(struct request_queue *q, char *disk_name); | |
181 | void nvme_nvm_unregister(struct request_queue *q, char *disk_name); | |
182 | ||
f11bb3e2 | 183 | #endif /* _NVME_H */ |