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nvme: don't bother to look up a namespace for controller ioctls
[mirror_ubuntu-jammy-kernel.git] / drivers / nvme / host / nvme.h
CommitLineData
bc50ad75 1/* SPDX-License-Identifier: GPL-2.0 */
f11bb3e2
CH
2/*
3 * Copyright (c) 2011-2014, Intel Corporation.
f11bb3e2
CH
4 */
5
6#ifndef _NVME_H
7#define _NVME_H
8
9#include <linux/nvme.h>
a6a5149b 10#include <linux/cdev.h>
f11bb3e2
CH
11#include <linux/pci.h>
12#include <linux/kref.h>
13#include <linux/blk-mq.h>
b0b4e09c 14#include <linux/lightnvm.h>
a98e58e5 15#include <linux/sed-opal.h>
b9e03857 16#include <linux/fault-inject.h>
978628ec 17#include <linux/rcupdate.h>
c1ac9a4b 18#include <linux/wait.h>
4d2ce688 19#include <linux/t10-pi.h>
f11bb3e2 20
35fe0d12
HR
21#include <trace/events/block.h>
22
8ae4e447 23extern unsigned int nvme_io_timeout;
f11bb3e2
CH
24#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
25
8ae4e447 26extern unsigned int admin_timeout;
dc96f938 27#define NVME_ADMIN_TIMEOUT (admin_timeout * HZ)
21d34711 28
038bd4cb
SG
29#define NVME_DEFAULT_KATO 5
30#define NVME_KATO_GRACE 10
31
38e18002
IR
32#ifdef CONFIG_ARCH_NO_SG_CHAIN
33#define NVME_INLINE_SG_CNT 0
ba7ca2ae 34#define NVME_INLINE_METADATA_SG_CNT 0
38e18002
IR
35#else
36#define NVME_INLINE_SG_CNT 2
ba7ca2ae 37#define NVME_INLINE_METADATA_SG_CNT 1
38e18002
IR
38#endif
39
6c3c05b0
CK
40/*
41 * Default to a 4K page size, with the intention to update this
42 * path in the future to accommodate architectures with differing
43 * kernel and IO page sizes.
44 */
45#define NVME_CTRL_PAGE_SHIFT 12
46#define NVME_CTRL_PAGE_SIZE (1 << NVME_CTRL_PAGE_SHIFT)
47
9a6327d2 48extern struct workqueue_struct *nvme_wq;
b227c59b
RS
49extern struct workqueue_struct *nvme_reset_wq;
50extern struct workqueue_struct *nvme_delete_wq;
9a6327d2 51
ca064085
MB
52enum {
53 NVME_NS_LBA = 0,
54 NVME_NS_LIGHTNVM = 1,
55};
56
f11bb3e2 57/*
106198ed
CH
58 * List of workarounds for devices that required behavior not specified in
59 * the standard.
f11bb3e2 60 */
106198ed
CH
61enum nvme_quirks {
62 /*
63 * Prefers I/O aligned to a stripe size specified in a vendor
64 * specific Identify field.
65 */
66 NVME_QUIRK_STRIPE_SIZE = (1 << 0),
540c801c
KB
67
68 /*
69 * The controller doesn't handle Identify value others than 0 or 1
70 * correctly.
71 */
72 NVME_QUIRK_IDENTIFY_CNS = (1 << 1),
08095e70
KB
73
74 /*
e850fd16
CH
75 * The controller deterministically returns O's on reads to
76 * logical blocks that deallocate was called on.
08095e70 77 */
e850fd16 78 NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2),
54adc010
GP
79
80 /*
81 * The controller needs a delay before starts checking the device
82 * readiness, which is done by reading the NVME_CSTS_RDY bit.
83 */
84 NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3),
c5552fde
AL
85
86 /*
87 * APST should not be used.
88 */
89 NVME_QUIRK_NO_APST = (1 << 4),
ff5350a8
AL
90
91 /*
92 * The deepest sleep state should not be used.
93 */
94 NVME_QUIRK_NO_DEEPEST_PS = (1 << 5),
608cc4b1
CH
95
96 /*
97 * Supports the LighNVM command set if indicated in vs[1].
98 */
99 NVME_QUIRK_LIGHTNVM = (1 << 6),
9abd68ef
JA
100
101 /*
102 * Set MEDIUM priority on SQ creation
103 */
104 NVME_QUIRK_MEDIUM_PRIO_SQ = (1 << 7),
6299358d
JD
105
106 /*
107 * Ignore device provided subnqn.
108 */
109 NVME_QUIRK_IGNORE_DEV_SUBNQN = (1 << 8),
7b210e4e
CH
110
111 /*
112 * Broken Write Zeroes.
113 */
114 NVME_QUIRK_DISABLE_WRITE_ZEROES = (1 << 9),
cb32de1b
ML
115
116 /*
117 * Force simple suspend/resume path.
118 */
119 NVME_QUIRK_SIMPLE_SUSPEND = (1 << 10),
7ad67ca5 120
66341331
BH
121 /*
122 * Use only one interrupt vector for all queues
123 */
7ad67ca5 124 NVME_QUIRK_SINGLE_VECTOR = (1 << 11),
66341331
BH
125
126 /*
127 * Use non-standard 128 bytes SQEs.
128 */
7ad67ca5 129 NVME_QUIRK_128_BYTES_SQES = (1 << 12),
d38e9f04
BH
130
131 /*
132 * Prevent tag overlap between queues
133 */
7ad67ca5 134 NVME_QUIRK_SHARED_TAGS = (1 << 13),
6c6aa2f2
AM
135
136 /*
137 * Don't change the value of the temperature threshold feature
138 */
139 NVME_QUIRK_NO_TEMP_THRESH_CHANGE = (1 << 14),
5bedd3af
CH
140
141 /*
142 * The controller doesn't handle the Identify Namespace
143 * Identification Descriptor list subcommand despite claiming
144 * NVMe 1.3 compliance.
145 */
146 NVME_QUIRK_NO_NS_DESC_LIST = (1 << 15),
4bdf2603
FS
147
148 /*
149 * The controller does not properly handle DMA addresses over
150 * 48 bits.
151 */
152 NVME_QUIRK_DMA_ADDRESS_BITS_48 = (1 << 16),
106198ed
CH
153};
154
d49187e9
CH
155/*
156 * Common request structure for NVMe passthrough. All drivers must have
157 * this structure as the first member of their request-private data.
158 */
159struct nvme_request {
160 struct nvme_command *cmd;
161 union nvme_result result;
44e44b29 162 u8 retries;
27fa9bc5
CH
163 u8 flags;
164 u16 status;
59e29ce6 165 struct nvme_ctrl *ctrl;
27fa9bc5
CH
166};
167
32acab31
CH
168/*
169 * Mark a bio as coming in through the mpath node.
170 */
171#define REQ_NVME_MPATH REQ_DRV
172
27fa9bc5
CH
173enum {
174 NVME_REQ_CANCELLED = (1 << 0),
bb06ec31 175 NVME_REQ_USERCMD = (1 << 1),
d49187e9
CH
176};
177
178static inline struct nvme_request *nvme_req(struct request *req)
179{
180 return blk_mq_rq_to_pdu(req);
181}
182
5d87eb94
KB
183static inline u16 nvme_req_qid(struct request *req)
184{
643c476d 185 if (!req->q->queuedata)
5d87eb94 186 return 0;
84115d6d
BW
187
188 return req->mq_hctx->queue_num + 1;
5d87eb94
KB
189}
190
54adc010
GP
191/* The below value is the specific amount of delay needed before checking
192 * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
193 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
194 * found empirically.
195 */
8c97eecc 196#define NVME_QUIRK_DELAY_AMOUNT 2300
54adc010 197
4212f4e9
SG
198/*
199 * enum nvme_ctrl_state: Controller state
200 *
201 * @NVME_CTRL_NEW: New controller just allocated, initial state
202 * @NVME_CTRL_LIVE: Controller is connected and I/O capable
203 * @NVME_CTRL_RESETTING: Controller is resetting (or scheduled reset)
204 * @NVME_CTRL_CONNECTING: Controller is disconnected, now connecting the
205 * transport
206 * @NVME_CTRL_DELETING: Controller is deleting (or scheduled deletion)
ecca390e
SG
207 * @NVME_CTRL_DELETING_NOIO: Controller is deleting and I/O is not
208 * disabled/failed immediately. This state comes
209 * after all async event processing took place and
210 * before ns removal and the controller deletion
211 * progress
4212f4e9
SG
212 * @NVME_CTRL_DEAD: Controller is non-present/unresponsive during
213 * shutdown or removal. In this case we forcibly
214 * kill all inflight I/O as they have no chance to
215 * complete
216 */
bb8d261e
CH
217enum nvme_ctrl_state {
218 NVME_CTRL_NEW,
219 NVME_CTRL_LIVE,
220 NVME_CTRL_RESETTING,
ad6a0a52 221 NVME_CTRL_CONNECTING,
bb8d261e 222 NVME_CTRL_DELETING,
ecca390e 223 NVME_CTRL_DELETING_NOIO,
0ff9d4e1 224 NVME_CTRL_DEAD,
bb8d261e
CH
225};
226
a3646451
AM
227struct nvme_fault_inject {
228#ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
229 struct fault_attr attr;
230 struct dentry *parent;
231 bool dont_retry; /* DNR, do not retry */
232 u16 status; /* status code */
233#endif
234};
235
1c63dc66 236struct nvme_ctrl {
6e3ca03e 237 bool comp_seen;
bb8d261e 238 enum nvme_ctrl_state state;
bd4da3ab 239 bool identified;
bb8d261e 240 spinlock_t lock;
e7ad43c3 241 struct mutex scan_lock;
1c63dc66 242 const struct nvme_ctrl_ops *ops;
f11bb3e2 243 struct request_queue *admin_q;
07bfcd09 244 struct request_queue *connect_q;
e7832cb4 245 struct request_queue *fabrics_q;
f11bb3e2 246 struct device *dev;
f11bb3e2 247 int instance;
103e515e 248 int numa_node;
5bae7f73 249 struct blk_mq_tag_set *tagset;
34b6c231 250 struct blk_mq_tag_set *admin_tagset;
f11bb3e2 251 struct list_head namespaces;
765cc031 252 struct rw_semaphore namespaces_rwsem;
d22524a4 253 struct device ctrl_device;
5bae7f73 254 struct device *device; /* char device */
ed7770f6
HR
255#ifdef CONFIG_NVME_HWMON
256 struct device *hwmon_device;
257#endif
a6a5149b 258 struct cdev cdev;
d86c4d8e 259 struct work_struct reset_work;
c5017e85 260 struct work_struct delete_work;
c1ac9a4b 261 wait_queue_head_t state_wq;
1c63dc66 262
ab9e00cc
CH
263 struct nvme_subsystem *subsys;
264 struct list_head subsys_entry;
265
4f1244c8 266 struct opal_dev *opal_dev;
a98e58e5 267
f11bb3e2 268 char name[12];
76e3914a 269 u16 cntlid;
5fd4ce1b
CH
270
271 u32 ctrl_config;
b6dccf7f 272 u16 mtfa;
d858e5f0 273 u32 queue_count;
5fd4ce1b 274
20d0dfe6 275 u64 cap;
f11bb3e2 276 u32 max_hw_sectors;
943e942e 277 u32 max_segments;
95093350 278 u32 max_integrity_segments;
5befc7c2
KB
279 u32 max_discard_sectors;
280 u32 max_discard_segments;
281 u32 max_zeroes_sectors;
240e6ee2
KB
282#ifdef CONFIG_BLK_DEV_ZONED
283 u32 max_zone_append;
284#endif
49cd84b6 285 u16 crdt[3];
f11bb3e2 286 u16 oncs;
8a9ae523 287 u16 oacs;
f5d11840
JA
288 u16 nssa;
289 u16 nr_streams;
f968688f 290 u16 sqsize;
0d0b660f 291 u32 max_namespaces;
6bf25d16 292 atomic_t abort_limit;
f11bb3e2 293 u8 vwc;
f3ca80fc 294 u32 vs;
07bfcd09 295 u32 sgls;
038bd4cb 296 u16 kas;
c5552fde
AL
297 u8 npss;
298 u8 apsta;
400b6a7b
GR
299 u16 wctemp;
300 u16 cctemp;
c0561f82 301 u32 oaes;
e3d7874d 302 u32 aen_result;
3e53ba38 303 u32 ctratt;
07fbd32a 304 unsigned int shutdown_timeout;
038bd4cb 305 unsigned int kato;
f3ca80fc 306 bool subsystem;
106198ed 307 unsigned long quirks;
c5552fde 308 struct nvme_id_power_state psd[32];
84fef62d 309 struct nvme_effects_log *effects;
1cf7a12e 310 struct xarray cels;
5955be21 311 struct work_struct scan_work;
f866fc42 312 struct work_struct async_event_work;
038bd4cb 313 struct delayed_work ka_work;
8c4dfea9 314 struct delayed_work failfast_work;
0a34e466 315 struct nvme_command ka_cmd;
b6dccf7f 316 struct work_struct fw_act_work;
30d90964 317 unsigned long events;
07bfcd09 318
0d0b660f
CH
319#ifdef CONFIG_NVME_MULTIPATH
320 /* asymmetric namespace access: */
321 u8 anacap;
322 u8 anatt;
323 u32 anagrpmax;
324 u32 nanagrpid;
325 struct mutex ana_lock;
326 struct nvme_ana_rsp_hdr *ana_log_buf;
327 size_t ana_log_size;
328 struct timer_list anatt_timer;
329 struct work_struct ana_work;
330#endif
331
c5552fde
AL
332 /* Power saving configuration */
333 u64 ps_max_latency_us;
76a5af84 334 bool apst_enabled;
c5552fde 335
044a9df1 336 /* PCIe only: */
fe6d53c9
CH
337 u32 hmpre;
338 u32 hmmin;
044a9df1
CH
339 u32 hmminds;
340 u16 hmmaxd;
fe6d53c9 341
07bfcd09 342 /* Fabrics only */
07bfcd09
CH
343 u32 ioccsz;
344 u32 iorcsz;
345 u16 icdoff;
346 u16 maxcmd;
fdf9dfa8 347 int nr_reconnects;
8c4dfea9
VG
348 unsigned long flags;
349#define NVME_CTRL_FAILFAST_EXPIRED 0
07bfcd09 350 struct nvmf_ctrl_options *opts;
cb5b7262
JA
351
352 struct page *discard_page;
353 unsigned long discard_page_busy;
f79d5fda
AM
354
355 struct nvme_fault_inject fault_inject;
f11bb3e2
CH
356};
357
75c10e73
HR
358enum nvme_iopolicy {
359 NVME_IOPOLICY_NUMA,
360 NVME_IOPOLICY_RR,
361};
362
ab9e00cc
CH
363struct nvme_subsystem {
364 int instance;
365 struct device dev;
366 /*
367 * Because we unregister the device on the last put we need
368 * a separate refcount.
369 */
370 struct kref ref;
371 struct list_head entry;
372 struct mutex lock;
373 struct list_head ctrls;
ed754e5d 374 struct list_head nsheads;
ab9e00cc
CH
375 char subnqn[NVMF_NQN_SIZE];
376 char serial[20];
377 char model[40];
378 char firmware_rev[8];
379 u8 cmic;
380 u16 vendor_id;
81adb863 381 u16 awupf; /* 0's based awupf value. */
ed754e5d 382 struct ida ns_ida;
75c10e73
HR
383#ifdef CONFIG_NVME_MULTIPATH
384 enum nvme_iopolicy iopolicy;
385#endif
ab9e00cc
CH
386};
387
002fab04
CH
388/*
389 * Container structure for uniqueue namespace identifiers.
390 */
391struct nvme_ns_ids {
392 u8 eui64[8];
393 u8 nguid[16];
394 uuid_t uuid;
71010c30 395 u8 csi;
002fab04
CH
396};
397
ed754e5d
CH
398/*
399 * Anchor structure for namespaces. There is one for each namespace in a
400 * NVMe subsystem that any of our controllers can see, and the namespace
401 * structure for each controller is chained of it. For private namespaces
402 * there is a 1:1 relation to our namespace structures, that is ->list
403 * only ever has a single entry for private namespaces.
404 */
405struct nvme_ns_head {
406 struct list_head list;
407 struct srcu_struct srcu;
408 struct nvme_subsystem *subsys;
409 unsigned ns_id;
410 struct nvme_ns_ids ids;
411 struct list_head entry;
412 struct kref ref;
0c284db7 413 bool shared;
ed754e5d 414 int instance;
be93e87e 415 struct nvme_effects_log *effects;
f3334447 416 struct gendisk *disk;
30897388 417#ifdef CONFIG_NVME_MULTIPATH
f3334447
CH
418 struct bio_list requeue_list;
419 spinlock_t requeue_lock;
420 struct work_struct requeue_work;
421 struct mutex lock;
d8a22f85
AE
422 unsigned long flags;
423#define NVME_NSHEAD_DISK_LIVE 0
f3334447
CH
424 struct nvme_ns __rcu *current_path[];
425#endif
ed754e5d
CH
426};
427
30897388
MI
428static inline bool nvme_ns_head_multipath(struct nvme_ns_head *head)
429{
430 return IS_ENABLED(CONFIG_NVME_MULTIPATH) && head->disk;
431}
432
ffc89b1d
MG
433enum nvme_ns_features {
434 NVME_NS_EXT_LBAS = 1 << 0, /* support extended LBA format */
b29f8485 435 NVME_NS_METADATA_SUPPORTED = 1 << 1, /* support getting generated md */
ffc89b1d
MG
436};
437
f11bb3e2
CH
438struct nvme_ns {
439 struct list_head list;
440
1c63dc66 441 struct nvme_ctrl *ctrl;
f11bb3e2
CH
442 struct request_queue *queue;
443 struct gendisk *disk;
0d0b660f
CH
444#ifdef CONFIG_NVME_MULTIPATH
445 enum nvme_ana_state ana_state;
446 u32 ana_grpid;
447#endif
ed754e5d 448 struct list_head siblings;
b0b4e09c 449 struct nvm_dev *ndev;
f11bb3e2 450 struct kref kref;
ed754e5d 451 struct nvme_ns_head *head;
f11bb3e2 452
f11bb3e2
CH
453 int lba_shift;
454 u16 ms;
f5d11840
JA
455 u16 sgs;
456 u32 sws;
f11bb3e2 457 u8 pi_type;
240e6ee2
KB
458#ifdef CONFIG_BLK_DEV_ZONED
459 u64 zsze;
460#endif
ffc89b1d 461 unsigned long features;
646017a6 462 unsigned long flags;
0d0b660f
CH
463#define NVME_NS_REMOVING 0
464#define NVME_NS_DEAD 1
465#define NVME_NS_ANA_PENDING 2
2f4c9ba2 466#define NVME_NS_FORCE_RO 3
b9e03857 467
b9e03857 468 struct nvme_fault_inject fault_inject;
b9e03857 469
f11bb3e2
CH
470};
471
4d2ce688
JS
472/* NVMe ns supports metadata actions by the controller (generate/strip) */
473static inline bool nvme_ns_has_pi(struct nvme_ns *ns)
474{
475 return ns->pi_type && ns->ms == sizeof(struct t10_pi_tuple);
476}
477
1c63dc66 478struct nvme_ctrl_ops {
1a353d85 479 const char *name;
e439bb12 480 struct module *module;
d3d5b87d
CH
481 unsigned int flags;
482#define NVME_F_FABRICS (1 << 0)
c81bfba9 483#define NVME_F_METADATA_SUPPORTED (1 << 1)
e0596ab2 484#define NVME_F_PCI_P2PDMA (1 << 2)
1c63dc66 485 int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val);
5fd4ce1b 486 int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val);
7fd8930f 487 int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val);
1673f1f0 488 void (*free_ctrl)(struct nvme_ctrl *ctrl);
ad22c355 489 void (*submit_async_event)(struct nvme_ctrl *ctrl);
c5017e85 490 void (*delete_ctrl)(struct nvme_ctrl *ctrl);
1a353d85 491 int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size);
f11bb3e2
CH
492};
493
b9e03857 494#ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
a3646451
AM
495void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj,
496 const char *dev_name);
497void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inject);
b9e03857
TT
498void nvme_should_fail(struct request *req);
499#else
a3646451
AM
500static inline void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj,
501 const char *dev_name)
502{
503}
504static inline void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inj)
505{
506}
b9e03857
TT
507static inline void nvme_should_fail(struct request *req) {}
508#endif
509
f3ca80fc
CH
510static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
511{
512 if (!ctrl->subsystem)
513 return -ENOTTY;
514 return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
515}
516
314d48dd
DLM
517/*
518 * Convert a 512B sector number to a device logical block number.
519 */
520static inline u64 nvme_sect_to_lba(struct nvme_ns *ns, sector_t sector)
f11bb3e2 521{
314d48dd 522 return sector >> (ns->lba_shift - SECTOR_SHIFT);
f11bb3e2
CH
523}
524
e08f2ae8
DLM
525/*
526 * Convert a device logical block number to a 512B sector number.
527 */
528static inline sector_t nvme_lba_to_sect(struct nvme_ns *ns, u64 lba)
f11bb3e2 529{
e08f2ae8 530 return lba << (ns->lba_shift - SECTOR_SHIFT);
f11bb3e2
CH
531}
532
71fb90eb
KB
533/*
534 * Convert byte length to nvme's 0-based num dwords
535 */
536static inline u32 nvme_bytes_to_numd(size_t len)
537{
538 return (len >> 2) - 1;
539}
540
5ddaabe8
CH
541static inline bool nvme_is_ana_error(u16 status)
542{
543 switch (status & 0x7ff) {
544 case NVME_SC_ANA_TRANSITION:
545 case NVME_SC_ANA_INACCESSIBLE:
546 case NVME_SC_ANA_PERSISTENT_LOSS:
547 return true;
548 default:
549 return false;
550 }
551}
552
553static inline bool nvme_is_path_error(u16 status)
554{
1e41f3bd
CH
555 /* check for a status code type of 'path related status' */
556 return (status & 0x700) == 0x300;
5ddaabe8
CH
557}
558
2eb81a33
CH
559/*
560 * Fill in the status and result information from the CQE, and then figure out
561 * if blk-mq will need to use IPI magic to complete the request, and if yes do
562 * so. If not let the caller complete the request without an indirect function
563 * call.
564 */
565static inline bool nvme_try_complete_req(struct request *req, __le16 status,
27fa9bc5 566 union nvme_result result)
15a190f7 567{
27fa9bc5 568 struct nvme_request *rq = nvme_req(req);
15a190f7 569
27fa9bc5
CH
570 rq->status = le16_to_cpu(status) >> 1;
571 rq->result = result;
b9e03857
TT
572 /* inject error when permitted by fault injection framework */
573 nvme_should_fail(req);
ff029451
CH
574 if (unlikely(blk_should_fake_timeout(req->q)))
575 return true;
576 return blk_mq_complete_request_remote(req);
7688faa6
CH
577}
578
d22524a4
CH
579static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl)
580{
581 get_device(ctrl->device);
582}
583
584static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl)
585{
586 put_device(ctrl->device);
587}
588
58a8df67
IR
589static inline bool nvme_is_aen_req(u16 qid, __u16 command_id)
590{
591 return !qid && command_id >= NVME_AQ_BLK_MQ_DEPTH;
592}
593
77f02a7a 594void nvme_complete_rq(struct request *req);
dda3248e 595blk_status_t nvme_host_path_error(struct request *req);
7baa8572 596bool nvme_cancel_request(struct request *req, void *data, bool reserved);
25479069
CL
597void nvme_cancel_tagset(struct nvme_ctrl *ctrl);
598void nvme_cancel_admin_tagset(struct nvme_ctrl *ctrl);
bb8d261e
CH
599bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
600 enum nvme_ctrl_state new_state);
c1ac9a4b 601bool nvme_wait_reset(struct nvme_ctrl *ctrl);
b5b05048 602int nvme_disable_ctrl(struct nvme_ctrl *ctrl);
c0f2f45b 603int nvme_enable_ctrl(struct nvme_ctrl *ctrl);
5fd4ce1b 604int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
f3ca80fc
CH
605int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
606 const struct nvme_ctrl_ops *ops, unsigned long quirks);
53029b04 607void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
d09f2b45
SG
608void nvme_start_ctrl(struct nvme_ctrl *ctrl);
609void nvme_stop_ctrl(struct nvme_ctrl *ctrl);
f21c4769 610int nvme_init_ctrl_finish(struct nvme_ctrl *ctrl);
5bae7f73 611
5bae7f73 612void nvme_remove_namespaces(struct nvme_ctrl *ctrl);
1673f1f0 613
4f1244c8
CH
614int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
615 bool send);
a98e58e5 616
7bf58533 617void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
287a63eb 618 volatile union nvme_result *res);
f866fc42 619
25646264
KB
620void nvme_stop_queues(struct nvme_ctrl *ctrl);
621void nvme_start_queues(struct nvme_ctrl *ctrl);
69d9a99c 622void nvme_kill_queues(struct nvme_ctrl *ctrl);
d6135c3a 623void nvme_sync_queues(struct nvme_ctrl *ctrl);
04800fbf 624void nvme_sync_io_queues(struct nvme_ctrl *ctrl);
302ad8cc
KB
625void nvme_unfreeze(struct nvme_ctrl *ctrl);
626void nvme_wait_freeze(struct nvme_ctrl *ctrl);
7cf0d7c0 627int nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
302ad8cc 628void nvme_start_freeze(struct nvme_ctrl *ctrl);
363c9aac 629
eb71f435 630#define NVME_QID_ANY -1
4160982e 631struct request *nvme_alloc_request(struct request_queue *q,
39dfe844 632 struct nvme_command *cmd, blk_mq_req_flags_t flags);
f7f1fc36 633void nvme_cleanup_cmd(struct request *req);
f4b9e6c9 634blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req);
f11bb3e2
CH
635int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
636 void *buf, unsigned bufflen);
637int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 638 union nvme_result *result, void *buffer, unsigned bufflen,
9a95e4ef 639 unsigned timeout, int qid, int at_head,
6287b51c 640 blk_mq_req_flags_t flags, bool poll);
1a87ee65
KB
641int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid,
642 unsigned int dword11, void *buffer, size_t buflen,
643 u32 *result);
644int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid,
645 unsigned int dword11, void *buffer, size_t buflen,
646 u32 *result);
9a0be7ab 647int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);
038bd4cb 648void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
d86c4d8e 649int nvme_reset_ctrl(struct nvme_ctrl *ctrl);
c1ac9a4b 650int nvme_try_sched_reset(struct nvme_ctrl *ctrl);
c5017e85 651int nvme_delete_ctrl(struct nvme_ctrl *ctrl);
f11bb3e2 652
be93e87e 653int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, u8 csi,
0e98719b 654 void *log, size_t size, u64 offset);
240e6ee2
KB
655struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk,
656 struct nvme_ns_head **head, int *srcu_idx);
657void nvme_put_ns_from_disk(struct nvme_ns_head *head, int idx);
d558fb51 658
33b14f67 659extern const struct attribute_group *nvme_ns_id_attr_groups[];
32acab31
CH
660extern const struct block_device_operations nvme_ns_head_ops;
661
662#ifdef CONFIG_NVME_MULTIPATH
66b20ac0
MR
663static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl)
664{
665 return ctrl->ana_log_buf != NULL;
666}
667
b9156dae
SG
668void nvme_mpath_unfreeze(struct nvme_subsystem *subsys);
669void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys);
670void nvme_mpath_start_freeze(struct nvme_subsystem *subsys);
9953ab0c 671bool nvme_mpath_set_disk_name(struct nvme_ns *ns, char *disk_name, int *flags);
5ddaabe8 672void nvme_failover_req(struct request *req);
32acab31
CH
673void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl);
674int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,struct nvme_ns_head *head);
0d0b660f 675void nvme_mpath_add_disk(struct nvme_ns *ns, struct nvme_id_ns *id);
32acab31 676void nvme_mpath_remove_disk(struct nvme_ns_head *head);
0d0b660f
CH
677int nvme_mpath_init(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id);
678void nvme_mpath_uninit(struct nvme_ctrl *ctrl);
679void nvme_mpath_stop(struct nvme_ctrl *ctrl);
0157ec8d
SG
680bool nvme_mpath_clear_current_path(struct nvme_ns *ns);
681void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl);
32acab31 682struct nvme_ns *nvme_find_path(struct nvme_ns_head *head);
c62b37d9 683blk_qc_t nvme_ns_head_submit_bio(struct bio *bio);
479a322f
SG
684
685static inline void nvme_mpath_check_last_path(struct nvme_ns *ns)
686{
687 struct nvme_ns_head *head = ns->head;
688
689 if (head->disk && list_empty(&head->list))
690 kblockd_schedule_work(&head->requeue_work);
691}
692
2b59787a 693static inline void nvme_trace_bio_complete(struct request *req)
35fe0d12
HR
694{
695 struct nvme_ns *ns = req->q->queuedata;
696
697 if (req->cmd_flags & REQ_NVME_MPATH)
d24de76a 698 trace_block_bio_complete(ns->head->disk->queue, req->bio);
35fe0d12
HR
699}
700
0d0b660f
CH
701extern struct device_attribute dev_attr_ana_grpid;
702extern struct device_attribute dev_attr_ana_state;
75c10e73 703extern struct device_attribute subsys_attr_iopolicy;
0d0b660f 704
32acab31 705#else
0d0b660f
CH
706static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl)
707{
708 return false;
709}
9953ab0c
CH
710static inline bool nvme_mpath_set_disk_name(struct nvme_ns *ns, char *disk_name,
711 int *flags)
a785dbcc 712{
9953ab0c 713 return false;
a785dbcc 714}
5ddaabe8 715static inline void nvme_failover_req(struct request *req)
32acab31
CH
716{
717}
32acab31
CH
718static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl)
719{
720}
721static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,
722 struct nvme_ns_head *head)
723{
724 return 0;
725}
0d0b660f
CH
726static inline void nvme_mpath_add_disk(struct nvme_ns *ns,
727 struct nvme_id_ns *id)
32acab31
CH
728{
729}
730static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head)
731{
732}
0157ec8d
SG
733static inline bool nvme_mpath_clear_current_path(struct nvme_ns *ns)
734{
735 return false;
736}
737static inline void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl)
479a322f
SG
738{
739}
740static inline void nvme_mpath_check_last_path(struct nvme_ns *ns)
32acab31
CH
741{
742}
2b59787a 743static inline void nvme_trace_bio_complete(struct request *req)
35fe0d12
HR
744{
745}
0d0b660f
CH
746static inline int nvme_mpath_init(struct nvme_ctrl *ctrl,
747 struct nvme_id_ctrl *id)
748{
2bd64307 749 if (ctrl->subsys->cmic & NVME_CTRL_CMIC_ANA)
14a1336e
CH
750 dev_warn(ctrl->device,
751"Please enable CONFIG_NVME_MULTIPATH for full support of multi-port devices.\n");
0d0b660f
CH
752 return 0;
753}
754static inline void nvme_mpath_uninit(struct nvme_ctrl *ctrl)
755{
756}
757static inline void nvme_mpath_stop(struct nvme_ctrl *ctrl)
758{
759}
b9156dae
SG
760static inline void nvme_mpath_unfreeze(struct nvme_subsystem *subsys)
761{
762}
763static inline void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys)
764{
765}
766static inline void nvme_mpath_start_freeze(struct nvme_subsystem *subsys)
767{
768}
32acab31
CH
769#endif /* CONFIG_NVME_MULTIPATH */
770
7fad20dd 771int nvme_revalidate_zones(struct nvme_ns *ns);
240e6ee2 772#ifdef CONFIG_BLK_DEV_ZONED
d525c3c0 773int nvme_update_zone_info(struct nvme_ns *ns, unsigned lbaf);
240e6ee2
KB
774int nvme_report_zones(struct gendisk *disk, sector_t sector,
775 unsigned int nr_zones, report_zones_cb cb, void *data);
776
777blk_status_t nvme_setup_zone_mgmt_send(struct nvme_ns *ns, struct request *req,
778 struct nvme_command *cmnd,
779 enum nvme_zone_mgmt_action action);
780#else
781#define nvme_report_zones NULL
782
783static inline blk_status_t nvme_setup_zone_mgmt_send(struct nvme_ns *ns,
784 struct request *req, struct nvme_command *cmnd,
785 enum nvme_zone_mgmt_action action)
786{
787 return BLK_STS_NOTSUPP;
788}
789
d525c3c0 790static inline int nvme_update_zone_info(struct nvme_ns *ns, unsigned lbaf)
240e6ee2
KB
791{
792 dev_warn(ns->ctrl->device,
793 "Please enable CONFIG_BLK_DEV_ZONED to support ZNS devices\n");
794 return -EPROTONOSUPPORT;
795}
796#endif
797
c4699e70 798#ifdef CONFIG_NVM
3dc87dd0 799int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node);
b0b4e09c 800void nvme_nvm_unregister(struct nvme_ns *ns);
33b14f67 801extern const struct attribute_group nvme_nvm_attr_group;
d7790d37 802int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, void __user *argp);
c4699e70 803#else
b0b4e09c 804static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name,
3dc87dd0 805 int node)
c4699e70
KB
806{
807 return 0;
808}
809
b0b4e09c 810static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
84d4add7 811static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
d7790d37 812 void __user *argp)
84d4add7
MB
813{
814 return -ENOTTY;
815}
3dc87dd0
MB
816#endif /* CONFIG_NVM */
817
40267efd
SL
818static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev)
819{
820 return dev_to_disk(dev)->private_data;
821}
ca064085 822
400b6a7b 823#ifdef CONFIG_NVME_HWMON
59e330f8 824int nvme_hwmon_init(struct nvme_ctrl *ctrl);
ed7770f6 825void nvme_hwmon_exit(struct nvme_ctrl *ctrl);
400b6a7b 826#else
59e330f8
KB
827static inline int nvme_hwmon_init(struct nvme_ctrl *ctrl)
828{
829 return 0;
830}
ed7770f6
HR
831
832static inline void nvme_hwmon_exit(struct nvme_ctrl *ctrl)
833{
834}
400b6a7b
GR
835#endif
836
df21b6b1
LG
837u32 nvme_command_effects(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
838 u8 opcode);
17365ae6 839void nvme_execute_passthru_rq(struct request *rq);
b2702aaa 840struct nvme_ctrl *nvme_ctrl_from_file(struct file *file);
24493b8b
LG
841struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid);
842void nvme_put_ns(struct nvme_ns *ns);
df21b6b1 843
f11bb3e2 844#endif /* _NVME_H */