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Commit | Line | Data |
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f11bb3e2 CH |
1 | /* |
2 | * Copyright (c) 2011-2014, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | */ | |
13 | ||
14 | #ifndef _NVME_H | |
15 | #define _NVME_H | |
16 | ||
17 | #include <linux/nvme.h> | |
a6a5149b | 18 | #include <linux/cdev.h> |
f11bb3e2 CH |
19 | #include <linux/pci.h> |
20 | #include <linux/kref.h> | |
21 | #include <linux/blk-mq.h> | |
b0b4e09c | 22 | #include <linux/lightnvm.h> |
a98e58e5 | 23 | #include <linux/sed-opal.h> |
b9e03857 | 24 | #include <linux/fault-inject.h> |
f11bb3e2 | 25 | |
8ae4e447 | 26 | extern unsigned int nvme_io_timeout; |
f11bb3e2 CH |
27 | #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) |
28 | ||
8ae4e447 | 29 | extern unsigned int admin_timeout; |
21d34711 CH |
30 | #define ADMIN_TIMEOUT (admin_timeout * HZ) |
31 | ||
038bd4cb SG |
32 | #define NVME_DEFAULT_KATO 5 |
33 | #define NVME_KATO_GRACE 10 | |
34 | ||
9a6327d2 | 35 | extern struct workqueue_struct *nvme_wq; |
b227c59b RS |
36 | extern struct workqueue_struct *nvme_reset_wq; |
37 | extern struct workqueue_struct *nvme_delete_wq; | |
9a6327d2 | 38 | |
ca064085 MB |
39 | enum { |
40 | NVME_NS_LBA = 0, | |
41 | NVME_NS_LIGHTNVM = 1, | |
42 | }; | |
43 | ||
f11bb3e2 | 44 | /* |
106198ed CH |
45 | * List of workarounds for devices that required behavior not specified in |
46 | * the standard. | |
f11bb3e2 | 47 | */ |
106198ed CH |
48 | enum nvme_quirks { |
49 | /* | |
50 | * Prefers I/O aligned to a stripe size specified in a vendor | |
51 | * specific Identify field. | |
52 | */ | |
53 | NVME_QUIRK_STRIPE_SIZE = (1 << 0), | |
540c801c KB |
54 | |
55 | /* | |
56 | * The controller doesn't handle Identify value others than 0 or 1 | |
57 | * correctly. | |
58 | */ | |
59 | NVME_QUIRK_IDENTIFY_CNS = (1 << 1), | |
08095e70 KB |
60 | |
61 | /* | |
e850fd16 CH |
62 | * The controller deterministically returns O's on reads to |
63 | * logical blocks that deallocate was called on. | |
08095e70 | 64 | */ |
e850fd16 | 65 | NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2), |
54adc010 GP |
66 | |
67 | /* | |
68 | * The controller needs a delay before starts checking the device | |
69 | * readiness, which is done by reading the NVME_CSTS_RDY bit. | |
70 | */ | |
71 | NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), | |
c5552fde AL |
72 | |
73 | /* | |
74 | * APST should not be used. | |
75 | */ | |
76 | NVME_QUIRK_NO_APST = (1 << 4), | |
ff5350a8 AL |
77 | |
78 | /* | |
79 | * The deepest sleep state should not be used. | |
80 | */ | |
81 | NVME_QUIRK_NO_DEEPEST_PS = (1 << 5), | |
608cc4b1 CH |
82 | |
83 | /* | |
84 | * Supports the LighNVM command set if indicated in vs[1]. | |
85 | */ | |
86 | NVME_QUIRK_LIGHTNVM = (1 << 6), | |
106198ed CH |
87 | }; |
88 | ||
d49187e9 CH |
89 | /* |
90 | * Common request structure for NVMe passthrough. All drivers must have | |
91 | * this structure as the first member of their request-private data. | |
92 | */ | |
93 | struct nvme_request { | |
94 | struct nvme_command *cmd; | |
95 | union nvme_result result; | |
44e44b29 | 96 | u8 retries; |
27fa9bc5 CH |
97 | u8 flags; |
98 | u16 status; | |
99 | }; | |
100 | ||
32acab31 CH |
101 | /* |
102 | * Mark a bio as coming in through the mpath node. | |
103 | */ | |
104 | #define REQ_NVME_MPATH REQ_DRV | |
105 | ||
27fa9bc5 CH |
106 | enum { |
107 | NVME_REQ_CANCELLED = (1 << 0), | |
bb06ec31 | 108 | NVME_REQ_USERCMD = (1 << 1), |
d49187e9 CH |
109 | }; |
110 | ||
111 | static inline struct nvme_request *nvme_req(struct request *req) | |
112 | { | |
113 | return blk_mq_rq_to_pdu(req); | |
114 | } | |
115 | ||
54adc010 GP |
116 | /* The below value is the specific amount of delay needed before checking |
117 | * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the | |
118 | * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was | |
119 | * found empirically. | |
120 | */ | |
8c97eecc | 121 | #define NVME_QUIRK_DELAY_AMOUNT 2300 |
54adc010 | 122 | |
bb8d261e CH |
123 | enum nvme_ctrl_state { |
124 | NVME_CTRL_NEW, | |
125 | NVME_CTRL_LIVE, | |
2b1b7e78 | 126 | NVME_CTRL_ADMIN_ONLY, /* Only admin queue live */ |
bb8d261e | 127 | NVME_CTRL_RESETTING, |
ad6a0a52 | 128 | NVME_CTRL_CONNECTING, |
bb8d261e | 129 | NVME_CTRL_DELETING, |
0ff9d4e1 | 130 | NVME_CTRL_DEAD, |
bb8d261e CH |
131 | }; |
132 | ||
1c63dc66 | 133 | struct nvme_ctrl { |
bb8d261e | 134 | enum nvme_ctrl_state state; |
bd4da3ab | 135 | bool identified; |
bb8d261e | 136 | spinlock_t lock; |
1c63dc66 | 137 | const struct nvme_ctrl_ops *ops; |
f11bb3e2 | 138 | struct request_queue *admin_q; |
07bfcd09 | 139 | struct request_queue *connect_q; |
f11bb3e2 | 140 | struct device *dev; |
f11bb3e2 | 141 | int instance; |
5bae7f73 | 142 | struct blk_mq_tag_set *tagset; |
34b6c231 | 143 | struct blk_mq_tag_set *admin_tagset; |
f11bb3e2 | 144 | struct list_head namespaces; |
765cc031 | 145 | struct rw_semaphore namespaces_rwsem; |
d22524a4 | 146 | struct device ctrl_device; |
5bae7f73 | 147 | struct device *device; /* char device */ |
a6a5149b | 148 | struct cdev cdev; |
d86c4d8e | 149 | struct work_struct reset_work; |
c5017e85 | 150 | struct work_struct delete_work; |
1c63dc66 | 151 | |
ab9e00cc CH |
152 | struct nvme_subsystem *subsys; |
153 | struct list_head subsys_entry; | |
154 | ||
4f1244c8 | 155 | struct opal_dev *opal_dev; |
a98e58e5 | 156 | |
f11bb3e2 | 157 | char name[12]; |
76e3914a | 158 | u16 cntlid; |
5fd4ce1b CH |
159 | |
160 | u32 ctrl_config; | |
b6dccf7f | 161 | u16 mtfa; |
d858e5f0 | 162 | u32 queue_count; |
5fd4ce1b | 163 | |
20d0dfe6 | 164 | u64 cap; |
5fd4ce1b | 165 | u32 page_size; |
f11bb3e2 | 166 | u32 max_hw_sectors; |
f11bb3e2 | 167 | u16 oncs; |
8a9ae523 | 168 | u16 oacs; |
f5d11840 JA |
169 | u16 nssa; |
170 | u16 nr_streams; | |
6bf25d16 | 171 | atomic_t abort_limit; |
f11bb3e2 | 172 | u8 vwc; |
f3ca80fc | 173 | u32 vs; |
07bfcd09 | 174 | u32 sgls; |
038bd4cb | 175 | u16 kas; |
c5552fde AL |
176 | u8 npss; |
177 | u8 apsta; | |
e3d7874d | 178 | u32 aen_result; |
07fbd32a | 179 | unsigned int shutdown_timeout; |
038bd4cb | 180 | unsigned int kato; |
f3ca80fc | 181 | bool subsystem; |
106198ed | 182 | unsigned long quirks; |
c5552fde | 183 | struct nvme_id_power_state psd[32]; |
84fef62d | 184 | struct nvme_effects_log *effects; |
5955be21 | 185 | struct work_struct scan_work; |
f866fc42 | 186 | struct work_struct async_event_work; |
038bd4cb | 187 | struct delayed_work ka_work; |
0a34e466 | 188 | struct nvme_command ka_cmd; |
b6dccf7f | 189 | struct work_struct fw_act_work; |
07bfcd09 | 190 | |
c5552fde AL |
191 | /* Power saving configuration */ |
192 | u64 ps_max_latency_us; | |
76a5af84 | 193 | bool apst_enabled; |
c5552fde | 194 | |
044a9df1 | 195 | /* PCIe only: */ |
fe6d53c9 CH |
196 | u32 hmpre; |
197 | u32 hmmin; | |
044a9df1 CH |
198 | u32 hmminds; |
199 | u16 hmmaxd; | |
fe6d53c9 | 200 | |
07bfcd09 CH |
201 | /* Fabrics only */ |
202 | u16 sqsize; | |
203 | u32 ioccsz; | |
204 | u32 iorcsz; | |
205 | u16 icdoff; | |
206 | u16 maxcmd; | |
fdf9dfa8 | 207 | int nr_reconnects; |
07bfcd09 | 208 | struct nvmf_ctrl_options *opts; |
f11bb3e2 CH |
209 | }; |
210 | ||
ab9e00cc CH |
211 | struct nvme_subsystem { |
212 | int instance; | |
213 | struct device dev; | |
214 | /* | |
215 | * Because we unregister the device on the last put we need | |
216 | * a separate refcount. | |
217 | */ | |
218 | struct kref ref; | |
219 | struct list_head entry; | |
220 | struct mutex lock; | |
221 | struct list_head ctrls; | |
ed754e5d | 222 | struct list_head nsheads; |
ab9e00cc CH |
223 | char subnqn[NVMF_NQN_SIZE]; |
224 | char serial[20]; | |
225 | char model[40]; | |
226 | char firmware_rev[8]; | |
227 | u8 cmic; | |
228 | u16 vendor_id; | |
ed754e5d | 229 | struct ida ns_ida; |
ab9e00cc CH |
230 | }; |
231 | ||
002fab04 CH |
232 | /* |
233 | * Container structure for uniqueue namespace identifiers. | |
234 | */ | |
235 | struct nvme_ns_ids { | |
236 | u8 eui64[8]; | |
237 | u8 nguid[16]; | |
238 | uuid_t uuid; | |
239 | }; | |
240 | ||
ed754e5d CH |
241 | /* |
242 | * Anchor structure for namespaces. There is one for each namespace in a | |
243 | * NVMe subsystem that any of our controllers can see, and the namespace | |
244 | * structure for each controller is chained of it. For private namespaces | |
245 | * there is a 1:1 relation to our namespace structures, that is ->list | |
246 | * only ever has a single entry for private namespaces. | |
247 | */ | |
248 | struct nvme_ns_head { | |
32acab31 CH |
249 | #ifdef CONFIG_NVME_MULTIPATH |
250 | struct gendisk *disk; | |
251 | struct nvme_ns __rcu *current_path; | |
252 | struct bio_list requeue_list; | |
253 | spinlock_t requeue_lock; | |
254 | struct work_struct requeue_work; | |
255 | #endif | |
ed754e5d CH |
256 | struct list_head list; |
257 | struct srcu_struct srcu; | |
258 | struct nvme_subsystem *subsys; | |
259 | unsigned ns_id; | |
260 | struct nvme_ns_ids ids; | |
261 | struct list_head entry; | |
262 | struct kref ref; | |
263 | int instance; | |
264 | }; | |
265 | ||
b9e03857 TT |
266 | #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS |
267 | struct nvme_fault_inject { | |
268 | struct fault_attr attr; | |
269 | struct dentry *parent; | |
270 | bool dont_retry; /* DNR, do not retry */ | |
271 | u16 status; /* status code */ | |
272 | }; | |
273 | #endif | |
274 | ||
f11bb3e2 CH |
275 | struct nvme_ns { |
276 | struct list_head list; | |
277 | ||
1c63dc66 | 278 | struct nvme_ctrl *ctrl; |
f11bb3e2 CH |
279 | struct request_queue *queue; |
280 | struct gendisk *disk; | |
ed754e5d | 281 | struct list_head siblings; |
b0b4e09c | 282 | struct nvm_dev *ndev; |
f11bb3e2 | 283 | struct kref kref; |
ed754e5d | 284 | struct nvme_ns_head *head; |
f11bb3e2 | 285 | |
f11bb3e2 CH |
286 | int lba_shift; |
287 | u16 ms; | |
f5d11840 JA |
288 | u16 sgs; |
289 | u32 sws; | |
f11bb3e2 CH |
290 | bool ext; |
291 | u8 pi_type; | |
646017a6 | 292 | unsigned long flags; |
646017a6 | 293 | #define NVME_NS_REMOVING 0 |
69d9a99c | 294 | #define NVME_NS_DEAD 1 |
57eeaf8e | 295 | u16 noiob; |
b9e03857 TT |
296 | |
297 | #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS | |
298 | struct nvme_fault_inject fault_inject; | |
299 | #endif | |
300 | ||
f11bb3e2 CH |
301 | }; |
302 | ||
1c63dc66 | 303 | struct nvme_ctrl_ops { |
1a353d85 | 304 | const char *name; |
e439bb12 | 305 | struct module *module; |
d3d5b87d CH |
306 | unsigned int flags; |
307 | #define NVME_F_FABRICS (1 << 0) | |
c81bfba9 | 308 | #define NVME_F_METADATA_SUPPORTED (1 << 1) |
1c63dc66 | 309 | int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); |
5fd4ce1b | 310 | int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); |
7fd8930f | 311 | int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); |
1673f1f0 | 312 | void (*free_ctrl)(struct nvme_ctrl *ctrl); |
ad22c355 | 313 | void (*submit_async_event)(struct nvme_ctrl *ctrl); |
c5017e85 | 314 | void (*delete_ctrl)(struct nvme_ctrl *ctrl); |
1a353d85 | 315 | int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); |
31b84460 | 316 | int (*reinit_request)(void *data, struct request *rq); |
b435ecea | 317 | void (*stop_ctrl)(struct nvme_ctrl *ctrl); |
f11bb3e2 CH |
318 | }; |
319 | ||
b9e03857 TT |
320 | #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS |
321 | void nvme_fault_inject_init(struct nvme_ns *ns); | |
322 | void nvme_fault_inject_fini(struct nvme_ns *ns); | |
323 | void nvme_should_fail(struct request *req); | |
324 | #else | |
325 | static inline void nvme_fault_inject_init(struct nvme_ns *ns) {} | |
326 | static inline void nvme_fault_inject_fini(struct nvme_ns *ns) {} | |
327 | static inline void nvme_should_fail(struct request *req) {} | |
328 | #endif | |
329 | ||
1c63dc66 CH |
330 | static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl) |
331 | { | |
332 | u32 val = 0; | |
333 | ||
334 | if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val)) | |
335 | return false; | |
336 | return val & NVME_CSTS_RDY; | |
337 | } | |
338 | ||
f3ca80fc CH |
339 | static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) |
340 | { | |
341 | if (!ctrl->subsystem) | |
342 | return -ENOTTY; | |
343 | return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); | |
344 | } | |
345 | ||
f11bb3e2 CH |
346 | static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector) |
347 | { | |
348 | return (sector >> (ns->lba_shift - 9)); | |
349 | } | |
350 | ||
6904242d ML |
351 | static inline void nvme_cleanup_cmd(struct request *req) |
352 | { | |
f9d03f96 CH |
353 | if (req->rq_flags & RQF_SPECIAL_PAYLOAD) { |
354 | kfree(page_address(req->special_vec.bv_page) + | |
355 | req->special_vec.bv_offset); | |
356 | } | |
6904242d ML |
357 | } |
358 | ||
27fa9bc5 CH |
359 | static inline void nvme_end_request(struct request *req, __le16 status, |
360 | union nvme_result result) | |
15a190f7 | 361 | { |
27fa9bc5 | 362 | struct nvme_request *rq = nvme_req(req); |
15a190f7 | 363 | |
27fa9bc5 CH |
364 | rq->status = le16_to_cpu(status) >> 1; |
365 | rq->result = result; | |
b9e03857 TT |
366 | /* inject error when permitted by fault injection framework */ |
367 | nvme_should_fail(req); | |
08e0029a | 368 | blk_mq_complete_request(req); |
7688faa6 CH |
369 | } |
370 | ||
d22524a4 CH |
371 | static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl) |
372 | { | |
373 | get_device(ctrl->device); | |
374 | } | |
375 | ||
376 | static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl) | |
377 | { | |
378 | put_device(ctrl->device); | |
379 | } | |
380 | ||
77f02a7a | 381 | void nvme_complete_rq(struct request *req); |
c55a2fd4 | 382 | void nvme_cancel_request(struct request *req, void *data, bool reserved); |
bb8d261e CH |
383 | bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, |
384 | enum nvme_ctrl_state new_state); | |
5fd4ce1b CH |
385 | int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap); |
386 | int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap); | |
387 | int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl); | |
f3ca80fc CH |
388 | int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, |
389 | const struct nvme_ctrl_ops *ops, unsigned long quirks); | |
53029b04 | 390 | void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); |
d09f2b45 SG |
391 | void nvme_start_ctrl(struct nvme_ctrl *ctrl); |
392 | void nvme_stop_ctrl(struct nvme_ctrl *ctrl); | |
1673f1f0 | 393 | void nvme_put_ctrl(struct nvme_ctrl *ctrl); |
7fd8930f | 394 | int nvme_init_identify(struct nvme_ctrl *ctrl); |
5bae7f73 | 395 | |
5955be21 | 396 | void nvme_queue_scan(struct nvme_ctrl *ctrl); |
5bae7f73 | 397 | void nvme_remove_namespaces(struct nvme_ctrl *ctrl); |
1673f1f0 | 398 | |
4f1244c8 CH |
399 | int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len, |
400 | bool send); | |
a98e58e5 | 401 | |
7bf58533 CH |
402 | void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, |
403 | union nvme_result *res); | |
f866fc42 | 404 | |
25646264 KB |
405 | void nvme_stop_queues(struct nvme_ctrl *ctrl); |
406 | void nvme_start_queues(struct nvme_ctrl *ctrl); | |
69d9a99c | 407 | void nvme_kill_queues(struct nvme_ctrl *ctrl); |
302ad8cc KB |
408 | void nvme_unfreeze(struct nvme_ctrl *ctrl); |
409 | void nvme_wait_freeze(struct nvme_ctrl *ctrl); | |
410 | void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout); | |
411 | void nvme_start_freeze(struct nvme_ctrl *ctrl); | |
31b84460 | 412 | int nvme_reinit_tagset(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set); |
363c9aac | 413 | |
eb71f435 | 414 | #define NVME_QID_ANY -1 |
4160982e | 415 | struct request *nvme_alloc_request(struct request_queue *q, |
9a95e4ef | 416 | struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid); |
fc17b653 | 417 | blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req, |
8093f7ca | 418 | struct nvme_command *cmd); |
f11bb3e2 CH |
419 | int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
420 | void *buf, unsigned bufflen); | |
421 | int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, | |
d49187e9 | 422 | union nvme_result *result, void *buffer, unsigned bufflen, |
9a95e4ef BVA |
423 | unsigned timeout, int qid, int at_head, |
424 | blk_mq_req_flags_t flags); | |
9a0be7ab | 425 | int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); |
038bd4cb | 426 | void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); |
d86c4d8e | 427 | int nvme_reset_ctrl(struct nvme_ctrl *ctrl); |
79c48ccf | 428 | int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl); |
c5017e85 CH |
429 | int nvme_delete_ctrl(struct nvme_ctrl *ctrl); |
430 | int nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl); | |
f11bb3e2 | 431 | |
d558fb51 | 432 | int nvme_get_log_ext(struct nvme_ctrl *ctrl, struct nvme_ns *ns, |
7ec6074f | 433 | u8 log_page, void *log, size_t size, u64 offset); |
d558fb51 | 434 | |
5b85b826 | 435 | extern const struct attribute_group nvme_ns_id_attr_group; |
32acab31 CH |
436 | extern const struct block_device_operations nvme_ns_head_ops; |
437 | ||
438 | #ifdef CONFIG_NVME_MULTIPATH | |
a785dbcc KB |
439 | void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns, |
440 | struct nvme_ctrl *ctrl, int *flags); | |
32acab31 | 441 | void nvme_failover_req(struct request *req); |
908e4564 | 442 | bool nvme_req_needs_failover(struct request *req, blk_status_t error); |
32acab31 CH |
443 | void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl); |
444 | int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,struct nvme_ns_head *head); | |
445 | void nvme_mpath_add_disk(struct nvme_ns_head *head); | |
446 | void nvme_mpath_remove_disk(struct nvme_ns_head *head); | |
447 | ||
448 | static inline void nvme_mpath_clear_current_path(struct nvme_ns *ns) | |
449 | { | |
450 | struct nvme_ns_head *head = ns->head; | |
451 | ||
452 | if (head && ns == srcu_dereference(head->current_path, &head->srcu)) | |
453 | rcu_assign_pointer(head->current_path, NULL); | |
454 | } | |
455 | struct nvme_ns *nvme_find_path(struct nvme_ns_head *head); | |
479a322f SG |
456 | |
457 | static inline void nvme_mpath_check_last_path(struct nvme_ns *ns) | |
458 | { | |
459 | struct nvme_ns_head *head = ns->head; | |
460 | ||
461 | if (head->disk && list_empty(&head->list)) | |
462 | kblockd_schedule_work(&head->requeue_work); | |
463 | } | |
464 | ||
32acab31 | 465 | #else |
a785dbcc KB |
466 | /* |
467 | * Without the multipath code enabled, multiple controller per subsystems are | |
468 | * visible as devices and thus we cannot use the subsystem instance. | |
469 | */ | |
470 | static inline void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns, | |
471 | struct nvme_ctrl *ctrl, int *flags) | |
472 | { | |
473 | sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->head->instance); | |
474 | } | |
475 | ||
32acab31 CH |
476 | static inline void nvme_failover_req(struct request *req) |
477 | { | |
478 | } | |
908e4564 KB |
479 | static inline bool nvme_req_needs_failover(struct request *req, |
480 | blk_status_t error) | |
32acab31 CH |
481 | { |
482 | return false; | |
483 | } | |
484 | static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl) | |
485 | { | |
486 | } | |
487 | static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl, | |
488 | struct nvme_ns_head *head) | |
489 | { | |
490 | return 0; | |
491 | } | |
492 | static inline void nvme_mpath_add_disk(struct nvme_ns_head *head) | |
493 | { | |
494 | } | |
495 | static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head) | |
496 | { | |
497 | } | |
498 | static inline void nvme_mpath_clear_current_path(struct nvme_ns *ns) | |
479a322f SG |
499 | { |
500 | } | |
501 | static inline void nvme_mpath_check_last_path(struct nvme_ns *ns) | |
32acab31 CH |
502 | { |
503 | } | |
504 | #endif /* CONFIG_NVME_MULTIPATH */ | |
505 | ||
c4699e70 | 506 | #ifdef CONFIG_NVM |
96257a8a | 507 | void nvme_nvm_update_nvm_info(struct nvme_ns *ns); |
3dc87dd0 | 508 | int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node); |
b0b4e09c | 509 | void nvme_nvm_unregister(struct nvme_ns *ns); |
3dc87dd0 MB |
510 | int nvme_nvm_register_sysfs(struct nvme_ns *ns); |
511 | void nvme_nvm_unregister_sysfs(struct nvme_ns *ns); | |
84d4add7 | 512 | int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg); |
c4699e70 | 513 | #else |
96257a8a | 514 | static inline void nvme_nvm_update_nvm_info(struct nvme_ns *ns) {}; |
b0b4e09c | 515 | static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, |
3dc87dd0 | 516 | int node) |
c4699e70 KB |
517 | { |
518 | return 0; | |
519 | } | |
520 | ||
b0b4e09c | 521 | static inline void nvme_nvm_unregister(struct nvme_ns *ns) {}; |
3dc87dd0 MB |
522 | static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns) |
523 | { | |
524 | return 0; | |
525 | } | |
526 | static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {}; | |
84d4add7 MB |
527 | static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, |
528 | unsigned long arg) | |
529 | { | |
530 | return -ENOTTY; | |
531 | } | |
3dc87dd0 MB |
532 | #endif /* CONFIG_NVM */ |
533 | ||
40267efd SL |
534 | static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev) |
535 | { | |
536 | return dev_to_disk(dev)->private_data; | |
537 | } | |
ca064085 | 538 | |
5bae7f73 CH |
539 | int __init nvme_core_init(void); |
540 | void nvme_core_exit(void); | |
541 | ||
f11bb3e2 | 542 | #endif /* _NVME_H */ |