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f11bb3e2 CH |
1 | /* |
2 | * Copyright (c) 2011-2014, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | */ | |
13 | ||
14 | #ifndef _NVME_H | |
15 | #define _NVME_H | |
16 | ||
17 | #include <linux/nvme.h> | |
a6a5149b | 18 | #include <linux/cdev.h> |
f11bb3e2 CH |
19 | #include <linux/pci.h> |
20 | #include <linux/kref.h> | |
21 | #include <linux/blk-mq.h> | |
b0b4e09c | 22 | #include <linux/lightnvm.h> |
a98e58e5 | 23 | #include <linux/sed-opal.h> |
b9e03857 | 24 | #include <linux/fault-inject.h> |
978628ec | 25 | #include <linux/rcupdate.h> |
f11bb3e2 | 26 | |
8ae4e447 | 27 | extern unsigned int nvme_io_timeout; |
f11bb3e2 CH |
28 | #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) |
29 | ||
8ae4e447 | 30 | extern unsigned int admin_timeout; |
21d34711 CH |
31 | #define ADMIN_TIMEOUT (admin_timeout * HZ) |
32 | ||
038bd4cb SG |
33 | #define NVME_DEFAULT_KATO 5 |
34 | #define NVME_KATO_GRACE 10 | |
35 | ||
9a6327d2 | 36 | extern struct workqueue_struct *nvme_wq; |
b227c59b RS |
37 | extern struct workqueue_struct *nvme_reset_wq; |
38 | extern struct workqueue_struct *nvme_delete_wq; | |
9a6327d2 | 39 | |
ca064085 MB |
40 | enum { |
41 | NVME_NS_LBA = 0, | |
42 | NVME_NS_LIGHTNVM = 1, | |
43 | }; | |
44 | ||
f11bb3e2 | 45 | /* |
106198ed CH |
46 | * List of workarounds for devices that required behavior not specified in |
47 | * the standard. | |
f11bb3e2 | 48 | */ |
106198ed CH |
49 | enum nvme_quirks { |
50 | /* | |
51 | * Prefers I/O aligned to a stripe size specified in a vendor | |
52 | * specific Identify field. | |
53 | */ | |
54 | NVME_QUIRK_STRIPE_SIZE = (1 << 0), | |
540c801c KB |
55 | |
56 | /* | |
57 | * The controller doesn't handle Identify value others than 0 or 1 | |
58 | * correctly. | |
59 | */ | |
60 | NVME_QUIRK_IDENTIFY_CNS = (1 << 1), | |
08095e70 KB |
61 | |
62 | /* | |
e850fd16 CH |
63 | * The controller deterministically returns O's on reads to |
64 | * logical blocks that deallocate was called on. | |
08095e70 | 65 | */ |
e850fd16 | 66 | NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2), |
54adc010 GP |
67 | |
68 | /* | |
69 | * The controller needs a delay before starts checking the device | |
70 | * readiness, which is done by reading the NVME_CSTS_RDY bit. | |
71 | */ | |
72 | NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), | |
c5552fde AL |
73 | |
74 | /* | |
75 | * APST should not be used. | |
76 | */ | |
77 | NVME_QUIRK_NO_APST = (1 << 4), | |
ff5350a8 AL |
78 | |
79 | /* | |
80 | * The deepest sleep state should not be used. | |
81 | */ | |
82 | NVME_QUIRK_NO_DEEPEST_PS = (1 << 5), | |
608cc4b1 CH |
83 | |
84 | /* | |
85 | * Supports the LighNVM command set if indicated in vs[1]. | |
86 | */ | |
87 | NVME_QUIRK_LIGHTNVM = (1 << 6), | |
9abd68ef JA |
88 | |
89 | /* | |
90 | * Set MEDIUM priority on SQ creation | |
91 | */ | |
92 | NVME_QUIRK_MEDIUM_PRIO_SQ = (1 << 7), | |
6299358d JD |
93 | |
94 | /* | |
95 | * Ignore device provided subnqn. | |
96 | */ | |
97 | NVME_QUIRK_IGNORE_DEV_SUBNQN = (1 << 8), | |
106198ed CH |
98 | }; |
99 | ||
d49187e9 CH |
100 | /* |
101 | * Common request structure for NVMe passthrough. All drivers must have | |
102 | * this structure as the first member of their request-private data. | |
103 | */ | |
104 | struct nvme_request { | |
105 | struct nvme_command *cmd; | |
106 | union nvme_result result; | |
44e44b29 | 107 | u8 retries; |
27fa9bc5 CH |
108 | u8 flags; |
109 | u16 status; | |
59e29ce6 | 110 | struct nvme_ctrl *ctrl; |
27fa9bc5 CH |
111 | }; |
112 | ||
32acab31 CH |
113 | /* |
114 | * Mark a bio as coming in through the mpath node. | |
115 | */ | |
116 | #define REQ_NVME_MPATH REQ_DRV | |
117 | ||
27fa9bc5 CH |
118 | enum { |
119 | NVME_REQ_CANCELLED = (1 << 0), | |
bb06ec31 | 120 | NVME_REQ_USERCMD = (1 << 1), |
d49187e9 CH |
121 | }; |
122 | ||
123 | static inline struct nvme_request *nvme_req(struct request *req) | |
124 | { | |
125 | return blk_mq_rq_to_pdu(req); | |
126 | } | |
127 | ||
5d87eb94 KB |
128 | static inline u16 nvme_req_qid(struct request *req) |
129 | { | |
130 | if (!req->rq_disk) | |
131 | return 0; | |
132 | return blk_mq_unique_tag_to_hwq(blk_mq_unique_tag(req)) + 1; | |
133 | } | |
134 | ||
54adc010 GP |
135 | /* The below value is the specific amount of delay needed before checking |
136 | * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the | |
137 | * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was | |
138 | * found empirically. | |
139 | */ | |
8c97eecc | 140 | #define NVME_QUIRK_DELAY_AMOUNT 2300 |
54adc010 | 141 | |
bb8d261e CH |
142 | enum nvme_ctrl_state { |
143 | NVME_CTRL_NEW, | |
144 | NVME_CTRL_LIVE, | |
2b1b7e78 | 145 | NVME_CTRL_ADMIN_ONLY, /* Only admin queue live */ |
bb8d261e | 146 | NVME_CTRL_RESETTING, |
ad6a0a52 | 147 | NVME_CTRL_CONNECTING, |
bb8d261e | 148 | NVME_CTRL_DELETING, |
0ff9d4e1 | 149 | NVME_CTRL_DEAD, |
bb8d261e CH |
150 | }; |
151 | ||
1c63dc66 | 152 | struct nvme_ctrl { |
6e3ca03e | 153 | bool comp_seen; |
bb8d261e | 154 | enum nvme_ctrl_state state; |
bd4da3ab | 155 | bool identified; |
bb8d261e | 156 | spinlock_t lock; |
e7ad43c3 | 157 | struct mutex scan_lock; |
1c63dc66 | 158 | const struct nvme_ctrl_ops *ops; |
f11bb3e2 | 159 | struct request_queue *admin_q; |
07bfcd09 | 160 | struct request_queue *connect_q; |
f11bb3e2 | 161 | struct device *dev; |
f11bb3e2 | 162 | int instance; |
103e515e | 163 | int numa_node; |
5bae7f73 | 164 | struct blk_mq_tag_set *tagset; |
34b6c231 | 165 | struct blk_mq_tag_set *admin_tagset; |
f11bb3e2 | 166 | struct list_head namespaces; |
765cc031 | 167 | struct rw_semaphore namespaces_rwsem; |
d22524a4 | 168 | struct device ctrl_device; |
5bae7f73 | 169 | struct device *device; /* char device */ |
a6a5149b | 170 | struct cdev cdev; |
d86c4d8e | 171 | struct work_struct reset_work; |
c5017e85 | 172 | struct work_struct delete_work; |
1c63dc66 | 173 | |
ab9e00cc CH |
174 | struct nvme_subsystem *subsys; |
175 | struct list_head subsys_entry; | |
176 | ||
4f1244c8 | 177 | struct opal_dev *opal_dev; |
a98e58e5 | 178 | |
f11bb3e2 | 179 | char name[12]; |
76e3914a | 180 | u16 cntlid; |
5fd4ce1b CH |
181 | |
182 | u32 ctrl_config; | |
b6dccf7f | 183 | u16 mtfa; |
d858e5f0 | 184 | u32 queue_count; |
5fd4ce1b | 185 | |
20d0dfe6 | 186 | u64 cap; |
5fd4ce1b | 187 | u32 page_size; |
f11bb3e2 | 188 | u32 max_hw_sectors; |
943e942e | 189 | u32 max_segments; |
49cd84b6 | 190 | u16 crdt[3]; |
f11bb3e2 | 191 | u16 oncs; |
8a9ae523 | 192 | u16 oacs; |
f5d11840 JA |
193 | u16 nssa; |
194 | u16 nr_streams; | |
0d0b660f | 195 | u32 max_namespaces; |
6bf25d16 | 196 | atomic_t abort_limit; |
f11bb3e2 | 197 | u8 vwc; |
f3ca80fc | 198 | u32 vs; |
07bfcd09 | 199 | u32 sgls; |
038bd4cb | 200 | u16 kas; |
c5552fde AL |
201 | u8 npss; |
202 | u8 apsta; | |
c0561f82 | 203 | u32 oaes; |
e3d7874d | 204 | u32 aen_result; |
3e53ba38 | 205 | u32 ctratt; |
07fbd32a | 206 | unsigned int shutdown_timeout; |
038bd4cb | 207 | unsigned int kato; |
f3ca80fc | 208 | bool subsystem; |
106198ed | 209 | unsigned long quirks; |
c5552fde | 210 | struct nvme_id_power_state psd[32]; |
84fef62d | 211 | struct nvme_effects_log *effects; |
5955be21 | 212 | struct work_struct scan_work; |
f866fc42 | 213 | struct work_struct async_event_work; |
038bd4cb | 214 | struct delayed_work ka_work; |
0a34e466 | 215 | struct nvme_command ka_cmd; |
b6dccf7f | 216 | struct work_struct fw_act_work; |
30d90964 | 217 | unsigned long events; |
07bfcd09 | 218 | |
0d0b660f CH |
219 | #ifdef CONFIG_NVME_MULTIPATH |
220 | /* asymmetric namespace access: */ | |
221 | u8 anacap; | |
222 | u8 anatt; | |
223 | u32 anagrpmax; | |
224 | u32 nanagrpid; | |
225 | struct mutex ana_lock; | |
226 | struct nvme_ana_rsp_hdr *ana_log_buf; | |
227 | size_t ana_log_size; | |
228 | struct timer_list anatt_timer; | |
229 | struct work_struct ana_work; | |
230 | #endif | |
231 | ||
c5552fde AL |
232 | /* Power saving configuration */ |
233 | u64 ps_max_latency_us; | |
76a5af84 | 234 | bool apst_enabled; |
c5552fde | 235 | |
044a9df1 | 236 | /* PCIe only: */ |
fe6d53c9 CH |
237 | u32 hmpre; |
238 | u32 hmmin; | |
044a9df1 CH |
239 | u32 hmminds; |
240 | u16 hmmaxd; | |
fe6d53c9 | 241 | |
07bfcd09 CH |
242 | /* Fabrics only */ |
243 | u16 sqsize; | |
244 | u32 ioccsz; | |
245 | u32 iorcsz; | |
246 | u16 icdoff; | |
247 | u16 maxcmd; | |
fdf9dfa8 | 248 | int nr_reconnects; |
07bfcd09 | 249 | struct nvmf_ctrl_options *opts; |
cb5b7262 JA |
250 | |
251 | struct page *discard_page; | |
252 | unsigned long discard_page_busy; | |
f11bb3e2 CH |
253 | }; |
254 | ||
ab9e00cc CH |
255 | struct nvme_subsystem { |
256 | int instance; | |
257 | struct device dev; | |
258 | /* | |
259 | * Because we unregister the device on the last put we need | |
260 | * a separate refcount. | |
261 | */ | |
262 | struct kref ref; | |
263 | struct list_head entry; | |
264 | struct mutex lock; | |
265 | struct list_head ctrls; | |
ed754e5d | 266 | struct list_head nsheads; |
ab9e00cc CH |
267 | char subnqn[NVMF_NQN_SIZE]; |
268 | char serial[20]; | |
269 | char model[40]; | |
270 | char firmware_rev[8]; | |
271 | u8 cmic; | |
272 | u16 vendor_id; | |
ed754e5d | 273 | struct ida ns_ida; |
ab9e00cc CH |
274 | }; |
275 | ||
002fab04 CH |
276 | /* |
277 | * Container structure for uniqueue namespace identifiers. | |
278 | */ | |
279 | struct nvme_ns_ids { | |
280 | u8 eui64[8]; | |
281 | u8 nguid[16]; | |
282 | uuid_t uuid; | |
283 | }; | |
284 | ||
ed754e5d CH |
285 | /* |
286 | * Anchor structure for namespaces. There is one for each namespace in a | |
287 | * NVMe subsystem that any of our controllers can see, and the namespace | |
288 | * structure for each controller is chained of it. For private namespaces | |
289 | * there is a 1:1 relation to our namespace structures, that is ->list | |
290 | * only ever has a single entry for private namespaces. | |
291 | */ | |
292 | struct nvme_ns_head { | |
293 | struct list_head list; | |
294 | struct srcu_struct srcu; | |
295 | struct nvme_subsystem *subsys; | |
296 | unsigned ns_id; | |
297 | struct nvme_ns_ids ids; | |
298 | struct list_head entry; | |
299 | struct kref ref; | |
300 | int instance; | |
f3334447 CH |
301 | #ifdef CONFIG_NVME_MULTIPATH |
302 | struct gendisk *disk; | |
303 | struct bio_list requeue_list; | |
304 | spinlock_t requeue_lock; | |
305 | struct work_struct requeue_work; | |
306 | struct mutex lock; | |
307 | struct nvme_ns __rcu *current_path[]; | |
308 | #endif | |
ed754e5d CH |
309 | }; |
310 | ||
b9e03857 TT |
311 | #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS |
312 | struct nvme_fault_inject { | |
313 | struct fault_attr attr; | |
314 | struct dentry *parent; | |
315 | bool dont_retry; /* DNR, do not retry */ | |
316 | u16 status; /* status code */ | |
317 | }; | |
318 | #endif | |
319 | ||
f11bb3e2 CH |
320 | struct nvme_ns { |
321 | struct list_head list; | |
322 | ||
1c63dc66 | 323 | struct nvme_ctrl *ctrl; |
f11bb3e2 CH |
324 | struct request_queue *queue; |
325 | struct gendisk *disk; | |
0d0b660f CH |
326 | #ifdef CONFIG_NVME_MULTIPATH |
327 | enum nvme_ana_state ana_state; | |
328 | u32 ana_grpid; | |
329 | #endif | |
ed754e5d | 330 | struct list_head siblings; |
b0b4e09c | 331 | struct nvm_dev *ndev; |
f11bb3e2 | 332 | struct kref kref; |
ed754e5d | 333 | struct nvme_ns_head *head; |
f11bb3e2 | 334 | |
f11bb3e2 CH |
335 | int lba_shift; |
336 | u16 ms; | |
f5d11840 JA |
337 | u16 sgs; |
338 | u32 sws; | |
f11bb3e2 CH |
339 | bool ext; |
340 | u8 pi_type; | |
646017a6 | 341 | unsigned long flags; |
0d0b660f CH |
342 | #define NVME_NS_REMOVING 0 |
343 | #define NVME_NS_DEAD 1 | |
344 | #define NVME_NS_ANA_PENDING 2 | |
57eeaf8e | 345 | u16 noiob; |
b9e03857 TT |
346 | |
347 | #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS | |
348 | struct nvme_fault_inject fault_inject; | |
349 | #endif | |
350 | ||
f11bb3e2 CH |
351 | }; |
352 | ||
1c63dc66 | 353 | struct nvme_ctrl_ops { |
1a353d85 | 354 | const char *name; |
e439bb12 | 355 | struct module *module; |
d3d5b87d CH |
356 | unsigned int flags; |
357 | #define NVME_F_FABRICS (1 << 0) | |
c81bfba9 | 358 | #define NVME_F_METADATA_SUPPORTED (1 << 1) |
e0596ab2 | 359 | #define NVME_F_PCI_P2PDMA (1 << 2) |
1c63dc66 | 360 | int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); |
5fd4ce1b | 361 | int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); |
7fd8930f | 362 | int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); |
1673f1f0 | 363 | void (*free_ctrl)(struct nvme_ctrl *ctrl); |
ad22c355 | 364 | void (*submit_async_event)(struct nvme_ctrl *ctrl); |
c5017e85 | 365 | void (*delete_ctrl)(struct nvme_ctrl *ctrl); |
1a353d85 | 366 | int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); |
b435ecea | 367 | void (*stop_ctrl)(struct nvme_ctrl *ctrl); |
f11bb3e2 CH |
368 | }; |
369 | ||
b9e03857 TT |
370 | #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS |
371 | void nvme_fault_inject_init(struct nvme_ns *ns); | |
372 | void nvme_fault_inject_fini(struct nvme_ns *ns); | |
373 | void nvme_should_fail(struct request *req); | |
374 | #else | |
375 | static inline void nvme_fault_inject_init(struct nvme_ns *ns) {} | |
376 | static inline void nvme_fault_inject_fini(struct nvme_ns *ns) {} | |
377 | static inline void nvme_should_fail(struct request *req) {} | |
378 | #endif | |
379 | ||
f3ca80fc CH |
380 | static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) |
381 | { | |
382 | if (!ctrl->subsystem) | |
383 | return -ENOTTY; | |
384 | return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); | |
385 | } | |
386 | ||
f11bb3e2 CH |
387 | static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector) |
388 | { | |
389 | return (sector >> (ns->lba_shift - 9)); | |
390 | } | |
391 | ||
27fa9bc5 CH |
392 | static inline void nvme_end_request(struct request *req, __le16 status, |
393 | union nvme_result result) | |
15a190f7 | 394 | { |
27fa9bc5 | 395 | struct nvme_request *rq = nvme_req(req); |
15a190f7 | 396 | |
27fa9bc5 CH |
397 | rq->status = le16_to_cpu(status) >> 1; |
398 | rq->result = result; | |
b9e03857 TT |
399 | /* inject error when permitted by fault injection framework */ |
400 | nvme_should_fail(req); | |
08e0029a | 401 | blk_mq_complete_request(req); |
7688faa6 CH |
402 | } |
403 | ||
d22524a4 CH |
404 | static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl) |
405 | { | |
406 | get_device(ctrl->device); | |
407 | } | |
408 | ||
409 | static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl) | |
410 | { | |
411 | put_device(ctrl->device); | |
412 | } | |
413 | ||
77f02a7a | 414 | void nvme_complete_rq(struct request *req); |
7baa8572 | 415 | bool nvme_cancel_request(struct request *req, void *data, bool reserved); |
bb8d261e CH |
416 | bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, |
417 | enum nvme_ctrl_state new_state); | |
5fd4ce1b CH |
418 | int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap); |
419 | int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap); | |
420 | int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl); | |
f3ca80fc CH |
421 | int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, |
422 | const struct nvme_ctrl_ops *ops, unsigned long quirks); | |
53029b04 | 423 | void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); |
d09f2b45 SG |
424 | void nvme_start_ctrl(struct nvme_ctrl *ctrl); |
425 | void nvme_stop_ctrl(struct nvme_ctrl *ctrl); | |
1673f1f0 | 426 | void nvme_put_ctrl(struct nvme_ctrl *ctrl); |
7fd8930f | 427 | int nvme_init_identify(struct nvme_ctrl *ctrl); |
5bae7f73 | 428 | |
5bae7f73 | 429 | void nvme_remove_namespaces(struct nvme_ctrl *ctrl); |
1673f1f0 | 430 | |
4f1244c8 CH |
431 | int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len, |
432 | bool send); | |
a98e58e5 | 433 | |
7bf58533 | 434 | void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, |
287a63eb | 435 | volatile union nvme_result *res); |
f866fc42 | 436 | |
25646264 KB |
437 | void nvme_stop_queues(struct nvme_ctrl *ctrl); |
438 | void nvme_start_queues(struct nvme_ctrl *ctrl); | |
69d9a99c | 439 | void nvme_kill_queues(struct nvme_ctrl *ctrl); |
302ad8cc KB |
440 | void nvme_unfreeze(struct nvme_ctrl *ctrl); |
441 | void nvme_wait_freeze(struct nvme_ctrl *ctrl); | |
442 | void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout); | |
443 | void nvme_start_freeze(struct nvme_ctrl *ctrl); | |
363c9aac | 444 | |
eb71f435 | 445 | #define NVME_QID_ANY -1 |
4160982e | 446 | struct request *nvme_alloc_request(struct request_queue *q, |
9a95e4ef | 447 | struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid); |
f7f1fc36 | 448 | void nvme_cleanup_cmd(struct request *req); |
fc17b653 | 449 | blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req, |
8093f7ca | 450 | struct nvme_command *cmd); |
f11bb3e2 CH |
451 | int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
452 | void *buf, unsigned bufflen); | |
453 | int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, | |
d49187e9 | 454 | union nvme_result *result, void *buffer, unsigned bufflen, |
9a95e4ef | 455 | unsigned timeout, int qid, int at_head, |
6287b51c | 456 | blk_mq_req_flags_t flags, bool poll); |
9a0be7ab | 457 | int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); |
038bd4cb | 458 | void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); |
d86c4d8e | 459 | int nvme_reset_ctrl(struct nvme_ctrl *ctrl); |
79c48ccf | 460 | int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl); |
c5017e85 CH |
461 | int nvme_delete_ctrl(struct nvme_ctrl *ctrl); |
462 | int nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl); | |
f11bb3e2 | 463 | |
0e98719b CH |
464 | int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, |
465 | void *log, size_t size, u64 offset); | |
d558fb51 | 466 | |
33b14f67 | 467 | extern const struct attribute_group *nvme_ns_id_attr_groups[]; |
32acab31 CH |
468 | extern const struct block_device_operations nvme_ns_head_ops; |
469 | ||
470 | #ifdef CONFIG_NVME_MULTIPATH | |
0d0b660f | 471 | bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl); |
a785dbcc KB |
472 | void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns, |
473 | struct nvme_ctrl *ctrl, int *flags); | |
32acab31 | 474 | void nvme_failover_req(struct request *req); |
32acab31 CH |
475 | void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl); |
476 | int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,struct nvme_ns_head *head); | |
0d0b660f | 477 | void nvme_mpath_add_disk(struct nvme_ns *ns, struct nvme_id_ns *id); |
32acab31 | 478 | void nvme_mpath_remove_disk(struct nvme_ns_head *head); |
0d0b660f CH |
479 | int nvme_mpath_init(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id); |
480 | void nvme_mpath_uninit(struct nvme_ctrl *ctrl); | |
481 | void nvme_mpath_stop(struct nvme_ctrl *ctrl); | |
f3334447 | 482 | void nvme_mpath_clear_current_path(struct nvme_ns *ns); |
32acab31 | 483 | struct nvme_ns *nvme_find_path(struct nvme_ns_head *head); |
479a322f SG |
484 | |
485 | static inline void nvme_mpath_check_last_path(struct nvme_ns *ns) | |
486 | { | |
487 | struct nvme_ns_head *head = ns->head; | |
488 | ||
489 | if (head->disk && list_empty(&head->list)) | |
490 | kblockd_schedule_work(&head->requeue_work); | |
491 | } | |
492 | ||
0d0b660f CH |
493 | extern struct device_attribute dev_attr_ana_grpid; |
494 | extern struct device_attribute dev_attr_ana_state; | |
495 | ||
32acab31 | 496 | #else |
0d0b660f CH |
497 | static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) |
498 | { | |
499 | return false; | |
500 | } | |
a785dbcc KB |
501 | /* |
502 | * Without the multipath code enabled, multiple controller per subsystems are | |
503 | * visible as devices and thus we cannot use the subsystem instance. | |
504 | */ | |
505 | static inline void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns, | |
506 | struct nvme_ctrl *ctrl, int *flags) | |
507 | { | |
508 | sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->head->instance); | |
509 | } | |
510 | ||
32acab31 CH |
511 | static inline void nvme_failover_req(struct request *req) |
512 | { | |
513 | } | |
32acab31 CH |
514 | static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl) |
515 | { | |
516 | } | |
517 | static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl, | |
518 | struct nvme_ns_head *head) | |
519 | { | |
520 | return 0; | |
521 | } | |
0d0b660f CH |
522 | static inline void nvme_mpath_add_disk(struct nvme_ns *ns, |
523 | struct nvme_id_ns *id) | |
32acab31 CH |
524 | { |
525 | } | |
526 | static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head) | |
527 | { | |
528 | } | |
529 | static inline void nvme_mpath_clear_current_path(struct nvme_ns *ns) | |
479a322f SG |
530 | { |
531 | } | |
532 | static inline void nvme_mpath_check_last_path(struct nvme_ns *ns) | |
32acab31 CH |
533 | { |
534 | } | |
0d0b660f CH |
535 | static inline int nvme_mpath_init(struct nvme_ctrl *ctrl, |
536 | struct nvme_id_ctrl *id) | |
537 | { | |
14a1336e CH |
538 | if (ctrl->subsys->cmic & (1 << 3)) |
539 | dev_warn(ctrl->device, | |
540 | "Please enable CONFIG_NVME_MULTIPATH for full support of multi-port devices.\n"); | |
0d0b660f CH |
541 | return 0; |
542 | } | |
543 | static inline void nvme_mpath_uninit(struct nvme_ctrl *ctrl) | |
544 | { | |
545 | } | |
546 | static inline void nvme_mpath_stop(struct nvme_ctrl *ctrl) | |
547 | { | |
548 | } | |
32acab31 CH |
549 | #endif /* CONFIG_NVME_MULTIPATH */ |
550 | ||
c4699e70 | 551 | #ifdef CONFIG_NVM |
3dc87dd0 | 552 | int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node); |
b0b4e09c | 553 | void nvme_nvm_unregister(struct nvme_ns *ns); |
33b14f67 | 554 | extern const struct attribute_group nvme_nvm_attr_group; |
84d4add7 | 555 | int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg); |
c4699e70 | 556 | #else |
b0b4e09c | 557 | static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, |
3dc87dd0 | 558 | int node) |
c4699e70 KB |
559 | { |
560 | return 0; | |
561 | } | |
562 | ||
b0b4e09c | 563 | static inline void nvme_nvm_unregister(struct nvme_ns *ns) {}; |
84d4add7 MB |
564 | static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, |
565 | unsigned long arg) | |
566 | { | |
567 | return -ENOTTY; | |
568 | } | |
3dc87dd0 MB |
569 | #endif /* CONFIG_NVM */ |
570 | ||
40267efd SL |
571 | static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev) |
572 | { | |
573 | return dev_to_disk(dev)->private_data; | |
574 | } | |
ca064085 | 575 | |
5bae7f73 | 576 | int __init nvme_core_init(void); |
8eb5d89f | 577 | void __exit nvme_core_exit(void); |
5bae7f73 | 578 | |
f11bb3e2 | 579 | #endif /* _NVME_H */ |