[mirror_ubuntu-bionic-kernel.git] / drivers / nvme / host / nvme.h

/*
 * Copyright (c) 2011-2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef _NVME_H
#define _NVME_H

#include <linux/nvme.h>
#include <linux/pci.h>
#include <linux/kref.h>
#include <linux/blk-mq.h>
#include <linux/lightnvm.h>
#include <linux/sed-opal.h>

extern unsigned char nvme_io_timeout;
#define NVME_IO_TIMEOUT	(nvme_io_timeout * HZ)

extern unsigned char admin_timeout;
#define ADMIN_TIMEOUT	(admin_timeout * HZ)

#define NVME_DEFAULT_KATO	5
#define NVME_KATO_GRACE		10

extern struct workqueue_struct *nvme_wq;

enum {
	NVME_NS_LBA		= 0,
	NVME_NS_LIGHTNVM	= 1,
};

/*
 * List of workarounds for devices that required behavior not specified in
 * the standard.
 */
enum nvme_quirks {
	/*
	 * Prefers I/O aligned to a stripe size specified in a vendor
	 * specific Identify field.
	 */
	NVME_QUIRK_STRIPE_SIZE			= (1 << 0),

	/*
	 * The controller doesn't handle Identify value others than 0 or 1
	 * correctly.
	 */
	NVME_QUIRK_IDENTIFY_CNS			= (1 << 1),

	/*
	 * The controller deterministically returns O's on reads to
	 * logical blocks that deallocate was called on.
	 */
	NVME_QUIRK_DEALLOCATE_ZEROES		= (1 << 2),

	/*
	 * The controller needs a delay before starts checking the device
	 * readiness, which is done by reading the NVME_CSTS_RDY bit.
	 */
	NVME_QUIRK_DELAY_BEFORE_CHK_RDY		= (1 << 3),

	/*
	 * APST should not be used.
	 */
	NVME_QUIRK_NO_APST			= (1 << 4),

	/*
	 * The deepest sleep state should not be used.
	 */
	NVME_QUIRK_NO_DEEPEST_PS		= (1 << 5),
};

/*
 * Common request structure for NVMe passthrough.  All drivers must have
 * this structure as the first member of their request-private data.
 */
struct nvme_request {
	struct nvme_command	*cmd;
	union nvme_result	result;
	u8			retries;
	u8			flags;
	u16			status;
};

enum {
	NVME_REQ_CANCELLED		= (1 << 0),
};

static inline struct nvme_request *nvme_req(struct request *req)
{
	return blk_mq_rq_to_pdu(req);
}

/* The below value is the specific amount of delay needed before checking
 * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
 * found empirically.
 */
#define NVME_QUIRK_DELAY_AMOUNT		2000

enum nvme_ctrl_state {
	NVME_CTRL_NEW,
	NVME_CTRL_LIVE,
	NVME_CTRL_RESETTING,
	NVME_CTRL_RECONNECTING,
	NVME_CTRL_DELETING,
	NVME_CTRL_DEAD,
};

struct nvme_ctrl {
	enum nvme_ctrl_state state;
	bool identified;
	spinlock_t lock;
	const struct nvme_ctrl_ops *ops;
	struct request_queue *admin_q;
	struct request_queue *connect_q;
	struct device *dev;
	struct kref kref;
	int instance;
	struct blk_mq_tag_set *tagset;
	struct blk_mq_tag_set *admin_tagset;
	struct list_head namespaces;
	struct mutex namespaces_mutex;
	struct device *device;	/* char device */
	struct list_head node;
	struct ida ns_ida;
	struct work_struct reset_work;

	struct opal_dev *opal_dev;

	char name[12];
	char serial[20];
	char model[40];
	char firmware_rev[8];
	char subnqn[NVMF_NQN_SIZE];
	u16 cntlid;

	u32 ctrl_config;
	u16 mtfa;
	u32 queue_count;

	u64 cap;
	u32 page_size;
	u32 max_hw_sectors;
	u16 oncs;
	u16 vid;
	u16 oacs;
	u16 nssa;
	u16 nr_streams;
	atomic_t abort_limit;
	u8 event_limit;
	u8 vwc;
	u32 vs;
	u32 sgls;
	u16 kas;
	u8 npss;
	u8 apsta;
	unsigned int kato;
	bool subsystem;
	unsigned long quirks;
	struct nvme_id_power_state psd[32];
	struct work_struct scan_work;
	struct work_struct async_event_work;
	struct delayed_work ka_work;
	struct work_struct fw_act_work;

	/* Power saving configuration */
	u64 ps_max_latency_us;
	bool apst_enabled;

	u32 hmpre;
	u32 hmmin;

	/* Fabrics only */
	u16 sqsize;
	u32 ioccsz;
	u32 iorcsz;
	u16 icdoff;
	u16 maxcmd;
	int nr_reconnects;
	struct nvmf_ctrl_options *opts;
};

struct nvme_ns {
	struct list_head list;

	struct nvme_ctrl *ctrl;
	struct request_queue *queue;
	struct gendisk *disk;
	struct nvm_dev *ndev;
	struct kref kref;
	int instance;

	u8 eui[8];
	u8 nguid[16];
	uuid_t uuid;

	unsigned ns_id;
	int lba_shift;
	u16 ms;
	u16 sgs;
	u32 sws;
	bool ext;
	u8 pi_type;
	unsigned long flags;
	u16 noiob;

#define NVME_NS_REMOVING 0
#define NVME_NS_DEAD     1

	u64 mode_select_num_blocks;
	u32 mode_select_block_len;
};

struct nvme_ctrl_ops {
	const char *name;
	struct module *module;
	unsigned int flags;
#define NVME_F_FABRICS			(1 << 0)
#define NVME_F_METADATA_SUPPORTED	(1 << 1)
	int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val);
	int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val);
	int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val);
	void (*free_ctrl)(struct nvme_ctrl *ctrl);
	void (*submit_async_event)(struct nvme_ctrl *ctrl, int aer_idx);
	int (*delete_ctrl)(struct nvme_ctrl *ctrl);
	int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size);
};

static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
{
	u32 val = 0;

	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
		return false;
	return val & NVME_CSTS_RDY;
}

static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
{
	if (!ctrl->subsystem)
		return -ENOTTY;
	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
}

static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
{
	return (sector >> (ns->lba_shift - 9));
}

static inline void nvme_cleanup_cmd(struct request *req)
{
	if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
		kfree(page_address(req->special_vec.bv_page) +
		      req->special_vec.bv_offset);
	}
}

static inline void nvme_end_request(struct request *req, __le16 status,
		union nvme_result result)
{
	struct nvme_request *rq = nvme_req(req);

	rq->status = le16_to_cpu(status) >> 1;
	rq->result = result;
	blk_mq_complete_request(req);
}

void nvme_complete_rq(struct request *req);
void nvme_cancel_request(struct request *req, void *data, bool reserved);
bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
		enum nvme_ctrl_state new_state);
int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
		const struct nvme_ctrl_ops *ops, unsigned long quirks);
void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
void nvme_start_ctrl(struct nvme_ctrl *ctrl);
void nvme_stop_ctrl(struct nvme_ctrl *ctrl);
void nvme_put_ctrl(struct nvme_ctrl *ctrl);
int nvme_init_identify(struct nvme_ctrl *ctrl);

void nvme_queue_scan(struct nvme_ctrl *ctrl);
void nvme_remove_namespaces(struct nvme_ctrl *ctrl);

int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
		bool send);

#define NVME_NR_AERS	1
void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
		union nvme_result *res);
void nvme_queue_async_events(struct nvme_ctrl *ctrl);

void nvme_stop_queues(struct nvme_ctrl *ctrl);
void nvme_start_queues(struct nvme_ctrl *ctrl);
void nvme_kill_queues(struct nvme_ctrl *ctrl);
void nvme_unfreeze(struct nvme_ctrl *ctrl);
void nvme_wait_freeze(struct nvme_ctrl *ctrl);
void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
void nvme_start_freeze(struct nvme_ctrl *ctrl);

#define NVME_QID_ANY -1
struct request *nvme_alloc_request(struct request_queue *q,
		struct nvme_command *cmd, unsigned int flags, int qid);
blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
		struct nvme_command *cmd);
int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		void *buf, unsigned bufflen);
int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		union nvme_result *result, void *buffer, unsigned bufflen,
		unsigned timeout, int qid, int at_head, int flags);
int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
		void __user *ubuffer, unsigned bufflen, u32 *result,
		unsigned timeout);
int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
		void __user *ubuffer, unsigned bufflen,
		void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
		u32 *result, unsigned timeout);
int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);
void nvme_start_keep_alive(struct nvme_ctrl *ctrl);
void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
int nvme_reset_ctrl(struct nvme_ctrl *ctrl);

#ifdef CONFIG_NVM
int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id);
int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node);
void nvme_nvm_unregister(struct nvme_ns *ns);
int nvme_nvm_register_sysfs(struct nvme_ns *ns);
void nvme_nvm_unregister_sysfs(struct nvme_ns *ns);
int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg);
#else
static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name,
				    int node)
{
	return 0;
}

static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns)
{
	return 0;
}
static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {};
static inline int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id)
{
	return 0;
}
static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
							unsigned long arg)
{
	return -ENOTTY;
}
#endif /* CONFIG_NVM */

static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev)
{
	return dev_to_disk(dev)->private_data;
}

int __init nvme_core_init(void);
void nvme_core_exit(void);

#endif /* _NVME_H */
Commit	Line	Data
f11bb3e2 CH	1	/*
	2	* Copyright (c) 2011-2014, Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*/
	13
	14	#ifndef _NVME_H
	15	#define _NVME_H
	16
	17	#include <linux/nvme.h>
	18	#include <linux/pci.h>
	19	#include <linux/kref.h>
	20	#include <linux/blk-mq.h>
b0b4e09c	21	#include <linux/lightnvm.h>
a98e58e5	22	#include <linux/sed-opal.h>
f11bb3e2 CH	23
	24	extern unsigned char nvme_io_timeout;
	25	#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
	26
21d34711 CH	27	extern unsigned char admin_timeout;
	28	#define ADMIN_TIMEOUT (admin_timeout * HZ)
	29
038bd4cb SG	30	#define NVME_DEFAULT_KATO 5
	31	#define NVME_KATO_GRACE 10
	32
9a6327d2 SG	33	extern struct workqueue_struct *nvme_wq;
9a6327d2 SG	34
ca064085 MB	35	enum {
	36	NVME_NS_LBA = 0,
	37	NVME_NS_LIGHTNVM = 1,
	38	};
	39
f11bb3e2	40	/*
106198ed CH	41	* List of workarounds for devices that required behavior not specified in
106198ed CH	42	* the standard.
f11bb3e2	43	*/
106198ed CH	44	enum nvme_quirks {
	45	/*
	46	* Prefers I/O aligned to a stripe size specified in a vendor
	47	* specific Identify field.
	48	*/
	49	NVME_QUIRK_STRIPE_SIZE = (1 << 0),
540c801c KB	50
	51	/*
	52	* The controller doesn't handle Identify value others than 0 or 1
	53	* correctly.
	54	*/
	55	NVME_QUIRK_IDENTIFY_CNS = (1 << 1),
08095e70 KB	56
08095e70 KB	57	/*
e850fd16 CH	58	* The controller deterministically returns O's on reads to
e850fd16 CH	59	* logical blocks that deallocate was called on.
08095e70	60	*/
e850fd16	61	NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2),
54adc010 GP	62
	63	/*
	64	* The controller needs a delay before starts checking the device
	65	* readiness, which is done by reading the NVME_CSTS_RDY bit.
	66	*/
	67	NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3),
c5552fde AL	68
	69	/*
	70	* APST should not be used.
	71	*/
	72	NVME_QUIRK_NO_APST = (1 << 4),
ff5350a8 AL	73
	74	/*
	75	* The deepest sleep state should not be used.
	76	*/
	77	NVME_QUIRK_NO_DEEPEST_PS = (1 << 5),
106198ed CH	78	};
106198ed CH	79
d49187e9 CH	80	/*
	81	* Common request structure for NVMe passthrough. All drivers must have
	82	* this structure as the first member of their request-private data.
	83	*/
	84	struct nvme_request {
	85	struct nvme_command *cmd;
	86	union nvme_result result;
44e44b29	87	u8 retries;
27fa9bc5 CH	88	u8 flags;
	89	u16 status;
	90	};
	91
	92	enum {
	93	NVME_REQ_CANCELLED = (1 << 0),
d49187e9 CH	94	};
	95
	96	static inline struct nvme_request nvme_req(struct request req)
	97	{
	98	return blk_mq_rq_to_pdu(req);
	99	}
	100
54adc010 GP	101	/* The below value is the specific amount of delay needed before checking
	102	* readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
	103	* NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
	104	* found empirically.
	105	*/
	106	#define NVME_QUIRK_DELAY_AMOUNT 2000
	107
bb8d261e CH	108	enum nvme_ctrl_state {
	109	NVME_CTRL_NEW,
	110	NVME_CTRL_LIVE,
	111	NVME_CTRL_RESETTING,
def61eca	112	NVME_CTRL_RECONNECTING,
bb8d261e	113	NVME_CTRL_DELETING,
0ff9d4e1	114	NVME_CTRL_DEAD,
bb8d261e CH	115	};
bb8d261e CH	116
1c63dc66	117	struct nvme_ctrl {
bb8d261e	118	enum nvme_ctrl_state state;
bd4da3ab	119	bool identified;
bb8d261e	120	spinlock_t lock;
1c63dc66	121	const struct nvme_ctrl_ops *ops;
f11bb3e2	122	struct request_queue *admin_q;
07bfcd09	123	struct request_queue *connect_q;
f11bb3e2	124	struct device *dev;
1673f1f0	125	struct kref kref;
f11bb3e2	126	int instance;
5bae7f73	127	struct blk_mq_tag_set *tagset;
34b6c231	128	struct blk_mq_tag_set *admin_tagset;
f11bb3e2	129	struct list_head namespaces;
69d3b8ac	130	struct mutex namespaces_mutex;
5bae7f73	131	struct device device; / char device */
f3ca80fc	132	struct list_head node;
075790eb	133	struct ida ns_ida;
d86c4d8e	134	struct work_struct reset_work;
1c63dc66	135
4f1244c8	136	struct opal_dev *opal_dev;
a98e58e5	137
f11bb3e2 CH	138	char name[12];
	139	char serial[20];
	140	char model[40];
	141	char firmware_rev[8];
180de007	142	char subnqn[NVMF_NQN_SIZE];
76e3914a	143	u16 cntlid;
5fd4ce1b CH	144
5fd4ce1b CH	145	u32 ctrl_config;
b6dccf7f	146	u16 mtfa;
d858e5f0	147	u32 queue_count;
5fd4ce1b	148
20d0dfe6	149	u64 cap;
5fd4ce1b	150	u32 page_size;
f11bb3e2	151	u32 max_hw_sectors;
f11bb3e2	152	u16 oncs;
118472ab	153	u16 vid;
8a9ae523	154	u16 oacs;
f5d11840 JA	155	u16 nssa;
f5d11840 JA	156	u16 nr_streams;
6bf25d16	157	atomic_t abort_limit;
f11bb3e2 CH	158	u8 event_limit;
f11bb3e2 CH	159	u8 vwc;
f3ca80fc	160	u32 vs;
07bfcd09	161	u32 sgls;
038bd4cb	162	u16 kas;
c5552fde AL	163	u8 npss;
c5552fde AL	164	u8 apsta;
038bd4cb	165	unsigned int kato;
f3ca80fc	166	bool subsystem;
106198ed	167	unsigned long quirks;
c5552fde	168	struct nvme_id_power_state psd[32];
5955be21	169	struct work_struct scan_work;
f866fc42	170	struct work_struct async_event_work;
038bd4cb	171	struct delayed_work ka_work;
b6dccf7f	172	struct work_struct fw_act_work;
07bfcd09	173
c5552fde AL	174	/* Power saving configuration */
c5552fde AL	175	u64 ps_max_latency_us;
76a5af84	176	bool apst_enabled;
c5552fde	177
fe6d53c9 CH	178	u32 hmpre;
	179	u32 hmmin;
	180
07bfcd09 CH	181	/* Fabrics only */
	182	u16 sqsize;
	183	u32 ioccsz;
	184	u32 iorcsz;
	185	u16 icdoff;
	186	u16 maxcmd;
fdf9dfa8	187	int nr_reconnects;
07bfcd09	188	struct nvmf_ctrl_options *opts;
f11bb3e2 CH	189	};
f11bb3e2 CH	190
f11bb3e2 CH	191	struct nvme_ns {
	192	struct list_head list;
	193
1c63dc66	194	struct nvme_ctrl *ctrl;
f11bb3e2 CH	195	struct request_queue *queue;
f11bb3e2 CH	196	struct gendisk *disk;
b0b4e09c	197	struct nvm_dev *ndev;
f11bb3e2	198	struct kref kref;
075790eb	199	int instance;
f11bb3e2	200
2b9b6e86	201	u8 eui[8];
90985b84	202	u8 nguid[16];
3b22ba26	203	uuid_t uuid;
2b9b6e86	204
f11bb3e2 CH	205	unsigned ns_id;
	206	int lba_shift;
	207	u16 ms;
f5d11840 JA	208	u16 sgs;
f5d11840 JA	209	u32 sws;
f11bb3e2 CH	210	bool ext;
f11bb3e2 CH	211	u8 pi_type;
646017a6	212	unsigned long flags;
6b8190d6	213	u16 noiob;
646017a6 KB	214
646017a6 KB	215	#define NVME_NS_REMOVING 0
69d9a99c	216	#define NVME_NS_DEAD 1
646017a6	217
f11bb3e2 CH	218	u64 mode_select_num_blocks;
	219	u32 mode_select_block_len;
	220	};
	221
1c63dc66	222	struct nvme_ctrl_ops {
1a353d85	223	const char *name;
e439bb12	224	struct module *module;
d3d5b87d CH	225	unsigned int flags;
d3d5b87d CH	226	#define NVME_F_FABRICS (1 << 0)
c81bfba9	227	#define NVME_F_METADATA_SUPPORTED (1 << 1)
1c63dc66	228	int (reg_read32)(struct nvme_ctrl ctrl, u32 off, u32 *val);
5fd4ce1b	229	int (reg_write32)(struct nvme_ctrl ctrl, u32 off, u32 val);
7fd8930f	230	int (reg_read64)(struct nvme_ctrl ctrl, u32 off, u64 *val);
1673f1f0	231	void (free_ctrl)(struct nvme_ctrl ctrl);
f866fc42	232	void (submit_async_event)(struct nvme_ctrl ctrl, int aer_idx);
1a353d85	233	int (delete_ctrl)(struct nvme_ctrl ctrl);
1a353d85	234	int (get_address)(struct nvme_ctrl ctrl, char *buf, int size);
f11bb3e2 CH	235	};
f11bb3e2 CH	236
1c63dc66 CH	237	static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
	238	{
	239	u32 val = 0;
	240
	241	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
	242	return false;
	243	return val & NVME_CSTS_RDY;
	244	}
	245
f3ca80fc CH	246	static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
	247	{
	248	if (!ctrl->subsystem)
	249	return -ENOTTY;
	250	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
	251	}
	252
f11bb3e2 CH	253	static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
	254	{
	255	return (sector >> (ns->lba_shift - 9));
	256	}
	257
6904242d ML	258	static inline void nvme_cleanup_cmd(struct request *req)
6904242d ML	259	{
f9d03f96 CH	260	if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
	261	kfree(page_address(req->special_vec.bv_page) +
	262	req->special_vec.bv_offset);
	263	}
6904242d ML	264	}
6904242d ML	265
27fa9bc5 CH	266	static inline void nvme_end_request(struct request *req, __le16 status,
27fa9bc5 CH	267	union nvme_result result)
15a190f7	268	{
27fa9bc5	269	struct nvme_request *rq = nvme_req(req);
15a190f7	270
27fa9bc5 CH	271	rq->status = le16_to_cpu(status) >> 1;
27fa9bc5 CH	272	rq->result = result;
08e0029a	273	blk_mq_complete_request(req);
7688faa6 CH	274	}
7688faa6 CH	275
77f02a7a	276	void nvme_complete_rq(struct request *req);
c55a2fd4	277	void nvme_cancel_request(struct request req, void data, bool reserved);
bb8d261e CH	278	bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
bb8d261e CH	279	enum nvme_ctrl_state new_state);
5fd4ce1b CH	280	int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	281	int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	282	int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
f3ca80fc CH	283	int nvme_init_ctrl(struct nvme_ctrl ctrl, struct device dev,
f3ca80fc CH	284	const struct nvme_ctrl_ops *ops, unsigned long quirks);
53029b04	285	void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
d09f2b45 SG	286	void nvme_start_ctrl(struct nvme_ctrl *ctrl);
d09f2b45 SG	287	void nvme_stop_ctrl(struct nvme_ctrl *ctrl);
1673f1f0	288	void nvme_put_ctrl(struct nvme_ctrl *ctrl);
7fd8930f	289	int nvme_init_identify(struct nvme_ctrl *ctrl);
5bae7f73	290
5955be21	291	void nvme_queue_scan(struct nvme_ctrl *ctrl);
5bae7f73	292	void nvme_remove_namespaces(struct nvme_ctrl *ctrl);
1673f1f0	293
4f1244c8 CH	294	int nvme_sec_submit(void data, u16 spsp, u8 secp, void buffer, size_t len,
4f1244c8 CH	295	bool send);
a98e58e5	296
f866fc42	297	#define NVME_NR_AERS 1
7bf58533 CH	298	void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
7bf58533 CH	299	union nvme_result *res);
f866fc42 CH	300	void nvme_queue_async_events(struct nvme_ctrl *ctrl);
f866fc42 CH	301
25646264 KB	302	void nvme_stop_queues(struct nvme_ctrl *ctrl);
25646264 KB	303	void nvme_start_queues(struct nvme_ctrl *ctrl);
69d9a99c	304	void nvme_kill_queues(struct nvme_ctrl *ctrl);
302ad8cc KB	305	void nvme_unfreeze(struct nvme_ctrl *ctrl);
	306	void nvme_wait_freeze(struct nvme_ctrl *ctrl);
	307	void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
	308	void nvme_start_freeze(struct nvme_ctrl *ctrl);
363c9aac	309
eb71f435	310	#define NVME_QID_ANY -1
4160982e	311	struct request nvme_alloc_request(struct request_queue q,
eb71f435	312	struct nvme_command *cmd, unsigned int flags, int qid);
fc17b653	313	blk_status_t nvme_setup_cmd(struct nvme_ns ns, struct request req,
8093f7ca	314	struct nvme_command *cmd);
f11bb3e2 CH	315	int nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
	316	void *buf, unsigned bufflen);
	317	int __nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
d49187e9	318	union nvme_result result, void buffer, unsigned bufflen,
eb71f435	319	unsigned timeout, int qid, int at_head, int flags);
4160982e CH	320	int nvme_submit_user_cmd(struct request_queue q, struct nvme_command cmd,
	321	void __user ubuffer, unsigned bufflen, u32 result,
	322	unsigned timeout);
0b7f1f26 KB	323	int __nvme_submit_user_cmd(struct request_queue q, struct nvme_command cmd,
	324	void __user *ubuffer, unsigned bufflen,
	325	void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
f11bb3e2	326	u32 *result, unsigned timeout);
9a0be7ab	327	int nvme_set_queue_count(struct nvme_ctrl ctrl, int count);
038bd4cb SG	328	void nvme_start_keep_alive(struct nvme_ctrl *ctrl);
038bd4cb SG	329	void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
d86c4d8e	330	int nvme_reset_ctrl(struct nvme_ctrl *ctrl);
f11bb3e2	331
c4699e70	332	#ifdef CONFIG_NVM
ca064085	333	int nvme_nvm_ns_supported(struct nvme_ns ns, struct nvme_id_ns id);
3dc87dd0	334	int nvme_nvm_register(struct nvme_ns ns, char disk_name, int node);
b0b4e09c	335	void nvme_nvm_unregister(struct nvme_ns *ns);
3dc87dd0 MB	336	int nvme_nvm_register_sysfs(struct nvme_ns *ns);
3dc87dd0 MB	337	void nvme_nvm_unregister_sysfs(struct nvme_ns *ns);
84d4add7	338	int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg);
c4699e70	339	#else
b0b4e09c	340	static inline int nvme_nvm_register(struct nvme_ns ns, char disk_name,
3dc87dd0	341	int node)
c4699e70 KB	342	{
	343	return 0;
	344	}
	345
b0b4e09c	346	static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
3dc87dd0 MB	347	static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns)
	348	{
	349	return 0;
	350	}
	351	static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {};
c4699e70 KB	352	static inline int nvme_nvm_ns_supported(struct nvme_ns ns, struct nvme_id_ns id)
	353	{
	354	return 0;
	355	}
84d4add7 MB	356	static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
	357	unsigned long arg)
	358	{
	359	return -ENOTTY;
	360	}
3dc87dd0 MB	361	#endif /* CONFIG_NVM */
3dc87dd0 MB	362
40267efd SL	363	static inline struct nvme_ns nvme_get_ns_from_dev(struct device dev)
	364	{
	365	return dev_to_disk(dev)->private_data;
	366	}
ca064085	367
5bae7f73 CH	368	int __init nvme_core_init(void);
	369	void nvme_core_exit(void);
	370
f11bb3e2	371	#endif /* _NVME_H */