[mirror_ubuntu-jammy-kernel.git] / drivers / nvme / host / nvme.h

/*
 * Copyright (c) 2011-2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef _NVME_H
#define _NVME_H

#include <linux/nvme.h>
#include <linux/cdev.h>
#include <linux/pci.h>
#include <linux/kref.h>
#include <linux/blk-mq.h>
#include <linux/lightnvm.h>
#include <linux/sed-opal.h>
#include <linux/fault-inject.h>
#include <linux/rcupdate.h>

extern unsigned int nvme_io_timeout;
#define NVME_IO_TIMEOUT	(nvme_io_timeout * HZ)

extern unsigned int admin_timeout;
#define ADMIN_TIMEOUT	(admin_timeout * HZ)

#define NVME_DEFAULT_KATO	5
#define NVME_KATO_GRACE		10

extern struct workqueue_struct *nvme_wq;
extern struct workqueue_struct *nvme_reset_wq;
extern struct workqueue_struct *nvme_delete_wq;

enum {
	NVME_NS_LBA		= 0,
	NVME_NS_LIGHTNVM	= 1,
};

/*
 * List of workarounds for devices that required behavior not specified in
 * the standard.
 */
enum nvme_quirks {
	/*
	 * Prefers I/O aligned to a stripe size specified in a vendor
	 * specific Identify field.
	 */
	NVME_QUIRK_STRIPE_SIZE			= (1 << 0),

	/*
	 * The controller doesn't handle Identify value others than 0 or 1
	 * correctly.
	 */
	NVME_QUIRK_IDENTIFY_CNS			= (1 << 1),

	/*
	 * The controller deterministically returns O's on reads to
	 * logical blocks that deallocate was called on.
	 */
	NVME_QUIRK_DEALLOCATE_ZEROES		= (1 << 2),

	/*
	 * The controller needs a delay before starts checking the device
	 * readiness, which is done by reading the NVME_CSTS_RDY bit.
	 */
	NVME_QUIRK_DELAY_BEFORE_CHK_RDY		= (1 << 3),

	/*
	 * APST should not be used.
	 */
	NVME_QUIRK_NO_APST			= (1 << 4),

	/*
	 * The deepest sleep state should not be used.
	 */
	NVME_QUIRK_NO_DEEPEST_PS		= (1 << 5),

	/*
	 * Supports the LighNVM command set if indicated in vs[1].
	 */
	NVME_QUIRK_LIGHTNVM			= (1 << 6),

	/*
	 * Set MEDIUM priority on SQ creation
	 */
	NVME_QUIRK_MEDIUM_PRIO_SQ		= (1 << 7),
};

/*
 * Common request structure for NVMe passthrough.  All drivers must have
 * this structure as the first member of their request-private data.
 */
struct nvme_request {
	struct nvme_command	*cmd;
	union nvme_result	result;
	u8			retries;
	u8			flags;
	u16			status;
	struct nvme_ctrl	*ctrl;
};

/*
 * Mark a bio as coming in through the mpath node.
 */
#define REQ_NVME_MPATH		REQ_DRV

enum {
	NVME_REQ_CANCELLED		= (1 << 0),
	NVME_REQ_USERCMD		= (1 << 1),
};

static inline struct nvme_request *nvme_req(struct request *req)
{
	return blk_mq_rq_to_pdu(req);
}

/* The below value is the specific amount of delay needed before checking
 * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
 * found empirically.
 */
#define NVME_QUIRK_DELAY_AMOUNT		2300

enum nvme_ctrl_state {
	NVME_CTRL_NEW,
	NVME_CTRL_LIVE,
	NVME_CTRL_ADMIN_ONLY,    /* Only admin queue live */
	NVME_CTRL_RESETTING,
	NVME_CTRL_CONNECTING,
	NVME_CTRL_DELETING,
	NVME_CTRL_DEAD,
};

struct nvme_ctrl {
	enum nvme_ctrl_state state;
	bool identified;
	spinlock_t lock;
	const struct nvme_ctrl_ops *ops;
	struct request_queue *admin_q;
	struct request_queue *connect_q;
	struct device *dev;
	int instance;
	struct blk_mq_tag_set *tagset;
	struct blk_mq_tag_set *admin_tagset;
	struct list_head namespaces;
	struct rw_semaphore namespaces_rwsem;
	struct device ctrl_device;
	struct device *device;	/* char device */
	struct cdev cdev;
	struct work_struct reset_work;
	struct work_struct delete_work;

	struct nvme_subsystem *subsys;
	struct list_head subsys_entry;

	struct opal_dev *opal_dev;

	char name[12];
	u16 cntlid;

	u32 ctrl_config;
	u16 mtfa;
	u32 queue_count;

	u64 cap;
	u32 page_size;
	u32 max_hw_sectors;
	u32 max_segments;
	u16 oncs;
	u16 oacs;
	u16 nssa;
	u16 nr_streams;
	atomic_t abort_limit;
	u8 vwc;
	u32 vs;
	u32 sgls;
	u16 kas;
	u8 npss;
	u8 apsta;
	u32 oaes;
	u32 aen_result;
	unsigned int shutdown_timeout;
	unsigned int kato;
	bool subsystem;
	unsigned long quirks;
	struct nvme_id_power_state psd[32];
	struct nvme_effects_log *effects;
	struct work_struct scan_work;
	struct work_struct async_event_work;
	struct delayed_work ka_work;
	struct nvme_command ka_cmd;
	struct work_struct fw_act_work;
	unsigned long events;

	/* Power saving configuration */
	u64 ps_max_latency_us;
	bool apst_enabled;

	/* PCIe only: */
	u32 hmpre;
	u32 hmmin;
	u32 hmminds;
	u16 hmmaxd;

	/* Fabrics only */
	u16 sqsize;
	u32 ioccsz;
	u32 iorcsz;
	u16 icdoff;
	u16 maxcmd;
	int nr_reconnects;
	struct nvmf_ctrl_options *opts;
};

struct nvme_subsystem {
	int			instance;
	struct device		dev;
	/*
	 * Because we unregister the device on the last put we need
	 * a separate refcount.
	 */
	struct kref		ref;
	struct list_head	entry;
	struct mutex		lock;
	struct list_head	ctrls;
	struct list_head	nsheads;
	char			subnqn[NVMF_NQN_SIZE];
	char			serial[20];
	char			model[40];
	char			firmware_rev[8];
	u8			cmic;
	u16			vendor_id;
	struct ida		ns_ida;
};

/*
 * Container structure for uniqueue namespace identifiers.
 */
struct nvme_ns_ids {
	u8	eui64[8];
	u8	nguid[16];
	uuid_t	uuid;
};

/*
 * Anchor structure for namespaces.  There is one for each namespace in a
 * NVMe subsystem that any of our controllers can see, and the namespace
 * structure for each controller is chained of it.  For private namespaces
 * there is a 1:1 relation to our namespace structures, that is ->list
 * only ever has a single entry for private namespaces.
 */
struct nvme_ns_head {
#ifdef CONFIG_NVME_MULTIPATH
	struct gendisk		*disk;
	struct nvme_ns __rcu	*current_path;
	struct bio_list		requeue_list;
	spinlock_t		requeue_lock;
	struct work_struct	requeue_work;
#endif
	struct list_head	list;
	struct srcu_struct      srcu;
	struct nvme_subsystem	*subsys;
	unsigned		ns_id;
	struct nvme_ns_ids	ids;
	struct list_head	entry;
	struct kref		ref;
	int			instance;
};

#ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
struct nvme_fault_inject {
	struct fault_attr attr;
	struct dentry *parent;
	bool dont_retry;	/* DNR, do not retry */
	u16 status;		/* status code */
};
#endif

struct nvme_ns {
	struct list_head list;

	struct nvme_ctrl *ctrl;
	struct request_queue *queue;
	struct gendisk *disk;
	struct list_head siblings;
	struct nvm_dev *ndev;
	struct kref kref;
	struct nvme_ns_head *head;

	int lba_shift;
	u16 ms;
	u16 sgs;
	u32 sws;
	bool ext;
	u8 pi_type;
	unsigned long flags;
#define NVME_NS_REMOVING 0
#define NVME_NS_DEAD     1
	u16 noiob;

#ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
	struct nvme_fault_inject fault_inject;
#endif

};

struct nvme_ctrl_ops {
	const char *name;
	struct module *module;
	unsigned int flags;
#define NVME_F_FABRICS			(1 << 0)
#define NVME_F_METADATA_SUPPORTED	(1 << 1)
	int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val);
	int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val);
	int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val);
	void (*free_ctrl)(struct nvme_ctrl *ctrl);
	void (*submit_async_event)(struct nvme_ctrl *ctrl);
	void (*delete_ctrl)(struct nvme_ctrl *ctrl);
	int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size);
	void (*stop_ctrl)(struct nvme_ctrl *ctrl);
};

#ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
void nvme_fault_inject_init(struct nvme_ns *ns);
void nvme_fault_inject_fini(struct nvme_ns *ns);
void nvme_should_fail(struct request *req);
#else
static inline void nvme_fault_inject_init(struct nvme_ns *ns) {}
static inline void nvme_fault_inject_fini(struct nvme_ns *ns) {}
static inline void nvme_should_fail(struct request *req) {}
#endif

static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
{
	u32 val = 0;

	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
		return false;
	return val & NVME_CSTS_RDY;
}

static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
{
	if (!ctrl->subsystem)
		return -ENOTTY;
	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
}

static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
{
	return (sector >> (ns->lba_shift - 9));
}

static inline void nvme_cleanup_cmd(struct request *req)
{
	if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
		kfree(page_address(req->special_vec.bv_page) +
		      req->special_vec.bv_offset);
	}
}

static inline void nvme_end_request(struct request *req, __le16 status,
		union nvme_result result)
{
	struct nvme_request *rq = nvme_req(req);

	rq->status = le16_to_cpu(status) >> 1;
	rq->result = result;
	/* inject error when permitted by fault injection framework */
	nvme_should_fail(req);
	blk_mq_complete_request(req);
}

static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl)
{
	get_device(ctrl->device);
}

static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl)
{
	put_device(ctrl->device);
}

void nvme_complete_rq(struct request *req);
void nvme_cancel_request(struct request *req, void *data, bool reserved);
bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
		enum nvme_ctrl_state new_state);
int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
		const struct nvme_ctrl_ops *ops, unsigned long quirks);
void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
void nvme_start_ctrl(struct nvme_ctrl *ctrl);
void nvme_stop_ctrl(struct nvme_ctrl *ctrl);
void nvme_put_ctrl(struct nvme_ctrl *ctrl);
int nvme_init_identify(struct nvme_ctrl *ctrl);

void nvme_remove_namespaces(struct nvme_ctrl *ctrl);

int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
		bool send);

void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
		volatile union nvme_result *res);

void nvme_stop_queues(struct nvme_ctrl *ctrl);
void nvme_start_queues(struct nvme_ctrl *ctrl);
void nvme_kill_queues(struct nvme_ctrl *ctrl);
void nvme_unfreeze(struct nvme_ctrl *ctrl);
void nvme_wait_freeze(struct nvme_ctrl *ctrl);
void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
void nvme_start_freeze(struct nvme_ctrl *ctrl);

#define NVME_QID_ANY -1
struct request *nvme_alloc_request(struct request_queue *q,
		struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid);
blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
		struct nvme_command *cmd);
int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		void *buf, unsigned bufflen);
int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		union nvme_result *result, void *buffer, unsigned bufflen,
		unsigned timeout, int qid, int at_head,
		blk_mq_req_flags_t flags);
int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);
void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
int nvme_reset_ctrl(struct nvme_ctrl *ctrl);
int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl);
int nvme_delete_ctrl(struct nvme_ctrl *ctrl);
int nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl);

int nvme_get_log_ext(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
		u8 log_page, void *log, size_t size, u64 offset);

extern const struct attribute_group nvme_ns_id_attr_group;
extern const struct block_device_operations nvme_ns_head_ops;

#ifdef CONFIG_NVME_MULTIPATH
void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns,
			struct nvme_ctrl *ctrl, int *flags);
void nvme_failover_req(struct request *req);
bool nvme_req_needs_failover(struct request *req, blk_status_t error);
void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl);
int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,struct nvme_ns_head *head);
void nvme_mpath_add_disk(struct nvme_ns_head *head);
void nvme_mpath_remove_disk(struct nvme_ns_head *head);

static inline void nvme_mpath_clear_current_path(struct nvme_ns *ns)
{
	struct nvme_ns_head *head = ns->head;

	if (head && ns == rcu_access_pointer(head->current_path))
		rcu_assign_pointer(head->current_path, NULL);
}
struct nvme_ns *nvme_find_path(struct nvme_ns_head *head);

static inline void nvme_mpath_check_last_path(struct nvme_ns *ns)
{
	struct nvme_ns_head *head = ns->head;

	if (head->disk && list_empty(&head->list))
		kblockd_schedule_work(&head->requeue_work);
}

#else
/*
 * Without the multipath code enabled, multiple controller per subsystems are
 * visible as devices and thus we cannot use the subsystem instance.
 */
static inline void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns,
				      struct nvme_ctrl *ctrl, int *flags)
{
	sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->head->instance);
}

static inline void nvme_failover_req(struct request *req)
{
}
static inline bool nvme_req_needs_failover(struct request *req,
					   blk_status_t error)
{
	return false;
}
static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl)
{
}
static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,
		struct nvme_ns_head *head)
{
	return 0;
}
static inline void nvme_mpath_add_disk(struct nvme_ns_head *head)
{
}
static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head)
{
}
static inline void nvme_mpath_clear_current_path(struct nvme_ns *ns)
{
}
static inline void nvme_mpath_check_last_path(struct nvme_ns *ns)
{
}
#endif /* CONFIG_NVME_MULTIPATH */

#ifdef CONFIG_NVM
void nvme_nvm_update_nvm_info(struct nvme_ns *ns);
int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node);
void nvme_nvm_unregister(struct nvme_ns *ns);
int nvme_nvm_register_sysfs(struct nvme_ns *ns);
void nvme_nvm_unregister_sysfs(struct nvme_ns *ns);
int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg);
#else
static inline void nvme_nvm_update_nvm_info(struct nvme_ns *ns) {};
static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name,
				    int node)
{
	return 0;
}

static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns)
{
	return 0;
}
static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {};
static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
							unsigned long arg)
{
	return -ENOTTY;
}
#endif /* CONFIG_NVM */

static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev)
{
	return dev_to_disk(dev)->private_data;
}

int __init nvme_core_init(void);
void nvme_core_exit(void);

#endif /* _NVME_H */
Commit	Line	Data
f11bb3e2 CH	1	/*
	2	* Copyright (c) 2011-2014, Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*/
	13
	14	#ifndef _NVME_H
	15	#define _NVME_H
	16
	17	#include <linux/nvme.h>
a6a5149b	18	#include <linux/cdev.h>
f11bb3e2 CH	19	#include <linux/pci.h>
	20	#include <linux/kref.h>
	21	#include <linux/blk-mq.h>
b0b4e09c	22	#include <linux/lightnvm.h>
a98e58e5	23	#include <linux/sed-opal.h>
b9e03857	24	#include <linux/fault-inject.h>
978628ec	25	#include <linux/rcupdate.h>
f11bb3e2	26
8ae4e447	27	extern unsigned int nvme_io_timeout;
f11bb3e2 CH	28	#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
f11bb3e2 CH	29
8ae4e447	30	extern unsigned int admin_timeout;
21d34711 CH	31	#define ADMIN_TIMEOUT (admin_timeout * HZ)
21d34711 CH	32
038bd4cb SG	33	#define NVME_DEFAULT_KATO 5
	34	#define NVME_KATO_GRACE 10
	35
9a6327d2	36	extern struct workqueue_struct *nvme_wq;
b227c59b RS	37	extern struct workqueue_struct *nvme_reset_wq;
b227c59b RS	38	extern struct workqueue_struct *nvme_delete_wq;
9a6327d2	39
ca064085 MB	40	enum {
	41	NVME_NS_LBA = 0,
	42	NVME_NS_LIGHTNVM = 1,
	43	};
	44
f11bb3e2	45	/*
106198ed CH	46	* List of workarounds for devices that required behavior not specified in
106198ed CH	47	* the standard.
f11bb3e2	48	*/
106198ed CH	49	enum nvme_quirks {
	50	/*
	51	* Prefers I/O aligned to a stripe size specified in a vendor
	52	* specific Identify field.
	53	*/
	54	NVME_QUIRK_STRIPE_SIZE = (1 << 0),
540c801c KB	55
	56	/*
	57	* The controller doesn't handle Identify value others than 0 or 1
	58	* correctly.
	59	*/
	60	NVME_QUIRK_IDENTIFY_CNS = (1 << 1),
08095e70 KB	61
08095e70 KB	62	/*
e850fd16 CH	63	* The controller deterministically returns O's on reads to
e850fd16 CH	64	* logical blocks that deallocate was called on.
08095e70	65	*/
e850fd16	66	NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2),
54adc010 GP	67
	68	/*
	69	* The controller needs a delay before starts checking the device
	70	* readiness, which is done by reading the NVME_CSTS_RDY bit.
	71	*/
	72	NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3),
c5552fde AL	73
	74	/*
	75	* APST should not be used.
	76	*/
	77	NVME_QUIRK_NO_APST = (1 << 4),
ff5350a8 AL	78
	79	/*
	80	* The deepest sleep state should not be used.
	81	*/
	82	NVME_QUIRK_NO_DEEPEST_PS = (1 << 5),
608cc4b1 CH	83
	84	/*
	85	* Supports the LighNVM command set if indicated in vs[1].
	86	*/
	87	NVME_QUIRK_LIGHTNVM = (1 << 6),
9abd68ef JA	88
	89	/*
	90	* Set MEDIUM priority on SQ creation
	91	*/
	92	NVME_QUIRK_MEDIUM_PRIO_SQ = (1 << 7),
106198ed CH	93	};
106198ed CH	94
d49187e9 CH	95	/*
	96	* Common request structure for NVMe passthrough. All drivers must have
	97	* this structure as the first member of their request-private data.
	98	*/
	99	struct nvme_request {
	100	struct nvme_command *cmd;
	101	union nvme_result result;
44e44b29	102	u8 retries;
27fa9bc5 CH	103	u8 flags;
27fa9bc5 CH	104	u16 status;
59e29ce6	105	struct nvme_ctrl *ctrl;
27fa9bc5 CH	106	};
27fa9bc5 CH	107
32acab31 CH	108	/*
	109	* Mark a bio as coming in through the mpath node.
	110	*/
	111	#define REQ_NVME_MPATH REQ_DRV
	112
27fa9bc5 CH	113	enum {
27fa9bc5 CH	114	NVME_REQ_CANCELLED = (1 << 0),
bb06ec31	115	NVME_REQ_USERCMD = (1 << 1),
d49187e9 CH	116	};
	117
	118	static inline struct nvme_request nvme_req(struct request req)
	119	{
	120	return blk_mq_rq_to_pdu(req);
	121	}
	122
54adc010 GP	123	/* The below value is the specific amount of delay needed before checking
	124	* readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
	125	* NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
	126	* found empirically.
	127	*/
8c97eecc	128	#define NVME_QUIRK_DELAY_AMOUNT 2300
54adc010	129
bb8d261e CH	130	enum nvme_ctrl_state {
	131	NVME_CTRL_NEW,
	132	NVME_CTRL_LIVE,
2b1b7e78	133	NVME_CTRL_ADMIN_ONLY, /* Only admin queue live */
bb8d261e	134	NVME_CTRL_RESETTING,
ad6a0a52	135	NVME_CTRL_CONNECTING,
bb8d261e	136	NVME_CTRL_DELETING,
0ff9d4e1	137	NVME_CTRL_DEAD,
bb8d261e CH	138	};
bb8d261e CH	139
1c63dc66	140	struct nvme_ctrl {
bb8d261e	141	enum nvme_ctrl_state state;
bd4da3ab	142	bool identified;
bb8d261e	143	spinlock_t lock;
1c63dc66	144	const struct nvme_ctrl_ops *ops;
f11bb3e2	145	struct request_queue *admin_q;
07bfcd09	146	struct request_queue *connect_q;
f11bb3e2	147	struct device *dev;
f11bb3e2	148	int instance;
5bae7f73	149	struct blk_mq_tag_set *tagset;
34b6c231	150	struct blk_mq_tag_set *admin_tagset;
f11bb3e2	151	struct list_head namespaces;
765cc031	152	struct rw_semaphore namespaces_rwsem;
d22524a4	153	struct device ctrl_device;
5bae7f73	154	struct device device; / char device */
a6a5149b	155	struct cdev cdev;
d86c4d8e	156	struct work_struct reset_work;
c5017e85	157	struct work_struct delete_work;
1c63dc66	158
ab9e00cc CH	159	struct nvme_subsystem *subsys;
	160	struct list_head subsys_entry;
	161
4f1244c8	162	struct opal_dev *opal_dev;
a98e58e5	163
f11bb3e2	164	char name[12];
76e3914a	165	u16 cntlid;
5fd4ce1b CH	166
5fd4ce1b CH	167	u32 ctrl_config;
b6dccf7f	168	u16 mtfa;
d858e5f0	169	u32 queue_count;
5fd4ce1b	170
20d0dfe6	171	u64 cap;
5fd4ce1b	172	u32 page_size;
f11bb3e2	173	u32 max_hw_sectors;
943e942e	174	u32 max_segments;
f11bb3e2	175	u16 oncs;
8a9ae523	176	u16 oacs;
f5d11840 JA	177	u16 nssa;
f5d11840 JA	178	u16 nr_streams;
6bf25d16	179	atomic_t abort_limit;
f11bb3e2	180	u8 vwc;
f3ca80fc	181	u32 vs;
07bfcd09	182	u32 sgls;
038bd4cb	183	u16 kas;
c5552fde AL	184	u8 npss;
c5552fde AL	185	u8 apsta;
c0561f82	186	u32 oaes;
e3d7874d	187	u32 aen_result;
07fbd32a	188	unsigned int shutdown_timeout;
038bd4cb	189	unsigned int kato;
f3ca80fc	190	bool subsystem;
106198ed	191	unsigned long quirks;
c5552fde	192	struct nvme_id_power_state psd[32];
84fef62d	193	struct nvme_effects_log *effects;
5955be21	194	struct work_struct scan_work;
f866fc42	195	struct work_struct async_event_work;
038bd4cb	196	struct delayed_work ka_work;
0a34e466	197	struct nvme_command ka_cmd;
b6dccf7f	198	struct work_struct fw_act_work;
30d90964	199	unsigned long events;
07bfcd09	200
c5552fde AL	201	/* Power saving configuration */
c5552fde AL	202	u64 ps_max_latency_us;
76a5af84	203	bool apst_enabled;
c5552fde	204
044a9df1	205	/* PCIe only: */
fe6d53c9 CH	206	u32 hmpre;
fe6d53c9 CH	207	u32 hmmin;
044a9df1 CH	208	u32 hmminds;
044a9df1 CH	209	u16 hmmaxd;
fe6d53c9	210
07bfcd09 CH	211	/* Fabrics only */
	212	u16 sqsize;
	213	u32 ioccsz;
	214	u32 iorcsz;
	215	u16 icdoff;
	216	u16 maxcmd;
fdf9dfa8	217	int nr_reconnects;
07bfcd09	218	struct nvmf_ctrl_options *opts;
f11bb3e2 CH	219	};
f11bb3e2 CH	220
ab9e00cc CH	221	struct nvme_subsystem {
	222	int instance;
	223	struct device dev;
	224	/*
	225	* Because we unregister the device on the last put we need
	226	* a separate refcount.
	227	*/
	228	struct kref ref;
	229	struct list_head entry;
	230	struct mutex lock;
	231	struct list_head ctrls;
ed754e5d	232	struct list_head nsheads;
ab9e00cc CH	233	char subnqn[NVMF_NQN_SIZE];
	234	char serial[20];
	235	char model[40];
	236	char firmware_rev[8];
	237	u8 cmic;
	238	u16 vendor_id;
ed754e5d	239	struct ida ns_ida;
ab9e00cc CH	240	};
ab9e00cc CH	241
002fab04 CH	242	/*
	243	* Container structure for uniqueue namespace identifiers.
	244	*/
	245	struct nvme_ns_ids {
	246	u8 eui64[8];
	247	u8 nguid[16];
	248	uuid_t uuid;
	249	};
	250
ed754e5d CH	251	/*
	252	* Anchor structure for namespaces. There is one for each namespace in a
	253	* NVMe subsystem that any of our controllers can see, and the namespace
	254	* structure for each controller is chained of it. For private namespaces
	255	* there is a 1:1 relation to our namespace structures, that is ->list
	256	* only ever has a single entry for private namespaces.
	257	*/
	258	struct nvme_ns_head {
32acab31 CH	259	#ifdef CONFIG_NVME_MULTIPATH
	260	struct gendisk *disk;
	261	struct nvme_ns __rcu *current_path;
	262	struct bio_list requeue_list;
	263	spinlock_t requeue_lock;
	264	struct work_struct requeue_work;
	265	#endif
ed754e5d CH	266	struct list_head list;
	267	struct srcu_struct srcu;
	268	struct nvme_subsystem *subsys;
	269	unsigned ns_id;
	270	struct nvme_ns_ids ids;
	271	struct list_head entry;
	272	struct kref ref;
	273	int instance;
	274	};
	275
b9e03857 TT	276	#ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
	277	struct nvme_fault_inject {
	278	struct fault_attr attr;
	279	struct dentry *parent;
	280	bool dont_retry; /* DNR, do not retry */
	281	u16 status; /* status code */
	282	};
	283	#endif
	284
f11bb3e2 CH	285	struct nvme_ns {
	286	struct list_head list;
	287
1c63dc66	288	struct nvme_ctrl *ctrl;
f11bb3e2 CH	289	struct request_queue *queue;
f11bb3e2 CH	290	struct gendisk *disk;
ed754e5d	291	struct list_head siblings;
b0b4e09c	292	struct nvm_dev *ndev;
f11bb3e2	293	struct kref kref;
ed754e5d	294	struct nvme_ns_head *head;
f11bb3e2	295
f11bb3e2 CH	296	int lba_shift;
f11bb3e2 CH	297	u16 ms;
f5d11840 JA	298	u16 sgs;
f5d11840 JA	299	u32 sws;
f11bb3e2 CH	300	bool ext;
f11bb3e2 CH	301	u8 pi_type;
646017a6	302	unsigned long flags;
646017a6	303	#define NVME_NS_REMOVING 0
69d9a99c	304	#define NVME_NS_DEAD 1
57eeaf8e	305	u16 noiob;
b9e03857 TT	306
	307	#ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
	308	struct nvme_fault_inject fault_inject;
	309	#endif
	310
f11bb3e2 CH	311	};
f11bb3e2 CH	312
1c63dc66	313	struct nvme_ctrl_ops {
1a353d85	314	const char *name;
e439bb12	315	struct module *module;
d3d5b87d CH	316	unsigned int flags;
d3d5b87d CH	317	#define NVME_F_FABRICS (1 << 0)
c81bfba9	318	#define NVME_F_METADATA_SUPPORTED (1 << 1)
1c63dc66	319	int (reg_read32)(struct nvme_ctrl ctrl, u32 off, u32 *val);
5fd4ce1b	320	int (reg_write32)(struct nvme_ctrl ctrl, u32 off, u32 val);
7fd8930f	321	int (reg_read64)(struct nvme_ctrl ctrl, u32 off, u64 *val);
1673f1f0	322	void (free_ctrl)(struct nvme_ctrl ctrl);
ad22c355	323	void (submit_async_event)(struct nvme_ctrl ctrl);
c5017e85	324	void (delete_ctrl)(struct nvme_ctrl ctrl);
1a353d85	325	int (get_address)(struct nvme_ctrl ctrl, char *buf, int size);
b435ecea	326	void (stop_ctrl)(struct nvme_ctrl ctrl);
f11bb3e2 CH	327	};
f11bb3e2 CH	328
b9e03857 TT	329	#ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
	330	void nvme_fault_inject_init(struct nvme_ns *ns);
	331	void nvme_fault_inject_fini(struct nvme_ns *ns);
	332	void nvme_should_fail(struct request *req);
	333	#else
	334	static inline void nvme_fault_inject_init(struct nvme_ns *ns) {}
	335	static inline void nvme_fault_inject_fini(struct nvme_ns *ns) {}
	336	static inline void nvme_should_fail(struct request *req) {}
	337	#endif
	338
1c63dc66 CH	339	static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
	340	{
	341	u32 val = 0;
	342
	343	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
	344	return false;
	345	return val & NVME_CSTS_RDY;
	346	}
	347
f3ca80fc CH	348	static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
	349	{
	350	if (!ctrl->subsystem)
	351	return -ENOTTY;
	352	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
	353	}
	354
f11bb3e2 CH	355	static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
	356	{
	357	return (sector >> (ns->lba_shift - 9));
	358	}
	359
6904242d ML	360	static inline void nvme_cleanup_cmd(struct request *req)
6904242d ML	361	{
f9d03f96 CH	362	if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
	363	kfree(page_address(req->special_vec.bv_page) +
	364	req->special_vec.bv_offset);
	365	}
6904242d ML	366	}
6904242d ML	367
27fa9bc5 CH	368	static inline void nvme_end_request(struct request *req, __le16 status,
27fa9bc5 CH	369	union nvme_result result)
15a190f7	370	{
27fa9bc5	371	struct nvme_request *rq = nvme_req(req);
15a190f7	372
27fa9bc5 CH	373	rq->status = le16_to_cpu(status) >> 1;
27fa9bc5 CH	374	rq->result = result;
b9e03857 TT	375	/* inject error when permitted by fault injection framework */
b9e03857 TT	376	nvme_should_fail(req);
08e0029a	377	blk_mq_complete_request(req);
7688faa6 CH	378	}
7688faa6 CH	379
d22524a4 CH	380	static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl)
	381	{
	382	get_device(ctrl->device);
	383	}
	384
	385	static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl)
	386	{
	387	put_device(ctrl->device);
	388	}
	389
77f02a7a	390	void nvme_complete_rq(struct request *req);
c55a2fd4	391	void nvme_cancel_request(struct request req, void data, bool reserved);
bb8d261e CH	392	bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
bb8d261e CH	393	enum nvme_ctrl_state new_state);
5fd4ce1b CH	394	int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	395	int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	396	int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
f3ca80fc CH	397	int nvme_init_ctrl(struct nvme_ctrl ctrl, struct device dev,
f3ca80fc CH	398	const struct nvme_ctrl_ops *ops, unsigned long quirks);
53029b04	399	void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
d09f2b45 SG	400	void nvme_start_ctrl(struct nvme_ctrl *ctrl);
d09f2b45 SG	401	void nvme_stop_ctrl(struct nvme_ctrl *ctrl);
1673f1f0	402	void nvme_put_ctrl(struct nvme_ctrl *ctrl);
7fd8930f	403	int nvme_init_identify(struct nvme_ctrl *ctrl);
5bae7f73	404
5bae7f73	405	void nvme_remove_namespaces(struct nvme_ctrl *ctrl);
1673f1f0	406
4f1244c8 CH	407	int nvme_sec_submit(void data, u16 spsp, u8 secp, void buffer, size_t len,
4f1244c8 CH	408	bool send);
a98e58e5	409
7bf58533	410	void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
287a63eb	411	volatile union nvme_result *res);
f866fc42	412
25646264 KB	413	void nvme_stop_queues(struct nvme_ctrl *ctrl);
25646264 KB	414	void nvme_start_queues(struct nvme_ctrl *ctrl);
69d9a99c	415	void nvme_kill_queues(struct nvme_ctrl *ctrl);
302ad8cc KB	416	void nvme_unfreeze(struct nvme_ctrl *ctrl);
	417	void nvme_wait_freeze(struct nvme_ctrl *ctrl);
	418	void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
	419	void nvme_start_freeze(struct nvme_ctrl *ctrl);
363c9aac	420
eb71f435	421	#define NVME_QID_ANY -1
4160982e	422	struct request nvme_alloc_request(struct request_queue q,
9a95e4ef	423	struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid);
fc17b653	424	blk_status_t nvme_setup_cmd(struct nvme_ns ns, struct request req,
8093f7ca	425	struct nvme_command *cmd);
f11bb3e2 CH	426	int nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
	427	void *buf, unsigned bufflen);
	428	int __nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
d49187e9	429	union nvme_result result, void buffer, unsigned bufflen,
9a95e4ef BVA	430	unsigned timeout, int qid, int at_head,
9a95e4ef BVA	431	blk_mq_req_flags_t flags);
9a0be7ab	432	int nvme_set_queue_count(struct nvme_ctrl ctrl, int count);
038bd4cb	433	void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
d86c4d8e	434	int nvme_reset_ctrl(struct nvme_ctrl *ctrl);
79c48ccf	435	int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl);
c5017e85 CH	436	int nvme_delete_ctrl(struct nvme_ctrl *ctrl);
c5017e85 CH	437	int nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl);
f11bb3e2	438
d558fb51	439	int nvme_get_log_ext(struct nvme_ctrl ctrl, struct nvme_ns ns,
7ec6074f	440	u8 log_page, void *log, size_t size, u64 offset);
d558fb51	441
5b85b826	442	extern const struct attribute_group nvme_ns_id_attr_group;
32acab31 CH	443	extern const struct block_device_operations nvme_ns_head_ops;
	444
	445	#ifdef CONFIG_NVME_MULTIPATH
a785dbcc KB	446	void nvme_set_disk_name(char disk_name, struct nvme_ns ns,
a785dbcc KB	447	struct nvme_ctrl ctrl, int flags);
32acab31	448	void nvme_failover_req(struct request *req);
908e4564	449	bool nvme_req_needs_failover(struct request *req, blk_status_t error);
32acab31 CH	450	void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl);
	451	int nvme_mpath_alloc_disk(struct nvme_ctrl ctrl,struct nvme_ns_head head);
	452	void nvme_mpath_add_disk(struct nvme_ns_head *head);
	453	void nvme_mpath_remove_disk(struct nvme_ns_head *head);
	454
	455	static inline void nvme_mpath_clear_current_path(struct nvme_ns *ns)
	456	{
	457	struct nvme_ns_head *head = ns->head;
	458
978628ec	459	if (head && ns == rcu_access_pointer(head->current_path))
32acab31 CH	460	rcu_assign_pointer(head->current_path, NULL);
	461	}
	462	struct nvme_ns nvme_find_path(struct nvme_ns_head head);
479a322f SG	463
	464	static inline void nvme_mpath_check_last_path(struct nvme_ns *ns)
	465	{
	466	struct nvme_ns_head *head = ns->head;
	467
	468	if (head->disk && list_empty(&head->list))
	469	kblockd_schedule_work(&head->requeue_work);
	470	}
	471
32acab31	472	#else
a785dbcc KB	473	/*
	474	* Without the multipath code enabled, multiple controller per subsystems are
	475	* visible as devices and thus we cannot use the subsystem instance.
	476	*/
	477	static inline void nvme_set_disk_name(char disk_name, struct nvme_ns ns,
	478	struct nvme_ctrl ctrl, int flags)
	479	{
	480	sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->head->instance);
	481	}
	482
32acab31 CH	483	static inline void nvme_failover_req(struct request *req)
	484	{
	485	}
908e4564 KB	486	static inline bool nvme_req_needs_failover(struct request *req,
908e4564 KB	487	blk_status_t error)
32acab31 CH	488	{
	489	return false;
	490	}
	491	static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl)
	492	{
	493	}
	494	static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,
	495	struct nvme_ns_head *head)
	496	{
	497	return 0;
	498	}
	499	static inline void nvme_mpath_add_disk(struct nvme_ns_head *head)
	500	{
	501	}
	502	static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head)
	503	{
	504	}
	505	static inline void nvme_mpath_clear_current_path(struct nvme_ns *ns)
479a322f SG	506	{
	507	}
	508	static inline void nvme_mpath_check_last_path(struct nvme_ns *ns)
32acab31 CH	509	{
	510	}
	511	#endif /* CONFIG_NVME_MULTIPATH */
	512
c4699e70	513	#ifdef CONFIG_NVM
96257a8a	514	void nvme_nvm_update_nvm_info(struct nvme_ns *ns);
3dc87dd0	515	int nvme_nvm_register(struct nvme_ns ns, char disk_name, int node);
b0b4e09c	516	void nvme_nvm_unregister(struct nvme_ns *ns);
3dc87dd0 MB	517	int nvme_nvm_register_sysfs(struct nvme_ns *ns);
3dc87dd0 MB	518	void nvme_nvm_unregister_sysfs(struct nvme_ns *ns);
84d4add7	519	int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg);
c4699e70	520	#else
96257a8a	521	static inline void nvme_nvm_update_nvm_info(struct nvme_ns *ns) {};
b0b4e09c	522	static inline int nvme_nvm_register(struct nvme_ns ns, char disk_name,
3dc87dd0	523	int node)
c4699e70 KB	524	{
	525	return 0;
	526	}
	527
b0b4e09c	528	static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
3dc87dd0 MB	529	static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns)
	530	{
	531	return 0;
	532	}
	533	static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {};
84d4add7 MB	534	static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
	535	unsigned long arg)
	536	{
	537	return -ENOTTY;
	538	}
3dc87dd0 MB	539	#endif /* CONFIG_NVM */
3dc87dd0 MB	540
40267efd SL	541	static inline struct nvme_ns nvme_get_ns_from_dev(struct device dev)
	542	{
	543	return dev_to_disk(dev)->private_data;
	544	}
ca064085	545
5bae7f73 CH	546	int __init nvme_core_init(void);
	547	void nvme_core_exit(void);
	548
f11bb3e2	549	#endif /* _NVME_H */