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nvme: refactor command completion
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CommitLineData
bc50ad75 1/* SPDX-License-Identifier: GPL-2.0 */
f11bb3e2
CH
2/*
3 * Copyright (c) 2011-2014, Intel Corporation.
f11bb3e2
CH
4 */
5
6#ifndef _NVME_H
7#define _NVME_H
8
9#include <linux/nvme.h>
a6a5149b 10#include <linux/cdev.h>
f11bb3e2
CH
11#include <linux/pci.h>
12#include <linux/kref.h>
13#include <linux/blk-mq.h>
b0b4e09c 14#include <linux/lightnvm.h>
a98e58e5 15#include <linux/sed-opal.h>
b9e03857 16#include <linux/fault-inject.h>
978628ec 17#include <linux/rcupdate.h>
c1ac9a4b 18#include <linux/wait.h>
4d2ce688 19#include <linux/t10-pi.h>
f11bb3e2 20
35fe0d12
HR
21#include <trace/events/block.h>
22
8ae4e447 23extern unsigned int nvme_io_timeout;
f11bb3e2
CH
24#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
25
8ae4e447 26extern unsigned int admin_timeout;
21d34711
CH
27#define ADMIN_TIMEOUT (admin_timeout * HZ)
28
038bd4cb
SG
29#define NVME_DEFAULT_KATO 5
30#define NVME_KATO_GRACE 10
31
38e18002
IR
32#ifdef CONFIG_ARCH_NO_SG_CHAIN
33#define NVME_INLINE_SG_CNT 0
ba7ca2ae 34#define NVME_INLINE_METADATA_SG_CNT 0
38e18002
IR
35#else
36#define NVME_INLINE_SG_CNT 2
ba7ca2ae 37#define NVME_INLINE_METADATA_SG_CNT 1
38e18002
IR
38#endif
39
6c3c05b0
CK
40/*
41 * Default to a 4K page size, with the intention to update this
42 * path in the future to accommodate architectures with differing
43 * kernel and IO page sizes.
44 */
45#define NVME_CTRL_PAGE_SHIFT 12
46#define NVME_CTRL_PAGE_SIZE (1 << NVME_CTRL_PAGE_SHIFT)
47
9a6327d2 48extern struct workqueue_struct *nvme_wq;
b227c59b
RS
49extern struct workqueue_struct *nvme_reset_wq;
50extern struct workqueue_struct *nvme_delete_wq;
9a6327d2 51
ca064085
MB
52enum {
53 NVME_NS_LBA = 0,
54 NVME_NS_LIGHTNVM = 1,
55};
56
f11bb3e2 57/*
106198ed
CH
58 * List of workarounds for devices that required behavior not specified in
59 * the standard.
f11bb3e2 60 */
106198ed
CH
61enum nvme_quirks {
62 /*
63 * Prefers I/O aligned to a stripe size specified in a vendor
64 * specific Identify field.
65 */
66 NVME_QUIRK_STRIPE_SIZE = (1 << 0),
540c801c
KB
67
68 /*
69 * The controller doesn't handle Identify value others than 0 or 1
70 * correctly.
71 */
72 NVME_QUIRK_IDENTIFY_CNS = (1 << 1),
08095e70
KB
73
74 /*
e850fd16
CH
75 * The controller deterministically returns O's on reads to
76 * logical blocks that deallocate was called on.
08095e70 77 */
e850fd16 78 NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2),
54adc010
GP
79
80 /*
81 * The controller needs a delay before starts checking the device
82 * readiness, which is done by reading the NVME_CSTS_RDY bit.
83 */
84 NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3),
c5552fde
AL
85
86 /*
87 * APST should not be used.
88 */
89 NVME_QUIRK_NO_APST = (1 << 4),
ff5350a8
AL
90
91 /*
92 * The deepest sleep state should not be used.
93 */
94 NVME_QUIRK_NO_DEEPEST_PS = (1 << 5),
608cc4b1
CH
95
96 /*
97 * Supports the LighNVM command set if indicated in vs[1].
98 */
99 NVME_QUIRK_LIGHTNVM = (1 << 6),
9abd68ef
JA
100
101 /*
102 * Set MEDIUM priority on SQ creation
103 */
104 NVME_QUIRK_MEDIUM_PRIO_SQ = (1 << 7),
6299358d
JD
105
106 /*
107 * Ignore device provided subnqn.
108 */
109 NVME_QUIRK_IGNORE_DEV_SUBNQN = (1 << 8),
7b210e4e
CH
110
111 /*
112 * Broken Write Zeroes.
113 */
114 NVME_QUIRK_DISABLE_WRITE_ZEROES = (1 << 9),
cb32de1b
ML
115
116 /*
117 * Force simple suspend/resume path.
118 */
119 NVME_QUIRK_SIMPLE_SUSPEND = (1 << 10),
7ad67ca5 120
66341331
BH
121 /*
122 * Use only one interrupt vector for all queues
123 */
7ad67ca5 124 NVME_QUIRK_SINGLE_VECTOR = (1 << 11),
66341331
BH
125
126 /*
127 * Use non-standard 128 bytes SQEs.
128 */
7ad67ca5 129 NVME_QUIRK_128_BYTES_SQES = (1 << 12),
d38e9f04
BH
130
131 /*
132 * Prevent tag overlap between queues
133 */
7ad67ca5 134 NVME_QUIRK_SHARED_TAGS = (1 << 13),
6c6aa2f2
AM
135
136 /*
137 * Don't change the value of the temperature threshold feature
138 */
139 NVME_QUIRK_NO_TEMP_THRESH_CHANGE = (1 << 14),
5bedd3af
CH
140
141 /*
142 * The controller doesn't handle the Identify Namespace
143 * Identification Descriptor list subcommand despite claiming
144 * NVMe 1.3 compliance.
145 */
146 NVME_QUIRK_NO_NS_DESC_LIST = (1 << 15),
106198ed
CH
147};
148
d49187e9
CH
149/*
150 * Common request structure for NVMe passthrough. All drivers must have
151 * this structure as the first member of their request-private data.
152 */
153struct nvme_request {
154 struct nvme_command *cmd;
155 union nvme_result result;
44e44b29 156 u8 retries;
27fa9bc5
CH
157 u8 flags;
158 u16 status;
59e29ce6 159 struct nvme_ctrl *ctrl;
27fa9bc5
CH
160};
161
32acab31
CH
162/*
163 * Mark a bio as coming in through the mpath node.
164 */
165#define REQ_NVME_MPATH REQ_DRV
166
27fa9bc5
CH
167enum {
168 NVME_REQ_CANCELLED = (1 << 0),
bb06ec31 169 NVME_REQ_USERCMD = (1 << 1),
d49187e9
CH
170};
171
172static inline struct nvme_request *nvme_req(struct request *req)
173{
174 return blk_mq_rq_to_pdu(req);
175}
176
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177static inline u16 nvme_req_qid(struct request *req)
178{
179 if (!req->rq_disk)
180 return 0;
181 return blk_mq_unique_tag_to_hwq(blk_mq_unique_tag(req)) + 1;
182}
183
54adc010
GP
184/* The below value is the specific amount of delay needed before checking
185 * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
186 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
187 * found empirically.
188 */
8c97eecc 189#define NVME_QUIRK_DELAY_AMOUNT 2300
54adc010 190
4212f4e9
SG
191/*
192 * enum nvme_ctrl_state: Controller state
193 *
194 * @NVME_CTRL_NEW: New controller just allocated, initial state
195 * @NVME_CTRL_LIVE: Controller is connected and I/O capable
196 * @NVME_CTRL_RESETTING: Controller is resetting (or scheduled reset)
197 * @NVME_CTRL_CONNECTING: Controller is disconnected, now connecting the
198 * transport
199 * @NVME_CTRL_DELETING: Controller is deleting (or scheduled deletion)
ecca390e
SG
200 * @NVME_CTRL_DELETING_NOIO: Controller is deleting and I/O is not
201 * disabled/failed immediately. This state comes
202 * after all async event processing took place and
203 * before ns removal and the controller deletion
204 * progress
4212f4e9
SG
205 * @NVME_CTRL_DEAD: Controller is non-present/unresponsive during
206 * shutdown or removal. In this case we forcibly
207 * kill all inflight I/O as they have no chance to
208 * complete
209 */
bb8d261e
CH
210enum nvme_ctrl_state {
211 NVME_CTRL_NEW,
212 NVME_CTRL_LIVE,
213 NVME_CTRL_RESETTING,
ad6a0a52 214 NVME_CTRL_CONNECTING,
bb8d261e 215 NVME_CTRL_DELETING,
ecca390e 216 NVME_CTRL_DELETING_NOIO,
0ff9d4e1 217 NVME_CTRL_DEAD,
bb8d261e
CH
218};
219
a3646451
AM
220struct nvme_fault_inject {
221#ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
222 struct fault_attr attr;
223 struct dentry *parent;
224 bool dont_retry; /* DNR, do not retry */
225 u16 status; /* status code */
226#endif
227};
228
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229struct nvme_cel {
230 struct list_head entry;
231 struct nvme_effects_log log;
232 u8 csi;
233};
234
1c63dc66 235struct nvme_ctrl {
6e3ca03e 236 bool comp_seen;
bb8d261e 237 enum nvme_ctrl_state state;
bd4da3ab 238 bool identified;
bb8d261e 239 spinlock_t lock;
e7ad43c3 240 struct mutex scan_lock;
1c63dc66 241 const struct nvme_ctrl_ops *ops;
f11bb3e2 242 struct request_queue *admin_q;
07bfcd09 243 struct request_queue *connect_q;
e7832cb4 244 struct request_queue *fabrics_q;
f11bb3e2 245 struct device *dev;
f11bb3e2 246 int instance;
103e515e 247 int numa_node;
5bae7f73 248 struct blk_mq_tag_set *tagset;
34b6c231 249 struct blk_mq_tag_set *admin_tagset;
f11bb3e2 250 struct list_head namespaces;
765cc031 251 struct rw_semaphore namespaces_rwsem;
d22524a4 252 struct device ctrl_device;
5bae7f73 253 struct device *device; /* char device */
a6a5149b 254 struct cdev cdev;
d86c4d8e 255 struct work_struct reset_work;
c5017e85 256 struct work_struct delete_work;
c1ac9a4b 257 wait_queue_head_t state_wq;
1c63dc66 258
ab9e00cc
CH
259 struct nvme_subsystem *subsys;
260 struct list_head subsys_entry;
261
4f1244c8 262 struct opal_dev *opal_dev;
a98e58e5 263
f11bb3e2 264 char name[12];
76e3914a 265 u16 cntlid;
5fd4ce1b
CH
266
267 u32 ctrl_config;
b6dccf7f 268 u16 mtfa;
d858e5f0 269 u32 queue_count;
5fd4ce1b 270
20d0dfe6 271 u64 cap;
f11bb3e2 272 u32 max_hw_sectors;
943e942e 273 u32 max_segments;
95093350 274 u32 max_integrity_segments;
240e6ee2
KB
275#ifdef CONFIG_BLK_DEV_ZONED
276 u32 max_zone_append;
277#endif
49cd84b6 278 u16 crdt[3];
f11bb3e2 279 u16 oncs;
8a9ae523 280 u16 oacs;
f5d11840
JA
281 u16 nssa;
282 u16 nr_streams;
f968688f 283 u16 sqsize;
0d0b660f 284 u32 max_namespaces;
6bf25d16 285 atomic_t abort_limit;
f11bb3e2 286 u8 vwc;
f3ca80fc 287 u32 vs;
07bfcd09 288 u32 sgls;
038bd4cb 289 u16 kas;
c5552fde
AL
290 u8 npss;
291 u8 apsta;
400b6a7b
GR
292 u16 wctemp;
293 u16 cctemp;
c0561f82 294 u32 oaes;
e3d7874d 295 u32 aen_result;
3e53ba38 296 u32 ctratt;
07fbd32a 297 unsigned int shutdown_timeout;
038bd4cb 298 unsigned int kato;
f3ca80fc 299 bool subsystem;
106198ed 300 unsigned long quirks;
c5552fde 301 struct nvme_id_power_state psd[32];
84fef62d 302 struct nvme_effects_log *effects;
be93e87e 303 struct list_head cels;
5955be21 304 struct work_struct scan_work;
f866fc42 305 struct work_struct async_event_work;
038bd4cb 306 struct delayed_work ka_work;
0a34e466 307 struct nvme_command ka_cmd;
b6dccf7f 308 struct work_struct fw_act_work;
30d90964 309 unsigned long events;
ce151813 310 bool created;
07bfcd09 311
0d0b660f
CH
312#ifdef CONFIG_NVME_MULTIPATH
313 /* asymmetric namespace access: */
314 u8 anacap;
315 u8 anatt;
316 u32 anagrpmax;
317 u32 nanagrpid;
318 struct mutex ana_lock;
319 struct nvme_ana_rsp_hdr *ana_log_buf;
320 size_t ana_log_size;
321 struct timer_list anatt_timer;
322 struct work_struct ana_work;
323#endif
324
c5552fde
AL
325 /* Power saving configuration */
326 u64 ps_max_latency_us;
76a5af84 327 bool apst_enabled;
c5552fde 328
044a9df1 329 /* PCIe only: */
fe6d53c9
CH
330 u32 hmpre;
331 u32 hmmin;
044a9df1
CH
332 u32 hmminds;
333 u16 hmmaxd;
fe6d53c9 334
07bfcd09 335 /* Fabrics only */
07bfcd09
CH
336 u32 ioccsz;
337 u32 iorcsz;
338 u16 icdoff;
339 u16 maxcmd;
fdf9dfa8 340 int nr_reconnects;
07bfcd09 341 struct nvmf_ctrl_options *opts;
cb5b7262
JA
342
343 struct page *discard_page;
344 unsigned long discard_page_busy;
f79d5fda
AM
345
346 struct nvme_fault_inject fault_inject;
f11bb3e2
CH
347};
348
75c10e73
HR
349enum nvme_iopolicy {
350 NVME_IOPOLICY_NUMA,
351 NVME_IOPOLICY_RR,
352};
353
ab9e00cc
CH
354struct nvme_subsystem {
355 int instance;
356 struct device dev;
357 /*
358 * Because we unregister the device on the last put we need
359 * a separate refcount.
360 */
361 struct kref ref;
362 struct list_head entry;
363 struct mutex lock;
364 struct list_head ctrls;
ed754e5d 365 struct list_head nsheads;
ab9e00cc
CH
366 char subnqn[NVMF_NQN_SIZE];
367 char serial[20];
368 char model[40];
369 char firmware_rev[8];
370 u8 cmic;
371 u16 vendor_id;
81adb863 372 u16 awupf; /* 0's based awupf value. */
ed754e5d 373 struct ida ns_ida;
75c10e73
HR
374#ifdef CONFIG_NVME_MULTIPATH
375 enum nvme_iopolicy iopolicy;
376#endif
ab9e00cc
CH
377};
378
002fab04
CH
379/*
380 * Container structure for uniqueue namespace identifiers.
381 */
382struct nvme_ns_ids {
383 u8 eui64[8];
384 u8 nguid[16];
385 uuid_t uuid;
71010c30 386 u8 csi;
002fab04
CH
387};
388
ed754e5d
CH
389/*
390 * Anchor structure for namespaces. There is one for each namespace in a
391 * NVMe subsystem that any of our controllers can see, and the namespace
392 * structure for each controller is chained of it. For private namespaces
393 * there is a 1:1 relation to our namespace structures, that is ->list
394 * only ever has a single entry for private namespaces.
395 */
396struct nvme_ns_head {
397 struct list_head list;
398 struct srcu_struct srcu;
399 struct nvme_subsystem *subsys;
400 unsigned ns_id;
401 struct nvme_ns_ids ids;
402 struct list_head entry;
403 struct kref ref;
0c284db7 404 bool shared;
ed754e5d 405 int instance;
be93e87e 406 struct nvme_effects_log *effects;
f3334447
CH
407#ifdef CONFIG_NVME_MULTIPATH
408 struct gendisk *disk;
409 struct bio_list requeue_list;
410 spinlock_t requeue_lock;
411 struct work_struct requeue_work;
412 struct mutex lock;
d8a22f85
AE
413 unsigned long flags;
414#define NVME_NSHEAD_DISK_LIVE 0
f3334447
CH
415 struct nvme_ns __rcu *current_path[];
416#endif
ed754e5d
CH
417};
418
ffc89b1d
MG
419enum nvme_ns_features {
420 NVME_NS_EXT_LBAS = 1 << 0, /* support extended LBA format */
b29f8485 421 NVME_NS_METADATA_SUPPORTED = 1 << 1, /* support getting generated md */
ffc89b1d
MG
422};
423
f11bb3e2
CH
424struct nvme_ns {
425 struct list_head list;
426
1c63dc66 427 struct nvme_ctrl *ctrl;
f11bb3e2
CH
428 struct request_queue *queue;
429 struct gendisk *disk;
0d0b660f
CH
430#ifdef CONFIG_NVME_MULTIPATH
431 enum nvme_ana_state ana_state;
432 u32 ana_grpid;
433#endif
ed754e5d 434 struct list_head siblings;
b0b4e09c 435 struct nvm_dev *ndev;
f11bb3e2 436 struct kref kref;
ed754e5d 437 struct nvme_ns_head *head;
f11bb3e2 438
f11bb3e2
CH
439 int lba_shift;
440 u16 ms;
f5d11840
JA
441 u16 sgs;
442 u32 sws;
f11bb3e2 443 u8 pi_type;
240e6ee2
KB
444#ifdef CONFIG_BLK_DEV_ZONED
445 u64 zsze;
446#endif
ffc89b1d 447 unsigned long features;
646017a6 448 unsigned long flags;
0d0b660f
CH
449#define NVME_NS_REMOVING 0
450#define NVME_NS_DEAD 1
451#define NVME_NS_ANA_PENDING 2
b9e03857 452
b9e03857 453 struct nvme_fault_inject fault_inject;
b9e03857 454
f11bb3e2
CH
455};
456
4d2ce688
JS
457/* NVMe ns supports metadata actions by the controller (generate/strip) */
458static inline bool nvme_ns_has_pi(struct nvme_ns *ns)
459{
460 return ns->pi_type && ns->ms == sizeof(struct t10_pi_tuple);
461}
462
1c63dc66 463struct nvme_ctrl_ops {
1a353d85 464 const char *name;
e439bb12 465 struct module *module;
d3d5b87d
CH
466 unsigned int flags;
467#define NVME_F_FABRICS (1 << 0)
c81bfba9 468#define NVME_F_METADATA_SUPPORTED (1 << 1)
e0596ab2 469#define NVME_F_PCI_P2PDMA (1 << 2)
1c63dc66 470 int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val);
5fd4ce1b 471 int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val);
7fd8930f 472 int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val);
1673f1f0 473 void (*free_ctrl)(struct nvme_ctrl *ctrl);
ad22c355 474 void (*submit_async_event)(struct nvme_ctrl *ctrl);
c5017e85 475 void (*delete_ctrl)(struct nvme_ctrl *ctrl);
1a353d85 476 int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size);
f11bb3e2
CH
477};
478
b9e03857 479#ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
a3646451
AM
480void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj,
481 const char *dev_name);
482void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inject);
b9e03857
TT
483void nvme_should_fail(struct request *req);
484#else
a3646451
AM
485static inline void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj,
486 const char *dev_name)
487{
488}
489static inline void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inj)
490{
491}
b9e03857
TT
492static inline void nvme_should_fail(struct request *req) {}
493#endif
494
f3ca80fc
CH
495static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
496{
497 if (!ctrl->subsystem)
498 return -ENOTTY;
499 return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
500}
501
314d48dd
DLM
502/*
503 * Convert a 512B sector number to a device logical block number.
504 */
505static inline u64 nvme_sect_to_lba(struct nvme_ns *ns, sector_t sector)
f11bb3e2 506{
314d48dd 507 return sector >> (ns->lba_shift - SECTOR_SHIFT);
f11bb3e2
CH
508}
509
e08f2ae8
DLM
510/*
511 * Convert a device logical block number to a 512B sector number.
512 */
513static inline sector_t nvme_lba_to_sect(struct nvme_ns *ns, u64 lba)
f11bb3e2 514{
e08f2ae8 515 return lba << (ns->lba_shift - SECTOR_SHIFT);
f11bb3e2
CH
516}
517
71fb90eb
KB
518/*
519 * Convert byte length to nvme's 0-based num dwords
520 */
521static inline u32 nvme_bytes_to_numd(size_t len)
522{
523 return (len >> 2) - 1;
524}
525
5ddaabe8
CH
526static inline bool nvme_is_ana_error(u16 status)
527{
528 switch (status & 0x7ff) {
529 case NVME_SC_ANA_TRANSITION:
530 case NVME_SC_ANA_INACCESSIBLE:
531 case NVME_SC_ANA_PERSISTENT_LOSS:
532 return true;
533 default:
534 return false;
535 }
536}
537
538static inline bool nvme_is_path_error(u16 status)
539{
540 switch (status & 0x7ff) {
541 case NVME_SC_HOST_PATH_ERROR:
542 case NVME_SC_HOST_ABORTED_CMD:
543 case NVME_SC_ANA_TRANSITION:
544 case NVME_SC_ANA_INACCESSIBLE:
545 case NVME_SC_ANA_PERSISTENT_LOSS:
546 return true;
547 default:
548 return false;
549 }
550}
551
2eb81a33
CH
552/*
553 * Fill in the status and result information from the CQE, and then figure out
554 * if blk-mq will need to use IPI magic to complete the request, and if yes do
555 * so. If not let the caller complete the request without an indirect function
556 * call.
557 */
558static inline bool nvme_try_complete_req(struct request *req, __le16 status,
27fa9bc5 559 union nvme_result result)
15a190f7 560{
27fa9bc5 561 struct nvme_request *rq = nvme_req(req);
15a190f7 562
27fa9bc5
CH
563 rq->status = le16_to_cpu(status) >> 1;
564 rq->result = result;
b9e03857
TT
565 /* inject error when permitted by fault injection framework */
566 nvme_should_fail(req);
ff029451
CH
567 if (unlikely(blk_should_fake_timeout(req->q)))
568 return true;
569 return blk_mq_complete_request_remote(req);
7688faa6
CH
570}
571
d22524a4
CH
572static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl)
573{
574 get_device(ctrl->device);
575}
576
577static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl)
578{
579 put_device(ctrl->device);
580}
581
58a8df67
IR
582static inline bool nvme_is_aen_req(u16 qid, __u16 command_id)
583{
584 return !qid && command_id >= NVME_AQ_BLK_MQ_DEPTH;
585}
586
77f02a7a 587void nvme_complete_rq(struct request *req);
7baa8572 588bool nvme_cancel_request(struct request *req, void *data, bool reserved);
bb8d261e
CH
589bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
590 enum nvme_ctrl_state new_state);
c1ac9a4b 591bool nvme_wait_reset(struct nvme_ctrl *ctrl);
b5b05048 592int nvme_disable_ctrl(struct nvme_ctrl *ctrl);
c0f2f45b 593int nvme_enable_ctrl(struct nvme_ctrl *ctrl);
5fd4ce1b 594int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
f3ca80fc
CH
595int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
596 const struct nvme_ctrl_ops *ops, unsigned long quirks);
53029b04 597void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
d09f2b45
SG
598void nvme_start_ctrl(struct nvme_ctrl *ctrl);
599void nvme_stop_ctrl(struct nvme_ctrl *ctrl);
7fd8930f 600int nvme_init_identify(struct nvme_ctrl *ctrl);
5bae7f73 601
5bae7f73 602void nvme_remove_namespaces(struct nvme_ctrl *ctrl);
1673f1f0 603
4f1244c8
CH
604int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
605 bool send);
a98e58e5 606
7bf58533 607void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
287a63eb 608 volatile union nvme_result *res);
f866fc42 609
25646264
KB
610void nvme_stop_queues(struct nvme_ctrl *ctrl);
611void nvme_start_queues(struct nvme_ctrl *ctrl);
69d9a99c 612void nvme_kill_queues(struct nvme_ctrl *ctrl);
d6135c3a 613void nvme_sync_queues(struct nvme_ctrl *ctrl);
302ad8cc
KB
614void nvme_unfreeze(struct nvme_ctrl *ctrl);
615void nvme_wait_freeze(struct nvme_ctrl *ctrl);
616void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
617void nvme_start_freeze(struct nvme_ctrl *ctrl);
363c9aac 618
eb71f435 619#define NVME_QID_ANY -1
4160982e 620struct request *nvme_alloc_request(struct request_queue *q,
9a95e4ef 621 struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid);
f7f1fc36 622void nvme_cleanup_cmd(struct request *req);
fc17b653 623blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
8093f7ca 624 struct nvme_command *cmd);
f11bb3e2
CH
625int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
626 void *buf, unsigned bufflen);
627int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 628 union nvme_result *result, void *buffer, unsigned bufflen,
9a95e4ef 629 unsigned timeout, int qid, int at_head,
6287b51c 630 blk_mq_req_flags_t flags, bool poll);
1a87ee65
KB
631int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid,
632 unsigned int dword11, void *buffer, size_t buflen,
633 u32 *result);
634int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid,
635 unsigned int dword11, void *buffer, size_t buflen,
636 u32 *result);
9a0be7ab 637int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);
038bd4cb 638void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
d86c4d8e 639int nvme_reset_ctrl(struct nvme_ctrl *ctrl);
79c48ccf 640int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl);
c1ac9a4b 641int nvme_try_sched_reset(struct nvme_ctrl *ctrl);
c5017e85 642int nvme_delete_ctrl(struct nvme_ctrl *ctrl);
f11bb3e2 643
be93e87e 644int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, u8 csi,
0e98719b 645 void *log, size_t size, u64 offset);
240e6ee2
KB
646struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk,
647 struct nvme_ns_head **head, int *srcu_idx);
648void nvme_put_ns_from_disk(struct nvme_ns_head *head, int idx);
d558fb51 649
33b14f67 650extern const struct attribute_group *nvme_ns_id_attr_groups[];
32acab31
CH
651extern const struct block_device_operations nvme_ns_head_ops;
652
653#ifdef CONFIG_NVME_MULTIPATH
66b20ac0
MR
654static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl)
655{
656 return ctrl->ana_log_buf != NULL;
657}
658
b9156dae
SG
659void nvme_mpath_unfreeze(struct nvme_subsystem *subsys);
660void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys);
661void nvme_mpath_start_freeze(struct nvme_subsystem *subsys);
a785dbcc
KB
662void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns,
663 struct nvme_ctrl *ctrl, int *flags);
5ddaabe8 664void nvme_failover_req(struct request *req);
32acab31
CH
665void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl);
666int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,struct nvme_ns_head *head);
0d0b660f 667void nvme_mpath_add_disk(struct nvme_ns *ns, struct nvme_id_ns *id);
32acab31 668void nvme_mpath_remove_disk(struct nvme_ns_head *head);
0d0b660f
CH
669int nvme_mpath_init(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id);
670void nvme_mpath_uninit(struct nvme_ctrl *ctrl);
671void nvme_mpath_stop(struct nvme_ctrl *ctrl);
0157ec8d
SG
672bool nvme_mpath_clear_current_path(struct nvme_ns *ns);
673void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl);
32acab31 674struct nvme_ns *nvme_find_path(struct nvme_ns_head *head);
c62b37d9 675blk_qc_t nvme_ns_head_submit_bio(struct bio *bio);
479a322f
SG
676
677static inline void nvme_mpath_check_last_path(struct nvme_ns *ns)
678{
679 struct nvme_ns_head *head = ns->head;
680
681 if (head->disk && list_empty(&head->list))
682 kblockd_schedule_work(&head->requeue_work);
683}
684
35fe0d12
HR
685static inline void nvme_trace_bio_complete(struct request *req,
686 blk_status_t status)
687{
688 struct nvme_ns *ns = req->q->queuedata;
689
690 if (req->cmd_flags & REQ_NVME_MPATH)
d24de76a 691 trace_block_bio_complete(ns->head->disk->queue, req->bio);
35fe0d12
HR
692}
693
05b29021
AI
694static inline void nvme_mpath_update_disk_size(struct gendisk *disk)
695{
696 struct block_device *bdev = bdget_disk(disk, 0);
697
698 if (bdev) {
699 bd_set_size(bdev, get_capacity(disk) << SECTOR_SHIFT);
700 bdput(bdev);
701 }
702}
703
0d0b660f
CH
704extern struct device_attribute dev_attr_ana_grpid;
705extern struct device_attribute dev_attr_ana_state;
75c10e73 706extern struct device_attribute subsys_attr_iopolicy;
0d0b660f 707
32acab31 708#else
0d0b660f
CH
709static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl)
710{
711 return false;
712}
a785dbcc
KB
713/*
714 * Without the multipath code enabled, multiple controller per subsystems are
715 * visible as devices and thus we cannot use the subsystem instance.
716 */
717static inline void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns,
718 struct nvme_ctrl *ctrl, int *flags)
719{
720 sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->head->instance);
721}
722
5ddaabe8 723static inline void nvme_failover_req(struct request *req)
32acab31
CH
724{
725}
32acab31
CH
726static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl)
727{
728}
729static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,
730 struct nvme_ns_head *head)
731{
732 return 0;
733}
0d0b660f
CH
734static inline void nvme_mpath_add_disk(struct nvme_ns *ns,
735 struct nvme_id_ns *id)
32acab31
CH
736{
737}
738static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head)
739{
740}
0157ec8d
SG
741static inline bool nvme_mpath_clear_current_path(struct nvme_ns *ns)
742{
743 return false;
744}
745static inline void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl)
479a322f
SG
746{
747}
748static inline void nvme_mpath_check_last_path(struct nvme_ns *ns)
32acab31
CH
749{
750}
35fe0d12
HR
751static inline void nvme_trace_bio_complete(struct request *req,
752 blk_status_t status)
753{
754}
0d0b660f
CH
755static inline int nvme_mpath_init(struct nvme_ctrl *ctrl,
756 struct nvme_id_ctrl *id)
757{
14a1336e
CH
758 if (ctrl->subsys->cmic & (1 << 3))
759 dev_warn(ctrl->device,
760"Please enable CONFIG_NVME_MULTIPATH for full support of multi-port devices.\n");
0d0b660f
CH
761 return 0;
762}
763static inline void nvme_mpath_uninit(struct nvme_ctrl *ctrl)
764{
765}
766static inline void nvme_mpath_stop(struct nvme_ctrl *ctrl)
767{
768}
b9156dae
SG
769static inline void nvme_mpath_unfreeze(struct nvme_subsystem *subsys)
770{
771}
772static inline void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys)
773{
774}
775static inline void nvme_mpath_start_freeze(struct nvme_subsystem *subsys)
776{
777}
05b29021
AI
778static inline void nvme_mpath_update_disk_size(struct gendisk *disk)
779{
780}
32acab31
CH
781#endif /* CONFIG_NVME_MULTIPATH */
782
240e6ee2
KB
783#ifdef CONFIG_BLK_DEV_ZONED
784int nvme_update_zone_info(struct gendisk *disk, struct nvme_ns *ns,
785 unsigned lbaf);
786
787int nvme_report_zones(struct gendisk *disk, sector_t sector,
788 unsigned int nr_zones, report_zones_cb cb, void *data);
789
790blk_status_t nvme_setup_zone_mgmt_send(struct nvme_ns *ns, struct request *req,
791 struct nvme_command *cmnd,
792 enum nvme_zone_mgmt_action action);
793#else
794#define nvme_report_zones NULL
795
796static inline blk_status_t nvme_setup_zone_mgmt_send(struct nvme_ns *ns,
797 struct request *req, struct nvme_command *cmnd,
798 enum nvme_zone_mgmt_action action)
799{
800 return BLK_STS_NOTSUPP;
801}
802
803static inline int nvme_update_zone_info(struct gendisk *disk,
804 struct nvme_ns *ns,
805 unsigned lbaf)
806{
807 dev_warn(ns->ctrl->device,
808 "Please enable CONFIG_BLK_DEV_ZONED to support ZNS devices\n");
809 return -EPROTONOSUPPORT;
810}
811#endif
812
c4699e70 813#ifdef CONFIG_NVM
3dc87dd0 814int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node);
b0b4e09c 815void nvme_nvm_unregister(struct nvme_ns *ns);
33b14f67 816extern const struct attribute_group nvme_nvm_attr_group;
84d4add7 817int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg);
c4699e70 818#else
b0b4e09c 819static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name,
3dc87dd0 820 int node)
c4699e70
KB
821{
822 return 0;
823}
824
b0b4e09c 825static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
84d4add7
MB
826static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
827 unsigned long arg)
828{
829 return -ENOTTY;
830}
3dc87dd0
MB
831#endif /* CONFIG_NVM */
832
40267efd
SL
833static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev)
834{
835 return dev_to_disk(dev)->private_data;
836}
ca064085 837
400b6a7b
GR
838#ifdef CONFIG_NVME_HWMON
839void nvme_hwmon_init(struct nvme_ctrl *ctrl);
840#else
841static inline void nvme_hwmon_init(struct nvme_ctrl *ctrl) { }
842#endif
843
df21b6b1
LG
844u32 nvme_command_effects(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
845 u8 opcode);
17365ae6 846void nvme_execute_passthru_rq(struct request *rq);
f783f444 847struct nvme_ctrl *nvme_ctrl_get_by_path(const char *path);
24493b8b
LG
848struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid);
849void nvme_put_ns(struct nvme_ns *ns);
df21b6b1 850
f11bb3e2 851#endif /* _NVME_H */