[mirror_ubuntu-jammy-kernel.git] / drivers / nvme / host / nvme.h

/*
 * Copyright (c) 2011-2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef _NVME_H
#define _NVME_H

#include <linux/nvme.h>
#include <linux/pci.h>
#include <linux/kref.h>
#include <linux/blk-mq.h>

enum {
	/*
	 * Driver internal status code for commands that were cancelled due
	 * to timeouts or controller shutdown.  The value is negative so
	 * that it a) doesn't overlap with the unsigned hardware error codes,
	 * and b) can easily be tested for.
	 */
	NVME_SC_CANCELLED		= -EINTR,
};

extern unsigned char nvme_io_timeout;
#define NVME_IO_TIMEOUT	(nvme_io_timeout * HZ)

extern unsigned char admin_timeout;
#define ADMIN_TIMEOUT	(admin_timeout * HZ)

extern unsigned char shutdown_timeout;
#define SHUTDOWN_TIMEOUT	(shutdown_timeout * HZ)

enum {
	NVME_NS_LBA		= 0,
	NVME_NS_LIGHTNVM	= 1,
};

/*
 * List of workarounds for devices that required behavior not specified in
 * the standard.
 */
enum nvme_quirks {
	/*
	 * Prefers I/O aligned to a stripe size specified in a vendor
	 * specific Identify field.
	 */
	NVME_QUIRK_STRIPE_SIZE			= (1 << 0),

	/*
	 * The controller doesn't handle Identify value others than 0 or 1
	 * correctly.
	 */
	NVME_QUIRK_IDENTIFY_CNS			= (1 << 1),
};

struct nvme_ctrl {
	const struct nvme_ctrl_ops *ops;
	struct request_queue *admin_q;
	struct device *dev;
	struct kref kref;
	int instance;
	struct blk_mq_tag_set *tagset;
	struct list_head namespaces;
	struct mutex namespaces_mutex;
	struct device *device;	/* char device */
	struct list_head node;

	char name[12];
	char serial[20];
	char model[40];
	char firmware_rev[8];
	int cntlid;

	u32 ctrl_config;

	u32 page_size;
	u32 max_hw_sectors;
	u32 stripe_size;
	u16 oncs;
	atomic_t abort_limit;
	u8 event_limit;
	u8 vwc;
	u32 vs;
	bool subsystem;
	unsigned long quirks;
};

/*
 * An NVM Express namespace is equivalent to a SCSI LUN
 */
struct nvme_ns {
	struct list_head list;

	struct nvme_ctrl *ctrl;
	struct request_queue *queue;
	struct gendisk *disk;
	struct kref kref;

	u8 eui[8];
	u8 uuid[16];

	unsigned ns_id;
	int lba_shift;
	u16 ms;
	bool ext;
	u8 pi_type;
	int type;
	u64 mode_select_num_blocks;
	u32 mode_select_block_len;
};

struct nvme_ctrl_ops {
	struct module *module;
	int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val);
	int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val);
	int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val);
	bool (*io_incapable)(struct nvme_ctrl *ctrl);
	int (*reset_ctrl)(struct nvme_ctrl *ctrl);
	void (*free_ctrl)(struct nvme_ctrl *ctrl);
};

static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
{
	u32 val = 0;

	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
		return false;
	return val & NVME_CSTS_RDY;
}

static inline bool nvme_io_incapable(struct nvme_ctrl *ctrl)
{
	u32 val = 0;

	if (ctrl->ops->io_incapable(ctrl))
		return false;
	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
		return false;
	return val & NVME_CSTS_CFS;
}

static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
{
	if (!ctrl->subsystem)
		return -ENOTTY;
	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
}

static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
{
	return (sector >> (ns->lba_shift - 9));
}

static inline void nvme_setup_flush(struct nvme_ns *ns,
		struct nvme_command *cmnd)
{
	memset(cmnd, 0, sizeof(*cmnd));
	cmnd->common.opcode = nvme_cmd_flush;
	cmnd->common.nsid = cpu_to_le32(ns->ns_id);
}

static inline void nvme_setup_rw(struct nvme_ns *ns, struct request *req,
		struct nvme_command *cmnd)
{
	u16 control = 0;
	u32 dsmgmt = 0;

	if (req->cmd_flags & REQ_FUA)
		control |= NVME_RW_FUA;
	if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
		control |= NVME_RW_LR;

	if (req->cmd_flags & REQ_RAHEAD)
		dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;

	memset(cmnd, 0, sizeof(*cmnd));
	cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
	cmnd->rw.command_id = req->tag;
	cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
	cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
	cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);

	if (ns->ms) {
		switch (ns->pi_type) {
		case NVME_NS_DPS_PI_TYPE3:
			control |= NVME_RW_PRINFO_PRCHK_GUARD;
			break;
		case NVME_NS_DPS_PI_TYPE1:
		case NVME_NS_DPS_PI_TYPE2:
			control |= NVME_RW_PRINFO_PRCHK_GUARD |
					NVME_RW_PRINFO_PRCHK_REF;
			cmnd->rw.reftag = cpu_to_le32(
					nvme_block_nr(ns, blk_rq_pos(req)));
			break;
		}
		if (!blk_integrity_rq(req))
			control |= NVME_RW_PRINFO_PRACT;
	}

	cmnd->rw.control = cpu_to_le16(control);
	cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
}


static inline int nvme_error_status(u16 status)
{
	switch (status & 0x7ff) {
	case NVME_SC_SUCCESS:
		return 0;
	case NVME_SC_CAP_EXCEEDED:
		return -ENOSPC;
	default:
		return -EIO;
	}
}

static inline bool nvme_req_needs_retry(struct request *req, u16 status)
{
	return !(status & NVME_SC_DNR || blk_noretry_request(req)) &&
		(jiffies - req->start_time) < req->timeout;
}

int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
		const struct nvme_ctrl_ops *ops, unsigned long quirks);
void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
void nvme_put_ctrl(struct nvme_ctrl *ctrl);
int nvme_init_identify(struct nvme_ctrl *ctrl);

void nvme_scan_namespaces(struct nvme_ctrl *ctrl);
void nvme_remove_namespaces(struct nvme_ctrl *ctrl);

void nvme_stop_queues(struct nvme_ctrl *ctrl);
void nvme_start_queues(struct nvme_ctrl *ctrl);

struct request *nvme_alloc_request(struct request_queue *q,
		struct nvme_command *cmd, unsigned int flags);
void nvme_requeue_req(struct request *req);
int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		void *buf, unsigned bufflen);
int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		struct nvme_completion *cqe, void *buffer, unsigned bufflen,
		unsigned timeout);
int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
		void __user *ubuffer, unsigned bufflen, u32 *result,
		unsigned timeout);
int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
		void __user *ubuffer, unsigned bufflen,
		void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
		u32 *result, unsigned timeout);
int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id);
int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
		struct nvme_id_ns **id);
int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log);
int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
			dma_addr_t dma_addr, u32 *result);
int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
			dma_addr_t dma_addr, u32 *result);
int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);

struct sg_io_hdr;

int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr);
int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
int nvme_sg_get_version_num(int __user *ip);

#ifdef CONFIG_NVM
int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id);
int nvme_nvm_register(struct request_queue *q, char *disk_name);
void nvme_nvm_unregister(struct request_queue *q, char *disk_name);
#else
static inline int nvme_nvm_register(struct request_queue *q, char *disk_name)
{
	return 0;
}

static inline void nvme_nvm_unregister(struct request_queue *q, char *disk_name) {};

static inline int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id)
{
	return 0;
}
#endif /* CONFIG_NVM */

int __init nvme_core_init(void);
void nvme_core_exit(void);

#endif /* _NVME_H */
Commit	Line	Data
f11bb3e2 CH	1	/*
	2	* Copyright (c) 2011-2014, Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*/
	13
	14	#ifndef _NVME_H
	15	#define _NVME_H
	16
	17	#include <linux/nvme.h>
	18	#include <linux/pci.h>
	19	#include <linux/kref.h>
	20	#include <linux/blk-mq.h>
	21
297465c8 CH	22	enum {
	23	/*
	24	* Driver internal status code for commands that were cancelled due
	25	* to timeouts or controller shutdown. The value is negative so
	26	* that it a) doesn't overlap with the unsigned hardware error codes,
	27	* and b) can easily be tested for.
	28	*/
	29	NVME_SC_CANCELLED = -EINTR,
	30	};
	31
f11bb3e2 CH	32	extern unsigned char nvme_io_timeout;
	33	#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
	34
21d34711 CH	35	extern unsigned char admin_timeout;
	36	#define ADMIN_TIMEOUT (admin_timeout * HZ)
	37
5fd4ce1b CH	38	extern unsigned char shutdown_timeout;
	39	#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
	40
ca064085 MB	41	enum {
	42	NVME_NS_LBA = 0,
	43	NVME_NS_LIGHTNVM = 1,
	44	};
	45
f11bb3e2	46	/*
106198ed CH	47	* List of workarounds for devices that required behavior not specified in
106198ed CH	48	* the standard.
f11bb3e2	49	*/
106198ed CH	50	enum nvme_quirks {
	51	/*
	52	* Prefers I/O aligned to a stripe size specified in a vendor
	53	* specific Identify field.
	54	*/
	55	NVME_QUIRK_STRIPE_SIZE = (1 << 0),
540c801c KB	56
	57	/*
	58	* The controller doesn't handle Identify value others than 0 or 1
	59	* correctly.
	60	*/
	61	NVME_QUIRK_IDENTIFY_CNS = (1 << 1),
106198ed CH	62	};
106198ed CH	63
1c63dc66 CH	64	struct nvme_ctrl {
1c63dc66 CH	65	const struct nvme_ctrl_ops *ops;
f11bb3e2	66	struct request_queue *admin_q;
f11bb3e2	67	struct device *dev;
1673f1f0	68	struct kref kref;
f11bb3e2	69	int instance;
5bae7f73	70	struct blk_mq_tag_set *tagset;
f11bb3e2	71	struct list_head namespaces;
69d3b8ac	72	struct mutex namespaces_mutex;
5bae7f73	73	struct device device; / char device */
f3ca80fc	74	struct list_head node;
1c63dc66	75
f11bb3e2 CH	76	char name[12];
	77	char serial[20];
	78	char model[40];
	79	char firmware_rev[8];
931e1c22	80	int cntlid;
5fd4ce1b CH	81
	82	u32 ctrl_config;
	83
	84	u32 page_size;
f11bb3e2 CH	85	u32 max_hw_sectors;
f11bb3e2 CH	86	u32 stripe_size;
f11bb3e2	87	u16 oncs;
6bf25d16	88	atomic_t abort_limit;
f11bb3e2 CH	89	u8 event_limit;
f11bb3e2 CH	90	u8 vwc;
f3ca80fc CH	91	u32 vs;
f3ca80fc CH	92	bool subsystem;
106198ed	93	unsigned long quirks;
f11bb3e2 CH	94	};
	95
	96	/*
	97	* An NVM Express namespace is equivalent to a SCSI LUN
	98	*/
	99	struct nvme_ns {
	100	struct list_head list;
	101
1c63dc66	102	struct nvme_ctrl *ctrl;
f11bb3e2 CH	103	struct request_queue *queue;
	104	struct gendisk *disk;
	105	struct kref kref;
	106
2b9b6e86 KB	107	u8 eui[8];
	108	u8 uuid[16];
	109
f11bb3e2 CH	110	unsigned ns_id;
	111	int lba_shift;
	112	u16 ms;
	113	bool ext;
	114	u8 pi_type;
ca064085	115	int type;
f11bb3e2 CH	116	u64 mode_select_num_blocks;
	117	u32 mode_select_block_len;
	118	};
	119
1c63dc66	120	struct nvme_ctrl_ops {
e439bb12	121	struct module *module;
1c63dc66	122	int (reg_read32)(struct nvme_ctrl ctrl, u32 off, u32 *val);
5fd4ce1b	123	int (reg_write32)(struct nvme_ctrl ctrl, u32 off, u32 val);
7fd8930f	124	int (reg_read64)(struct nvme_ctrl ctrl, u32 off, u64 *val);
5bae7f73	125	bool (io_incapable)(struct nvme_ctrl ctrl);
f3ca80fc	126	int (reset_ctrl)(struct nvme_ctrl ctrl);
1673f1f0	127	void (free_ctrl)(struct nvme_ctrl ctrl);
f11bb3e2 CH	128	};
f11bb3e2 CH	129
1c63dc66 CH	130	static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
	131	{
	132	u32 val = 0;
	133
	134	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
	135	return false;
	136	return val & NVME_CSTS_RDY;
	137	}
	138
5bae7f73 CH	139	static inline bool nvme_io_incapable(struct nvme_ctrl *ctrl)
	140	{
	141	u32 val = 0;
	142
	143	if (ctrl->ops->io_incapable(ctrl))
	144	return false;
	145	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
	146	return false;
	147	return val & NVME_CSTS_CFS;
	148	}
	149
f3ca80fc CH	150	static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
	151	{
	152	if (!ctrl->subsystem)
	153	return -ENOTTY;
	154	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
	155	}
	156
f11bb3e2 CH	157	static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
	158	{
	159	return (sector >> (ns->lba_shift - 9));
	160	}
	161
22944e99 CH	162	static inline void nvme_setup_flush(struct nvme_ns *ns,
	163	struct nvme_command *cmnd)
	164	{
	165	memset(cmnd, 0, sizeof(*cmnd));
	166	cmnd->common.opcode = nvme_cmd_flush;
	167	cmnd->common.nsid = cpu_to_le32(ns->ns_id);
	168	}
	169
	170	static inline void nvme_setup_rw(struct nvme_ns ns, struct request req,
	171	struct nvme_command *cmnd)
	172	{
	173	u16 control = 0;
	174	u32 dsmgmt = 0;
	175
	176	if (req->cmd_flags & REQ_FUA)
	177	control \|= NVME_RW_FUA;
	178	if (req->cmd_flags & (REQ_FAILFAST_DEV \| REQ_RAHEAD))
	179	control \|= NVME_RW_LR;
	180
	181	if (req->cmd_flags & REQ_RAHEAD)
	182	dsmgmt \|= NVME_RW_DSM_FREQ_PREFETCH;
	183
	184	memset(cmnd, 0, sizeof(*cmnd));
	185	cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
	186	cmnd->rw.command_id = req->tag;
	187	cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
	188	cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
	189	cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
	190
	191	if (ns->ms) {
	192	switch (ns->pi_type) {
	193	case NVME_NS_DPS_PI_TYPE3:
	194	control \|= NVME_RW_PRINFO_PRCHK_GUARD;
	195	break;
	196	case NVME_NS_DPS_PI_TYPE1:
	197	case NVME_NS_DPS_PI_TYPE2:
	198	control \|= NVME_RW_PRINFO_PRCHK_GUARD \|
	199	NVME_RW_PRINFO_PRCHK_REF;
	200	cmnd->rw.reftag = cpu_to_le32(
	201	nvme_block_nr(ns, blk_rq_pos(req)));
	202	break;
	203	}
	204	if (!blk_integrity_rq(req))
	205	control \|= NVME_RW_PRINFO_PRACT;
	206	}
	207
	208	cmnd->rw.control = cpu_to_le16(control);
	209	cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
	210	}
	211
	212
15a190f7 CH	213	static inline int nvme_error_status(u16 status)
	214	{
	215	switch (status & 0x7ff) {
	216	case NVME_SC_SUCCESS:
	217	return 0;
	218	case NVME_SC_CAP_EXCEEDED:
	219	return -ENOSPC;
	220	default:
	221	return -EIO;
	222	}
	223	}
	224
7688faa6 CH	225	static inline bool nvme_req_needs_retry(struct request *req, u16 status)
	226	{
	227	return !(status & NVME_SC_DNR \|\| blk_noretry_request(req)) &&
	228	(jiffies - req->start_time) < req->timeout;
	229	}
	230
5fd4ce1b CH	231	int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	232	int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	233	int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
f3ca80fc CH	234	int nvme_init_ctrl(struct nvme_ctrl ctrl, struct device dev,
f3ca80fc CH	235	const struct nvme_ctrl_ops *ops, unsigned long quirks);
53029b04	236	void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
1673f1f0	237	void nvme_put_ctrl(struct nvme_ctrl *ctrl);
7fd8930f	238	int nvme_init_identify(struct nvme_ctrl *ctrl);
5bae7f73 CH	239
	240	void nvme_scan_namespaces(struct nvme_ctrl *ctrl);
	241	void nvme_remove_namespaces(struct nvme_ctrl *ctrl);
1673f1f0	242
25646264 KB	243	void nvme_stop_queues(struct nvme_ctrl *ctrl);
25646264 KB	244	void nvme_start_queues(struct nvme_ctrl *ctrl);
363c9aac	245
4160982e CH	246	struct request nvme_alloc_request(struct request_queue q,
4160982e CH	247	struct nvme_command *cmd, unsigned int flags);
7688faa6	248	void nvme_requeue_req(struct request *req);
f11bb3e2 CH	249	int nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
	250	void *buf, unsigned bufflen);
	251	int __nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
1cb3cce5 CH	252	struct nvme_completion cqe, void buffer, unsigned bufflen,
1cb3cce5 CH	253	unsigned timeout);
4160982e CH	254	int nvme_submit_user_cmd(struct request_queue q, struct nvme_command cmd,
	255	void __user ubuffer, unsigned bufflen, u32 result,
	256	unsigned timeout);
0b7f1f26 KB	257	int __nvme_submit_user_cmd(struct request_queue q, struct nvme_command cmd,
	258	void __user *ubuffer, unsigned bufflen,
	259	void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
f11bb3e2	260	u32 *result, unsigned timeout);
1c63dc66 CH	261	int nvme_identify_ctrl(struct nvme_ctrl dev, struct nvme_id_ctrl *id);
1c63dc66 CH	262	int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
f11bb3e2	263	struct nvme_id_ns **id);
1c63dc66 CH	264	int nvme_get_log_page(struct nvme_ctrl dev, struct nvme_smart_log *log);
1c63dc66 CH	265	int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
f11bb3e2	266	dma_addr_t dma_addr, u32 *result);
1c63dc66	267	int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
f11bb3e2	268	dma_addr_t dma_addr, u32 *result);
9a0be7ab	269	int nvme_set_queue_count(struct nvme_ctrl ctrl, int count);
f11bb3e2 CH	270
	271	struct sg_io_hdr;
	272
	273	int nvme_sg_io(struct nvme_ns ns, struct sg_io_hdr __user u_hdr);
	274	int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
	275	int nvme_sg_get_version_num(int __user *ip);
	276
c4699e70	277	#ifdef CONFIG_NVM
ca064085 MB	278	int nvme_nvm_ns_supported(struct nvme_ns ns, struct nvme_id_ns id);
	279	int nvme_nvm_register(struct request_queue q, char disk_name);
	280	void nvme_nvm_unregister(struct request_queue q, char disk_name);
c4699e70 KB	281	#else
	282	static inline int nvme_nvm_register(struct request_queue q, char disk_name)
	283	{
	284	return 0;
	285	}
	286
	287	static inline void nvme_nvm_unregister(struct request_queue q, char disk_name) {};
	288
	289	static inline int nvme_nvm_ns_supported(struct nvme_ns ns, struct nvme_id_ns id)
	290	{
	291	return 0;
	292	}
	293	#endif /* CONFIG_NVM */
ca064085	294
5bae7f73 CH	295	int __init nvme_core_init(void);
	296	void nvme_core_exit(void);
	297
f11bb3e2	298	#endif /* _NVME_H */