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bc50ad75 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
f11bb3e2 CH |
2 | /* |
3 | * Copyright (c) 2011-2014, Intel Corporation. | |
f11bb3e2 CH |
4 | */ |
5 | ||
6 | #ifndef _NVME_H | |
7 | #define _NVME_H | |
8 | ||
9 | #include <linux/nvme.h> | |
a6a5149b | 10 | #include <linux/cdev.h> |
f11bb3e2 CH |
11 | #include <linux/pci.h> |
12 | #include <linux/kref.h> | |
13 | #include <linux/blk-mq.h> | |
b0b4e09c | 14 | #include <linux/lightnvm.h> |
a98e58e5 | 15 | #include <linux/sed-opal.h> |
b9e03857 | 16 | #include <linux/fault-inject.h> |
978628ec | 17 | #include <linux/rcupdate.h> |
f11bb3e2 | 18 | |
35fe0d12 HR |
19 | #include <trace/events/block.h> |
20 | ||
8ae4e447 | 21 | extern unsigned int nvme_io_timeout; |
f11bb3e2 CH |
22 | #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) |
23 | ||
8ae4e447 | 24 | extern unsigned int admin_timeout; |
21d34711 CH |
25 | #define ADMIN_TIMEOUT (admin_timeout * HZ) |
26 | ||
038bd4cb SG |
27 | #define NVME_DEFAULT_KATO 5 |
28 | #define NVME_KATO_GRACE 10 | |
29 | ||
9a6327d2 | 30 | extern struct workqueue_struct *nvme_wq; |
b227c59b RS |
31 | extern struct workqueue_struct *nvme_reset_wq; |
32 | extern struct workqueue_struct *nvme_delete_wq; | |
9a6327d2 | 33 | |
ca064085 MB |
34 | enum { |
35 | NVME_NS_LBA = 0, | |
36 | NVME_NS_LIGHTNVM = 1, | |
37 | }; | |
38 | ||
f11bb3e2 | 39 | /* |
106198ed CH |
40 | * List of workarounds for devices that required behavior not specified in |
41 | * the standard. | |
f11bb3e2 | 42 | */ |
106198ed CH |
43 | enum nvme_quirks { |
44 | /* | |
45 | * Prefers I/O aligned to a stripe size specified in a vendor | |
46 | * specific Identify field. | |
47 | */ | |
48 | NVME_QUIRK_STRIPE_SIZE = (1 << 0), | |
540c801c KB |
49 | |
50 | /* | |
51 | * The controller doesn't handle Identify value others than 0 or 1 | |
52 | * correctly. | |
53 | */ | |
54 | NVME_QUIRK_IDENTIFY_CNS = (1 << 1), | |
08095e70 KB |
55 | |
56 | /* | |
e850fd16 CH |
57 | * The controller deterministically returns O's on reads to |
58 | * logical blocks that deallocate was called on. | |
08095e70 | 59 | */ |
e850fd16 | 60 | NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2), |
54adc010 GP |
61 | |
62 | /* | |
63 | * The controller needs a delay before starts checking the device | |
64 | * readiness, which is done by reading the NVME_CSTS_RDY bit. | |
65 | */ | |
66 | NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), | |
c5552fde AL |
67 | |
68 | /* | |
69 | * APST should not be used. | |
70 | */ | |
71 | NVME_QUIRK_NO_APST = (1 << 4), | |
ff5350a8 AL |
72 | |
73 | /* | |
74 | * The deepest sleep state should not be used. | |
75 | */ | |
76 | NVME_QUIRK_NO_DEEPEST_PS = (1 << 5), | |
608cc4b1 CH |
77 | |
78 | /* | |
79 | * Supports the LighNVM command set if indicated in vs[1]. | |
80 | */ | |
81 | NVME_QUIRK_LIGHTNVM = (1 << 6), | |
9abd68ef JA |
82 | |
83 | /* | |
84 | * Set MEDIUM priority on SQ creation | |
85 | */ | |
86 | NVME_QUIRK_MEDIUM_PRIO_SQ = (1 << 7), | |
6299358d JD |
87 | |
88 | /* | |
89 | * Ignore device provided subnqn. | |
90 | */ | |
91 | NVME_QUIRK_IGNORE_DEV_SUBNQN = (1 << 8), | |
7b210e4e CH |
92 | |
93 | /* | |
94 | * Broken Write Zeroes. | |
95 | */ | |
96 | NVME_QUIRK_DISABLE_WRITE_ZEROES = (1 << 9), | |
cb32de1b ML |
97 | |
98 | /* | |
99 | * Force simple suspend/resume path. | |
100 | */ | |
101 | NVME_QUIRK_SIMPLE_SUSPEND = (1 << 10), | |
7ad67ca5 | 102 | |
66341331 BH |
103 | /* |
104 | * Use only one interrupt vector for all queues | |
105 | */ | |
7ad67ca5 | 106 | NVME_QUIRK_SINGLE_VECTOR = (1 << 11), |
66341331 BH |
107 | |
108 | /* | |
109 | * Use non-standard 128 bytes SQEs. | |
110 | */ | |
7ad67ca5 | 111 | NVME_QUIRK_128_BYTES_SQES = (1 << 12), |
d38e9f04 BH |
112 | |
113 | /* | |
114 | * Prevent tag overlap between queues | |
115 | */ | |
7ad67ca5 | 116 | NVME_QUIRK_SHARED_TAGS = (1 << 13), |
106198ed CH |
117 | }; |
118 | ||
d49187e9 CH |
119 | /* |
120 | * Common request structure for NVMe passthrough. All drivers must have | |
121 | * this structure as the first member of their request-private data. | |
122 | */ | |
123 | struct nvme_request { | |
124 | struct nvme_command *cmd; | |
125 | union nvme_result result; | |
44e44b29 | 126 | u8 retries; |
27fa9bc5 CH |
127 | u8 flags; |
128 | u16 status; | |
59e29ce6 | 129 | struct nvme_ctrl *ctrl; |
27fa9bc5 CH |
130 | }; |
131 | ||
32acab31 CH |
132 | /* |
133 | * Mark a bio as coming in through the mpath node. | |
134 | */ | |
135 | #define REQ_NVME_MPATH REQ_DRV | |
136 | ||
27fa9bc5 CH |
137 | enum { |
138 | NVME_REQ_CANCELLED = (1 << 0), | |
bb06ec31 | 139 | NVME_REQ_USERCMD = (1 << 1), |
d49187e9 CH |
140 | }; |
141 | ||
142 | static inline struct nvme_request *nvme_req(struct request *req) | |
143 | { | |
144 | return blk_mq_rq_to_pdu(req); | |
145 | } | |
146 | ||
5d87eb94 KB |
147 | static inline u16 nvme_req_qid(struct request *req) |
148 | { | |
149 | if (!req->rq_disk) | |
150 | return 0; | |
151 | return blk_mq_unique_tag_to_hwq(blk_mq_unique_tag(req)) + 1; | |
152 | } | |
153 | ||
54adc010 GP |
154 | /* The below value is the specific amount of delay needed before checking |
155 | * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the | |
156 | * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was | |
157 | * found empirically. | |
158 | */ | |
8c97eecc | 159 | #define NVME_QUIRK_DELAY_AMOUNT 2300 |
54adc010 | 160 | |
bb8d261e CH |
161 | enum nvme_ctrl_state { |
162 | NVME_CTRL_NEW, | |
163 | NVME_CTRL_LIVE, | |
2b1b7e78 | 164 | NVME_CTRL_ADMIN_ONLY, /* Only admin queue live */ |
bb8d261e | 165 | NVME_CTRL_RESETTING, |
ad6a0a52 | 166 | NVME_CTRL_CONNECTING, |
bb8d261e | 167 | NVME_CTRL_DELETING, |
0ff9d4e1 | 168 | NVME_CTRL_DEAD, |
bb8d261e CH |
169 | }; |
170 | ||
a3646451 AM |
171 | struct nvme_fault_inject { |
172 | #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS | |
173 | struct fault_attr attr; | |
174 | struct dentry *parent; | |
175 | bool dont_retry; /* DNR, do not retry */ | |
176 | u16 status; /* status code */ | |
177 | #endif | |
178 | }; | |
179 | ||
1c63dc66 | 180 | struct nvme_ctrl { |
6e3ca03e | 181 | bool comp_seen; |
bb8d261e | 182 | enum nvme_ctrl_state state; |
bd4da3ab | 183 | bool identified; |
bb8d261e | 184 | spinlock_t lock; |
e7ad43c3 | 185 | struct mutex scan_lock; |
1c63dc66 | 186 | const struct nvme_ctrl_ops *ops; |
f11bb3e2 | 187 | struct request_queue *admin_q; |
07bfcd09 | 188 | struct request_queue *connect_q; |
e7832cb4 | 189 | struct request_queue *fabrics_q; |
f11bb3e2 | 190 | struct device *dev; |
f11bb3e2 | 191 | int instance; |
103e515e | 192 | int numa_node; |
5bae7f73 | 193 | struct blk_mq_tag_set *tagset; |
34b6c231 | 194 | struct blk_mq_tag_set *admin_tagset; |
f11bb3e2 | 195 | struct list_head namespaces; |
765cc031 | 196 | struct rw_semaphore namespaces_rwsem; |
d22524a4 | 197 | struct device ctrl_device; |
5bae7f73 | 198 | struct device *device; /* char device */ |
a6a5149b | 199 | struct cdev cdev; |
d86c4d8e | 200 | struct work_struct reset_work; |
c5017e85 | 201 | struct work_struct delete_work; |
1c63dc66 | 202 | |
ab9e00cc CH |
203 | struct nvme_subsystem *subsys; |
204 | struct list_head subsys_entry; | |
205 | ||
4f1244c8 | 206 | struct opal_dev *opal_dev; |
a98e58e5 | 207 | |
f11bb3e2 | 208 | char name[12]; |
76e3914a | 209 | u16 cntlid; |
5fd4ce1b CH |
210 | |
211 | u32 ctrl_config; | |
b6dccf7f | 212 | u16 mtfa; |
d858e5f0 | 213 | u32 queue_count; |
5fd4ce1b | 214 | |
20d0dfe6 | 215 | u64 cap; |
5fd4ce1b | 216 | u32 page_size; |
f11bb3e2 | 217 | u32 max_hw_sectors; |
943e942e | 218 | u32 max_segments; |
49cd84b6 | 219 | u16 crdt[3]; |
f11bb3e2 | 220 | u16 oncs; |
8a9ae523 | 221 | u16 oacs; |
f5d11840 JA |
222 | u16 nssa; |
223 | u16 nr_streams; | |
f968688f | 224 | u16 sqsize; |
0d0b660f | 225 | u32 max_namespaces; |
6bf25d16 | 226 | atomic_t abort_limit; |
f11bb3e2 | 227 | u8 vwc; |
f3ca80fc | 228 | u32 vs; |
07bfcd09 | 229 | u32 sgls; |
038bd4cb | 230 | u16 kas; |
c5552fde AL |
231 | u8 npss; |
232 | u8 apsta; | |
c0561f82 | 233 | u32 oaes; |
e3d7874d | 234 | u32 aen_result; |
3e53ba38 | 235 | u32 ctratt; |
07fbd32a | 236 | unsigned int shutdown_timeout; |
038bd4cb | 237 | unsigned int kato; |
f3ca80fc | 238 | bool subsystem; |
106198ed | 239 | unsigned long quirks; |
c5552fde | 240 | struct nvme_id_power_state psd[32]; |
84fef62d | 241 | struct nvme_effects_log *effects; |
5955be21 | 242 | struct work_struct scan_work; |
f866fc42 | 243 | struct work_struct async_event_work; |
038bd4cb | 244 | struct delayed_work ka_work; |
0a34e466 | 245 | struct nvme_command ka_cmd; |
b6dccf7f | 246 | struct work_struct fw_act_work; |
30d90964 | 247 | unsigned long events; |
07bfcd09 | 248 | |
0d0b660f CH |
249 | #ifdef CONFIG_NVME_MULTIPATH |
250 | /* asymmetric namespace access: */ | |
251 | u8 anacap; | |
252 | u8 anatt; | |
253 | u32 anagrpmax; | |
254 | u32 nanagrpid; | |
255 | struct mutex ana_lock; | |
256 | struct nvme_ana_rsp_hdr *ana_log_buf; | |
257 | size_t ana_log_size; | |
258 | struct timer_list anatt_timer; | |
259 | struct work_struct ana_work; | |
260 | #endif | |
261 | ||
c5552fde AL |
262 | /* Power saving configuration */ |
263 | u64 ps_max_latency_us; | |
76a5af84 | 264 | bool apst_enabled; |
c5552fde | 265 | |
044a9df1 | 266 | /* PCIe only: */ |
fe6d53c9 CH |
267 | u32 hmpre; |
268 | u32 hmmin; | |
044a9df1 CH |
269 | u32 hmminds; |
270 | u16 hmmaxd; | |
fe6d53c9 | 271 | |
07bfcd09 | 272 | /* Fabrics only */ |
07bfcd09 CH |
273 | u32 ioccsz; |
274 | u32 iorcsz; | |
275 | u16 icdoff; | |
276 | u16 maxcmd; | |
fdf9dfa8 | 277 | int nr_reconnects; |
07bfcd09 | 278 | struct nvmf_ctrl_options *opts; |
cb5b7262 JA |
279 | |
280 | struct page *discard_page; | |
281 | unsigned long discard_page_busy; | |
f79d5fda AM |
282 | |
283 | struct nvme_fault_inject fault_inject; | |
f11bb3e2 CH |
284 | }; |
285 | ||
75c10e73 HR |
286 | enum nvme_iopolicy { |
287 | NVME_IOPOLICY_NUMA, | |
288 | NVME_IOPOLICY_RR, | |
289 | }; | |
290 | ||
ab9e00cc CH |
291 | struct nvme_subsystem { |
292 | int instance; | |
293 | struct device dev; | |
294 | /* | |
295 | * Because we unregister the device on the last put we need | |
296 | * a separate refcount. | |
297 | */ | |
298 | struct kref ref; | |
299 | struct list_head entry; | |
300 | struct mutex lock; | |
301 | struct list_head ctrls; | |
ed754e5d | 302 | struct list_head nsheads; |
ab9e00cc CH |
303 | char subnqn[NVMF_NQN_SIZE]; |
304 | char serial[20]; | |
305 | char model[40]; | |
306 | char firmware_rev[8]; | |
307 | u8 cmic; | |
308 | u16 vendor_id; | |
81adb863 | 309 | u16 awupf; /* 0's based awupf value. */ |
ed754e5d | 310 | struct ida ns_ida; |
75c10e73 HR |
311 | #ifdef CONFIG_NVME_MULTIPATH |
312 | enum nvme_iopolicy iopolicy; | |
313 | #endif | |
ab9e00cc CH |
314 | }; |
315 | ||
002fab04 CH |
316 | /* |
317 | * Container structure for uniqueue namespace identifiers. | |
318 | */ | |
319 | struct nvme_ns_ids { | |
320 | u8 eui64[8]; | |
321 | u8 nguid[16]; | |
322 | uuid_t uuid; | |
323 | }; | |
324 | ||
ed754e5d CH |
325 | /* |
326 | * Anchor structure for namespaces. There is one for each namespace in a | |
327 | * NVMe subsystem that any of our controllers can see, and the namespace | |
328 | * structure for each controller is chained of it. For private namespaces | |
329 | * there is a 1:1 relation to our namespace structures, that is ->list | |
330 | * only ever has a single entry for private namespaces. | |
331 | */ | |
332 | struct nvme_ns_head { | |
333 | struct list_head list; | |
334 | struct srcu_struct srcu; | |
335 | struct nvme_subsystem *subsys; | |
336 | unsigned ns_id; | |
337 | struct nvme_ns_ids ids; | |
338 | struct list_head entry; | |
339 | struct kref ref; | |
340 | int instance; | |
f3334447 CH |
341 | #ifdef CONFIG_NVME_MULTIPATH |
342 | struct gendisk *disk; | |
343 | struct bio_list requeue_list; | |
344 | spinlock_t requeue_lock; | |
345 | struct work_struct requeue_work; | |
346 | struct mutex lock; | |
347 | struct nvme_ns __rcu *current_path[]; | |
348 | #endif | |
ed754e5d CH |
349 | }; |
350 | ||
f11bb3e2 CH |
351 | struct nvme_ns { |
352 | struct list_head list; | |
353 | ||
1c63dc66 | 354 | struct nvme_ctrl *ctrl; |
f11bb3e2 CH |
355 | struct request_queue *queue; |
356 | struct gendisk *disk; | |
0d0b660f CH |
357 | #ifdef CONFIG_NVME_MULTIPATH |
358 | enum nvme_ana_state ana_state; | |
359 | u32 ana_grpid; | |
360 | #endif | |
ed754e5d | 361 | struct list_head siblings; |
b0b4e09c | 362 | struct nvm_dev *ndev; |
f11bb3e2 | 363 | struct kref kref; |
ed754e5d | 364 | struct nvme_ns_head *head; |
f11bb3e2 | 365 | |
f11bb3e2 CH |
366 | int lba_shift; |
367 | u16 ms; | |
f5d11840 JA |
368 | u16 sgs; |
369 | u32 sws; | |
f11bb3e2 CH |
370 | bool ext; |
371 | u8 pi_type; | |
646017a6 | 372 | unsigned long flags; |
0d0b660f CH |
373 | #define NVME_NS_REMOVING 0 |
374 | #define NVME_NS_DEAD 1 | |
375 | #define NVME_NS_ANA_PENDING 2 | |
57eeaf8e | 376 | u16 noiob; |
b9e03857 | 377 | |
b9e03857 | 378 | struct nvme_fault_inject fault_inject; |
b9e03857 | 379 | |
f11bb3e2 CH |
380 | }; |
381 | ||
1c63dc66 | 382 | struct nvme_ctrl_ops { |
1a353d85 | 383 | const char *name; |
e439bb12 | 384 | struct module *module; |
d3d5b87d CH |
385 | unsigned int flags; |
386 | #define NVME_F_FABRICS (1 << 0) | |
c81bfba9 | 387 | #define NVME_F_METADATA_SUPPORTED (1 << 1) |
e0596ab2 | 388 | #define NVME_F_PCI_P2PDMA (1 << 2) |
1c63dc66 | 389 | int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); |
5fd4ce1b | 390 | int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); |
7fd8930f | 391 | int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); |
1673f1f0 | 392 | void (*free_ctrl)(struct nvme_ctrl *ctrl); |
ad22c355 | 393 | void (*submit_async_event)(struct nvme_ctrl *ctrl); |
c5017e85 | 394 | void (*delete_ctrl)(struct nvme_ctrl *ctrl); |
1a353d85 | 395 | int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); |
f11bb3e2 CH |
396 | }; |
397 | ||
b9e03857 | 398 | #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS |
a3646451 AM |
399 | void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj, |
400 | const char *dev_name); | |
401 | void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inject); | |
b9e03857 TT |
402 | void nvme_should_fail(struct request *req); |
403 | #else | |
a3646451 AM |
404 | static inline void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj, |
405 | const char *dev_name) | |
406 | { | |
407 | } | |
408 | static inline void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inj) | |
409 | { | |
410 | } | |
b9e03857 TT |
411 | static inline void nvme_should_fail(struct request *req) {} |
412 | #endif | |
413 | ||
f3ca80fc CH |
414 | static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) |
415 | { | |
416 | if (!ctrl->subsystem) | |
417 | return -ENOTTY; | |
418 | return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); | |
419 | } | |
420 | ||
314d48dd DLM |
421 | /* |
422 | * Convert a 512B sector number to a device logical block number. | |
423 | */ | |
424 | static inline u64 nvme_sect_to_lba(struct nvme_ns *ns, sector_t sector) | |
f11bb3e2 | 425 | { |
314d48dd | 426 | return sector >> (ns->lba_shift - SECTOR_SHIFT); |
f11bb3e2 CH |
427 | } |
428 | ||
e08f2ae8 DLM |
429 | /* |
430 | * Convert a device logical block number to a 512B sector number. | |
431 | */ | |
432 | static inline sector_t nvme_lba_to_sect(struct nvme_ns *ns, u64 lba) | |
433 | { | |
434 | return lba << (ns->lba_shift - SECTOR_SHIFT); | |
435 | } | |
436 | ||
27fa9bc5 CH |
437 | static inline void nvme_end_request(struct request *req, __le16 status, |
438 | union nvme_result result) | |
15a190f7 | 439 | { |
27fa9bc5 | 440 | struct nvme_request *rq = nvme_req(req); |
15a190f7 | 441 | |
27fa9bc5 CH |
442 | rq->status = le16_to_cpu(status) >> 1; |
443 | rq->result = result; | |
b9e03857 TT |
444 | /* inject error when permitted by fault injection framework */ |
445 | nvme_should_fail(req); | |
08e0029a | 446 | blk_mq_complete_request(req); |
7688faa6 CH |
447 | } |
448 | ||
d22524a4 CH |
449 | static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl) |
450 | { | |
451 | get_device(ctrl->device); | |
452 | } | |
453 | ||
454 | static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl) | |
455 | { | |
456 | put_device(ctrl->device); | |
457 | } | |
458 | ||
58a8df67 IR |
459 | static inline bool nvme_is_aen_req(u16 qid, __u16 command_id) |
460 | { | |
461 | return !qid && command_id >= NVME_AQ_BLK_MQ_DEPTH; | |
462 | } | |
463 | ||
77f02a7a | 464 | void nvme_complete_rq(struct request *req); |
7baa8572 | 465 | bool nvme_cancel_request(struct request *req, void *data, bool reserved); |
bb8d261e CH |
466 | bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, |
467 | enum nvme_ctrl_state new_state); | |
b5b05048 | 468 | int nvme_disable_ctrl(struct nvme_ctrl *ctrl); |
c0f2f45b | 469 | int nvme_enable_ctrl(struct nvme_ctrl *ctrl); |
5fd4ce1b | 470 | int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl); |
f3ca80fc CH |
471 | int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, |
472 | const struct nvme_ctrl_ops *ops, unsigned long quirks); | |
53029b04 | 473 | void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); |
d09f2b45 SG |
474 | void nvme_start_ctrl(struct nvme_ctrl *ctrl); |
475 | void nvme_stop_ctrl(struct nvme_ctrl *ctrl); | |
1673f1f0 | 476 | void nvme_put_ctrl(struct nvme_ctrl *ctrl); |
7fd8930f | 477 | int nvme_init_identify(struct nvme_ctrl *ctrl); |
5bae7f73 | 478 | |
5bae7f73 | 479 | void nvme_remove_namespaces(struct nvme_ctrl *ctrl); |
1673f1f0 | 480 | |
4f1244c8 CH |
481 | int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len, |
482 | bool send); | |
a98e58e5 | 483 | |
7bf58533 | 484 | void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, |
287a63eb | 485 | volatile union nvme_result *res); |
f866fc42 | 486 | |
25646264 KB |
487 | void nvme_stop_queues(struct nvme_ctrl *ctrl); |
488 | void nvme_start_queues(struct nvme_ctrl *ctrl); | |
69d9a99c | 489 | void nvme_kill_queues(struct nvme_ctrl *ctrl); |
d6135c3a | 490 | void nvme_sync_queues(struct nvme_ctrl *ctrl); |
302ad8cc KB |
491 | void nvme_unfreeze(struct nvme_ctrl *ctrl); |
492 | void nvme_wait_freeze(struct nvme_ctrl *ctrl); | |
493 | void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout); | |
494 | void nvme_start_freeze(struct nvme_ctrl *ctrl); | |
363c9aac | 495 | |
eb71f435 | 496 | #define NVME_QID_ANY -1 |
4160982e | 497 | struct request *nvme_alloc_request(struct request_queue *q, |
9a95e4ef | 498 | struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid); |
f7f1fc36 | 499 | void nvme_cleanup_cmd(struct request *req); |
fc17b653 | 500 | blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req, |
8093f7ca | 501 | struct nvme_command *cmd); |
f11bb3e2 CH |
502 | int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
503 | void *buf, unsigned bufflen); | |
504 | int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, | |
d49187e9 | 505 | union nvme_result *result, void *buffer, unsigned bufflen, |
9a95e4ef | 506 | unsigned timeout, int qid, int at_head, |
6287b51c | 507 | blk_mq_req_flags_t flags, bool poll); |
1a87ee65 KB |
508 | int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid, |
509 | unsigned int dword11, void *buffer, size_t buflen, | |
510 | u32 *result); | |
511 | int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid, | |
512 | unsigned int dword11, void *buffer, size_t buflen, | |
513 | u32 *result); | |
9a0be7ab | 514 | int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); |
038bd4cb | 515 | void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); |
d86c4d8e | 516 | int nvme_reset_ctrl(struct nvme_ctrl *ctrl); |
79c48ccf | 517 | int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl); |
c5017e85 | 518 | int nvme_delete_ctrl(struct nvme_ctrl *ctrl); |
f11bb3e2 | 519 | |
0e98719b CH |
520 | int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, |
521 | void *log, size_t size, u64 offset); | |
d558fb51 | 522 | |
33b14f67 | 523 | extern const struct attribute_group *nvme_ns_id_attr_groups[]; |
32acab31 CH |
524 | extern const struct block_device_operations nvme_ns_head_ops; |
525 | ||
526 | #ifdef CONFIG_NVME_MULTIPATH | |
66b20ac0 MR |
527 | static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) |
528 | { | |
529 | return ctrl->ana_log_buf != NULL; | |
530 | } | |
531 | ||
b9156dae SG |
532 | void nvme_mpath_unfreeze(struct nvme_subsystem *subsys); |
533 | void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys); | |
534 | void nvme_mpath_start_freeze(struct nvme_subsystem *subsys); | |
a785dbcc KB |
535 | void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns, |
536 | struct nvme_ctrl *ctrl, int *flags); | |
32acab31 | 537 | void nvme_failover_req(struct request *req); |
32acab31 CH |
538 | void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl); |
539 | int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,struct nvme_ns_head *head); | |
0d0b660f | 540 | void nvme_mpath_add_disk(struct nvme_ns *ns, struct nvme_id_ns *id); |
32acab31 | 541 | void nvme_mpath_remove_disk(struct nvme_ns_head *head); |
0d0b660f CH |
542 | int nvme_mpath_init(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id); |
543 | void nvme_mpath_uninit(struct nvme_ctrl *ctrl); | |
544 | void nvme_mpath_stop(struct nvme_ctrl *ctrl); | |
0157ec8d SG |
545 | bool nvme_mpath_clear_current_path(struct nvme_ns *ns); |
546 | void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl); | |
32acab31 | 547 | struct nvme_ns *nvme_find_path(struct nvme_ns_head *head); |
479a322f SG |
548 | |
549 | static inline void nvme_mpath_check_last_path(struct nvme_ns *ns) | |
550 | { | |
551 | struct nvme_ns_head *head = ns->head; | |
552 | ||
553 | if (head->disk && list_empty(&head->list)) | |
554 | kblockd_schedule_work(&head->requeue_work); | |
555 | } | |
556 | ||
35fe0d12 HR |
557 | static inline void nvme_trace_bio_complete(struct request *req, |
558 | blk_status_t status) | |
559 | { | |
560 | struct nvme_ns *ns = req->q->queuedata; | |
561 | ||
562 | if (req->cmd_flags & REQ_NVME_MPATH) | |
563 | trace_block_bio_complete(ns->head->disk->queue, | |
564 | req->bio, status); | |
565 | } | |
566 | ||
0d0b660f CH |
567 | extern struct device_attribute dev_attr_ana_grpid; |
568 | extern struct device_attribute dev_attr_ana_state; | |
75c10e73 | 569 | extern struct device_attribute subsys_attr_iopolicy; |
0d0b660f | 570 | |
32acab31 | 571 | #else |
0d0b660f CH |
572 | static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) |
573 | { | |
574 | return false; | |
575 | } | |
a785dbcc KB |
576 | /* |
577 | * Without the multipath code enabled, multiple controller per subsystems are | |
578 | * visible as devices and thus we cannot use the subsystem instance. | |
579 | */ | |
580 | static inline void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns, | |
581 | struct nvme_ctrl *ctrl, int *flags) | |
582 | { | |
583 | sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->head->instance); | |
584 | } | |
585 | ||
32acab31 CH |
586 | static inline void nvme_failover_req(struct request *req) |
587 | { | |
588 | } | |
32acab31 CH |
589 | static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl) |
590 | { | |
591 | } | |
592 | static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl, | |
593 | struct nvme_ns_head *head) | |
594 | { | |
595 | return 0; | |
596 | } | |
0d0b660f CH |
597 | static inline void nvme_mpath_add_disk(struct nvme_ns *ns, |
598 | struct nvme_id_ns *id) | |
32acab31 CH |
599 | { |
600 | } | |
601 | static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head) | |
602 | { | |
603 | } | |
0157ec8d SG |
604 | static inline bool nvme_mpath_clear_current_path(struct nvme_ns *ns) |
605 | { | |
606 | return false; | |
607 | } | |
608 | static inline void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl) | |
479a322f SG |
609 | { |
610 | } | |
611 | static inline void nvme_mpath_check_last_path(struct nvme_ns *ns) | |
32acab31 CH |
612 | { |
613 | } | |
35fe0d12 HR |
614 | static inline void nvme_trace_bio_complete(struct request *req, |
615 | blk_status_t status) | |
616 | { | |
617 | } | |
0d0b660f CH |
618 | static inline int nvme_mpath_init(struct nvme_ctrl *ctrl, |
619 | struct nvme_id_ctrl *id) | |
620 | { | |
14a1336e CH |
621 | if (ctrl->subsys->cmic & (1 << 3)) |
622 | dev_warn(ctrl->device, | |
623 | "Please enable CONFIG_NVME_MULTIPATH for full support of multi-port devices.\n"); | |
0d0b660f CH |
624 | return 0; |
625 | } | |
626 | static inline void nvme_mpath_uninit(struct nvme_ctrl *ctrl) | |
627 | { | |
628 | } | |
629 | static inline void nvme_mpath_stop(struct nvme_ctrl *ctrl) | |
630 | { | |
631 | } | |
b9156dae SG |
632 | static inline void nvme_mpath_unfreeze(struct nvme_subsystem *subsys) |
633 | { | |
634 | } | |
635 | static inline void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys) | |
636 | { | |
637 | } | |
638 | static inline void nvme_mpath_start_freeze(struct nvme_subsystem *subsys) | |
639 | { | |
640 | } | |
32acab31 CH |
641 | #endif /* CONFIG_NVME_MULTIPATH */ |
642 | ||
c4699e70 | 643 | #ifdef CONFIG_NVM |
3dc87dd0 | 644 | int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node); |
b0b4e09c | 645 | void nvme_nvm_unregister(struct nvme_ns *ns); |
33b14f67 | 646 | extern const struct attribute_group nvme_nvm_attr_group; |
84d4add7 | 647 | int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg); |
c4699e70 | 648 | #else |
b0b4e09c | 649 | static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, |
3dc87dd0 | 650 | int node) |
c4699e70 KB |
651 | { |
652 | return 0; | |
653 | } | |
654 | ||
b0b4e09c | 655 | static inline void nvme_nvm_unregister(struct nvme_ns *ns) {}; |
84d4add7 MB |
656 | static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, |
657 | unsigned long arg) | |
658 | { | |
659 | return -ENOTTY; | |
660 | } | |
3dc87dd0 MB |
661 | #endif /* CONFIG_NVM */ |
662 | ||
40267efd SL |
663 | static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev) |
664 | { | |
665 | return dev_to_disk(dev)->private_data; | |
666 | } | |
ca064085 | 667 | |
f11bb3e2 | 668 | #endif /* _NVME_H */ |