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loop: Fix wrong masking of status flags
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CommitLineData
bc50ad75 1/* SPDX-License-Identifier: GPL-2.0 */
f11bb3e2
CH
2/*
3 * Copyright (c) 2011-2014, Intel Corporation.
f11bb3e2
CH
4 */
5
6#ifndef _NVME_H
7#define _NVME_H
8
9#include <linux/nvme.h>
a6a5149b 10#include <linux/cdev.h>
f11bb3e2
CH
11#include <linux/pci.h>
12#include <linux/kref.h>
13#include <linux/blk-mq.h>
b0b4e09c 14#include <linux/lightnvm.h>
a98e58e5 15#include <linux/sed-opal.h>
b9e03857 16#include <linux/fault-inject.h>
978628ec 17#include <linux/rcupdate.h>
c1ac9a4b 18#include <linux/wait.h>
4d2ce688 19#include <linux/t10-pi.h>
f11bb3e2 20
35fe0d12
HR
21#include <trace/events/block.h>
22
8ae4e447 23extern unsigned int nvme_io_timeout;
f11bb3e2
CH
24#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
25
8ae4e447 26extern unsigned int admin_timeout;
21d34711
CH
27#define ADMIN_TIMEOUT (admin_timeout * HZ)
28
038bd4cb
SG
29#define NVME_DEFAULT_KATO 5
30#define NVME_KATO_GRACE 10
31
38e18002
IR
32#ifdef CONFIG_ARCH_NO_SG_CHAIN
33#define NVME_INLINE_SG_CNT 0
ba7ca2ae 34#define NVME_INLINE_METADATA_SG_CNT 0
38e18002
IR
35#else
36#define NVME_INLINE_SG_CNT 2
ba7ca2ae 37#define NVME_INLINE_METADATA_SG_CNT 1
38e18002
IR
38#endif
39
9a6327d2 40extern struct workqueue_struct *nvme_wq;
b227c59b
RS
41extern struct workqueue_struct *nvme_reset_wq;
42extern struct workqueue_struct *nvme_delete_wq;
9a6327d2 43
ca064085
MB
44enum {
45 NVME_NS_LBA = 0,
46 NVME_NS_LIGHTNVM = 1,
47};
48
f11bb3e2 49/*
106198ed
CH
50 * List of workarounds for devices that required behavior not specified in
51 * the standard.
f11bb3e2 52 */
106198ed
CH
53enum nvme_quirks {
54 /*
55 * Prefers I/O aligned to a stripe size specified in a vendor
56 * specific Identify field.
57 */
58 NVME_QUIRK_STRIPE_SIZE = (1 << 0),
540c801c
KB
59
60 /*
61 * The controller doesn't handle Identify value others than 0 or 1
62 * correctly.
63 */
64 NVME_QUIRK_IDENTIFY_CNS = (1 << 1),
08095e70
KB
65
66 /*
e850fd16
CH
67 * The controller deterministically returns O's on reads to
68 * logical blocks that deallocate was called on.
08095e70 69 */
e850fd16 70 NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2),
54adc010
GP
71
72 /*
73 * The controller needs a delay before starts checking the device
74 * readiness, which is done by reading the NVME_CSTS_RDY bit.
75 */
76 NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3),
c5552fde
AL
77
78 /*
79 * APST should not be used.
80 */
81 NVME_QUIRK_NO_APST = (1 << 4),
ff5350a8
AL
82
83 /*
84 * The deepest sleep state should not be used.
85 */
86 NVME_QUIRK_NO_DEEPEST_PS = (1 << 5),
608cc4b1
CH
87
88 /*
89 * Supports the LighNVM command set if indicated in vs[1].
90 */
91 NVME_QUIRK_LIGHTNVM = (1 << 6),
9abd68ef
JA
92
93 /*
94 * Set MEDIUM priority on SQ creation
95 */
96 NVME_QUIRK_MEDIUM_PRIO_SQ = (1 << 7),
6299358d
JD
97
98 /*
99 * Ignore device provided subnqn.
100 */
101 NVME_QUIRK_IGNORE_DEV_SUBNQN = (1 << 8),
7b210e4e
CH
102
103 /*
104 * Broken Write Zeroes.
105 */
106 NVME_QUIRK_DISABLE_WRITE_ZEROES = (1 << 9),
cb32de1b
ML
107
108 /*
109 * Force simple suspend/resume path.
110 */
111 NVME_QUIRK_SIMPLE_SUSPEND = (1 << 10),
7ad67ca5 112
66341331
BH
113 /*
114 * Use only one interrupt vector for all queues
115 */
7ad67ca5 116 NVME_QUIRK_SINGLE_VECTOR = (1 << 11),
66341331
BH
117
118 /*
119 * Use non-standard 128 bytes SQEs.
120 */
7ad67ca5 121 NVME_QUIRK_128_BYTES_SQES = (1 << 12),
d38e9f04
BH
122
123 /*
124 * Prevent tag overlap between queues
125 */
7ad67ca5 126 NVME_QUIRK_SHARED_TAGS = (1 << 13),
6c6aa2f2
AM
127
128 /*
129 * Don't change the value of the temperature threshold feature
130 */
131 NVME_QUIRK_NO_TEMP_THRESH_CHANGE = (1 << 14),
106198ed
CH
132};
133
d49187e9
CH
134/*
135 * Common request structure for NVMe passthrough. All drivers must have
136 * this structure as the first member of their request-private data.
137 */
138struct nvme_request {
139 struct nvme_command *cmd;
140 union nvme_result result;
44e44b29 141 u8 retries;
27fa9bc5
CH
142 u8 flags;
143 u16 status;
59e29ce6 144 struct nvme_ctrl *ctrl;
27fa9bc5
CH
145};
146
32acab31
CH
147/*
148 * Mark a bio as coming in through the mpath node.
149 */
150#define REQ_NVME_MPATH REQ_DRV
151
27fa9bc5
CH
152enum {
153 NVME_REQ_CANCELLED = (1 << 0),
bb06ec31 154 NVME_REQ_USERCMD = (1 << 1),
d49187e9
CH
155};
156
157static inline struct nvme_request *nvme_req(struct request *req)
158{
159 return blk_mq_rq_to_pdu(req);
160}
161
5d87eb94
KB
162static inline u16 nvme_req_qid(struct request *req)
163{
164 if (!req->rq_disk)
165 return 0;
166 return blk_mq_unique_tag_to_hwq(blk_mq_unique_tag(req)) + 1;
167}
168
54adc010
GP
169/* The below value is the specific amount of delay needed before checking
170 * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
171 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
172 * found empirically.
173 */
8c97eecc 174#define NVME_QUIRK_DELAY_AMOUNT 2300
54adc010 175
bb8d261e
CH
176enum nvme_ctrl_state {
177 NVME_CTRL_NEW,
178 NVME_CTRL_LIVE,
179 NVME_CTRL_RESETTING,
ad6a0a52 180 NVME_CTRL_CONNECTING,
bb8d261e 181 NVME_CTRL_DELETING,
0ff9d4e1 182 NVME_CTRL_DEAD,
bb8d261e
CH
183};
184
a3646451
AM
185struct nvme_fault_inject {
186#ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
187 struct fault_attr attr;
188 struct dentry *parent;
189 bool dont_retry; /* DNR, do not retry */
190 u16 status; /* status code */
191#endif
192};
193
1c63dc66 194struct nvme_ctrl {
6e3ca03e 195 bool comp_seen;
bb8d261e 196 enum nvme_ctrl_state state;
bd4da3ab 197 bool identified;
bb8d261e 198 spinlock_t lock;
e7ad43c3 199 struct mutex scan_lock;
1c63dc66 200 const struct nvme_ctrl_ops *ops;
f11bb3e2 201 struct request_queue *admin_q;
07bfcd09 202 struct request_queue *connect_q;
e7832cb4 203 struct request_queue *fabrics_q;
f11bb3e2 204 struct device *dev;
f11bb3e2 205 int instance;
103e515e 206 int numa_node;
5bae7f73 207 struct blk_mq_tag_set *tagset;
34b6c231 208 struct blk_mq_tag_set *admin_tagset;
f11bb3e2 209 struct list_head namespaces;
765cc031 210 struct rw_semaphore namespaces_rwsem;
d22524a4 211 struct device ctrl_device;
5bae7f73 212 struct device *device; /* char device */
a6a5149b 213 struct cdev cdev;
d86c4d8e 214 struct work_struct reset_work;
c5017e85 215 struct work_struct delete_work;
c1ac9a4b 216 wait_queue_head_t state_wq;
1c63dc66 217
ab9e00cc
CH
218 struct nvme_subsystem *subsys;
219 struct list_head subsys_entry;
220
4f1244c8 221 struct opal_dev *opal_dev;
a98e58e5 222
f11bb3e2 223 char name[12];
76e3914a 224 u16 cntlid;
5fd4ce1b
CH
225
226 u32 ctrl_config;
b6dccf7f 227 u16 mtfa;
d858e5f0 228 u32 queue_count;
5fd4ce1b 229
20d0dfe6 230 u64 cap;
5fd4ce1b 231 u32 page_size;
f11bb3e2 232 u32 max_hw_sectors;
943e942e 233 u32 max_segments;
95093350 234 u32 max_integrity_segments;
49cd84b6 235 u16 crdt[3];
f11bb3e2 236 u16 oncs;
8a9ae523 237 u16 oacs;
f5d11840
JA
238 u16 nssa;
239 u16 nr_streams;
f968688f 240 u16 sqsize;
0d0b660f 241 u32 max_namespaces;
6bf25d16 242 atomic_t abort_limit;
f11bb3e2 243 u8 vwc;
f3ca80fc 244 u32 vs;
07bfcd09 245 u32 sgls;
038bd4cb 246 u16 kas;
c5552fde
AL
247 u8 npss;
248 u8 apsta;
400b6a7b
GR
249 u16 wctemp;
250 u16 cctemp;
c0561f82 251 u32 oaes;
e3d7874d 252 u32 aen_result;
3e53ba38 253 u32 ctratt;
07fbd32a 254 unsigned int shutdown_timeout;
038bd4cb 255 unsigned int kato;
f3ca80fc 256 bool subsystem;
106198ed 257 unsigned long quirks;
c5552fde 258 struct nvme_id_power_state psd[32];
84fef62d 259 struct nvme_effects_log *effects;
5955be21 260 struct work_struct scan_work;
f866fc42 261 struct work_struct async_event_work;
038bd4cb 262 struct delayed_work ka_work;
0a34e466 263 struct nvme_command ka_cmd;
b6dccf7f 264 struct work_struct fw_act_work;
30d90964 265 unsigned long events;
ce151813 266 bool created;
07bfcd09 267
0d0b660f
CH
268#ifdef CONFIG_NVME_MULTIPATH
269 /* asymmetric namespace access: */
270 u8 anacap;
271 u8 anatt;
272 u32 anagrpmax;
273 u32 nanagrpid;
274 struct mutex ana_lock;
275 struct nvme_ana_rsp_hdr *ana_log_buf;
276 size_t ana_log_size;
277 struct timer_list anatt_timer;
278 struct work_struct ana_work;
279#endif
280
c5552fde
AL
281 /* Power saving configuration */
282 u64 ps_max_latency_us;
76a5af84 283 bool apst_enabled;
c5552fde 284
044a9df1 285 /* PCIe only: */
fe6d53c9
CH
286 u32 hmpre;
287 u32 hmmin;
044a9df1
CH
288 u32 hmminds;
289 u16 hmmaxd;
fe6d53c9 290
07bfcd09 291 /* Fabrics only */
07bfcd09
CH
292 u32 ioccsz;
293 u32 iorcsz;
294 u16 icdoff;
295 u16 maxcmd;
fdf9dfa8 296 int nr_reconnects;
07bfcd09 297 struct nvmf_ctrl_options *opts;
cb5b7262
JA
298
299 struct page *discard_page;
300 unsigned long discard_page_busy;
f79d5fda
AM
301
302 struct nvme_fault_inject fault_inject;
f11bb3e2
CH
303};
304
75c10e73
HR
305enum nvme_iopolicy {
306 NVME_IOPOLICY_NUMA,
307 NVME_IOPOLICY_RR,
308};
309
ab9e00cc
CH
310struct nvme_subsystem {
311 int instance;
312 struct device dev;
313 /*
314 * Because we unregister the device on the last put we need
315 * a separate refcount.
316 */
317 struct kref ref;
318 struct list_head entry;
319 struct mutex lock;
320 struct list_head ctrls;
ed754e5d 321 struct list_head nsheads;
ab9e00cc
CH
322 char subnqn[NVMF_NQN_SIZE];
323 char serial[20];
324 char model[40];
325 char firmware_rev[8];
326 u8 cmic;
327 u16 vendor_id;
81adb863 328 u16 awupf; /* 0's based awupf value. */
ed754e5d 329 struct ida ns_ida;
75c10e73
HR
330#ifdef CONFIG_NVME_MULTIPATH
331 enum nvme_iopolicy iopolicy;
332#endif
ab9e00cc
CH
333};
334
002fab04
CH
335/*
336 * Container structure for uniqueue namespace identifiers.
337 */
338struct nvme_ns_ids {
339 u8 eui64[8];
340 u8 nguid[16];
341 uuid_t uuid;
342};
343
ed754e5d
CH
344/*
345 * Anchor structure for namespaces. There is one for each namespace in a
346 * NVMe subsystem that any of our controllers can see, and the namespace
347 * structure for each controller is chained of it. For private namespaces
348 * there is a 1:1 relation to our namespace structures, that is ->list
349 * only ever has a single entry for private namespaces.
350 */
351struct nvme_ns_head {
352 struct list_head list;
353 struct srcu_struct srcu;
354 struct nvme_subsystem *subsys;
355 unsigned ns_id;
356 struct nvme_ns_ids ids;
357 struct list_head entry;
358 struct kref ref;
0c284db7 359 bool shared;
ed754e5d 360 int instance;
f3334447
CH
361#ifdef CONFIG_NVME_MULTIPATH
362 struct gendisk *disk;
363 struct bio_list requeue_list;
364 spinlock_t requeue_lock;
365 struct work_struct requeue_work;
366 struct mutex lock;
367 struct nvme_ns __rcu *current_path[];
368#endif
ed754e5d
CH
369};
370
ffc89b1d
MG
371enum nvme_ns_features {
372 NVME_NS_EXT_LBAS = 1 << 0, /* support extended LBA format */
b29f8485 373 NVME_NS_METADATA_SUPPORTED = 1 << 1, /* support getting generated md */
ffc89b1d
MG
374};
375
f11bb3e2
CH
376struct nvme_ns {
377 struct list_head list;
378
1c63dc66 379 struct nvme_ctrl *ctrl;
f11bb3e2
CH
380 struct request_queue *queue;
381 struct gendisk *disk;
0d0b660f
CH
382#ifdef CONFIG_NVME_MULTIPATH
383 enum nvme_ana_state ana_state;
384 u32 ana_grpid;
385#endif
ed754e5d 386 struct list_head siblings;
b0b4e09c 387 struct nvm_dev *ndev;
f11bb3e2 388 struct kref kref;
ed754e5d 389 struct nvme_ns_head *head;
f11bb3e2 390
f11bb3e2
CH
391 int lba_shift;
392 u16 ms;
f5d11840
JA
393 u16 sgs;
394 u32 sws;
f11bb3e2 395 u8 pi_type;
ffc89b1d 396 unsigned long features;
646017a6 397 unsigned long flags;
0d0b660f
CH
398#define NVME_NS_REMOVING 0
399#define NVME_NS_DEAD 1
400#define NVME_NS_ANA_PENDING 2
b9e03857 401
b9e03857 402 struct nvme_fault_inject fault_inject;
b9e03857 403
f11bb3e2
CH
404};
405
4d2ce688
JS
406/* NVMe ns supports metadata actions by the controller (generate/strip) */
407static inline bool nvme_ns_has_pi(struct nvme_ns *ns)
408{
409 return ns->pi_type && ns->ms == sizeof(struct t10_pi_tuple);
410}
411
1c63dc66 412struct nvme_ctrl_ops {
1a353d85 413 const char *name;
e439bb12 414 struct module *module;
d3d5b87d
CH
415 unsigned int flags;
416#define NVME_F_FABRICS (1 << 0)
c81bfba9 417#define NVME_F_METADATA_SUPPORTED (1 << 1)
e0596ab2 418#define NVME_F_PCI_P2PDMA (1 << 2)
1c63dc66 419 int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val);
5fd4ce1b 420 int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val);
7fd8930f 421 int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val);
1673f1f0 422 void (*free_ctrl)(struct nvme_ctrl *ctrl);
ad22c355 423 void (*submit_async_event)(struct nvme_ctrl *ctrl);
c5017e85 424 void (*delete_ctrl)(struct nvme_ctrl *ctrl);
1a353d85 425 int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size);
f11bb3e2
CH
426};
427
b9e03857 428#ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
a3646451
AM
429void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj,
430 const char *dev_name);
431void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inject);
b9e03857
TT
432void nvme_should_fail(struct request *req);
433#else
a3646451
AM
434static inline void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj,
435 const char *dev_name)
436{
437}
438static inline void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inj)
439{
440}
b9e03857
TT
441static inline void nvme_should_fail(struct request *req) {}
442#endif
443
f3ca80fc
CH
444static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
445{
446 if (!ctrl->subsystem)
447 return -ENOTTY;
448 return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
449}
450
314d48dd
DLM
451/*
452 * Convert a 512B sector number to a device logical block number.
453 */
454static inline u64 nvme_sect_to_lba(struct nvme_ns *ns, sector_t sector)
f11bb3e2 455{
314d48dd 456 return sector >> (ns->lba_shift - SECTOR_SHIFT);
f11bb3e2
CH
457}
458
e08f2ae8
DLM
459/*
460 * Convert a device logical block number to a 512B sector number.
461 */
462static inline sector_t nvme_lba_to_sect(struct nvme_ns *ns, u64 lba)
f11bb3e2 463{
e08f2ae8 464 return lba << (ns->lba_shift - SECTOR_SHIFT);
f11bb3e2
CH
465}
466
71fb90eb
KB
467/*
468 * Convert byte length to nvme's 0-based num dwords
469 */
470static inline u32 nvme_bytes_to_numd(size_t len)
471{
472 return (len >> 2) - 1;
473}
474
27fa9bc5
CH
475static inline void nvme_end_request(struct request *req, __le16 status,
476 union nvme_result result)
15a190f7 477{
27fa9bc5 478 struct nvme_request *rq = nvme_req(req);
15a190f7 479
27fa9bc5
CH
480 rq->status = le16_to_cpu(status) >> 1;
481 rq->result = result;
b9e03857
TT
482 /* inject error when permitted by fault injection framework */
483 nvme_should_fail(req);
08e0029a 484 blk_mq_complete_request(req);
7688faa6
CH
485}
486
d22524a4
CH
487static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl)
488{
489 get_device(ctrl->device);
490}
491
492static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl)
493{
494 put_device(ctrl->device);
495}
496
58a8df67
IR
497static inline bool nvme_is_aen_req(u16 qid, __u16 command_id)
498{
499 return !qid && command_id >= NVME_AQ_BLK_MQ_DEPTH;
500}
501
77f02a7a 502void nvme_complete_rq(struct request *req);
7baa8572 503bool nvme_cancel_request(struct request *req, void *data, bool reserved);
bb8d261e
CH
504bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
505 enum nvme_ctrl_state new_state);
c1ac9a4b 506bool nvme_wait_reset(struct nvme_ctrl *ctrl);
b5b05048 507int nvme_disable_ctrl(struct nvme_ctrl *ctrl);
c0f2f45b 508int nvme_enable_ctrl(struct nvme_ctrl *ctrl);
5fd4ce1b 509int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
f3ca80fc
CH
510int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
511 const struct nvme_ctrl_ops *ops, unsigned long quirks);
53029b04 512void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
d09f2b45
SG
513void nvme_start_ctrl(struct nvme_ctrl *ctrl);
514void nvme_stop_ctrl(struct nvme_ctrl *ctrl);
7fd8930f 515int nvme_init_identify(struct nvme_ctrl *ctrl);
5bae7f73 516
5bae7f73 517void nvme_remove_namespaces(struct nvme_ctrl *ctrl);
1673f1f0 518
4f1244c8
CH
519int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
520 bool send);
a98e58e5 521
7bf58533 522void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
287a63eb 523 volatile union nvme_result *res);
f866fc42 524
25646264
KB
525void nvme_stop_queues(struct nvme_ctrl *ctrl);
526void nvme_start_queues(struct nvme_ctrl *ctrl);
69d9a99c 527void nvme_kill_queues(struct nvme_ctrl *ctrl);
d6135c3a 528void nvme_sync_queues(struct nvme_ctrl *ctrl);
302ad8cc
KB
529void nvme_unfreeze(struct nvme_ctrl *ctrl);
530void nvme_wait_freeze(struct nvme_ctrl *ctrl);
531void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
532void nvme_start_freeze(struct nvme_ctrl *ctrl);
363c9aac 533
eb71f435 534#define NVME_QID_ANY -1
4160982e 535struct request *nvme_alloc_request(struct request_queue *q,
9a95e4ef 536 struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid);
f7f1fc36 537void nvme_cleanup_cmd(struct request *req);
fc17b653 538blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
8093f7ca 539 struct nvme_command *cmd);
f11bb3e2
CH
540int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
541 void *buf, unsigned bufflen);
542int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 543 union nvme_result *result, void *buffer, unsigned bufflen,
9a95e4ef 544 unsigned timeout, int qid, int at_head,
6287b51c 545 blk_mq_req_flags_t flags, bool poll);
1a87ee65
KB
546int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid,
547 unsigned int dword11, void *buffer, size_t buflen,
548 u32 *result);
549int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid,
550 unsigned int dword11, void *buffer, size_t buflen,
551 u32 *result);
9a0be7ab 552int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);
038bd4cb 553void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
d86c4d8e 554int nvme_reset_ctrl(struct nvme_ctrl *ctrl);
79c48ccf 555int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl);
c1ac9a4b 556int nvme_try_sched_reset(struct nvme_ctrl *ctrl);
c5017e85 557int nvme_delete_ctrl(struct nvme_ctrl *ctrl);
f11bb3e2 558
0e98719b
CH
559int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp,
560 void *log, size_t size, u64 offset);
d558fb51 561
33b14f67 562extern const struct attribute_group *nvme_ns_id_attr_groups[];
32acab31
CH
563extern const struct block_device_operations nvme_ns_head_ops;
564
565#ifdef CONFIG_NVME_MULTIPATH
66b20ac0
MR
566static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl)
567{
568 return ctrl->ana_log_buf != NULL;
569}
570
b9156dae
SG
571void nvme_mpath_unfreeze(struct nvme_subsystem *subsys);
572void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys);
573void nvme_mpath_start_freeze(struct nvme_subsystem *subsys);
a785dbcc
KB
574void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns,
575 struct nvme_ctrl *ctrl, int *flags);
764e9332 576bool nvme_failover_req(struct request *req);
32acab31
CH
577void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl);
578int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,struct nvme_ns_head *head);
0d0b660f 579void nvme_mpath_add_disk(struct nvme_ns *ns, struct nvme_id_ns *id);
32acab31 580void nvme_mpath_remove_disk(struct nvme_ns_head *head);
0d0b660f
CH
581int nvme_mpath_init(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id);
582void nvme_mpath_uninit(struct nvme_ctrl *ctrl);
583void nvme_mpath_stop(struct nvme_ctrl *ctrl);
0157ec8d
SG
584bool nvme_mpath_clear_current_path(struct nvme_ns *ns);
585void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl);
32acab31 586struct nvme_ns *nvme_find_path(struct nvme_ns_head *head);
479a322f
SG
587
588static inline void nvme_mpath_check_last_path(struct nvme_ns *ns)
589{
590 struct nvme_ns_head *head = ns->head;
591
592 if (head->disk && list_empty(&head->list))
593 kblockd_schedule_work(&head->requeue_work);
594}
595
35fe0d12
HR
596static inline void nvme_trace_bio_complete(struct request *req,
597 blk_status_t status)
598{
599 struct nvme_ns *ns = req->q->queuedata;
600
601 if (req->cmd_flags & REQ_NVME_MPATH)
602 trace_block_bio_complete(ns->head->disk->queue,
603 req->bio, status);
604}
605
0d0b660f
CH
606extern struct device_attribute dev_attr_ana_grpid;
607extern struct device_attribute dev_attr_ana_state;
75c10e73 608extern struct device_attribute subsys_attr_iopolicy;
0d0b660f 609
32acab31 610#else
0d0b660f
CH
611static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl)
612{
613 return false;
614}
a785dbcc
KB
615/*
616 * Without the multipath code enabled, multiple controller per subsystems are
617 * visible as devices and thus we cannot use the subsystem instance.
618 */
619static inline void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns,
620 struct nvme_ctrl *ctrl, int *flags)
621{
622 sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->head->instance);
623}
624
764e9332 625static inline bool nvme_failover_req(struct request *req)
32acab31 626{
764e9332 627 return false;
32acab31 628}
32acab31
CH
629static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl)
630{
631}
632static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,
633 struct nvme_ns_head *head)
634{
635 return 0;
636}
0d0b660f
CH
637static inline void nvme_mpath_add_disk(struct nvme_ns *ns,
638 struct nvme_id_ns *id)
32acab31
CH
639{
640}
641static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head)
642{
643}
0157ec8d
SG
644static inline bool nvme_mpath_clear_current_path(struct nvme_ns *ns)
645{
646 return false;
647}
648static inline void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl)
479a322f
SG
649{
650}
651static inline void nvme_mpath_check_last_path(struct nvme_ns *ns)
32acab31
CH
652{
653}
35fe0d12
HR
654static inline void nvme_trace_bio_complete(struct request *req,
655 blk_status_t status)
656{
657}
0d0b660f
CH
658static inline int nvme_mpath_init(struct nvme_ctrl *ctrl,
659 struct nvme_id_ctrl *id)
660{
14a1336e
CH
661 if (ctrl->subsys->cmic & (1 << 3))
662 dev_warn(ctrl->device,
663"Please enable CONFIG_NVME_MULTIPATH for full support of multi-port devices.\n");
0d0b660f
CH
664 return 0;
665}
666static inline void nvme_mpath_uninit(struct nvme_ctrl *ctrl)
667{
668}
669static inline void nvme_mpath_stop(struct nvme_ctrl *ctrl)
670{
671}
b9156dae
SG
672static inline void nvme_mpath_unfreeze(struct nvme_subsystem *subsys)
673{
674}
675static inline void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys)
676{
677}
678static inline void nvme_mpath_start_freeze(struct nvme_subsystem *subsys)
679{
680}
32acab31
CH
681#endif /* CONFIG_NVME_MULTIPATH */
682
c4699e70 683#ifdef CONFIG_NVM
3dc87dd0 684int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node);
b0b4e09c 685void nvme_nvm_unregister(struct nvme_ns *ns);
33b14f67 686extern const struct attribute_group nvme_nvm_attr_group;
84d4add7 687int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg);
c4699e70 688#else
b0b4e09c 689static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name,
3dc87dd0 690 int node)
c4699e70
KB
691{
692 return 0;
693}
694
b0b4e09c 695static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
84d4add7
MB
696static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
697 unsigned long arg)
698{
699 return -ENOTTY;
700}
3dc87dd0
MB
701#endif /* CONFIG_NVM */
702
40267efd
SL
703static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev)
704{
705 return dev_to_disk(dev)->private_data;
706}
ca064085 707
400b6a7b
GR
708#ifdef CONFIG_NVME_HWMON
709void nvme_hwmon_init(struct nvme_ctrl *ctrl);
710#else
711static inline void nvme_hwmon_init(struct nvme_ctrl *ctrl) { }
712#endif
713
f11bb3e2 714#endif /* _NVME_H */