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f11bb3e2 CH |
1 | /* |
2 | * Copyright (c) 2011-2014, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | */ | |
13 | ||
14 | #ifndef _NVME_H | |
15 | #define _NVME_H | |
16 | ||
17 | #include <linux/nvme.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/kref.h> | |
20 | #include <linux/blk-mq.h> | |
21 | ||
297465c8 CH |
22 | enum { |
23 | /* | |
24 | * Driver internal status code for commands that were cancelled due | |
25 | * to timeouts or controller shutdown. The value is negative so | |
26 | * that it a) doesn't overlap with the unsigned hardware error codes, | |
27 | * and b) can easily be tested for. | |
28 | */ | |
29 | NVME_SC_CANCELLED = -EINTR, | |
30 | }; | |
31 | ||
f11bb3e2 CH |
32 | extern unsigned char nvme_io_timeout; |
33 | #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) | |
34 | ||
21d34711 CH |
35 | extern unsigned char admin_timeout; |
36 | #define ADMIN_TIMEOUT (admin_timeout * HZ) | |
37 | ||
5fd4ce1b CH |
38 | extern unsigned char shutdown_timeout; |
39 | #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ) | |
40 | ||
ca064085 MB |
41 | enum { |
42 | NVME_NS_LBA = 0, | |
43 | NVME_NS_LIGHTNVM = 1, | |
44 | }; | |
45 | ||
106198ed CH |
46 | /* |
47 | * List of workarounds for devices that required behavior not specified in | |
48 | * the standard. | |
49 | */ | |
50 | enum nvme_quirks { | |
51 | /* | |
52 | * Prefers I/O aligned to a stripe size specified in a vendor | |
53 | * specific Identify field. | |
54 | */ | |
55 | NVME_QUIRK_STRIPE_SIZE = (1 << 0), | |
56 | }; | |
57 | ||
1c63dc66 CH |
58 | struct nvme_ctrl { |
59 | const struct nvme_ctrl_ops *ops; | |
f11bb3e2 | 60 | struct request_queue *admin_q; |
f11bb3e2 | 61 | struct device *dev; |
1673f1f0 | 62 | struct kref kref; |
f11bb3e2 | 63 | int instance; |
5bae7f73 CH |
64 | struct blk_mq_tag_set *tagset; |
65 | struct list_head namespaces; | |
66 | struct device *device; /* char device */ | |
f3ca80fc | 67 | struct list_head node; |
1c63dc66 | 68 | |
f11bb3e2 CH |
69 | char name[12]; |
70 | char serial[20]; | |
71 | char model[40]; | |
72 | char firmware_rev[8]; | |
5fd4ce1b CH |
73 | |
74 | u32 ctrl_config; | |
75 | ||
76 | u32 page_size; | |
7fd8930f CH |
77 | u32 max_hw_sectors; |
78 | u32 stripe_size; | |
f11bb3e2 | 79 | u16 oncs; |
6bf25d16 | 80 | atomic_t abort_limit; |
f11bb3e2 CH |
81 | u8 event_limit; |
82 | u8 vwc; | |
f3ca80fc CH |
83 | u32 vs; |
84 | bool subsystem; | |
106198ed | 85 | unsigned long quirks; |
f11bb3e2 CH |
86 | }; |
87 | ||
88 | /* | |
89 | * An NVM Express namespace is equivalent to a SCSI LUN | |
90 | */ | |
91 | struct nvme_ns { | |
92 | struct list_head list; | |
93 | ||
1c63dc66 | 94 | struct nvme_ctrl *ctrl; |
f11bb3e2 CH |
95 | struct request_queue *queue; |
96 | struct gendisk *disk; | |
97 | struct kref kref; | |
98 | ||
99 | unsigned ns_id; | |
100 | int lba_shift; | |
101 | u16 ms; | |
102 | bool ext; | |
103 | u8 pi_type; | |
ca064085 | 104 | int type; |
f11bb3e2 CH |
105 | u64 mode_select_num_blocks; |
106 | u32 mode_select_block_len; | |
107 | }; | |
108 | ||
1c63dc66 CH |
109 | struct nvme_ctrl_ops { |
110 | int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); | |
5fd4ce1b | 111 | int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); |
7fd8930f | 112 | int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); |
5bae7f73 | 113 | bool (*io_incapable)(struct nvme_ctrl *ctrl); |
f3ca80fc | 114 | int (*reset_ctrl)(struct nvme_ctrl *ctrl); |
1673f1f0 | 115 | void (*free_ctrl)(struct nvme_ctrl *ctrl); |
1c63dc66 CH |
116 | }; |
117 | ||
118 | static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl) | |
119 | { | |
120 | u32 val = 0; | |
121 | ||
122 | if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val)) | |
123 | return false; | |
124 | return val & NVME_CSTS_RDY; | |
125 | } | |
126 | ||
5bae7f73 CH |
127 | static inline bool nvme_io_incapable(struct nvme_ctrl *ctrl) |
128 | { | |
129 | u32 val = 0; | |
130 | ||
131 | if (ctrl->ops->io_incapable(ctrl)) | |
132 | return false; | |
133 | if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val)) | |
134 | return false; | |
135 | return val & NVME_CSTS_CFS; | |
136 | } | |
137 | ||
f3ca80fc CH |
138 | static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) |
139 | { | |
140 | if (!ctrl->subsystem) | |
141 | return -ENOTTY; | |
142 | return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); | |
143 | } | |
144 | ||
f11bb3e2 CH |
145 | static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector) |
146 | { | |
147 | return (sector >> (ns->lba_shift - 9)); | |
148 | } | |
149 | ||
22944e99 CH |
150 | static inline void nvme_setup_flush(struct nvme_ns *ns, |
151 | struct nvme_command *cmnd) | |
152 | { | |
153 | memset(cmnd, 0, sizeof(*cmnd)); | |
154 | cmnd->common.opcode = nvme_cmd_flush; | |
155 | cmnd->common.nsid = cpu_to_le32(ns->ns_id); | |
156 | } | |
157 | ||
158 | static inline void nvme_setup_rw(struct nvme_ns *ns, struct request *req, | |
159 | struct nvme_command *cmnd) | |
160 | { | |
161 | u16 control = 0; | |
162 | u32 dsmgmt = 0; | |
163 | ||
164 | if (req->cmd_flags & REQ_FUA) | |
165 | control |= NVME_RW_FUA; | |
166 | if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD)) | |
167 | control |= NVME_RW_LR; | |
168 | ||
169 | if (req->cmd_flags & REQ_RAHEAD) | |
170 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; | |
171 | ||
172 | memset(cmnd, 0, sizeof(*cmnd)); | |
173 | cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read); | |
174 | cmnd->rw.command_id = req->tag; | |
175 | cmnd->rw.nsid = cpu_to_le32(ns->ns_id); | |
176 | cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
177 | cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1); | |
178 | ||
179 | if (ns->ms) { | |
180 | switch (ns->pi_type) { | |
181 | case NVME_NS_DPS_PI_TYPE3: | |
182 | control |= NVME_RW_PRINFO_PRCHK_GUARD; | |
183 | break; | |
184 | case NVME_NS_DPS_PI_TYPE1: | |
185 | case NVME_NS_DPS_PI_TYPE2: | |
186 | control |= NVME_RW_PRINFO_PRCHK_GUARD | | |
187 | NVME_RW_PRINFO_PRCHK_REF; | |
188 | cmnd->rw.reftag = cpu_to_le32( | |
189 | nvme_block_nr(ns, blk_rq_pos(req))); | |
190 | break; | |
191 | } | |
192 | if (!blk_integrity_rq(req)) | |
193 | control |= NVME_RW_PRINFO_PRACT; | |
194 | } | |
195 | ||
196 | cmnd->rw.control = cpu_to_le16(control); | |
197 | cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); | |
198 | } | |
199 | ||
200 | ||
15a190f7 CH |
201 | static inline int nvme_error_status(u16 status) |
202 | { | |
203 | switch (status & 0x7ff) { | |
204 | case NVME_SC_SUCCESS: | |
205 | return 0; | |
206 | case NVME_SC_CAP_EXCEEDED: | |
207 | return -ENOSPC; | |
208 | default: | |
209 | return -EIO; | |
210 | } | |
211 | } | |
212 | ||
5fd4ce1b CH |
213 | int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap); |
214 | int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap); | |
215 | int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl); | |
f3ca80fc CH |
216 | int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, |
217 | const struct nvme_ctrl_ops *ops, unsigned long quirks); | |
1673f1f0 | 218 | void nvme_put_ctrl(struct nvme_ctrl *ctrl); |
7fd8930f | 219 | int nvme_init_identify(struct nvme_ctrl *ctrl); |
5bae7f73 CH |
220 | |
221 | void nvme_scan_namespaces(struct nvme_ctrl *ctrl); | |
222 | void nvme_remove_namespaces(struct nvme_ctrl *ctrl); | |
1673f1f0 | 223 | |
4160982e CH |
224 | struct request *nvme_alloc_request(struct request_queue *q, |
225 | struct nvme_command *cmd, unsigned int flags); | |
f11bb3e2 CH |
226 | int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
227 | void *buf, unsigned bufflen); | |
228 | int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, | |
4160982e CH |
229 | void *buffer, unsigned bufflen, u32 *result, unsigned timeout); |
230 | int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd, | |
231 | void __user *ubuffer, unsigned bufflen, u32 *result, | |
232 | unsigned timeout); | |
0b7f1f26 KB |
233 | int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd, |
234 | void __user *ubuffer, unsigned bufflen, | |
235 | void __user *meta_buffer, unsigned meta_len, u32 meta_seed, | |
236 | u32 *result, unsigned timeout); | |
1c63dc66 CH |
237 | int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id); |
238 | int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid, | |
f11bb3e2 | 239 | struct nvme_id_ns **id); |
1c63dc66 CH |
240 | int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log); |
241 | int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid, | |
f11bb3e2 | 242 | dma_addr_t dma_addr, u32 *result); |
1c63dc66 | 243 | int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11, |
f11bb3e2 | 244 | dma_addr_t dma_addr, u32 *result); |
9a0be7ab | 245 | int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); |
f11bb3e2 | 246 | |
1673f1f0 CH |
247 | extern spinlock_t dev_list_lock; |
248 | ||
f11bb3e2 CH |
249 | struct sg_io_hdr; |
250 | ||
251 | int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr); | |
252 | int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg); | |
253 | int nvme_sg_get_version_num(int __user *ip); | |
254 | ||
ca064085 MB |
255 | int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id); |
256 | int nvme_nvm_register(struct request_queue *q, char *disk_name); | |
257 | void nvme_nvm_unregister(struct request_queue *q, char *disk_name); | |
258 | ||
5bae7f73 CH |
259 | int __init nvme_core_init(void); |
260 | void nvme_core_exit(void); | |
261 | ||
f11bb3e2 | 262 | #endif /* _NVME_H */ |