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f11bb3e2 CH |
1 | /* |
2 | * Copyright (c) 2011-2014, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | */ | |
13 | ||
14 | #ifndef _NVME_H | |
15 | #define _NVME_H | |
16 | ||
17 | #include <linux/nvme.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/kref.h> | |
20 | #include <linux/blk-mq.h> | |
b0b4e09c | 21 | #include <linux/lightnvm.h> |
a98e58e5 | 22 | #include <linux/sed-opal.h> |
f11bb3e2 CH |
23 | |
24 | extern unsigned char nvme_io_timeout; | |
25 | #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) | |
26 | ||
21d34711 CH |
27 | extern unsigned char admin_timeout; |
28 | #define ADMIN_TIMEOUT (admin_timeout * HZ) | |
29 | ||
038bd4cb SG |
30 | #define NVME_DEFAULT_KATO 5 |
31 | #define NVME_KATO_GRACE 10 | |
32 | ||
9a6327d2 SG |
33 | extern struct workqueue_struct *nvme_wq; |
34 | ||
ca064085 MB |
35 | enum { |
36 | NVME_NS_LBA = 0, | |
37 | NVME_NS_LIGHTNVM = 1, | |
38 | }; | |
39 | ||
f11bb3e2 | 40 | /* |
106198ed CH |
41 | * List of workarounds for devices that required behavior not specified in |
42 | * the standard. | |
f11bb3e2 | 43 | */ |
106198ed CH |
44 | enum nvme_quirks { |
45 | /* | |
46 | * Prefers I/O aligned to a stripe size specified in a vendor | |
47 | * specific Identify field. | |
48 | */ | |
49 | NVME_QUIRK_STRIPE_SIZE = (1 << 0), | |
540c801c KB |
50 | |
51 | /* | |
52 | * The controller doesn't handle Identify value others than 0 or 1 | |
53 | * correctly. | |
54 | */ | |
55 | NVME_QUIRK_IDENTIFY_CNS = (1 << 1), | |
08095e70 KB |
56 | |
57 | /* | |
e850fd16 CH |
58 | * The controller deterministically returns O's on reads to |
59 | * logical blocks that deallocate was called on. | |
08095e70 | 60 | */ |
e850fd16 | 61 | NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2), |
54adc010 GP |
62 | |
63 | /* | |
64 | * The controller needs a delay before starts checking the device | |
65 | * readiness, which is done by reading the NVME_CSTS_RDY bit. | |
66 | */ | |
67 | NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), | |
c5552fde AL |
68 | |
69 | /* | |
70 | * APST should not be used. | |
71 | */ | |
72 | NVME_QUIRK_NO_APST = (1 << 4), | |
ff5350a8 AL |
73 | |
74 | /* | |
75 | * The deepest sleep state should not be used. | |
76 | */ | |
77 | NVME_QUIRK_NO_DEEPEST_PS = (1 << 5), | |
106198ed CH |
78 | }; |
79 | ||
d49187e9 CH |
80 | /* |
81 | * Common request structure for NVMe passthrough. All drivers must have | |
82 | * this structure as the first member of their request-private data. | |
83 | */ | |
84 | struct nvme_request { | |
85 | struct nvme_command *cmd; | |
86 | union nvme_result result; | |
44e44b29 | 87 | u8 retries; |
27fa9bc5 CH |
88 | u8 flags; |
89 | u16 status; | |
90 | }; | |
91 | ||
92 | enum { | |
93 | NVME_REQ_CANCELLED = (1 << 0), | |
d49187e9 CH |
94 | }; |
95 | ||
96 | static inline struct nvme_request *nvme_req(struct request *req) | |
97 | { | |
98 | return blk_mq_rq_to_pdu(req); | |
99 | } | |
100 | ||
54adc010 GP |
101 | /* The below value is the specific amount of delay needed before checking |
102 | * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the | |
103 | * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was | |
104 | * found empirically. | |
105 | */ | |
106 | #define NVME_QUIRK_DELAY_AMOUNT 2000 | |
107 | ||
bb8d261e CH |
108 | enum nvme_ctrl_state { |
109 | NVME_CTRL_NEW, | |
110 | NVME_CTRL_LIVE, | |
111 | NVME_CTRL_RESETTING, | |
def61eca | 112 | NVME_CTRL_RECONNECTING, |
bb8d261e | 113 | NVME_CTRL_DELETING, |
0ff9d4e1 | 114 | NVME_CTRL_DEAD, |
bb8d261e CH |
115 | }; |
116 | ||
1c63dc66 | 117 | struct nvme_ctrl { |
bb8d261e | 118 | enum nvme_ctrl_state state; |
bd4da3ab | 119 | bool identified; |
bb8d261e | 120 | spinlock_t lock; |
1c63dc66 | 121 | const struct nvme_ctrl_ops *ops; |
f11bb3e2 | 122 | struct request_queue *admin_q; |
07bfcd09 | 123 | struct request_queue *connect_q; |
f11bb3e2 | 124 | struct device *dev; |
1673f1f0 | 125 | struct kref kref; |
f11bb3e2 | 126 | int instance; |
5bae7f73 | 127 | struct blk_mq_tag_set *tagset; |
f11bb3e2 | 128 | struct list_head namespaces; |
69d3b8ac | 129 | struct mutex namespaces_mutex; |
5bae7f73 | 130 | struct device *device; /* char device */ |
f3ca80fc | 131 | struct list_head node; |
075790eb | 132 | struct ida ns_ida; |
d86c4d8e | 133 | struct work_struct reset_work; |
1c63dc66 | 134 | |
4f1244c8 | 135 | struct opal_dev *opal_dev; |
a98e58e5 | 136 | |
f11bb3e2 CH |
137 | char name[12]; |
138 | char serial[20]; | |
139 | char model[40]; | |
140 | char firmware_rev[8]; | |
180de007 | 141 | char subnqn[NVMF_NQN_SIZE]; |
76e3914a | 142 | u16 cntlid; |
5fd4ce1b CH |
143 | |
144 | u32 ctrl_config; | |
d858e5f0 | 145 | u32 queue_count; |
5fd4ce1b | 146 | |
20d0dfe6 | 147 | u64 cap; |
5fd4ce1b | 148 | u32 page_size; |
f11bb3e2 | 149 | u32 max_hw_sectors; |
f11bb3e2 | 150 | u16 oncs; |
118472ab | 151 | u16 vid; |
8a9ae523 | 152 | u16 oacs; |
f5d11840 JA |
153 | u16 nssa; |
154 | u16 nr_streams; | |
6bf25d16 | 155 | atomic_t abort_limit; |
f11bb3e2 CH |
156 | u8 event_limit; |
157 | u8 vwc; | |
f3ca80fc | 158 | u32 vs; |
07bfcd09 | 159 | u32 sgls; |
038bd4cb | 160 | u16 kas; |
c5552fde AL |
161 | u8 npss; |
162 | u8 apsta; | |
038bd4cb | 163 | unsigned int kato; |
f3ca80fc | 164 | bool subsystem; |
106198ed | 165 | unsigned long quirks; |
c5552fde | 166 | struct nvme_id_power_state psd[32]; |
5955be21 | 167 | struct work_struct scan_work; |
f866fc42 | 168 | struct work_struct async_event_work; |
038bd4cb | 169 | struct delayed_work ka_work; |
07bfcd09 | 170 | |
c5552fde AL |
171 | /* Power saving configuration */ |
172 | u64 ps_max_latency_us; | |
76a5af84 | 173 | bool apst_enabled; |
c5552fde | 174 | |
fe6d53c9 CH |
175 | u32 hmpre; |
176 | u32 hmmin; | |
177 | ||
07bfcd09 CH |
178 | /* Fabrics only */ |
179 | u16 sqsize; | |
180 | u32 ioccsz; | |
181 | u32 iorcsz; | |
182 | u16 icdoff; | |
183 | u16 maxcmd; | |
fdf9dfa8 | 184 | int nr_reconnects; |
07bfcd09 | 185 | struct nvmf_ctrl_options *opts; |
f11bb3e2 CH |
186 | }; |
187 | ||
f11bb3e2 CH |
188 | struct nvme_ns { |
189 | struct list_head list; | |
190 | ||
1c63dc66 | 191 | struct nvme_ctrl *ctrl; |
f11bb3e2 CH |
192 | struct request_queue *queue; |
193 | struct gendisk *disk; | |
b0b4e09c | 194 | struct nvm_dev *ndev; |
f11bb3e2 | 195 | struct kref kref; |
075790eb | 196 | int instance; |
f11bb3e2 | 197 | |
2b9b6e86 | 198 | u8 eui[8]; |
90985b84 | 199 | u8 nguid[16]; |
3b22ba26 | 200 | uuid_t uuid; |
2b9b6e86 | 201 | |
f11bb3e2 CH |
202 | unsigned ns_id; |
203 | int lba_shift; | |
204 | u16 ms; | |
f5d11840 JA |
205 | u16 sgs; |
206 | u32 sws; | |
f11bb3e2 CH |
207 | bool ext; |
208 | u8 pi_type; | |
646017a6 | 209 | unsigned long flags; |
6b8190d6 | 210 | u16 noiob; |
646017a6 KB |
211 | |
212 | #define NVME_NS_REMOVING 0 | |
69d9a99c | 213 | #define NVME_NS_DEAD 1 |
646017a6 | 214 | |
f11bb3e2 CH |
215 | u64 mode_select_num_blocks; |
216 | u32 mode_select_block_len; | |
217 | }; | |
218 | ||
1c63dc66 | 219 | struct nvme_ctrl_ops { |
1a353d85 | 220 | const char *name; |
e439bb12 | 221 | struct module *module; |
d3d5b87d CH |
222 | unsigned int flags; |
223 | #define NVME_F_FABRICS (1 << 0) | |
c81bfba9 | 224 | #define NVME_F_METADATA_SUPPORTED (1 << 1) |
1c63dc66 | 225 | int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); |
5fd4ce1b | 226 | int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); |
7fd8930f | 227 | int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); |
1673f1f0 | 228 | void (*free_ctrl)(struct nvme_ctrl *ctrl); |
f866fc42 | 229 | void (*submit_async_event)(struct nvme_ctrl *ctrl, int aer_idx); |
1a353d85 | 230 | int (*delete_ctrl)(struct nvme_ctrl *ctrl); |
1a353d85 | 231 | int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); |
f11bb3e2 CH |
232 | }; |
233 | ||
1c63dc66 CH |
234 | static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl) |
235 | { | |
236 | u32 val = 0; | |
237 | ||
238 | if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val)) | |
239 | return false; | |
240 | return val & NVME_CSTS_RDY; | |
241 | } | |
242 | ||
f3ca80fc CH |
243 | static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) |
244 | { | |
245 | if (!ctrl->subsystem) | |
246 | return -ENOTTY; | |
247 | return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); | |
248 | } | |
249 | ||
f11bb3e2 CH |
250 | static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector) |
251 | { | |
252 | return (sector >> (ns->lba_shift - 9)); | |
253 | } | |
254 | ||
6904242d ML |
255 | static inline void nvme_cleanup_cmd(struct request *req) |
256 | { | |
f9d03f96 CH |
257 | if (req->rq_flags & RQF_SPECIAL_PAYLOAD) { |
258 | kfree(page_address(req->special_vec.bv_page) + | |
259 | req->special_vec.bv_offset); | |
260 | } | |
6904242d ML |
261 | } |
262 | ||
27fa9bc5 CH |
263 | static inline void nvme_end_request(struct request *req, __le16 status, |
264 | union nvme_result result) | |
15a190f7 | 265 | { |
27fa9bc5 | 266 | struct nvme_request *rq = nvme_req(req); |
15a190f7 | 267 | |
27fa9bc5 CH |
268 | rq->status = le16_to_cpu(status) >> 1; |
269 | rq->result = result; | |
08e0029a | 270 | blk_mq_complete_request(req); |
7688faa6 CH |
271 | } |
272 | ||
77f02a7a | 273 | void nvme_complete_rq(struct request *req); |
c55a2fd4 | 274 | void nvme_cancel_request(struct request *req, void *data, bool reserved); |
bb8d261e CH |
275 | bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, |
276 | enum nvme_ctrl_state new_state); | |
5fd4ce1b CH |
277 | int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap); |
278 | int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap); | |
279 | int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl); | |
f3ca80fc CH |
280 | int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, |
281 | const struct nvme_ctrl_ops *ops, unsigned long quirks); | |
53029b04 | 282 | void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); |
1673f1f0 | 283 | void nvme_put_ctrl(struct nvme_ctrl *ctrl); |
7fd8930f | 284 | int nvme_init_identify(struct nvme_ctrl *ctrl); |
5bae7f73 | 285 | |
5955be21 | 286 | void nvme_queue_scan(struct nvme_ctrl *ctrl); |
5bae7f73 | 287 | void nvme_remove_namespaces(struct nvme_ctrl *ctrl); |
1673f1f0 | 288 | |
4f1244c8 CH |
289 | int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len, |
290 | bool send); | |
a98e58e5 | 291 | |
f866fc42 | 292 | #define NVME_NR_AERS 1 |
7bf58533 CH |
293 | void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, |
294 | union nvme_result *res); | |
f866fc42 CH |
295 | void nvme_queue_async_events(struct nvme_ctrl *ctrl); |
296 | ||
25646264 KB |
297 | void nvme_stop_queues(struct nvme_ctrl *ctrl); |
298 | void nvme_start_queues(struct nvme_ctrl *ctrl); | |
69d9a99c | 299 | void nvme_kill_queues(struct nvme_ctrl *ctrl); |
302ad8cc KB |
300 | void nvme_unfreeze(struct nvme_ctrl *ctrl); |
301 | void nvme_wait_freeze(struct nvme_ctrl *ctrl); | |
302 | void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout); | |
303 | void nvme_start_freeze(struct nvme_ctrl *ctrl); | |
363c9aac | 304 | |
eb71f435 | 305 | #define NVME_QID_ANY -1 |
4160982e | 306 | struct request *nvme_alloc_request(struct request_queue *q, |
eb71f435 | 307 | struct nvme_command *cmd, unsigned int flags, int qid); |
fc17b653 | 308 | blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req, |
8093f7ca | 309 | struct nvme_command *cmd); |
f11bb3e2 CH |
310 | int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
311 | void *buf, unsigned bufflen); | |
312 | int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, | |
d49187e9 | 313 | union nvme_result *result, void *buffer, unsigned bufflen, |
eb71f435 | 314 | unsigned timeout, int qid, int at_head, int flags); |
4160982e CH |
315 | int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd, |
316 | void __user *ubuffer, unsigned bufflen, u32 *result, | |
317 | unsigned timeout); | |
0b7f1f26 KB |
318 | int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd, |
319 | void __user *ubuffer, unsigned bufflen, | |
320 | void __user *meta_buffer, unsigned meta_len, u32 meta_seed, | |
f11bb3e2 | 321 | u32 *result, unsigned timeout); |
9a0be7ab | 322 | int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); |
038bd4cb SG |
323 | void nvme_start_keep_alive(struct nvme_ctrl *ctrl); |
324 | void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); | |
d86c4d8e | 325 | int nvme_reset_ctrl(struct nvme_ctrl *ctrl); |
f11bb3e2 | 326 | |
c4699e70 | 327 | #ifdef CONFIG_NVM |
ca064085 | 328 | int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id); |
3dc87dd0 | 329 | int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node); |
b0b4e09c | 330 | void nvme_nvm_unregister(struct nvme_ns *ns); |
3dc87dd0 MB |
331 | int nvme_nvm_register_sysfs(struct nvme_ns *ns); |
332 | void nvme_nvm_unregister_sysfs(struct nvme_ns *ns); | |
84d4add7 | 333 | int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg); |
c4699e70 | 334 | #else |
b0b4e09c | 335 | static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, |
3dc87dd0 | 336 | int node) |
c4699e70 KB |
337 | { |
338 | return 0; | |
339 | } | |
340 | ||
b0b4e09c | 341 | static inline void nvme_nvm_unregister(struct nvme_ns *ns) {}; |
3dc87dd0 MB |
342 | static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns) |
343 | { | |
344 | return 0; | |
345 | } | |
346 | static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {}; | |
c4699e70 KB |
347 | static inline int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id) |
348 | { | |
349 | return 0; | |
350 | } | |
84d4add7 MB |
351 | static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, |
352 | unsigned long arg) | |
353 | { | |
354 | return -ENOTTY; | |
355 | } | |
3dc87dd0 MB |
356 | #endif /* CONFIG_NVM */ |
357 | ||
40267efd SL |
358 | static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev) |
359 | { | |
360 | return dev_to_disk(dev)->private_data; | |
361 | } | |
ca064085 | 362 | |
5bae7f73 CH |
363 | int __init nvme_core_init(void); |
364 | void nvme_core_exit(void); | |
365 | ||
f11bb3e2 | 366 | #endif /* _NVME_H */ |