[mirror_ubuntu-bionic-kernel.git] / drivers / nvme / host / nvme.h

/*
 * Copyright (c) 2011-2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef _NVME_H
#define _NVME_H

#include <linux/nvme.h>
#include <linux/pci.h>
#include <linux/kref.h>
#include <linux/blk-mq.h>
#include <linux/lightnvm.h>
#include <linux/sed-opal.h>

extern unsigned char nvme_io_timeout;
#define NVME_IO_TIMEOUT	(nvme_io_timeout * HZ)

extern unsigned char admin_timeout;
#define ADMIN_TIMEOUT	(admin_timeout * HZ)

#define NVME_DEFAULT_KATO	5
#define NVME_KATO_GRACE		10

extern struct workqueue_struct *nvme_wq;

enum {
	NVME_NS_LBA		= 0,
	NVME_NS_LIGHTNVM	= 1,
};

/*
 * List of workarounds for devices that required behavior not specified in
 * the standard.
 */
enum nvme_quirks {
	/*
	 * Prefers I/O aligned to a stripe size specified in a vendor
	 * specific Identify field.
	 */
	NVME_QUIRK_STRIPE_SIZE			= (1 << 0),

	/*
	 * The controller doesn't handle Identify value others than 0 or 1
	 * correctly.
	 */
	NVME_QUIRK_IDENTIFY_CNS			= (1 << 1),

	/*
	 * The controller deterministically returns O's on reads to
	 * logical blocks that deallocate was called on.
	 */
	NVME_QUIRK_DEALLOCATE_ZEROES		= (1 << 2),

	/*
	 * The controller needs a delay before starts checking the device
	 * readiness, which is done by reading the NVME_CSTS_RDY bit.
	 */
	NVME_QUIRK_DELAY_BEFORE_CHK_RDY		= (1 << 3),

	/*
	 * APST should not be used.
	 */
	NVME_QUIRK_NO_APST			= (1 << 4),

	/*
	 * The deepest sleep state should not be used.
	 */
	NVME_QUIRK_NO_DEEPEST_PS		= (1 << 5),

	/*
	 * Supports the LighNVM command set if indicated in vs[1].
	 */
	NVME_QUIRK_LIGHTNVM			= (1 << 6),
};

/*
 * Common request structure for NVMe passthrough.  All drivers must have
 * this structure as the first member of their request-private data.
 */
struct nvme_request {
	struct nvme_command	*cmd;
	union nvme_result	result;
	u8			retries;
	u8			flags;
	u16			status;
};

enum {
	NVME_REQ_CANCELLED		= (1 << 0),
};

static inline struct nvme_request *nvme_req(struct request *req)
{
	return blk_mq_rq_to_pdu(req);
}

/* The below value is the specific amount of delay needed before checking
 * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
 * found empirically.
 */
#define NVME_QUIRK_DELAY_AMOUNT		2000

enum nvme_ctrl_state {
	NVME_CTRL_NEW,
	NVME_CTRL_LIVE,
	NVME_CTRL_RESETTING,
	NVME_CTRL_RECONNECTING,
	NVME_CTRL_DELETING,
	NVME_CTRL_DEAD,
};

struct nvme_ctrl {
	enum nvme_ctrl_state state;
	bool identified;
	spinlock_t lock;
	const struct nvme_ctrl_ops *ops;
	struct request_queue *admin_q;
	struct request_queue *connect_q;
	struct device *dev;
	struct kref kref;
	int instance;
	struct blk_mq_tag_set *tagset;
	struct blk_mq_tag_set *admin_tagset;
	struct list_head namespaces;
	struct mutex namespaces_mutex;
	struct device *device;	/* char device */
	struct list_head node;
	struct ida ns_ida;
	struct work_struct reset_work;

	struct opal_dev *opal_dev;

	char name[12];
	char serial[20];
	char model[40];
	char firmware_rev[8];
	char subnqn[NVMF_NQN_SIZE];
	u16 cntlid;

	u32 ctrl_config;
	u16 mtfa;
	u32 queue_count;

	u64 cap;
	u32 page_size;
	u32 max_hw_sectors;
	u16 oncs;
	u16 vid;
	u16 oacs;
	u16 nssa;
	u16 nr_streams;
	atomic_t abort_limit;
	u8 event_limit;
	u8 vwc;
	u32 vs;
	u32 sgls;
	u16 kas;
	u8 npss;
	u8 apsta;
	unsigned int shutdown_timeout;
	unsigned int kato;
	bool subsystem;
	unsigned long quirks;
	struct nvme_id_power_state psd[32];
	struct work_struct scan_work;
	struct work_struct async_event_work;
	struct delayed_work ka_work;
	struct work_struct fw_act_work;

	/* Power saving configuration */
	u64 ps_max_latency_us;
	bool apst_enabled;

	/* PCIe only: */
	u32 hmpre;
	u32 hmmin;
	u32 hmminds;
	u16 hmmaxd;

	/* Fabrics only */
	u16 sqsize;
	u32 ioccsz;
	u32 iorcsz;
	u16 icdoff;
	u16 maxcmd;
	int nr_reconnects;
	struct nvmf_ctrl_options *opts;
};

struct nvme_ns {
	struct list_head list;

	struct nvme_ctrl *ctrl;
	struct request_queue *queue;
	struct gendisk *disk;
	struct nvm_dev *ndev;
	struct kref kref;
	int instance;

	u8 eui[8];
	u8 nguid[16];
	uuid_t uuid;

	unsigned ns_id;
	int lba_shift;
	u16 ms;
	u16 sgs;
	u32 sws;
	bool ext;
	u8 pi_type;
	unsigned long flags;
#define NVME_NS_REMOVING 0
#define NVME_NS_DEAD     1
	u16 noiob;
};

struct nvme_ctrl_ops {
	const char *name;
	struct module *module;
	unsigned int flags;
#define NVME_F_FABRICS			(1 << 0)
#define NVME_F_METADATA_SUPPORTED	(1 << 1)
	int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val);
	int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val);
	int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val);
	void (*free_ctrl)(struct nvme_ctrl *ctrl);
	void (*submit_async_event)(struct nvme_ctrl *ctrl, int aer_idx);
	int (*delete_ctrl)(struct nvme_ctrl *ctrl);
	int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size);
};

static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
{
	u32 val = 0;

	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
		return false;
	return val & NVME_CSTS_RDY;
}

static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
{
	if (!ctrl->subsystem)
		return -ENOTTY;
	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
}

static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
{
	return (sector >> (ns->lba_shift - 9));
}

static inline void nvme_cleanup_cmd(struct request *req)
{
	if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
		kfree(page_address(req->special_vec.bv_page) +
		      req->special_vec.bv_offset);
	}
}

static inline void nvme_end_request(struct request *req, __le16 status,
		union nvme_result result)
{
	struct nvme_request *rq = nvme_req(req);

	rq->status = le16_to_cpu(status) >> 1;
	rq->result = result;
	blk_mq_complete_request(req);
}

void nvme_complete_rq(struct request *req);
void nvme_cancel_request(struct request *req, void *data, bool reserved);
bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
		enum nvme_ctrl_state new_state);
int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
		const struct nvme_ctrl_ops *ops, unsigned long quirks);
void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
void nvme_start_ctrl(struct nvme_ctrl *ctrl);
void nvme_stop_ctrl(struct nvme_ctrl *ctrl);
void nvme_put_ctrl(struct nvme_ctrl *ctrl);
int nvme_init_identify(struct nvme_ctrl *ctrl);

void nvme_queue_scan(struct nvme_ctrl *ctrl);
void nvme_remove_namespaces(struct nvme_ctrl *ctrl);

int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
		bool send);

#define NVME_NR_AERS	1
void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
		union nvme_result *res);
void nvme_queue_async_events(struct nvme_ctrl *ctrl);

void nvme_stop_queues(struct nvme_ctrl *ctrl);
void nvme_start_queues(struct nvme_ctrl *ctrl);
void nvme_kill_queues(struct nvme_ctrl *ctrl);
void nvme_unfreeze(struct nvme_ctrl *ctrl);
void nvme_wait_freeze(struct nvme_ctrl *ctrl);
void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
void nvme_start_freeze(struct nvme_ctrl *ctrl);

#define NVME_QID_ANY -1
struct request *nvme_alloc_request(struct request_queue *q,
		struct nvme_command *cmd, unsigned int flags, int qid);
blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
		struct nvme_command *cmd);
int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		void *buf, unsigned bufflen);
int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		union nvme_result *result, void *buffer, unsigned bufflen,
		unsigned timeout, int qid, int at_head, int flags);
int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);
void nvme_start_keep_alive(struct nvme_ctrl *ctrl);
void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
int nvme_reset_ctrl(struct nvme_ctrl *ctrl);

#ifdef CONFIG_NVM
int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node);
void nvme_nvm_unregister(struct nvme_ns *ns);
int nvme_nvm_register_sysfs(struct nvme_ns *ns);
void nvme_nvm_unregister_sysfs(struct nvme_ns *ns);
int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg);
#else
static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name,
				    int node)
{
	return 0;
}

static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns)
{
	return 0;
}
static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {};
static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
							unsigned long arg)
{
	return -ENOTTY;
}
#endif /* CONFIG_NVM */

static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev)
{
	return dev_to_disk(dev)->private_data;
}

int __init nvme_core_init(void);
void nvme_core_exit(void);

#endif /* _NVME_H */
Commit	Line	Data
f11bb3e2 CH	1	/*
	2	* Copyright (c) 2011-2014, Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*/
	13
	14	#ifndef _NVME_H
	15	#define _NVME_H
	16
	17	#include <linux/nvme.h>
	18	#include <linux/pci.h>
	19	#include <linux/kref.h>
	20	#include <linux/blk-mq.h>
b0b4e09c	21	#include <linux/lightnvm.h>
a98e58e5	22	#include <linux/sed-opal.h>
f11bb3e2 CH	23
	24	extern unsigned char nvme_io_timeout;
	25	#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
	26
21d34711 CH	27	extern unsigned char admin_timeout;
	28	#define ADMIN_TIMEOUT (admin_timeout * HZ)
	29
038bd4cb SG	30	#define NVME_DEFAULT_KATO 5
	31	#define NVME_KATO_GRACE 10
	32
9a6327d2 SG	33	extern struct workqueue_struct *nvme_wq;
9a6327d2 SG	34
ca064085 MB	35	enum {
	36	NVME_NS_LBA = 0,
	37	NVME_NS_LIGHTNVM = 1,
	38	};
	39
f11bb3e2	40	/*
106198ed CH	41	* List of workarounds for devices that required behavior not specified in
106198ed CH	42	* the standard.
f11bb3e2	43	*/
106198ed CH	44	enum nvme_quirks {
	45	/*
	46	* Prefers I/O aligned to a stripe size specified in a vendor
	47	* specific Identify field.
	48	*/
	49	NVME_QUIRK_STRIPE_SIZE = (1 << 0),
540c801c KB	50
	51	/*
	52	* The controller doesn't handle Identify value others than 0 or 1
	53	* correctly.
	54	*/
	55	NVME_QUIRK_IDENTIFY_CNS = (1 << 1),
08095e70 KB	56
08095e70 KB	57	/*
e850fd16 CH	58	* The controller deterministically returns O's on reads to
e850fd16 CH	59	* logical blocks that deallocate was called on.
08095e70	60	*/
e850fd16	61	NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2),
54adc010 GP	62
	63	/*
	64	* The controller needs a delay before starts checking the device
	65	* readiness, which is done by reading the NVME_CSTS_RDY bit.
	66	*/
	67	NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3),
c5552fde AL	68
	69	/*
	70	* APST should not be used.
	71	*/
	72	NVME_QUIRK_NO_APST = (1 << 4),
ff5350a8 AL	73
	74	/*
	75	* The deepest sleep state should not be used.
	76	*/
	77	NVME_QUIRK_NO_DEEPEST_PS = (1 << 5),
608cc4b1 CH	78
	79	/*
	80	* Supports the LighNVM command set if indicated in vs[1].
	81	*/
	82	NVME_QUIRK_LIGHTNVM = (1 << 6),
106198ed CH	83	};
106198ed CH	84
d49187e9 CH	85	/*
	86	* Common request structure for NVMe passthrough. All drivers must have
	87	* this structure as the first member of their request-private data.
	88	*/
	89	struct nvme_request {
	90	struct nvme_command *cmd;
	91	union nvme_result result;
44e44b29	92	u8 retries;
27fa9bc5 CH	93	u8 flags;
	94	u16 status;
	95	};
	96
	97	enum {
	98	NVME_REQ_CANCELLED = (1 << 0),
d49187e9 CH	99	};
	100
	101	static inline struct nvme_request nvme_req(struct request req)
	102	{
	103	return blk_mq_rq_to_pdu(req);
	104	}
	105
54adc010 GP	106	/* The below value is the specific amount of delay needed before checking
	107	* readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
	108	* NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
	109	* found empirically.
	110	*/
	111	#define NVME_QUIRK_DELAY_AMOUNT 2000
	112
bb8d261e CH	113	enum nvme_ctrl_state {
	114	NVME_CTRL_NEW,
	115	NVME_CTRL_LIVE,
	116	NVME_CTRL_RESETTING,
def61eca	117	NVME_CTRL_RECONNECTING,
bb8d261e	118	NVME_CTRL_DELETING,
0ff9d4e1	119	NVME_CTRL_DEAD,
bb8d261e CH	120	};
bb8d261e CH	121
1c63dc66	122	struct nvme_ctrl {
bb8d261e	123	enum nvme_ctrl_state state;
bd4da3ab	124	bool identified;
bb8d261e	125	spinlock_t lock;
1c63dc66	126	const struct nvme_ctrl_ops *ops;
f11bb3e2	127	struct request_queue *admin_q;
07bfcd09	128	struct request_queue *connect_q;
f11bb3e2	129	struct device *dev;
1673f1f0	130	struct kref kref;
f11bb3e2	131	int instance;
5bae7f73	132	struct blk_mq_tag_set *tagset;
34b6c231	133	struct blk_mq_tag_set *admin_tagset;
f11bb3e2	134	struct list_head namespaces;
69d3b8ac	135	struct mutex namespaces_mutex;
5bae7f73	136	struct device device; / char device */
f3ca80fc	137	struct list_head node;
075790eb	138	struct ida ns_ida;
d86c4d8e	139	struct work_struct reset_work;
1c63dc66	140
4f1244c8	141	struct opal_dev *opal_dev;
a98e58e5	142
f11bb3e2 CH	143	char name[12];
	144	char serial[20];
	145	char model[40];
	146	char firmware_rev[8];
180de007	147	char subnqn[NVMF_NQN_SIZE];
76e3914a	148	u16 cntlid;
5fd4ce1b CH	149
5fd4ce1b CH	150	u32 ctrl_config;
b6dccf7f	151	u16 mtfa;
d858e5f0	152	u32 queue_count;
5fd4ce1b	153
20d0dfe6	154	u64 cap;
5fd4ce1b	155	u32 page_size;
f11bb3e2	156	u32 max_hw_sectors;
f11bb3e2	157	u16 oncs;
118472ab	158	u16 vid;
8a9ae523	159	u16 oacs;
f5d11840 JA	160	u16 nssa;
f5d11840 JA	161	u16 nr_streams;
6bf25d16	162	atomic_t abort_limit;
f11bb3e2 CH	163	u8 event_limit;
f11bb3e2 CH	164	u8 vwc;
f3ca80fc	165	u32 vs;
07bfcd09	166	u32 sgls;
038bd4cb	167	u16 kas;
c5552fde AL	168	u8 npss;
c5552fde AL	169	u8 apsta;
07fbd32a	170	unsigned int shutdown_timeout;
038bd4cb	171	unsigned int kato;
f3ca80fc	172	bool subsystem;
106198ed	173	unsigned long quirks;
c5552fde	174	struct nvme_id_power_state psd[32];
5955be21	175	struct work_struct scan_work;
f866fc42	176	struct work_struct async_event_work;
038bd4cb	177	struct delayed_work ka_work;
b6dccf7f	178	struct work_struct fw_act_work;
07bfcd09	179
c5552fde AL	180	/* Power saving configuration */
c5552fde AL	181	u64 ps_max_latency_us;
76a5af84	182	bool apst_enabled;
c5552fde	183
044a9df1	184	/* PCIe only: */
fe6d53c9 CH	185	u32 hmpre;
fe6d53c9 CH	186	u32 hmmin;
044a9df1 CH	187	u32 hmminds;
044a9df1 CH	188	u16 hmmaxd;
fe6d53c9	189
07bfcd09 CH	190	/* Fabrics only */
	191	u16 sqsize;
	192	u32 ioccsz;
	193	u32 iorcsz;
	194	u16 icdoff;
	195	u16 maxcmd;
fdf9dfa8	196	int nr_reconnects;
07bfcd09	197	struct nvmf_ctrl_options *opts;
f11bb3e2 CH	198	};
f11bb3e2 CH	199
f11bb3e2 CH	200	struct nvme_ns {
	201	struct list_head list;
	202
1c63dc66	203	struct nvme_ctrl *ctrl;
f11bb3e2 CH	204	struct request_queue *queue;
f11bb3e2 CH	205	struct gendisk *disk;
b0b4e09c	206	struct nvm_dev *ndev;
f11bb3e2	207	struct kref kref;
075790eb	208	int instance;
f11bb3e2	209
2b9b6e86	210	u8 eui[8];
90985b84	211	u8 nguid[16];
3b22ba26	212	uuid_t uuid;
2b9b6e86	213
f11bb3e2 CH	214	unsigned ns_id;
	215	int lba_shift;
	216	u16 ms;
f5d11840 JA	217	u16 sgs;
f5d11840 JA	218	u32 sws;
f11bb3e2 CH	219	bool ext;
f11bb3e2 CH	220	u8 pi_type;
646017a6	221	unsigned long flags;
646017a6	222	#define NVME_NS_REMOVING 0
69d9a99c	223	#define NVME_NS_DEAD 1
57eeaf8e	224	u16 noiob;
f11bb3e2 CH	225	};
f11bb3e2 CH	226
1c63dc66	227	struct nvme_ctrl_ops {
1a353d85	228	const char *name;
e439bb12	229	struct module *module;
d3d5b87d CH	230	unsigned int flags;
d3d5b87d CH	231	#define NVME_F_FABRICS (1 << 0)
c81bfba9	232	#define NVME_F_METADATA_SUPPORTED (1 << 1)
1c63dc66	233	int (reg_read32)(struct nvme_ctrl ctrl, u32 off, u32 *val);
5fd4ce1b	234	int (reg_write32)(struct nvme_ctrl ctrl, u32 off, u32 val);
7fd8930f	235	int (reg_read64)(struct nvme_ctrl ctrl, u32 off, u64 *val);
1673f1f0	236	void (free_ctrl)(struct nvme_ctrl ctrl);
f866fc42	237	void (submit_async_event)(struct nvme_ctrl ctrl, int aer_idx);
1a353d85	238	int (delete_ctrl)(struct nvme_ctrl ctrl);
1a353d85	239	int (get_address)(struct nvme_ctrl ctrl, char *buf, int size);
f11bb3e2 CH	240	};
f11bb3e2 CH	241
1c63dc66 CH	242	static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
	243	{
	244	u32 val = 0;
	245
	246	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
	247	return false;
	248	return val & NVME_CSTS_RDY;
	249	}
	250
f3ca80fc CH	251	static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
	252	{
	253	if (!ctrl->subsystem)
	254	return -ENOTTY;
	255	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
	256	}
	257
f11bb3e2 CH	258	static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
	259	{
	260	return (sector >> (ns->lba_shift - 9));
	261	}
	262
6904242d ML	263	static inline void nvme_cleanup_cmd(struct request *req)
6904242d ML	264	{
f9d03f96 CH	265	if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
	266	kfree(page_address(req->special_vec.bv_page) +
	267	req->special_vec.bv_offset);
	268	}
6904242d ML	269	}
6904242d ML	270
27fa9bc5 CH	271	static inline void nvme_end_request(struct request *req, __le16 status,
27fa9bc5 CH	272	union nvme_result result)
15a190f7	273	{
27fa9bc5	274	struct nvme_request *rq = nvme_req(req);
15a190f7	275
27fa9bc5 CH	276	rq->status = le16_to_cpu(status) >> 1;
27fa9bc5 CH	277	rq->result = result;
08e0029a	278	blk_mq_complete_request(req);
7688faa6 CH	279	}
7688faa6 CH	280
77f02a7a	281	void nvme_complete_rq(struct request *req);
c55a2fd4	282	void nvme_cancel_request(struct request req, void data, bool reserved);
bb8d261e CH	283	bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
bb8d261e CH	284	enum nvme_ctrl_state new_state);
5fd4ce1b CH	285	int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	286	int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	287	int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
f3ca80fc CH	288	int nvme_init_ctrl(struct nvme_ctrl ctrl, struct device dev,
f3ca80fc CH	289	const struct nvme_ctrl_ops *ops, unsigned long quirks);
53029b04	290	void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
d09f2b45 SG	291	void nvme_start_ctrl(struct nvme_ctrl *ctrl);
d09f2b45 SG	292	void nvme_stop_ctrl(struct nvme_ctrl *ctrl);
1673f1f0	293	void nvme_put_ctrl(struct nvme_ctrl *ctrl);
7fd8930f	294	int nvme_init_identify(struct nvme_ctrl *ctrl);
5bae7f73	295
5955be21	296	void nvme_queue_scan(struct nvme_ctrl *ctrl);
5bae7f73	297	void nvme_remove_namespaces(struct nvme_ctrl *ctrl);
1673f1f0	298
4f1244c8 CH	299	int nvme_sec_submit(void data, u16 spsp, u8 secp, void buffer, size_t len,
4f1244c8 CH	300	bool send);
a98e58e5	301
f866fc42	302	#define NVME_NR_AERS 1
7bf58533 CH	303	void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
7bf58533 CH	304	union nvme_result *res);
f866fc42 CH	305	void nvme_queue_async_events(struct nvme_ctrl *ctrl);
f866fc42 CH	306
25646264 KB	307	void nvme_stop_queues(struct nvme_ctrl *ctrl);
25646264 KB	308	void nvme_start_queues(struct nvme_ctrl *ctrl);
69d9a99c	309	void nvme_kill_queues(struct nvme_ctrl *ctrl);
302ad8cc KB	310	void nvme_unfreeze(struct nvme_ctrl *ctrl);
	311	void nvme_wait_freeze(struct nvme_ctrl *ctrl);
	312	void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
	313	void nvme_start_freeze(struct nvme_ctrl *ctrl);
363c9aac	314
eb71f435	315	#define NVME_QID_ANY -1
4160982e	316	struct request nvme_alloc_request(struct request_queue q,
eb71f435	317	struct nvme_command *cmd, unsigned int flags, int qid);
fc17b653	318	blk_status_t nvme_setup_cmd(struct nvme_ns ns, struct request req,
8093f7ca	319	struct nvme_command *cmd);
f11bb3e2 CH	320	int nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
	321	void *buf, unsigned bufflen);
	322	int __nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
d49187e9	323	union nvme_result result, void buffer, unsigned bufflen,
eb71f435	324	unsigned timeout, int qid, int at_head, int flags);
9a0be7ab	325	int nvme_set_queue_count(struct nvme_ctrl ctrl, int count);
038bd4cb SG	326	void nvme_start_keep_alive(struct nvme_ctrl *ctrl);
038bd4cb SG	327	void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
d86c4d8e	328	int nvme_reset_ctrl(struct nvme_ctrl *ctrl);
f11bb3e2	329
c4699e70	330	#ifdef CONFIG_NVM
3dc87dd0	331	int nvme_nvm_register(struct nvme_ns ns, char disk_name, int node);
b0b4e09c	332	void nvme_nvm_unregister(struct nvme_ns *ns);
3dc87dd0 MB	333	int nvme_nvm_register_sysfs(struct nvme_ns *ns);
3dc87dd0 MB	334	void nvme_nvm_unregister_sysfs(struct nvme_ns *ns);
84d4add7	335	int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg);
c4699e70	336	#else
b0b4e09c	337	static inline int nvme_nvm_register(struct nvme_ns ns, char disk_name,
3dc87dd0	338	int node)
c4699e70 KB	339	{
	340	return 0;
	341	}
	342
b0b4e09c	343	static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
3dc87dd0 MB	344	static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns)
	345	{
	346	return 0;
	347	}
	348	static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {};
84d4add7 MB	349	static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
	350	unsigned long arg)
	351	{
	352	return -ENOTTY;
	353	}
3dc87dd0 MB	354	#endif /* CONFIG_NVM */
3dc87dd0 MB	355
40267efd SL	356	static inline struct nvme_ns nvme_get_ns_from_dev(struct device dev)
	357	{
	358	return dev_to_disk(dev)->private_data;
	359	}
ca064085	360
5bae7f73 CH	361	int __init nvme_core_init(void);
	362	void nvme_core_exit(void);
	363
f11bb3e2	364	#endif /* _NVME_H */