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f11bb3e2 CH |
1 | /* |
2 | * Copyright (c) 2011-2014, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | */ | |
13 | ||
14 | #ifndef _NVME_H | |
15 | #define _NVME_H | |
16 | ||
17 | #include <linux/nvme.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/kref.h> | |
20 | #include <linux/blk-mq.h> | |
b0b4e09c | 21 | #include <linux/lightnvm.h> |
f11bb3e2 | 22 | |
297465c8 CH |
23 | enum { |
24 | /* | |
25 | * Driver internal status code for commands that were cancelled due | |
26 | * to timeouts or controller shutdown. The value is negative so | |
27 | * that it a) doesn't overlap with the unsigned hardware error codes, | |
28 | * and b) can easily be tested for. | |
29 | */ | |
30 | NVME_SC_CANCELLED = -EINTR, | |
31 | }; | |
32 | ||
f11bb3e2 CH |
33 | extern unsigned char nvme_io_timeout; |
34 | #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) | |
35 | ||
21d34711 CH |
36 | extern unsigned char admin_timeout; |
37 | #define ADMIN_TIMEOUT (admin_timeout * HZ) | |
38 | ||
5fd4ce1b CH |
39 | extern unsigned char shutdown_timeout; |
40 | #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ) | |
41 | ||
038bd4cb SG |
42 | #define NVME_DEFAULT_KATO 5 |
43 | #define NVME_KATO_GRACE 10 | |
44 | ||
f80ec966 KB |
45 | extern unsigned int nvme_max_retries; |
46 | ||
ca064085 MB |
47 | enum { |
48 | NVME_NS_LBA = 0, | |
49 | NVME_NS_LIGHTNVM = 1, | |
50 | }; | |
51 | ||
f11bb3e2 | 52 | /* |
106198ed CH |
53 | * List of workarounds for devices that required behavior not specified in |
54 | * the standard. | |
f11bb3e2 | 55 | */ |
106198ed CH |
56 | enum nvme_quirks { |
57 | /* | |
58 | * Prefers I/O aligned to a stripe size specified in a vendor | |
59 | * specific Identify field. | |
60 | */ | |
61 | NVME_QUIRK_STRIPE_SIZE = (1 << 0), | |
540c801c KB |
62 | |
63 | /* | |
64 | * The controller doesn't handle Identify value others than 0 or 1 | |
65 | * correctly. | |
66 | */ | |
67 | NVME_QUIRK_IDENTIFY_CNS = (1 << 1), | |
08095e70 KB |
68 | |
69 | /* | |
70 | * The controller deterministically returns O's on reads to discarded | |
71 | * logical blocks. | |
72 | */ | |
73 | NVME_QUIRK_DISCARD_ZEROES = (1 << 2), | |
54adc010 GP |
74 | |
75 | /* | |
76 | * The controller needs a delay before starts checking the device | |
77 | * readiness, which is done by reading the NVME_CSTS_RDY bit. | |
78 | */ | |
79 | NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), | |
106198ed CH |
80 | }; |
81 | ||
54adc010 GP |
82 | /* The below value is the specific amount of delay needed before checking |
83 | * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the | |
84 | * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was | |
85 | * found empirically. | |
86 | */ | |
87 | #define NVME_QUIRK_DELAY_AMOUNT 2000 | |
88 | ||
bb8d261e CH |
89 | enum nvme_ctrl_state { |
90 | NVME_CTRL_NEW, | |
91 | NVME_CTRL_LIVE, | |
92 | NVME_CTRL_RESETTING, | |
def61eca | 93 | NVME_CTRL_RECONNECTING, |
bb8d261e | 94 | NVME_CTRL_DELETING, |
0ff9d4e1 | 95 | NVME_CTRL_DEAD, |
bb8d261e CH |
96 | }; |
97 | ||
1c63dc66 | 98 | struct nvme_ctrl { |
bb8d261e CH |
99 | enum nvme_ctrl_state state; |
100 | spinlock_t lock; | |
1c63dc66 | 101 | const struct nvme_ctrl_ops *ops; |
f11bb3e2 | 102 | struct request_queue *admin_q; |
07bfcd09 | 103 | struct request_queue *connect_q; |
f11bb3e2 | 104 | struct device *dev; |
1673f1f0 | 105 | struct kref kref; |
f11bb3e2 | 106 | int instance; |
5bae7f73 | 107 | struct blk_mq_tag_set *tagset; |
f11bb3e2 | 108 | struct list_head namespaces; |
69d3b8ac | 109 | struct mutex namespaces_mutex; |
5bae7f73 | 110 | struct device *device; /* char device */ |
f3ca80fc | 111 | struct list_head node; |
075790eb | 112 | struct ida ns_ida; |
1c63dc66 | 113 | |
f11bb3e2 CH |
114 | char name[12]; |
115 | char serial[20]; | |
116 | char model[40]; | |
117 | char firmware_rev[8]; | |
76e3914a | 118 | u16 cntlid; |
5fd4ce1b CH |
119 | |
120 | u32 ctrl_config; | |
121 | ||
122 | u32 page_size; | |
f11bb3e2 CH |
123 | u32 max_hw_sectors; |
124 | u32 stripe_size; | |
f11bb3e2 | 125 | u16 oncs; |
118472ab | 126 | u16 vid; |
6bf25d16 | 127 | atomic_t abort_limit; |
f11bb3e2 CH |
128 | u8 event_limit; |
129 | u8 vwc; | |
f3ca80fc | 130 | u32 vs; |
07bfcd09 | 131 | u32 sgls; |
038bd4cb SG |
132 | u16 kas; |
133 | unsigned int kato; | |
f3ca80fc | 134 | bool subsystem; |
106198ed | 135 | unsigned long quirks; |
5955be21 | 136 | struct work_struct scan_work; |
f866fc42 | 137 | struct work_struct async_event_work; |
038bd4cb | 138 | struct delayed_work ka_work; |
07bfcd09 CH |
139 | |
140 | /* Fabrics only */ | |
141 | u16 sqsize; | |
142 | u32 ioccsz; | |
143 | u32 iorcsz; | |
144 | u16 icdoff; | |
145 | u16 maxcmd; | |
146 | struct nvmf_ctrl_options *opts; | |
f11bb3e2 CH |
147 | }; |
148 | ||
149 | /* | |
150 | * An NVM Express namespace is equivalent to a SCSI LUN | |
151 | */ | |
152 | struct nvme_ns { | |
153 | struct list_head list; | |
154 | ||
1c63dc66 | 155 | struct nvme_ctrl *ctrl; |
f11bb3e2 CH |
156 | struct request_queue *queue; |
157 | struct gendisk *disk; | |
b0b4e09c | 158 | struct nvm_dev *ndev; |
f11bb3e2 | 159 | struct kref kref; |
075790eb | 160 | int instance; |
f11bb3e2 | 161 | |
2b9b6e86 KB |
162 | u8 eui[8]; |
163 | u8 uuid[16]; | |
164 | ||
f11bb3e2 CH |
165 | unsigned ns_id; |
166 | int lba_shift; | |
167 | u16 ms; | |
168 | bool ext; | |
169 | u8 pi_type; | |
646017a6 KB |
170 | unsigned long flags; |
171 | ||
172 | #define NVME_NS_REMOVING 0 | |
69d9a99c | 173 | #define NVME_NS_DEAD 1 |
646017a6 | 174 | |
f11bb3e2 CH |
175 | u64 mode_select_num_blocks; |
176 | u32 mode_select_block_len; | |
177 | }; | |
178 | ||
1c63dc66 | 179 | struct nvme_ctrl_ops { |
1a353d85 | 180 | const char *name; |
e439bb12 | 181 | struct module *module; |
07bfcd09 | 182 | bool is_fabrics; |
1c63dc66 | 183 | int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); |
5fd4ce1b | 184 | int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); |
7fd8930f | 185 | int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); |
f3ca80fc | 186 | int (*reset_ctrl)(struct nvme_ctrl *ctrl); |
1673f1f0 | 187 | void (*free_ctrl)(struct nvme_ctrl *ctrl); |
5955be21 | 188 | void (*post_scan)(struct nvme_ctrl *ctrl); |
f866fc42 | 189 | void (*submit_async_event)(struct nvme_ctrl *ctrl, int aer_idx); |
1a353d85 ML |
190 | int (*delete_ctrl)(struct nvme_ctrl *ctrl); |
191 | const char *(*get_subsysnqn)(struct nvme_ctrl *ctrl); | |
192 | int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); | |
f11bb3e2 CH |
193 | }; |
194 | ||
1c63dc66 CH |
195 | static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl) |
196 | { | |
197 | u32 val = 0; | |
198 | ||
199 | if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val)) | |
200 | return false; | |
201 | return val & NVME_CSTS_RDY; | |
202 | } | |
203 | ||
f3ca80fc CH |
204 | static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) |
205 | { | |
206 | if (!ctrl->subsystem) | |
207 | return -ENOTTY; | |
208 | return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); | |
209 | } | |
210 | ||
f11bb3e2 CH |
211 | static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector) |
212 | { | |
213 | return (sector >> (ns->lba_shift - 9)); | |
214 | } | |
215 | ||
58b45602 ML |
216 | static inline unsigned nvme_map_len(struct request *rq) |
217 | { | |
c2df40df | 218 | if (req_op(rq) == REQ_OP_DISCARD) |
58b45602 ML |
219 | return sizeof(struct nvme_dsm_range); |
220 | else | |
221 | return blk_rq_bytes(rq); | |
222 | } | |
223 | ||
6904242d ML |
224 | static inline void nvme_cleanup_cmd(struct request *req) |
225 | { | |
c2df40df | 226 | if (req_op(req) == REQ_OP_DISCARD) |
6904242d ML |
227 | kfree(req->completion_data); |
228 | } | |
229 | ||
15a190f7 CH |
230 | static inline int nvme_error_status(u16 status) |
231 | { | |
232 | switch (status & 0x7ff) { | |
233 | case NVME_SC_SUCCESS: | |
234 | return 0; | |
235 | case NVME_SC_CAP_EXCEEDED: | |
236 | return -ENOSPC; | |
237 | default: | |
238 | return -EIO; | |
239 | } | |
240 | } | |
241 | ||
7688faa6 CH |
242 | static inline bool nvme_req_needs_retry(struct request *req, u16 status) |
243 | { | |
244 | return !(status & NVME_SC_DNR || blk_noretry_request(req)) && | |
f80ec966 KB |
245 | (jiffies - req->start_time) < req->timeout && |
246 | req->retries < nvme_max_retries; | |
7688faa6 CH |
247 | } |
248 | ||
c55a2fd4 | 249 | void nvme_cancel_request(struct request *req, void *data, bool reserved); |
bb8d261e CH |
250 | bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, |
251 | enum nvme_ctrl_state new_state); | |
5fd4ce1b CH |
252 | int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap); |
253 | int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap); | |
254 | int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl); | |
f3ca80fc CH |
255 | int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, |
256 | const struct nvme_ctrl_ops *ops, unsigned long quirks); | |
53029b04 | 257 | void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); |
1673f1f0 | 258 | void nvme_put_ctrl(struct nvme_ctrl *ctrl); |
7fd8930f | 259 | int nvme_init_identify(struct nvme_ctrl *ctrl); |
5bae7f73 | 260 | |
5955be21 | 261 | void nvme_queue_scan(struct nvme_ctrl *ctrl); |
5bae7f73 | 262 | void nvme_remove_namespaces(struct nvme_ctrl *ctrl); |
1673f1f0 | 263 | |
f866fc42 CH |
264 | #define NVME_NR_AERS 1 |
265 | void nvme_complete_async_event(struct nvme_ctrl *ctrl, | |
266 | struct nvme_completion *cqe); | |
267 | void nvme_queue_async_events(struct nvme_ctrl *ctrl); | |
268 | ||
25646264 KB |
269 | void nvme_stop_queues(struct nvme_ctrl *ctrl); |
270 | void nvme_start_queues(struct nvme_ctrl *ctrl); | |
69d9a99c | 271 | void nvme_kill_queues(struct nvme_ctrl *ctrl); |
363c9aac | 272 | |
eb71f435 | 273 | #define NVME_QID_ANY -1 |
4160982e | 274 | struct request *nvme_alloc_request(struct request_queue *q, |
eb71f435 | 275 | struct nvme_command *cmd, unsigned int flags, int qid); |
7688faa6 | 276 | void nvme_requeue_req(struct request *req); |
8093f7ca ML |
277 | int nvme_setup_cmd(struct nvme_ns *ns, struct request *req, |
278 | struct nvme_command *cmd); | |
f11bb3e2 CH |
279 | int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
280 | void *buf, unsigned bufflen); | |
281 | int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, | |
1cb3cce5 | 282 | struct nvme_completion *cqe, void *buffer, unsigned bufflen, |
eb71f435 | 283 | unsigned timeout, int qid, int at_head, int flags); |
4160982e CH |
284 | int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd, |
285 | void __user *ubuffer, unsigned bufflen, u32 *result, | |
286 | unsigned timeout); | |
0b7f1f26 KB |
287 | int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd, |
288 | void __user *ubuffer, unsigned bufflen, | |
289 | void __user *meta_buffer, unsigned meta_len, u32 meta_seed, | |
f11bb3e2 | 290 | u32 *result, unsigned timeout); |
1c63dc66 CH |
291 | int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id); |
292 | int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid, | |
f11bb3e2 | 293 | struct nvme_id_ns **id); |
1c63dc66 CH |
294 | int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log); |
295 | int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid, | |
f11bb3e2 | 296 | dma_addr_t dma_addr, u32 *result); |
1c63dc66 | 297 | int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11, |
f11bb3e2 | 298 | dma_addr_t dma_addr, u32 *result); |
9a0be7ab | 299 | int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); |
038bd4cb SG |
300 | void nvme_start_keep_alive(struct nvme_ctrl *ctrl); |
301 | void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); | |
f11bb3e2 CH |
302 | |
303 | struct sg_io_hdr; | |
304 | ||
305 | int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr); | |
306 | int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg); | |
307 | int nvme_sg_get_version_num(int __user *ip); | |
308 | ||
c4699e70 | 309 | #ifdef CONFIG_NVM |
ca064085 | 310 | int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id); |
b0b4e09c MB |
311 | int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node); |
312 | void nvme_nvm_unregister(struct nvme_ns *ns); | |
c4699e70 | 313 | #else |
b0b4e09c MB |
314 | static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, |
315 | int node) | |
c4699e70 KB |
316 | { |
317 | return 0; | |
318 | } | |
319 | ||
b0b4e09c | 320 | static inline void nvme_nvm_unregister(struct nvme_ns *ns) {}; |
c4699e70 KB |
321 | |
322 | static inline int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id) | |
323 | { | |
324 | return 0; | |
325 | } | |
326 | #endif /* CONFIG_NVM */ | |
ca064085 | 327 | |
5bae7f73 CH |
328 | int __init nvme_core_init(void); |
329 | void nvme_core_exit(void); | |
330 | ||
f11bb3e2 | 331 | #endif /* _NVME_H */ |