[mirror_ubuntu-bionic-kernel.git] / drivers / nvme / host / nvme.h

/*
 * Copyright (c) 2011-2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef _NVME_H
#define _NVME_H

#include <linux/nvme.h>
#include <linux/pci.h>
#include <linux/kref.h>
#include <linux/blk-mq.h>

enum {
	/*
	 * Driver internal status code for commands that were cancelled due
	 * to timeouts or controller shutdown.  The value is negative so
	 * that it a) doesn't overlap with the unsigned hardware error codes,
	 * and b) can easily be tested for.
	 */
	NVME_SC_CANCELLED		= -EINTR,
};

extern unsigned char nvme_io_timeout;
#define NVME_IO_TIMEOUT	(nvme_io_timeout * HZ)

extern unsigned char admin_timeout;
#define ADMIN_TIMEOUT	(admin_timeout * HZ)

extern unsigned char shutdown_timeout;
#define SHUTDOWN_TIMEOUT	(shutdown_timeout * HZ)

#define NVME_DEFAULT_KATO	5
#define NVME_KATO_GRACE		10

extern unsigned int nvme_max_retries;

enum {
	NVME_NS_LBA		= 0,
	NVME_NS_LIGHTNVM	= 1,
};

/*
 * List of workarounds for devices that required behavior not specified in
 * the standard.
 */
enum nvme_quirks {
	/*
	 * Prefers I/O aligned to a stripe size specified in a vendor
	 * specific Identify field.
	 */
	NVME_QUIRK_STRIPE_SIZE			= (1 << 0),

	/*
	 * The controller doesn't handle Identify value others than 0 or 1
	 * correctly.
	 */
	NVME_QUIRK_IDENTIFY_CNS			= (1 << 1),

	/*
	 * The controller deterministically returns O's on reads to discarded
	 * logical blocks.
	 */
	NVME_QUIRK_DISCARD_ZEROES		= (1 << 2),

	/*
	 * The controller needs a delay before starts checking the device
	 * readiness, which is done by reading the NVME_CSTS_RDY bit.
	 */
	NVME_QUIRK_DELAY_BEFORE_CHK_RDY		= (1 << 3),
};

/* The below value is the specific amount of delay needed before checking
 * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
 * found empirically.
 */
#define NVME_QUIRK_DELAY_AMOUNT		2000

enum nvme_ctrl_state {
	NVME_CTRL_NEW,
	NVME_CTRL_LIVE,
	NVME_CTRL_RESETTING,
	NVME_CTRL_RECONNECTING,
	NVME_CTRL_DELETING,
	NVME_CTRL_DEAD,
};

struct nvme_ctrl {
	enum nvme_ctrl_state state;
	spinlock_t lock;
	const struct nvme_ctrl_ops *ops;
	struct request_queue *admin_q;
	struct request_queue *connect_q;
	struct device *dev;
	struct kref kref;
	int instance;
	struct blk_mq_tag_set *tagset;
	struct list_head namespaces;
	struct mutex namespaces_mutex;
	struct device *device;	/* char device */
	struct list_head node;
	struct ida ns_ida;

	char name[12];
	char serial[20];
	char model[40];
	char firmware_rev[8];
	u16 cntlid;

	u32 ctrl_config;

	u32 page_size;
	u32 max_hw_sectors;
	u32 stripe_size;
	u16 oncs;
	u16 vid;
	atomic_t abort_limit;
	u8 event_limit;
	u8 vwc;
	u32 vs;
	u32 sgls;
	u16 kas;
	unsigned int kato;
	bool subsystem;
	unsigned long quirks;
	struct work_struct scan_work;
	struct work_struct async_event_work;
	struct delayed_work ka_work;

	/* Fabrics only */
	u16 sqsize;
	u32 ioccsz;
	u32 iorcsz;
	u16 icdoff;
	u16 maxcmd;
	struct nvmf_ctrl_options *opts;
};

/*
 * An NVM Express namespace is equivalent to a SCSI LUN
 */
struct nvme_ns {
	struct list_head list;

	struct nvme_ctrl *ctrl;
	struct request_queue *queue;
	struct gendisk *disk;
	struct kref kref;
	int instance;

	u8 eui[8];
	u8 uuid[16];

	unsigned ns_id;
	int lba_shift;
	u16 ms;
	bool ext;
	u8 pi_type;
	int type;
	unsigned long flags;

#define NVME_NS_REMOVING 0
#define NVME_NS_DEAD     1

	u64 mode_select_num_blocks;
	u32 mode_select_block_len;
};

struct nvme_ctrl_ops {
	const char *name;
	struct module *module;
	bool is_fabrics;
	int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val);
	int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val);
	int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val);
	int (*reset_ctrl)(struct nvme_ctrl *ctrl);
	void (*free_ctrl)(struct nvme_ctrl *ctrl);
	void (*post_scan)(struct nvme_ctrl *ctrl);
	void (*submit_async_event)(struct nvme_ctrl *ctrl, int aer_idx);
	int (*delete_ctrl)(struct nvme_ctrl *ctrl);
	const char *(*get_subsysnqn)(struct nvme_ctrl *ctrl);
	int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size);
};

static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
{
	u32 val = 0;

	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
		return false;
	return val & NVME_CSTS_RDY;
}

static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
{
	if (!ctrl->subsystem)
		return -ENOTTY;
	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
}

static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
{
	return (sector >> (ns->lba_shift - 9));
}

static inline unsigned nvme_map_len(struct request *rq)
{
	if (req_op(rq) == REQ_OP_DISCARD)
		return sizeof(struct nvme_dsm_range);
	else
		return blk_rq_bytes(rq);
}

static inline void nvme_cleanup_cmd(struct request *req)
{
	if (req_op(req) == REQ_OP_DISCARD)
		kfree(req->completion_data);
}

static inline int nvme_error_status(u16 status)
{
	switch (status & 0x7ff) {
	case NVME_SC_SUCCESS:
		return 0;
	case NVME_SC_CAP_EXCEEDED:
		return -ENOSPC;
	default:
		return -EIO;
	}
}

static inline bool nvme_req_needs_retry(struct request *req, u16 status)
{
	return !(status & NVME_SC_DNR || blk_noretry_request(req)) &&
		(jiffies - req->start_time) < req->timeout &&
		req->retries < nvme_max_retries;
}

void nvme_cancel_request(struct request *req, void *data, bool reserved);
bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
		enum nvme_ctrl_state new_state);
int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
		const struct nvme_ctrl_ops *ops, unsigned long quirks);
void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
void nvme_put_ctrl(struct nvme_ctrl *ctrl);
int nvme_init_identify(struct nvme_ctrl *ctrl);

void nvme_queue_scan(struct nvme_ctrl *ctrl);
void nvme_remove_namespaces(struct nvme_ctrl *ctrl);

#define NVME_NR_AERS	1
void nvme_complete_async_event(struct nvme_ctrl *ctrl,
		struct nvme_completion *cqe);
void nvme_queue_async_events(struct nvme_ctrl *ctrl);

void nvme_stop_queues(struct nvme_ctrl *ctrl);
void nvme_start_queues(struct nvme_ctrl *ctrl);
void nvme_kill_queues(struct nvme_ctrl *ctrl);

#define NVME_QID_ANY -1
struct request *nvme_alloc_request(struct request_queue *q,
		struct nvme_command *cmd, unsigned int flags, int qid);
void nvme_requeue_req(struct request *req);
int nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
		struct nvme_command *cmd);
int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		void *buf, unsigned bufflen);
int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		struct nvme_completion *cqe, void *buffer, unsigned bufflen,
		unsigned timeout, int qid, int at_head, int flags);
int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
		void __user *ubuffer, unsigned bufflen, u32 *result,
		unsigned timeout);
int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
		void __user *ubuffer, unsigned bufflen,
		void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
		u32 *result, unsigned timeout);
int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id);
int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
		struct nvme_id_ns **id);
int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log);
int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
			dma_addr_t dma_addr, u32 *result);
int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
			dma_addr_t dma_addr, u32 *result);
int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);
void nvme_start_keep_alive(struct nvme_ctrl *ctrl);
void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);

struct sg_io_hdr;

int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr);
int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
int nvme_sg_get_version_num(int __user *ip);

#ifdef CONFIG_NVM
int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id);
int nvme_nvm_register(struct request_queue *q, char *disk_name);
void nvme_nvm_unregister(struct request_queue *q, char *disk_name);
#else
static inline int nvme_nvm_register(struct request_queue *q, char *disk_name)
{
	return 0;
}

static inline void nvme_nvm_unregister(struct request_queue *q, char *disk_name) {};

static inline int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id)
{
	return 0;
}
#endif /* CONFIG_NVM */

int __init nvme_core_init(void);
void nvme_core_exit(void);

#endif /* _NVME_H */
Commit	Line	Data
f11bb3e2 CH	1	/*
	2	* Copyright (c) 2011-2014, Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*/
	13
	14	#ifndef _NVME_H
	15	#define _NVME_H
	16
	17	#include <linux/nvme.h>
	18	#include <linux/pci.h>
	19	#include <linux/kref.h>
	20	#include <linux/blk-mq.h>
	21
297465c8 CH	22	enum {
	23	/*
	24	* Driver internal status code for commands that were cancelled due
	25	* to timeouts or controller shutdown. The value is negative so
	26	* that it a) doesn't overlap with the unsigned hardware error codes,
	27	* and b) can easily be tested for.
	28	*/
	29	NVME_SC_CANCELLED = -EINTR,
	30	};
	31
f11bb3e2 CH	32	extern unsigned char nvme_io_timeout;
	33	#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
	34
21d34711 CH	35	extern unsigned char admin_timeout;
	36	#define ADMIN_TIMEOUT (admin_timeout * HZ)
	37
5fd4ce1b CH	38	extern unsigned char shutdown_timeout;
	39	#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
	40
038bd4cb SG	41	#define NVME_DEFAULT_KATO 5
	42	#define NVME_KATO_GRACE 10
	43
f80ec966 KB	44	extern unsigned int nvme_max_retries;
f80ec966 KB	45
ca064085 MB	46	enum {
	47	NVME_NS_LBA = 0,
	48	NVME_NS_LIGHTNVM = 1,
	49	};
	50
f11bb3e2	51	/*
106198ed CH	52	* List of workarounds for devices that required behavior not specified in
106198ed CH	53	* the standard.
f11bb3e2	54	*/
106198ed CH	55	enum nvme_quirks {
	56	/*
	57	* Prefers I/O aligned to a stripe size specified in a vendor
	58	* specific Identify field.
	59	*/
	60	NVME_QUIRK_STRIPE_SIZE = (1 << 0),
540c801c KB	61
	62	/*
	63	* The controller doesn't handle Identify value others than 0 or 1
	64	* correctly.
	65	*/
	66	NVME_QUIRK_IDENTIFY_CNS = (1 << 1),
08095e70 KB	67
	68	/*
	69	* The controller deterministically returns O's on reads to discarded
	70	* logical blocks.
	71	*/
	72	NVME_QUIRK_DISCARD_ZEROES = (1 << 2),
54adc010 GP	73
	74	/*
	75	* The controller needs a delay before starts checking the device
	76	* readiness, which is done by reading the NVME_CSTS_RDY bit.
	77	*/
	78	NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3),
106198ed CH	79	};
106198ed CH	80
54adc010 GP	81	/* The below value is the specific amount of delay needed before checking
	82	* readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
	83	* NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
	84	* found empirically.
	85	*/
	86	#define NVME_QUIRK_DELAY_AMOUNT 2000
	87
bb8d261e CH	88	enum nvme_ctrl_state {
	89	NVME_CTRL_NEW,
	90	NVME_CTRL_LIVE,
	91	NVME_CTRL_RESETTING,
def61eca	92	NVME_CTRL_RECONNECTING,
bb8d261e	93	NVME_CTRL_DELETING,
0ff9d4e1	94	NVME_CTRL_DEAD,
bb8d261e CH	95	};
bb8d261e CH	96
1c63dc66	97	struct nvme_ctrl {
bb8d261e CH	98	enum nvme_ctrl_state state;
bb8d261e CH	99	spinlock_t lock;
1c63dc66	100	const struct nvme_ctrl_ops *ops;
f11bb3e2	101	struct request_queue *admin_q;
07bfcd09	102	struct request_queue *connect_q;
f11bb3e2	103	struct device *dev;
1673f1f0	104	struct kref kref;
f11bb3e2	105	int instance;
5bae7f73	106	struct blk_mq_tag_set *tagset;
f11bb3e2	107	struct list_head namespaces;
69d3b8ac	108	struct mutex namespaces_mutex;
5bae7f73	109	struct device device; / char device */
f3ca80fc	110	struct list_head node;
075790eb	111	struct ida ns_ida;
1c63dc66	112
f11bb3e2 CH	113	char name[12];
	114	char serial[20];
	115	char model[40];
	116	char firmware_rev[8];
76e3914a	117	u16 cntlid;
5fd4ce1b CH	118
	119	u32 ctrl_config;
	120
	121	u32 page_size;
f11bb3e2 CH	122	u32 max_hw_sectors;
f11bb3e2 CH	123	u32 stripe_size;
f11bb3e2	124	u16 oncs;
118472ab	125	u16 vid;
6bf25d16	126	atomic_t abort_limit;
f11bb3e2 CH	127	u8 event_limit;
f11bb3e2 CH	128	u8 vwc;
f3ca80fc	129	u32 vs;
07bfcd09	130	u32 sgls;
038bd4cb SG	131	u16 kas;
038bd4cb SG	132	unsigned int kato;
f3ca80fc	133	bool subsystem;
106198ed	134	unsigned long quirks;
5955be21	135	struct work_struct scan_work;
f866fc42	136	struct work_struct async_event_work;
038bd4cb	137	struct delayed_work ka_work;
07bfcd09 CH	138
	139	/* Fabrics only */
	140	u16 sqsize;
	141	u32 ioccsz;
	142	u32 iorcsz;
	143	u16 icdoff;
	144	u16 maxcmd;
	145	struct nvmf_ctrl_options *opts;
f11bb3e2 CH	146	};
	147
	148	/*
	149	* An NVM Express namespace is equivalent to a SCSI LUN
	150	*/
	151	struct nvme_ns {
	152	struct list_head list;
	153
1c63dc66	154	struct nvme_ctrl *ctrl;
f11bb3e2 CH	155	struct request_queue *queue;
	156	struct gendisk *disk;
	157	struct kref kref;
075790eb	158	int instance;
f11bb3e2	159
2b9b6e86 KB	160	u8 eui[8];
	161	u8 uuid[16];
	162
f11bb3e2 CH	163	unsigned ns_id;
	164	int lba_shift;
	165	u16 ms;
	166	bool ext;
	167	u8 pi_type;
ca064085	168	int type;
646017a6 KB	169	unsigned long flags;
	170
	171	#define NVME_NS_REMOVING 0
69d9a99c	172	#define NVME_NS_DEAD 1
646017a6	173
f11bb3e2 CH	174	u64 mode_select_num_blocks;
	175	u32 mode_select_block_len;
	176	};
	177
1c63dc66	178	struct nvme_ctrl_ops {
1a353d85	179	const char *name;
e439bb12	180	struct module *module;
07bfcd09	181	bool is_fabrics;
1c63dc66	182	int (reg_read32)(struct nvme_ctrl ctrl, u32 off, u32 *val);
5fd4ce1b	183	int (reg_write32)(struct nvme_ctrl ctrl, u32 off, u32 val);
7fd8930f	184	int (reg_read64)(struct nvme_ctrl ctrl, u32 off, u64 *val);
f3ca80fc	185	int (reset_ctrl)(struct nvme_ctrl ctrl);
1673f1f0	186	void (free_ctrl)(struct nvme_ctrl ctrl);
5955be21	187	void (post_scan)(struct nvme_ctrl ctrl);
f866fc42	188	void (submit_async_event)(struct nvme_ctrl ctrl, int aer_idx);
1a353d85 ML	189	int (delete_ctrl)(struct nvme_ctrl ctrl);
	190	const char (get_subsysnqn)(struct nvme_ctrl *ctrl);
	191	int (get_address)(struct nvme_ctrl ctrl, char *buf, int size);
f11bb3e2 CH	192	};
f11bb3e2 CH	193
1c63dc66 CH	194	static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
	195	{
	196	u32 val = 0;
	197
	198	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
	199	return false;
	200	return val & NVME_CSTS_RDY;
	201	}
	202
f3ca80fc CH	203	static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
	204	{
	205	if (!ctrl->subsystem)
	206	return -ENOTTY;
	207	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
	208	}
	209
f11bb3e2 CH	210	static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
	211	{
	212	return (sector >> (ns->lba_shift - 9));
	213	}
	214
58b45602 ML	215	static inline unsigned nvme_map_len(struct request *rq)
58b45602 ML	216	{
c2df40df	217	if (req_op(rq) == REQ_OP_DISCARD)
58b45602 ML	218	return sizeof(struct nvme_dsm_range);
	219	else
	220	return blk_rq_bytes(rq);
	221	}
	222
6904242d ML	223	static inline void nvme_cleanup_cmd(struct request *req)
6904242d ML	224	{
c2df40df	225	if (req_op(req) == REQ_OP_DISCARD)
6904242d ML	226	kfree(req->completion_data);
	227	}
	228
15a190f7 CH	229	static inline int nvme_error_status(u16 status)
	230	{
	231	switch (status & 0x7ff) {
	232	case NVME_SC_SUCCESS:
	233	return 0;
	234	case NVME_SC_CAP_EXCEEDED:
	235	return -ENOSPC;
	236	default:
	237	return -EIO;
	238	}
	239	}
	240
7688faa6 CH	241	static inline bool nvme_req_needs_retry(struct request *req, u16 status)
	242	{
	243	return !(status & NVME_SC_DNR \|\| blk_noretry_request(req)) &&
f80ec966 KB	244	(jiffies - req->start_time) < req->timeout &&
f80ec966 KB	245	req->retries < nvme_max_retries;
7688faa6 CH	246	}
7688faa6 CH	247
c55a2fd4	248	void nvme_cancel_request(struct request req, void data, bool reserved);
bb8d261e CH	249	bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
bb8d261e CH	250	enum nvme_ctrl_state new_state);
5fd4ce1b CH	251	int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	252	int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	253	int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
f3ca80fc CH	254	int nvme_init_ctrl(struct nvme_ctrl ctrl, struct device dev,
f3ca80fc CH	255	const struct nvme_ctrl_ops *ops, unsigned long quirks);
53029b04	256	void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
1673f1f0	257	void nvme_put_ctrl(struct nvme_ctrl *ctrl);
7fd8930f	258	int nvme_init_identify(struct nvme_ctrl *ctrl);
5bae7f73	259
5955be21	260	void nvme_queue_scan(struct nvme_ctrl *ctrl);
5bae7f73	261	void nvme_remove_namespaces(struct nvme_ctrl *ctrl);
1673f1f0	262
f866fc42 CH	263	#define NVME_NR_AERS 1
	264	void nvme_complete_async_event(struct nvme_ctrl *ctrl,
	265	struct nvme_completion *cqe);
	266	void nvme_queue_async_events(struct nvme_ctrl *ctrl);
	267
25646264 KB	268	void nvme_stop_queues(struct nvme_ctrl *ctrl);
25646264 KB	269	void nvme_start_queues(struct nvme_ctrl *ctrl);
69d9a99c	270	void nvme_kill_queues(struct nvme_ctrl *ctrl);
363c9aac	271
eb71f435	272	#define NVME_QID_ANY -1
4160982e	273	struct request nvme_alloc_request(struct request_queue q,
eb71f435	274	struct nvme_command *cmd, unsigned int flags, int qid);
7688faa6	275	void nvme_requeue_req(struct request *req);
8093f7ca ML	276	int nvme_setup_cmd(struct nvme_ns ns, struct request req,
8093f7ca ML	277	struct nvme_command *cmd);
f11bb3e2 CH	278	int nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
	279	void *buf, unsigned bufflen);
	280	int __nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
1cb3cce5	281	struct nvme_completion cqe, void buffer, unsigned bufflen,
eb71f435	282	unsigned timeout, int qid, int at_head, int flags);
4160982e CH	283	int nvme_submit_user_cmd(struct request_queue q, struct nvme_command cmd,
	284	void __user ubuffer, unsigned bufflen, u32 result,
	285	unsigned timeout);
0b7f1f26 KB	286	int __nvme_submit_user_cmd(struct request_queue q, struct nvme_command cmd,
	287	void __user *ubuffer, unsigned bufflen,
	288	void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
f11bb3e2	289	u32 *result, unsigned timeout);
1c63dc66 CH	290	int nvme_identify_ctrl(struct nvme_ctrl dev, struct nvme_id_ctrl *id);
1c63dc66 CH	291	int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
f11bb3e2	292	struct nvme_id_ns **id);
1c63dc66 CH	293	int nvme_get_log_page(struct nvme_ctrl dev, struct nvme_smart_log *log);
1c63dc66 CH	294	int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
f11bb3e2	295	dma_addr_t dma_addr, u32 *result);
1c63dc66	296	int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
f11bb3e2	297	dma_addr_t dma_addr, u32 *result);
9a0be7ab	298	int nvme_set_queue_count(struct nvme_ctrl ctrl, int count);
038bd4cb SG	299	void nvme_start_keep_alive(struct nvme_ctrl *ctrl);
038bd4cb SG	300	void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
f11bb3e2 CH	301
	302	struct sg_io_hdr;
	303
	304	int nvme_sg_io(struct nvme_ns ns, struct sg_io_hdr __user u_hdr);
	305	int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
	306	int nvme_sg_get_version_num(int __user *ip);
	307
c4699e70	308	#ifdef CONFIG_NVM
ca064085 MB	309	int nvme_nvm_ns_supported(struct nvme_ns ns, struct nvme_id_ns id);
	310	int nvme_nvm_register(struct request_queue q, char disk_name);
	311	void nvme_nvm_unregister(struct request_queue q, char disk_name);
c4699e70 KB	312	#else
	313	static inline int nvme_nvm_register(struct request_queue q, char disk_name)
	314	{
	315	return 0;
	316	}
	317
	318	static inline void nvme_nvm_unregister(struct request_queue q, char disk_name) {};
	319
	320	static inline int nvme_nvm_ns_supported(struct nvme_ns ns, struct nvme_id_ns id)
	321	{
	322	return 0;
	323	}
	324	#endif /* CONFIG_NVM */
ca064085	325
5bae7f73 CH	326	int __init nvme_core_init(void);
	327	void nvme_core_exit(void);
	328
f11bb3e2	329	#endif /* _NVME_H */