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bc50ad75 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
f11bb3e2 CH |
2 | /* |
3 | * Copyright (c) 2011-2014, Intel Corporation. | |
f11bb3e2 CH |
4 | */ |
5 | ||
6 | #ifndef _NVME_H | |
7 | #define _NVME_H | |
8 | ||
9 | #include <linux/nvme.h> | |
a6a5149b | 10 | #include <linux/cdev.h> |
f11bb3e2 CH |
11 | #include <linux/pci.h> |
12 | #include <linux/kref.h> | |
13 | #include <linux/blk-mq.h> | |
b0b4e09c | 14 | #include <linux/lightnvm.h> |
a98e58e5 | 15 | #include <linux/sed-opal.h> |
b9e03857 | 16 | #include <linux/fault-inject.h> |
978628ec | 17 | #include <linux/rcupdate.h> |
c1ac9a4b | 18 | #include <linux/wait.h> |
f11bb3e2 | 19 | |
35fe0d12 HR |
20 | #include <trace/events/block.h> |
21 | ||
8ae4e447 | 22 | extern unsigned int nvme_io_timeout; |
f11bb3e2 CH |
23 | #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) |
24 | ||
8ae4e447 | 25 | extern unsigned int admin_timeout; |
21d34711 CH |
26 | #define ADMIN_TIMEOUT (admin_timeout * HZ) |
27 | ||
038bd4cb SG |
28 | #define NVME_DEFAULT_KATO 5 |
29 | #define NVME_KATO_GRACE 10 | |
30 | ||
38e18002 IR |
31 | #ifdef CONFIG_ARCH_NO_SG_CHAIN |
32 | #define NVME_INLINE_SG_CNT 0 | |
33 | #else | |
34 | #define NVME_INLINE_SG_CNT 2 | |
35 | #endif | |
36 | ||
9a6327d2 | 37 | extern struct workqueue_struct *nvme_wq; |
b227c59b RS |
38 | extern struct workqueue_struct *nvme_reset_wq; |
39 | extern struct workqueue_struct *nvme_delete_wq; | |
9a6327d2 | 40 | |
ca064085 MB |
41 | enum { |
42 | NVME_NS_LBA = 0, | |
43 | NVME_NS_LIGHTNVM = 1, | |
44 | }; | |
45 | ||
f11bb3e2 | 46 | /* |
106198ed CH |
47 | * List of workarounds for devices that required behavior not specified in |
48 | * the standard. | |
f11bb3e2 | 49 | */ |
106198ed CH |
50 | enum nvme_quirks { |
51 | /* | |
52 | * Prefers I/O aligned to a stripe size specified in a vendor | |
53 | * specific Identify field. | |
54 | */ | |
55 | NVME_QUIRK_STRIPE_SIZE = (1 << 0), | |
540c801c KB |
56 | |
57 | /* | |
58 | * The controller doesn't handle Identify value others than 0 or 1 | |
59 | * correctly. | |
60 | */ | |
61 | NVME_QUIRK_IDENTIFY_CNS = (1 << 1), | |
08095e70 KB |
62 | |
63 | /* | |
e850fd16 CH |
64 | * The controller deterministically returns O's on reads to |
65 | * logical blocks that deallocate was called on. | |
08095e70 | 66 | */ |
e850fd16 | 67 | NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2), |
54adc010 GP |
68 | |
69 | /* | |
70 | * The controller needs a delay before starts checking the device | |
71 | * readiness, which is done by reading the NVME_CSTS_RDY bit. | |
72 | */ | |
73 | NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), | |
c5552fde AL |
74 | |
75 | /* | |
76 | * APST should not be used. | |
77 | */ | |
78 | NVME_QUIRK_NO_APST = (1 << 4), | |
ff5350a8 AL |
79 | |
80 | /* | |
81 | * The deepest sleep state should not be used. | |
82 | */ | |
83 | NVME_QUIRK_NO_DEEPEST_PS = (1 << 5), | |
608cc4b1 CH |
84 | |
85 | /* | |
86 | * Supports the LighNVM command set if indicated in vs[1]. | |
87 | */ | |
88 | NVME_QUIRK_LIGHTNVM = (1 << 6), | |
9abd68ef JA |
89 | |
90 | /* | |
91 | * Set MEDIUM priority on SQ creation | |
92 | */ | |
93 | NVME_QUIRK_MEDIUM_PRIO_SQ = (1 << 7), | |
6299358d JD |
94 | |
95 | /* | |
96 | * Ignore device provided subnqn. | |
97 | */ | |
98 | NVME_QUIRK_IGNORE_DEV_SUBNQN = (1 << 8), | |
7b210e4e CH |
99 | |
100 | /* | |
101 | * Broken Write Zeroes. | |
102 | */ | |
103 | NVME_QUIRK_DISABLE_WRITE_ZEROES = (1 << 9), | |
cb32de1b ML |
104 | |
105 | /* | |
106 | * Force simple suspend/resume path. | |
107 | */ | |
108 | NVME_QUIRK_SIMPLE_SUSPEND = (1 << 10), | |
7ad67ca5 | 109 | |
66341331 BH |
110 | /* |
111 | * Use only one interrupt vector for all queues | |
112 | */ | |
7ad67ca5 | 113 | NVME_QUIRK_SINGLE_VECTOR = (1 << 11), |
66341331 BH |
114 | |
115 | /* | |
116 | * Use non-standard 128 bytes SQEs. | |
117 | */ | |
7ad67ca5 | 118 | NVME_QUIRK_128_BYTES_SQES = (1 << 12), |
d38e9f04 BH |
119 | |
120 | /* | |
121 | * Prevent tag overlap between queues | |
122 | */ | |
7ad67ca5 | 123 | NVME_QUIRK_SHARED_TAGS = (1 << 13), |
6c6aa2f2 AM |
124 | |
125 | /* | |
126 | * Don't change the value of the temperature threshold feature | |
127 | */ | |
128 | NVME_QUIRK_NO_TEMP_THRESH_CHANGE = (1 << 14), | |
106198ed CH |
129 | }; |
130 | ||
d49187e9 CH |
131 | /* |
132 | * Common request structure for NVMe passthrough. All drivers must have | |
133 | * this structure as the first member of their request-private data. | |
134 | */ | |
135 | struct nvme_request { | |
136 | struct nvme_command *cmd; | |
137 | union nvme_result result; | |
44e44b29 | 138 | u8 retries; |
27fa9bc5 CH |
139 | u8 flags; |
140 | u16 status; | |
59e29ce6 | 141 | struct nvme_ctrl *ctrl; |
27fa9bc5 CH |
142 | }; |
143 | ||
32acab31 CH |
144 | /* |
145 | * Mark a bio as coming in through the mpath node. | |
146 | */ | |
147 | #define REQ_NVME_MPATH REQ_DRV | |
148 | ||
27fa9bc5 CH |
149 | enum { |
150 | NVME_REQ_CANCELLED = (1 << 0), | |
bb06ec31 | 151 | NVME_REQ_USERCMD = (1 << 1), |
d49187e9 CH |
152 | }; |
153 | ||
154 | static inline struct nvme_request *nvme_req(struct request *req) | |
155 | { | |
156 | return blk_mq_rq_to_pdu(req); | |
157 | } | |
158 | ||
5d87eb94 KB |
159 | static inline u16 nvme_req_qid(struct request *req) |
160 | { | |
161 | if (!req->rq_disk) | |
162 | return 0; | |
163 | return blk_mq_unique_tag_to_hwq(blk_mq_unique_tag(req)) + 1; | |
164 | } | |
165 | ||
54adc010 GP |
166 | /* The below value is the specific amount of delay needed before checking |
167 | * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the | |
168 | * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was | |
169 | * found empirically. | |
170 | */ | |
8c97eecc | 171 | #define NVME_QUIRK_DELAY_AMOUNT 2300 |
54adc010 | 172 | |
bb8d261e CH |
173 | enum nvme_ctrl_state { |
174 | NVME_CTRL_NEW, | |
175 | NVME_CTRL_LIVE, | |
176 | NVME_CTRL_RESETTING, | |
ad6a0a52 | 177 | NVME_CTRL_CONNECTING, |
bb8d261e | 178 | NVME_CTRL_DELETING, |
0ff9d4e1 | 179 | NVME_CTRL_DEAD, |
bb8d261e CH |
180 | }; |
181 | ||
a3646451 AM |
182 | struct nvme_fault_inject { |
183 | #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS | |
184 | struct fault_attr attr; | |
185 | struct dentry *parent; | |
186 | bool dont_retry; /* DNR, do not retry */ | |
187 | u16 status; /* status code */ | |
188 | #endif | |
189 | }; | |
190 | ||
1c63dc66 | 191 | struct nvme_ctrl { |
6e3ca03e | 192 | bool comp_seen; |
bb8d261e | 193 | enum nvme_ctrl_state state; |
bd4da3ab | 194 | bool identified; |
bb8d261e | 195 | spinlock_t lock; |
e7ad43c3 | 196 | struct mutex scan_lock; |
1c63dc66 | 197 | const struct nvme_ctrl_ops *ops; |
f11bb3e2 | 198 | struct request_queue *admin_q; |
07bfcd09 | 199 | struct request_queue *connect_q; |
e7832cb4 | 200 | struct request_queue *fabrics_q; |
f11bb3e2 | 201 | struct device *dev; |
f11bb3e2 | 202 | int instance; |
103e515e | 203 | int numa_node; |
5bae7f73 | 204 | struct blk_mq_tag_set *tagset; |
34b6c231 | 205 | struct blk_mq_tag_set *admin_tagset; |
f11bb3e2 | 206 | struct list_head namespaces; |
765cc031 | 207 | struct rw_semaphore namespaces_rwsem; |
d22524a4 | 208 | struct device ctrl_device; |
5bae7f73 | 209 | struct device *device; /* char device */ |
a6a5149b | 210 | struct cdev cdev; |
d86c4d8e | 211 | struct work_struct reset_work; |
c5017e85 | 212 | struct work_struct delete_work; |
c1ac9a4b | 213 | wait_queue_head_t state_wq; |
1c63dc66 | 214 | |
ab9e00cc CH |
215 | struct nvme_subsystem *subsys; |
216 | struct list_head subsys_entry; | |
217 | ||
4f1244c8 | 218 | struct opal_dev *opal_dev; |
a98e58e5 | 219 | |
f11bb3e2 | 220 | char name[12]; |
76e3914a | 221 | u16 cntlid; |
5fd4ce1b CH |
222 | |
223 | u32 ctrl_config; | |
b6dccf7f | 224 | u16 mtfa; |
d858e5f0 | 225 | u32 queue_count; |
5fd4ce1b | 226 | |
20d0dfe6 | 227 | u64 cap; |
5fd4ce1b | 228 | u32 page_size; |
f11bb3e2 | 229 | u32 max_hw_sectors; |
943e942e | 230 | u32 max_segments; |
49cd84b6 | 231 | u16 crdt[3]; |
f11bb3e2 | 232 | u16 oncs; |
8a9ae523 | 233 | u16 oacs; |
f5d11840 JA |
234 | u16 nssa; |
235 | u16 nr_streams; | |
f968688f | 236 | u16 sqsize; |
0d0b660f | 237 | u32 max_namespaces; |
6bf25d16 | 238 | atomic_t abort_limit; |
f11bb3e2 | 239 | u8 vwc; |
f3ca80fc | 240 | u32 vs; |
07bfcd09 | 241 | u32 sgls; |
038bd4cb | 242 | u16 kas; |
c5552fde AL |
243 | u8 npss; |
244 | u8 apsta; | |
400b6a7b GR |
245 | u16 wctemp; |
246 | u16 cctemp; | |
c0561f82 | 247 | u32 oaes; |
e3d7874d | 248 | u32 aen_result; |
3e53ba38 | 249 | u32 ctratt; |
07fbd32a | 250 | unsigned int shutdown_timeout; |
038bd4cb | 251 | unsigned int kato; |
f3ca80fc | 252 | bool subsystem; |
106198ed | 253 | unsigned long quirks; |
c5552fde | 254 | struct nvme_id_power_state psd[32]; |
84fef62d | 255 | struct nvme_effects_log *effects; |
5955be21 | 256 | struct work_struct scan_work; |
f866fc42 | 257 | struct work_struct async_event_work; |
038bd4cb | 258 | struct delayed_work ka_work; |
0a34e466 | 259 | struct nvme_command ka_cmd; |
b6dccf7f | 260 | struct work_struct fw_act_work; |
30d90964 | 261 | unsigned long events; |
ce151813 | 262 | bool created; |
07bfcd09 | 263 | |
0d0b660f CH |
264 | #ifdef CONFIG_NVME_MULTIPATH |
265 | /* asymmetric namespace access: */ | |
266 | u8 anacap; | |
267 | u8 anatt; | |
268 | u32 anagrpmax; | |
269 | u32 nanagrpid; | |
270 | struct mutex ana_lock; | |
271 | struct nvme_ana_rsp_hdr *ana_log_buf; | |
272 | size_t ana_log_size; | |
273 | struct timer_list anatt_timer; | |
274 | struct work_struct ana_work; | |
275 | #endif | |
276 | ||
c5552fde AL |
277 | /* Power saving configuration */ |
278 | u64 ps_max_latency_us; | |
76a5af84 | 279 | bool apst_enabled; |
c5552fde | 280 | |
044a9df1 | 281 | /* PCIe only: */ |
fe6d53c9 CH |
282 | u32 hmpre; |
283 | u32 hmmin; | |
044a9df1 CH |
284 | u32 hmminds; |
285 | u16 hmmaxd; | |
fe6d53c9 | 286 | |
07bfcd09 | 287 | /* Fabrics only */ |
07bfcd09 CH |
288 | u32 ioccsz; |
289 | u32 iorcsz; | |
290 | u16 icdoff; | |
291 | u16 maxcmd; | |
fdf9dfa8 | 292 | int nr_reconnects; |
07bfcd09 | 293 | struct nvmf_ctrl_options *opts; |
cb5b7262 JA |
294 | |
295 | struct page *discard_page; | |
296 | unsigned long discard_page_busy; | |
f79d5fda AM |
297 | |
298 | struct nvme_fault_inject fault_inject; | |
f11bb3e2 CH |
299 | }; |
300 | ||
75c10e73 HR |
301 | enum nvme_iopolicy { |
302 | NVME_IOPOLICY_NUMA, | |
303 | NVME_IOPOLICY_RR, | |
304 | }; | |
305 | ||
ab9e00cc CH |
306 | struct nvme_subsystem { |
307 | int instance; | |
308 | struct device dev; | |
309 | /* | |
310 | * Because we unregister the device on the last put we need | |
311 | * a separate refcount. | |
312 | */ | |
313 | struct kref ref; | |
314 | struct list_head entry; | |
315 | struct mutex lock; | |
316 | struct list_head ctrls; | |
ed754e5d | 317 | struct list_head nsheads; |
ab9e00cc CH |
318 | char subnqn[NVMF_NQN_SIZE]; |
319 | char serial[20]; | |
320 | char model[40]; | |
321 | char firmware_rev[8]; | |
322 | u8 cmic; | |
323 | u16 vendor_id; | |
81adb863 | 324 | u16 awupf; /* 0's based awupf value. */ |
ed754e5d | 325 | struct ida ns_ida; |
75c10e73 HR |
326 | #ifdef CONFIG_NVME_MULTIPATH |
327 | enum nvme_iopolicy iopolicy; | |
328 | #endif | |
ab9e00cc CH |
329 | }; |
330 | ||
002fab04 CH |
331 | /* |
332 | * Container structure for uniqueue namespace identifiers. | |
333 | */ | |
334 | struct nvme_ns_ids { | |
335 | u8 eui64[8]; | |
336 | u8 nguid[16]; | |
337 | uuid_t uuid; | |
338 | }; | |
339 | ||
ed754e5d CH |
340 | /* |
341 | * Anchor structure for namespaces. There is one for each namespace in a | |
342 | * NVMe subsystem that any of our controllers can see, and the namespace | |
343 | * structure for each controller is chained of it. For private namespaces | |
344 | * there is a 1:1 relation to our namespace structures, that is ->list | |
345 | * only ever has a single entry for private namespaces. | |
346 | */ | |
347 | struct nvme_ns_head { | |
348 | struct list_head list; | |
349 | struct srcu_struct srcu; | |
350 | struct nvme_subsystem *subsys; | |
351 | unsigned ns_id; | |
352 | struct nvme_ns_ids ids; | |
353 | struct list_head entry; | |
354 | struct kref ref; | |
0c284db7 | 355 | bool shared; |
ed754e5d | 356 | int instance; |
f3334447 CH |
357 | #ifdef CONFIG_NVME_MULTIPATH |
358 | struct gendisk *disk; | |
359 | struct bio_list requeue_list; | |
360 | spinlock_t requeue_lock; | |
361 | struct work_struct requeue_work; | |
362 | struct mutex lock; | |
363 | struct nvme_ns __rcu *current_path[]; | |
364 | #endif | |
ed754e5d CH |
365 | }; |
366 | ||
ffc89b1d MG |
367 | enum nvme_ns_features { |
368 | NVME_NS_EXT_LBAS = 1 << 0, /* support extended LBA format */ | |
b29f8485 | 369 | NVME_NS_METADATA_SUPPORTED = 1 << 1, /* support getting generated md */ |
ffc89b1d MG |
370 | }; |
371 | ||
f11bb3e2 CH |
372 | struct nvme_ns { |
373 | struct list_head list; | |
374 | ||
1c63dc66 | 375 | struct nvme_ctrl *ctrl; |
f11bb3e2 CH |
376 | struct request_queue *queue; |
377 | struct gendisk *disk; | |
0d0b660f CH |
378 | #ifdef CONFIG_NVME_MULTIPATH |
379 | enum nvme_ana_state ana_state; | |
380 | u32 ana_grpid; | |
381 | #endif | |
ed754e5d | 382 | struct list_head siblings; |
b0b4e09c | 383 | struct nvm_dev *ndev; |
f11bb3e2 | 384 | struct kref kref; |
ed754e5d | 385 | struct nvme_ns_head *head; |
f11bb3e2 | 386 | |
f11bb3e2 CH |
387 | int lba_shift; |
388 | u16 ms; | |
f5d11840 JA |
389 | u16 sgs; |
390 | u32 sws; | |
f11bb3e2 | 391 | u8 pi_type; |
ffc89b1d | 392 | unsigned long features; |
646017a6 | 393 | unsigned long flags; |
0d0b660f CH |
394 | #define NVME_NS_REMOVING 0 |
395 | #define NVME_NS_DEAD 1 | |
396 | #define NVME_NS_ANA_PENDING 2 | |
b9e03857 | 397 | |
b9e03857 | 398 | struct nvme_fault_inject fault_inject; |
b9e03857 | 399 | |
f11bb3e2 CH |
400 | }; |
401 | ||
1c63dc66 | 402 | struct nvme_ctrl_ops { |
1a353d85 | 403 | const char *name; |
e439bb12 | 404 | struct module *module; |
d3d5b87d CH |
405 | unsigned int flags; |
406 | #define NVME_F_FABRICS (1 << 0) | |
c81bfba9 | 407 | #define NVME_F_METADATA_SUPPORTED (1 << 1) |
e0596ab2 | 408 | #define NVME_F_PCI_P2PDMA (1 << 2) |
1c63dc66 | 409 | int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); |
5fd4ce1b | 410 | int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); |
7fd8930f | 411 | int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); |
1673f1f0 | 412 | void (*free_ctrl)(struct nvme_ctrl *ctrl); |
ad22c355 | 413 | void (*submit_async_event)(struct nvme_ctrl *ctrl); |
c5017e85 | 414 | void (*delete_ctrl)(struct nvme_ctrl *ctrl); |
1a353d85 | 415 | int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); |
f11bb3e2 CH |
416 | }; |
417 | ||
b9e03857 | 418 | #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS |
a3646451 AM |
419 | void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj, |
420 | const char *dev_name); | |
421 | void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inject); | |
b9e03857 TT |
422 | void nvme_should_fail(struct request *req); |
423 | #else | |
a3646451 AM |
424 | static inline void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj, |
425 | const char *dev_name) | |
426 | { | |
427 | } | |
428 | static inline void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inj) | |
429 | { | |
430 | } | |
b9e03857 TT |
431 | static inline void nvme_should_fail(struct request *req) {} |
432 | #endif | |
433 | ||
f3ca80fc CH |
434 | static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) |
435 | { | |
436 | if (!ctrl->subsystem) | |
437 | return -ENOTTY; | |
438 | return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); | |
439 | } | |
440 | ||
314d48dd DLM |
441 | /* |
442 | * Convert a 512B sector number to a device logical block number. | |
443 | */ | |
444 | static inline u64 nvme_sect_to_lba(struct nvme_ns *ns, sector_t sector) | |
f11bb3e2 | 445 | { |
314d48dd | 446 | return sector >> (ns->lba_shift - SECTOR_SHIFT); |
f11bb3e2 CH |
447 | } |
448 | ||
e08f2ae8 DLM |
449 | /* |
450 | * Convert a device logical block number to a 512B sector number. | |
451 | */ | |
452 | static inline sector_t nvme_lba_to_sect(struct nvme_ns *ns, u64 lba) | |
f11bb3e2 | 453 | { |
e08f2ae8 | 454 | return lba << (ns->lba_shift - SECTOR_SHIFT); |
f11bb3e2 CH |
455 | } |
456 | ||
71fb90eb KB |
457 | /* |
458 | * Convert byte length to nvme's 0-based num dwords | |
459 | */ | |
460 | static inline u32 nvme_bytes_to_numd(size_t len) | |
461 | { | |
462 | return (len >> 2) - 1; | |
463 | } | |
464 | ||
27fa9bc5 CH |
465 | static inline void nvme_end_request(struct request *req, __le16 status, |
466 | union nvme_result result) | |
15a190f7 | 467 | { |
27fa9bc5 | 468 | struct nvme_request *rq = nvme_req(req); |
15a190f7 | 469 | |
27fa9bc5 CH |
470 | rq->status = le16_to_cpu(status) >> 1; |
471 | rq->result = result; | |
b9e03857 TT |
472 | /* inject error when permitted by fault injection framework */ |
473 | nvme_should_fail(req); | |
08e0029a | 474 | blk_mq_complete_request(req); |
7688faa6 CH |
475 | } |
476 | ||
d22524a4 CH |
477 | static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl) |
478 | { | |
479 | get_device(ctrl->device); | |
480 | } | |
481 | ||
482 | static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl) | |
483 | { | |
484 | put_device(ctrl->device); | |
485 | } | |
486 | ||
58a8df67 IR |
487 | static inline bool nvme_is_aen_req(u16 qid, __u16 command_id) |
488 | { | |
489 | return !qid && command_id >= NVME_AQ_BLK_MQ_DEPTH; | |
490 | } | |
491 | ||
77f02a7a | 492 | void nvme_complete_rq(struct request *req); |
7baa8572 | 493 | bool nvme_cancel_request(struct request *req, void *data, bool reserved); |
bb8d261e CH |
494 | bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, |
495 | enum nvme_ctrl_state new_state); | |
c1ac9a4b | 496 | bool nvme_wait_reset(struct nvme_ctrl *ctrl); |
b5b05048 | 497 | int nvme_disable_ctrl(struct nvme_ctrl *ctrl); |
c0f2f45b | 498 | int nvme_enable_ctrl(struct nvme_ctrl *ctrl); |
5fd4ce1b | 499 | int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl); |
f3ca80fc CH |
500 | int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, |
501 | const struct nvme_ctrl_ops *ops, unsigned long quirks); | |
53029b04 | 502 | void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); |
d09f2b45 SG |
503 | void nvme_start_ctrl(struct nvme_ctrl *ctrl); |
504 | void nvme_stop_ctrl(struct nvme_ctrl *ctrl); | |
7fd8930f | 505 | int nvme_init_identify(struct nvme_ctrl *ctrl); |
5bae7f73 | 506 | |
5bae7f73 | 507 | void nvme_remove_namespaces(struct nvme_ctrl *ctrl); |
1673f1f0 | 508 | |
4f1244c8 CH |
509 | int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len, |
510 | bool send); | |
a98e58e5 | 511 | |
7bf58533 | 512 | void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, |
287a63eb | 513 | volatile union nvme_result *res); |
f866fc42 | 514 | |
25646264 KB |
515 | void nvme_stop_queues(struct nvme_ctrl *ctrl); |
516 | void nvme_start_queues(struct nvme_ctrl *ctrl); | |
69d9a99c | 517 | void nvme_kill_queues(struct nvme_ctrl *ctrl); |
d6135c3a | 518 | void nvme_sync_queues(struct nvme_ctrl *ctrl); |
302ad8cc KB |
519 | void nvme_unfreeze(struct nvme_ctrl *ctrl); |
520 | void nvme_wait_freeze(struct nvme_ctrl *ctrl); | |
521 | void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout); | |
522 | void nvme_start_freeze(struct nvme_ctrl *ctrl); | |
363c9aac | 523 | |
eb71f435 | 524 | #define NVME_QID_ANY -1 |
4160982e | 525 | struct request *nvme_alloc_request(struct request_queue *q, |
9a95e4ef | 526 | struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid); |
f7f1fc36 | 527 | void nvme_cleanup_cmd(struct request *req); |
fc17b653 | 528 | blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req, |
8093f7ca | 529 | struct nvme_command *cmd); |
f11bb3e2 CH |
530 | int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
531 | void *buf, unsigned bufflen); | |
532 | int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, | |
d49187e9 | 533 | union nvme_result *result, void *buffer, unsigned bufflen, |
9a95e4ef | 534 | unsigned timeout, int qid, int at_head, |
6287b51c | 535 | blk_mq_req_flags_t flags, bool poll); |
1a87ee65 KB |
536 | int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid, |
537 | unsigned int dword11, void *buffer, size_t buflen, | |
538 | u32 *result); | |
539 | int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid, | |
540 | unsigned int dword11, void *buffer, size_t buflen, | |
541 | u32 *result); | |
9a0be7ab | 542 | int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); |
038bd4cb | 543 | void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); |
d86c4d8e | 544 | int nvme_reset_ctrl(struct nvme_ctrl *ctrl); |
79c48ccf | 545 | int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl); |
c1ac9a4b | 546 | int nvme_try_sched_reset(struct nvme_ctrl *ctrl); |
c5017e85 | 547 | int nvme_delete_ctrl(struct nvme_ctrl *ctrl); |
f11bb3e2 | 548 | |
0e98719b CH |
549 | int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, |
550 | void *log, size_t size, u64 offset); | |
d558fb51 | 551 | |
33b14f67 | 552 | extern const struct attribute_group *nvme_ns_id_attr_groups[]; |
32acab31 CH |
553 | extern const struct block_device_operations nvme_ns_head_ops; |
554 | ||
555 | #ifdef CONFIG_NVME_MULTIPATH | |
66b20ac0 MR |
556 | static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) |
557 | { | |
558 | return ctrl->ana_log_buf != NULL; | |
559 | } | |
560 | ||
b9156dae SG |
561 | void nvme_mpath_unfreeze(struct nvme_subsystem *subsys); |
562 | void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys); | |
563 | void nvme_mpath_start_freeze(struct nvme_subsystem *subsys); | |
a785dbcc KB |
564 | void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns, |
565 | struct nvme_ctrl *ctrl, int *flags); | |
764e9332 | 566 | bool nvme_failover_req(struct request *req); |
32acab31 CH |
567 | void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl); |
568 | int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,struct nvme_ns_head *head); | |
0d0b660f | 569 | void nvme_mpath_add_disk(struct nvme_ns *ns, struct nvme_id_ns *id); |
32acab31 | 570 | void nvme_mpath_remove_disk(struct nvme_ns_head *head); |
0d0b660f CH |
571 | int nvme_mpath_init(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id); |
572 | void nvme_mpath_uninit(struct nvme_ctrl *ctrl); | |
573 | void nvme_mpath_stop(struct nvme_ctrl *ctrl); | |
0157ec8d SG |
574 | bool nvme_mpath_clear_current_path(struct nvme_ns *ns); |
575 | void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl); | |
32acab31 | 576 | struct nvme_ns *nvme_find_path(struct nvme_ns_head *head); |
479a322f SG |
577 | |
578 | static inline void nvme_mpath_check_last_path(struct nvme_ns *ns) | |
579 | { | |
580 | struct nvme_ns_head *head = ns->head; | |
581 | ||
582 | if (head->disk && list_empty(&head->list)) | |
583 | kblockd_schedule_work(&head->requeue_work); | |
584 | } | |
585 | ||
35fe0d12 HR |
586 | static inline void nvme_trace_bio_complete(struct request *req, |
587 | blk_status_t status) | |
588 | { | |
589 | struct nvme_ns *ns = req->q->queuedata; | |
590 | ||
591 | if (req->cmd_flags & REQ_NVME_MPATH) | |
592 | trace_block_bio_complete(ns->head->disk->queue, | |
593 | req->bio, status); | |
594 | } | |
595 | ||
0d0b660f CH |
596 | extern struct device_attribute dev_attr_ana_grpid; |
597 | extern struct device_attribute dev_attr_ana_state; | |
75c10e73 | 598 | extern struct device_attribute subsys_attr_iopolicy; |
0d0b660f | 599 | |
32acab31 | 600 | #else |
0d0b660f CH |
601 | static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) |
602 | { | |
603 | return false; | |
604 | } | |
a785dbcc KB |
605 | /* |
606 | * Without the multipath code enabled, multiple controller per subsystems are | |
607 | * visible as devices and thus we cannot use the subsystem instance. | |
608 | */ | |
609 | static inline void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns, | |
610 | struct nvme_ctrl *ctrl, int *flags) | |
611 | { | |
612 | sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->head->instance); | |
613 | } | |
614 | ||
764e9332 | 615 | static inline bool nvme_failover_req(struct request *req) |
32acab31 | 616 | { |
764e9332 | 617 | return false; |
32acab31 | 618 | } |
32acab31 CH |
619 | static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl) |
620 | { | |
621 | } | |
622 | static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl, | |
623 | struct nvme_ns_head *head) | |
624 | { | |
625 | return 0; | |
626 | } | |
0d0b660f CH |
627 | static inline void nvme_mpath_add_disk(struct nvme_ns *ns, |
628 | struct nvme_id_ns *id) | |
32acab31 CH |
629 | { |
630 | } | |
631 | static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head) | |
632 | { | |
633 | } | |
0157ec8d SG |
634 | static inline bool nvme_mpath_clear_current_path(struct nvme_ns *ns) |
635 | { | |
636 | return false; | |
637 | } | |
638 | static inline void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl) | |
479a322f SG |
639 | { |
640 | } | |
641 | static inline void nvme_mpath_check_last_path(struct nvme_ns *ns) | |
32acab31 CH |
642 | { |
643 | } | |
35fe0d12 HR |
644 | static inline void nvme_trace_bio_complete(struct request *req, |
645 | blk_status_t status) | |
646 | { | |
647 | } | |
0d0b660f CH |
648 | static inline int nvme_mpath_init(struct nvme_ctrl *ctrl, |
649 | struct nvme_id_ctrl *id) | |
650 | { | |
14a1336e CH |
651 | if (ctrl->subsys->cmic & (1 << 3)) |
652 | dev_warn(ctrl->device, | |
653 | "Please enable CONFIG_NVME_MULTIPATH for full support of multi-port devices.\n"); | |
0d0b660f CH |
654 | return 0; |
655 | } | |
656 | static inline void nvme_mpath_uninit(struct nvme_ctrl *ctrl) | |
657 | { | |
658 | } | |
659 | static inline void nvme_mpath_stop(struct nvme_ctrl *ctrl) | |
660 | { | |
661 | } | |
b9156dae SG |
662 | static inline void nvme_mpath_unfreeze(struct nvme_subsystem *subsys) |
663 | { | |
664 | } | |
665 | static inline void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys) | |
666 | { | |
667 | } | |
668 | static inline void nvme_mpath_start_freeze(struct nvme_subsystem *subsys) | |
669 | { | |
670 | } | |
32acab31 CH |
671 | #endif /* CONFIG_NVME_MULTIPATH */ |
672 | ||
c4699e70 | 673 | #ifdef CONFIG_NVM |
3dc87dd0 | 674 | int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node); |
b0b4e09c | 675 | void nvme_nvm_unregister(struct nvme_ns *ns); |
33b14f67 | 676 | extern const struct attribute_group nvme_nvm_attr_group; |
84d4add7 | 677 | int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg); |
c4699e70 | 678 | #else |
b0b4e09c | 679 | static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, |
3dc87dd0 | 680 | int node) |
c4699e70 KB |
681 | { |
682 | return 0; | |
683 | } | |
684 | ||
b0b4e09c | 685 | static inline void nvme_nvm_unregister(struct nvme_ns *ns) {}; |
84d4add7 MB |
686 | static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, |
687 | unsigned long arg) | |
688 | { | |
689 | return -ENOTTY; | |
690 | } | |
3dc87dd0 MB |
691 | #endif /* CONFIG_NVM */ |
692 | ||
40267efd SL |
693 | static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev) |
694 | { | |
695 | return dev_to_disk(dev)->private_data; | |
696 | } | |
ca064085 | 697 | |
400b6a7b GR |
698 | #ifdef CONFIG_NVME_HWMON |
699 | void nvme_hwmon_init(struct nvme_ctrl *ctrl); | |
700 | #else | |
701 | static inline void nvme_hwmon_init(struct nvme_ctrl *ctrl) { } | |
702 | #endif | |
703 | ||
f11bb3e2 | 704 | #endif /* _NVME_H */ |