[mirror_ubuntu-bionic-kernel.git] / drivers / nvme / host / nvme.h

/*
 * Copyright (c) 2011-2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef _NVME_H
#define _NVME_H

#include <linux/nvme.h>
#include <linux/pci.h>
#include <linux/kref.h>
#include <linux/blk-mq.h>
#include <linux/lightnvm.h>
#include <linux/sed-opal.h>

extern unsigned char nvme_io_timeout;
#define NVME_IO_TIMEOUT	(nvme_io_timeout * HZ)

extern unsigned char admin_timeout;
#define ADMIN_TIMEOUT	(admin_timeout * HZ)

extern unsigned char shutdown_timeout;
#define SHUTDOWN_TIMEOUT	(shutdown_timeout * HZ)

#define NVME_DEFAULT_KATO	5
#define NVME_KATO_GRACE		10

enum {
	NVME_NS_LBA		= 0,
	NVME_NS_LIGHTNVM	= 1,
};

/*
 * List of workarounds for devices that required behavior not specified in
 * the standard.
 */
enum nvme_quirks {
	/*
	 * Prefers I/O aligned to a stripe size specified in a vendor
	 * specific Identify field.
	 */
	NVME_QUIRK_STRIPE_SIZE			= (1 << 0),

	/*
	 * The controller doesn't handle Identify value others than 0 or 1
	 * correctly.
	 */
	NVME_QUIRK_IDENTIFY_CNS			= (1 << 1),

	/*
	 * The controller deterministically returns O's on reads to
	 * logical blocks that deallocate was called on.
	 */
	NVME_QUIRK_DEALLOCATE_ZEROES		= (1 << 2),

	/*
	 * The controller needs a delay before starts checking the device
	 * readiness, which is done by reading the NVME_CSTS_RDY bit.
	 */
	NVME_QUIRK_DELAY_BEFORE_CHK_RDY		= (1 << 3),

	/*
	 * APST should not be used.
	 */
	NVME_QUIRK_NO_APST			= (1 << 4),

	/*
	 * The deepest sleep state should not be used.
	 */
	NVME_QUIRK_NO_DEEPEST_PS		= (1 << 5),
};

/*
 * Common request structure for NVMe passthrough.  All drivers must have
 * this structure as the first member of their request-private data.
 */
struct nvme_request {
	struct nvme_command	*cmd;
	union nvme_result	result;
	u8			retries;
	u8			flags;
	u16			status;
};

enum {
	NVME_REQ_CANCELLED		= (1 << 0),
};

static inline struct nvme_request *nvme_req(struct request *req)
{
	return blk_mq_rq_to_pdu(req);
}

/* The below value is the specific amount of delay needed before checking
 * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
 * found empirically.
 */
#define NVME_QUIRK_DELAY_AMOUNT		2000

enum nvme_ctrl_state {
	NVME_CTRL_NEW,
	NVME_CTRL_LIVE,
	NVME_CTRL_RESETTING,
	NVME_CTRL_RECONNECTING,
	NVME_CTRL_DELETING,
	NVME_CTRL_DEAD,
};

struct nvme_ctrl {
	enum nvme_ctrl_state state;
	bool identified;
	spinlock_t lock;
	const struct nvme_ctrl_ops *ops;
	struct request_queue *admin_q;
	struct request_queue *connect_q;
	struct device *dev;
	struct kref kref;
	int instance;
	struct blk_mq_tag_set *tagset;
	struct list_head namespaces;
	struct mutex namespaces_mutex;
	struct device *device;	/* char device */
	struct list_head node;
	struct ida ns_ida;

	struct opal_dev *opal_dev;

	char name[12];
	char serial[20];
	char model[40];
	char firmware_rev[8];
	u16 cntlid;

	u32 ctrl_config;

	u32 page_size;
	u32 max_hw_sectors;
	u16 oncs;
	u16 vid;
	u16 oacs;
	atomic_t abort_limit;
	u8 event_limit;
	u8 vwc;
	u32 vs;
	u32 sgls;
	u16 kas;
	u8 npss;
	u8 apsta;
	unsigned int kato;
	bool subsystem;
	unsigned long quirks;
	struct nvme_id_power_state psd[32];
	struct work_struct scan_work;
	struct work_struct async_event_work;
	struct delayed_work ka_work;

	/* Power saving configuration */
	u64 ps_max_latency_us;

	/* Fabrics only */
	u16 sqsize;
	u32 ioccsz;
	u32 iorcsz;
	u16 icdoff;
	u16 maxcmd;
	struct nvmf_ctrl_options *opts;
};

/*
 * An NVM Express namespace is equivalent to a SCSI LUN
 */
struct nvme_ns {
	struct list_head list;

	struct nvme_ctrl *ctrl;
	struct request_queue *queue;
	struct gendisk *disk;
	struct nvm_dev *ndev;
	struct kref kref;
	int instance;

	u8 eui[8];
	u8 uuid[16];

	unsigned ns_id;
	int lba_shift;
	u16 ms;
	bool ext;
	u8 pi_type;
	unsigned long flags;

#define NVME_NS_REMOVING 0
#define NVME_NS_DEAD     1

	u64 mode_select_num_blocks;
	u32 mode_select_block_len;
};

struct nvme_ctrl_ops {
	const char *name;
	struct module *module;
	unsigned int flags;
#define NVME_F_FABRICS			(1 << 0)
#define NVME_F_METADATA_SUPPORTED	(1 << 1)
	int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val);
	int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val);
	int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val);
	int (*reset_ctrl)(struct nvme_ctrl *ctrl);
	void (*free_ctrl)(struct nvme_ctrl *ctrl);
	void (*submit_async_event)(struct nvme_ctrl *ctrl, int aer_idx);
	int (*delete_ctrl)(struct nvme_ctrl *ctrl);
	const char *(*get_subsysnqn)(struct nvme_ctrl *ctrl);
	int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size);
};

static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
{
	u32 val = 0;

	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
		return false;
	return val & NVME_CSTS_RDY;
}

static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
{
	if (!ctrl->subsystem)
		return -ENOTTY;
	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
}

static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
{
	return (sector >> (ns->lba_shift - 9));
}

static inline void nvme_cleanup_cmd(struct request *req)
{
	if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
		kfree(page_address(req->special_vec.bv_page) +
		      req->special_vec.bv_offset);
	}
}

static inline void nvme_end_request(struct request *req, __le16 status,
		union nvme_result result)
{
	struct nvme_request *rq = nvme_req(req);

	rq->status = le16_to_cpu(status) >> 1;
	rq->result = result;
	blk_mq_complete_request(req);
}

void nvme_complete_rq(struct request *req);
void nvme_cancel_request(struct request *req, void *data, bool reserved);
bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
		enum nvme_ctrl_state new_state);
int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
		const struct nvme_ctrl_ops *ops, unsigned long quirks);
void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
void nvme_put_ctrl(struct nvme_ctrl *ctrl);
int nvme_init_identify(struct nvme_ctrl *ctrl);

void nvme_queue_scan(struct nvme_ctrl *ctrl);
void nvme_remove_namespaces(struct nvme_ctrl *ctrl);

int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
		bool send);

#define NVME_NR_AERS	1
void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
		union nvme_result *res);
void nvme_queue_async_events(struct nvme_ctrl *ctrl);

void nvme_stop_queues(struct nvme_ctrl *ctrl);
void nvme_start_queues(struct nvme_ctrl *ctrl);
void nvme_kill_queues(struct nvme_ctrl *ctrl);
void nvme_unfreeze(struct nvme_ctrl *ctrl);
void nvme_wait_freeze(struct nvme_ctrl *ctrl);
void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
void nvme_start_freeze(struct nvme_ctrl *ctrl);

#define NVME_QID_ANY -1
struct request *nvme_alloc_request(struct request_queue *q,
		struct nvme_command *cmd, unsigned int flags, int qid);
blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
		struct nvme_command *cmd);
int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		void *buf, unsigned bufflen);
int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		union nvme_result *result, void *buffer, unsigned bufflen,
		unsigned timeout, int qid, int at_head, int flags);
int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
		void __user *ubuffer, unsigned bufflen, u32 *result,
		unsigned timeout);
int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
		void __user *ubuffer, unsigned bufflen,
		void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
		u32 *result, unsigned timeout);
int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id);
int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
		struct nvme_id_ns **id);
int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log);
int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
		      void *buffer, size_t buflen, u32 *result);
int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
		      void *buffer, size_t buflen, u32 *result);
int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);
void nvme_start_keep_alive(struct nvme_ctrl *ctrl);
void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);

struct sg_io_hdr;

int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr);
int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
int nvme_sg_get_version_num(int __user *ip);

#ifdef CONFIG_NVM
int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id);
int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node);
void nvme_nvm_unregister(struct nvme_ns *ns);
int nvme_nvm_register_sysfs(struct nvme_ns *ns);
void nvme_nvm_unregister_sysfs(struct nvme_ns *ns);
int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg);
#else
static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name,
				    int node)
{
	return 0;
}

static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns)
{
	return 0;
}
static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {};
static inline int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id)
{
	return 0;
}
static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
							unsigned long arg)
{
	return -ENOTTY;
}
#endif /* CONFIG_NVM */

static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev)
{
	return dev_to_disk(dev)->private_data;
}

int __init nvme_core_init(void);
void nvme_core_exit(void);

#endif /* _NVME_H */
Commit	Line	Data
f11bb3e2 CH	1	/*
	2	* Copyright (c) 2011-2014, Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*/
	13
	14	#ifndef _NVME_H
	15	#define _NVME_H
	16
	17	#include <linux/nvme.h>
	18	#include <linux/pci.h>
	19	#include <linux/kref.h>
	20	#include <linux/blk-mq.h>
b0b4e09c	21	#include <linux/lightnvm.h>
a98e58e5	22	#include <linux/sed-opal.h>
f11bb3e2 CH	23
	24	extern unsigned char nvme_io_timeout;
	25	#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
	26
21d34711 CH	27	extern unsigned char admin_timeout;
	28	#define ADMIN_TIMEOUT (admin_timeout * HZ)
	29
5fd4ce1b CH	30	extern unsigned char shutdown_timeout;
	31	#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
	32
038bd4cb SG	33	#define NVME_DEFAULT_KATO 5
	34	#define NVME_KATO_GRACE 10
	35
ca064085 MB	36	enum {
	37	NVME_NS_LBA = 0,
	38	NVME_NS_LIGHTNVM = 1,
	39	};
	40
f11bb3e2	41	/*
106198ed CH	42	* List of workarounds for devices that required behavior not specified in
106198ed CH	43	* the standard.
f11bb3e2	44	*/
106198ed CH	45	enum nvme_quirks {
	46	/*
	47	* Prefers I/O aligned to a stripe size specified in a vendor
	48	* specific Identify field.
	49	*/
	50	NVME_QUIRK_STRIPE_SIZE = (1 << 0),
540c801c KB	51
	52	/*
	53	* The controller doesn't handle Identify value others than 0 or 1
	54	* correctly.
	55	*/
	56	NVME_QUIRK_IDENTIFY_CNS = (1 << 1),
08095e70 KB	57
08095e70 KB	58	/*
e850fd16 CH	59	* The controller deterministically returns O's on reads to
e850fd16 CH	60	* logical blocks that deallocate was called on.
08095e70	61	*/
e850fd16	62	NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2),
54adc010 GP	63
	64	/*
	65	* The controller needs a delay before starts checking the device
	66	* readiness, which is done by reading the NVME_CSTS_RDY bit.
	67	*/
	68	NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3),
c5552fde AL	69
	70	/*
	71	* APST should not be used.
	72	*/
	73	NVME_QUIRK_NO_APST = (1 << 4),
ff5350a8 AL	74
	75	/*
	76	* The deepest sleep state should not be used.
	77	*/
	78	NVME_QUIRK_NO_DEEPEST_PS = (1 << 5),
106198ed CH	79	};
106198ed CH	80
d49187e9 CH	81	/*
	82	* Common request structure for NVMe passthrough. All drivers must have
	83	* this structure as the first member of their request-private data.
	84	*/
	85	struct nvme_request {
	86	struct nvme_command *cmd;
	87	union nvme_result result;
44e44b29	88	u8 retries;
27fa9bc5 CH	89	u8 flags;
	90	u16 status;
	91	};
	92
	93	enum {
	94	NVME_REQ_CANCELLED = (1 << 0),
d49187e9 CH	95	};
	96
	97	static inline struct nvme_request nvme_req(struct request req)
	98	{
	99	return blk_mq_rq_to_pdu(req);
	100	}
	101
54adc010 GP	102	/* The below value is the specific amount of delay needed before checking
	103	* readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
	104	* NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
	105	* found empirically.
	106	*/
	107	#define NVME_QUIRK_DELAY_AMOUNT 2000
	108
bb8d261e CH	109	enum nvme_ctrl_state {
	110	NVME_CTRL_NEW,
	111	NVME_CTRL_LIVE,
	112	NVME_CTRL_RESETTING,
def61eca	113	NVME_CTRL_RECONNECTING,
bb8d261e	114	NVME_CTRL_DELETING,
0ff9d4e1	115	NVME_CTRL_DEAD,
bb8d261e CH	116	};
bb8d261e CH	117
1c63dc66	118	struct nvme_ctrl {
bb8d261e	119	enum nvme_ctrl_state state;
bd4da3ab	120	bool identified;
bb8d261e	121	spinlock_t lock;
1c63dc66	122	const struct nvme_ctrl_ops *ops;
f11bb3e2	123	struct request_queue *admin_q;
07bfcd09	124	struct request_queue *connect_q;
f11bb3e2	125	struct device *dev;
1673f1f0	126	struct kref kref;
f11bb3e2	127	int instance;
5bae7f73	128	struct blk_mq_tag_set *tagset;
f11bb3e2	129	struct list_head namespaces;
69d3b8ac	130	struct mutex namespaces_mutex;
5bae7f73	131	struct device device; / char device */
f3ca80fc	132	struct list_head node;
075790eb	133	struct ida ns_ida;
1c63dc66	134
4f1244c8	135	struct opal_dev *opal_dev;
a98e58e5	136
f11bb3e2 CH	137	char name[12];
	138	char serial[20];
	139	char model[40];
	140	char firmware_rev[8];
76e3914a	141	u16 cntlid;
5fd4ce1b CH	142
	143	u32 ctrl_config;
	144
	145	u32 page_size;
f11bb3e2	146	u32 max_hw_sectors;
f11bb3e2	147	u16 oncs;
118472ab	148	u16 vid;
8a9ae523	149	u16 oacs;
6bf25d16	150	atomic_t abort_limit;
f11bb3e2 CH	151	u8 event_limit;
f11bb3e2 CH	152	u8 vwc;
f3ca80fc	153	u32 vs;
07bfcd09	154	u32 sgls;
038bd4cb	155	u16 kas;
c5552fde AL	156	u8 npss;
c5552fde AL	157	u8 apsta;
038bd4cb	158	unsigned int kato;
f3ca80fc	159	bool subsystem;
106198ed	160	unsigned long quirks;
c5552fde	161	struct nvme_id_power_state psd[32];
5955be21	162	struct work_struct scan_work;
f866fc42	163	struct work_struct async_event_work;
038bd4cb	164	struct delayed_work ka_work;
07bfcd09	165
c5552fde AL	166	/* Power saving configuration */
	167	u64 ps_max_latency_us;
	168
07bfcd09 CH	169	/* Fabrics only */
	170	u16 sqsize;
	171	u32 ioccsz;
	172	u32 iorcsz;
	173	u16 icdoff;
	174	u16 maxcmd;
	175	struct nvmf_ctrl_options *opts;
f11bb3e2 CH	176	};
	177
	178	/*
	179	* An NVM Express namespace is equivalent to a SCSI LUN
	180	*/
	181	struct nvme_ns {
	182	struct list_head list;
	183
1c63dc66	184	struct nvme_ctrl *ctrl;
f11bb3e2 CH	185	struct request_queue *queue;
f11bb3e2 CH	186	struct gendisk *disk;
b0b4e09c	187	struct nvm_dev *ndev;
f11bb3e2	188	struct kref kref;
075790eb	189	int instance;
f11bb3e2	190
2b9b6e86 KB	191	u8 eui[8];
	192	u8 uuid[16];
	193
f11bb3e2 CH	194	unsigned ns_id;
	195	int lba_shift;
	196	u16 ms;
	197	bool ext;
	198	u8 pi_type;
646017a6 KB	199	unsigned long flags;
	200
	201	#define NVME_NS_REMOVING 0
69d9a99c	202	#define NVME_NS_DEAD 1
646017a6	203
f11bb3e2 CH	204	u64 mode_select_num_blocks;
	205	u32 mode_select_block_len;
	206	};
	207
1c63dc66	208	struct nvme_ctrl_ops {
1a353d85	209	const char *name;
e439bb12	210	struct module *module;
d3d5b87d CH	211	unsigned int flags;
d3d5b87d CH	212	#define NVME_F_FABRICS (1 << 0)
c81bfba9	213	#define NVME_F_METADATA_SUPPORTED (1 << 1)
1c63dc66	214	int (reg_read32)(struct nvme_ctrl ctrl, u32 off, u32 *val);
5fd4ce1b	215	int (reg_write32)(struct nvme_ctrl ctrl, u32 off, u32 val);
7fd8930f	216	int (reg_read64)(struct nvme_ctrl ctrl, u32 off, u64 *val);
f3ca80fc	217	int (reset_ctrl)(struct nvme_ctrl ctrl);
1673f1f0	218	void (free_ctrl)(struct nvme_ctrl ctrl);
f866fc42	219	void (submit_async_event)(struct nvme_ctrl ctrl, int aer_idx);
1a353d85 ML	220	int (delete_ctrl)(struct nvme_ctrl ctrl);
	221	const char (get_subsysnqn)(struct nvme_ctrl *ctrl);
	222	int (get_address)(struct nvme_ctrl ctrl, char *buf, int size);
f11bb3e2 CH	223	};
f11bb3e2 CH	224
1c63dc66 CH	225	static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
	226	{
	227	u32 val = 0;
	228
	229	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
	230	return false;
	231	return val & NVME_CSTS_RDY;
	232	}
	233
f3ca80fc CH	234	static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
	235	{
	236	if (!ctrl->subsystem)
	237	return -ENOTTY;
	238	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
	239	}
	240
f11bb3e2 CH	241	static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
	242	{
	243	return (sector >> (ns->lba_shift - 9));
	244	}
	245
6904242d ML	246	static inline void nvme_cleanup_cmd(struct request *req)
6904242d ML	247	{
f9d03f96 CH	248	if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
	249	kfree(page_address(req->special_vec.bv_page) +
	250	req->special_vec.bv_offset);
	251	}
6904242d ML	252	}
6904242d ML	253
27fa9bc5 CH	254	static inline void nvme_end_request(struct request *req, __le16 status,
27fa9bc5 CH	255	union nvme_result result)
15a190f7	256	{
27fa9bc5	257	struct nvme_request *rq = nvme_req(req);
15a190f7	258
27fa9bc5 CH	259	rq->status = le16_to_cpu(status) >> 1;
27fa9bc5 CH	260	rq->result = result;
08e0029a	261	blk_mq_complete_request(req);
7688faa6 CH	262	}
7688faa6 CH	263
77f02a7a	264	void nvme_complete_rq(struct request *req);
c55a2fd4	265	void nvme_cancel_request(struct request req, void data, bool reserved);
bb8d261e CH	266	bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
bb8d261e CH	267	enum nvme_ctrl_state new_state);
5fd4ce1b CH	268	int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	269	int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	270	int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
f3ca80fc CH	271	int nvme_init_ctrl(struct nvme_ctrl ctrl, struct device dev,
f3ca80fc CH	272	const struct nvme_ctrl_ops *ops, unsigned long quirks);
53029b04	273	void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
1673f1f0	274	void nvme_put_ctrl(struct nvme_ctrl *ctrl);
7fd8930f	275	int nvme_init_identify(struct nvme_ctrl *ctrl);
5bae7f73	276
5955be21	277	void nvme_queue_scan(struct nvme_ctrl *ctrl);
5bae7f73	278	void nvme_remove_namespaces(struct nvme_ctrl *ctrl);
1673f1f0	279
4f1244c8 CH	280	int nvme_sec_submit(void data, u16 spsp, u8 secp, void buffer, size_t len,
4f1244c8 CH	281	bool send);
a98e58e5	282
f866fc42	283	#define NVME_NR_AERS 1
7bf58533 CH	284	void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
7bf58533 CH	285	union nvme_result *res);
f866fc42 CH	286	void nvme_queue_async_events(struct nvme_ctrl *ctrl);
f866fc42 CH	287
25646264 KB	288	void nvme_stop_queues(struct nvme_ctrl *ctrl);
25646264 KB	289	void nvme_start_queues(struct nvme_ctrl *ctrl);
69d9a99c	290	void nvme_kill_queues(struct nvme_ctrl *ctrl);
302ad8cc KB	291	void nvme_unfreeze(struct nvme_ctrl *ctrl);
	292	void nvme_wait_freeze(struct nvme_ctrl *ctrl);
	293	void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
	294	void nvme_start_freeze(struct nvme_ctrl *ctrl);
363c9aac	295
eb71f435	296	#define NVME_QID_ANY -1
4160982e	297	struct request nvme_alloc_request(struct request_queue q,
eb71f435	298	struct nvme_command *cmd, unsigned int flags, int qid);
fc17b653	299	blk_status_t nvme_setup_cmd(struct nvme_ns ns, struct request req,
8093f7ca	300	struct nvme_command *cmd);
f11bb3e2 CH	301	int nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
	302	void *buf, unsigned bufflen);
	303	int __nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
d49187e9	304	union nvme_result result, void buffer, unsigned bufflen,
eb71f435	305	unsigned timeout, int qid, int at_head, int flags);
4160982e CH	306	int nvme_submit_user_cmd(struct request_queue q, struct nvme_command cmd,
	307	void __user ubuffer, unsigned bufflen, u32 result,
	308	unsigned timeout);
0b7f1f26 KB	309	int __nvme_submit_user_cmd(struct request_queue q, struct nvme_command cmd,
	310	void __user *ubuffer, unsigned bufflen,
	311	void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
f11bb3e2	312	u32 *result, unsigned timeout);
1c63dc66 CH	313	int nvme_identify_ctrl(struct nvme_ctrl dev, struct nvme_id_ctrl *id);
1c63dc66 CH	314	int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
f11bb3e2	315	struct nvme_id_ns **id);
1c63dc66 CH	316	int nvme_get_log_page(struct nvme_ctrl dev, struct nvme_smart_log *log);
1c63dc66 CH	317	int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
1a6fe74d	318	void buffer, size_t buflen, u32 result);
1c63dc66	319	int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
1a6fe74d	320	void buffer, size_t buflen, u32 result);
9a0be7ab	321	int nvme_set_queue_count(struct nvme_ctrl ctrl, int count);
038bd4cb SG	322	void nvme_start_keep_alive(struct nvme_ctrl *ctrl);
038bd4cb SG	323	void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
f11bb3e2 CH	324
	325	struct sg_io_hdr;
	326
	327	int nvme_sg_io(struct nvme_ns ns, struct sg_io_hdr __user u_hdr);
	328	int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
	329	int nvme_sg_get_version_num(int __user *ip);
	330
c4699e70	331	#ifdef CONFIG_NVM
ca064085	332	int nvme_nvm_ns_supported(struct nvme_ns ns, struct nvme_id_ns id);
3dc87dd0	333	int nvme_nvm_register(struct nvme_ns ns, char disk_name, int node);
b0b4e09c	334	void nvme_nvm_unregister(struct nvme_ns *ns);
3dc87dd0 MB	335	int nvme_nvm_register_sysfs(struct nvme_ns *ns);
3dc87dd0 MB	336	void nvme_nvm_unregister_sysfs(struct nvme_ns *ns);
84d4add7	337	int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg);
c4699e70	338	#else
b0b4e09c	339	static inline int nvme_nvm_register(struct nvme_ns ns, char disk_name,
3dc87dd0	340	int node)
c4699e70 KB	341	{
	342	return 0;
	343	}
	344
b0b4e09c	345	static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
3dc87dd0 MB	346	static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns)
	347	{
	348	return 0;
	349	}
	350	static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {};
c4699e70 KB	351	static inline int nvme_nvm_ns_supported(struct nvme_ns ns, struct nvme_id_ns id)
	352	{
	353	return 0;
	354	}
84d4add7 MB	355	static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
	356	unsigned long arg)
	357	{
	358	return -ENOTTY;
	359	}
3dc87dd0 MB	360	#endif /* CONFIG_NVM */
3dc87dd0 MB	361
40267efd SL	362	static inline struct nvme_ns nvme_get_ns_from_dev(struct device dev)
	363	{
	364	return dev_to_disk(dev)->private_data;
	365	}
ca064085	366
5bae7f73 CH	367	int __init nvme_core_init(void);
	368	void nvme_core_exit(void);
	369
f11bb3e2	370	#endif /* _NVME_H */