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bc50ad75 1/* SPDX-License-Identifier: GPL-2.0 */
f11bb3e2
CH
2/*
3 * Copyright (c) 2011-2014, Intel Corporation.
f11bb3e2
CH
4 */
5
6#ifndef _NVME_H
7#define _NVME_H
8
9#include <linux/nvme.h>
a6a5149b 10#include <linux/cdev.h>
f11bb3e2
CH
11#include <linux/pci.h>
12#include <linux/kref.h>
13#include <linux/blk-mq.h>
b0b4e09c 14#include <linux/lightnvm.h>
a98e58e5 15#include <linux/sed-opal.h>
b9e03857 16#include <linux/fault-inject.h>
978628ec 17#include <linux/rcupdate.h>
c1ac9a4b 18#include <linux/wait.h>
f11bb3e2 19
35fe0d12
HR
20#include <trace/events/block.h>
21
8ae4e447 22extern unsigned int nvme_io_timeout;
f11bb3e2
CH
23#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
24
8ae4e447 25extern unsigned int admin_timeout;
21d34711
CH
26#define ADMIN_TIMEOUT (admin_timeout * HZ)
27
038bd4cb
SG
28#define NVME_DEFAULT_KATO 5
29#define NVME_KATO_GRACE 10
30
38e18002
IR
31#ifdef CONFIG_ARCH_NO_SG_CHAIN
32#define NVME_INLINE_SG_CNT 0
33#else
34#define NVME_INLINE_SG_CNT 2
35#endif
36
9a6327d2 37extern struct workqueue_struct *nvme_wq;
b227c59b
RS
38extern struct workqueue_struct *nvme_reset_wq;
39extern struct workqueue_struct *nvme_delete_wq;
9a6327d2 40
ca064085
MB
41enum {
42 NVME_NS_LBA = 0,
43 NVME_NS_LIGHTNVM = 1,
44};
45
f11bb3e2 46/*
106198ed
CH
47 * List of workarounds for devices that required behavior not specified in
48 * the standard.
f11bb3e2 49 */
106198ed
CH
50enum nvme_quirks {
51 /*
52 * Prefers I/O aligned to a stripe size specified in a vendor
53 * specific Identify field.
54 */
55 NVME_QUIRK_STRIPE_SIZE = (1 << 0),
540c801c
KB
56
57 /*
58 * The controller doesn't handle Identify value others than 0 or 1
59 * correctly.
60 */
61 NVME_QUIRK_IDENTIFY_CNS = (1 << 1),
08095e70
KB
62
63 /*
e850fd16
CH
64 * The controller deterministically returns O's on reads to
65 * logical blocks that deallocate was called on.
08095e70 66 */
e850fd16 67 NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2),
54adc010
GP
68
69 /*
70 * The controller needs a delay before starts checking the device
71 * readiness, which is done by reading the NVME_CSTS_RDY bit.
72 */
73 NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3),
c5552fde
AL
74
75 /*
76 * APST should not be used.
77 */
78 NVME_QUIRK_NO_APST = (1 << 4),
ff5350a8
AL
79
80 /*
81 * The deepest sleep state should not be used.
82 */
83 NVME_QUIRK_NO_DEEPEST_PS = (1 << 5),
608cc4b1
CH
84
85 /*
86 * Supports the LighNVM command set if indicated in vs[1].
87 */
88 NVME_QUIRK_LIGHTNVM = (1 << 6),
9abd68ef
JA
89
90 /*
91 * Set MEDIUM priority on SQ creation
92 */
93 NVME_QUIRK_MEDIUM_PRIO_SQ = (1 << 7),
6299358d
JD
94
95 /*
96 * Ignore device provided subnqn.
97 */
98 NVME_QUIRK_IGNORE_DEV_SUBNQN = (1 << 8),
7b210e4e
CH
99
100 /*
101 * Broken Write Zeroes.
102 */
103 NVME_QUIRK_DISABLE_WRITE_ZEROES = (1 << 9),
cb32de1b
ML
104
105 /*
106 * Force simple suspend/resume path.
107 */
108 NVME_QUIRK_SIMPLE_SUSPEND = (1 << 10),
7ad67ca5 109
66341331
BH
110 /*
111 * Use only one interrupt vector for all queues
112 */
7ad67ca5 113 NVME_QUIRK_SINGLE_VECTOR = (1 << 11),
66341331
BH
114
115 /*
116 * Use non-standard 128 bytes SQEs.
117 */
7ad67ca5 118 NVME_QUIRK_128_BYTES_SQES = (1 << 12),
d38e9f04
BH
119
120 /*
121 * Prevent tag overlap between queues
122 */
7ad67ca5 123 NVME_QUIRK_SHARED_TAGS = (1 << 13),
6c6aa2f2
AM
124
125 /*
126 * Don't change the value of the temperature threshold feature
127 */
128 NVME_QUIRK_NO_TEMP_THRESH_CHANGE = (1 << 14),
106198ed
CH
129};
130
d49187e9
CH
131/*
132 * Common request structure for NVMe passthrough. All drivers must have
133 * this structure as the first member of their request-private data.
134 */
135struct nvme_request {
136 struct nvme_command *cmd;
137 union nvme_result result;
44e44b29 138 u8 retries;
27fa9bc5
CH
139 u8 flags;
140 u16 status;
59e29ce6 141 struct nvme_ctrl *ctrl;
27fa9bc5
CH
142};
143
32acab31
CH
144/*
145 * Mark a bio as coming in through the mpath node.
146 */
147#define REQ_NVME_MPATH REQ_DRV
148
27fa9bc5
CH
149enum {
150 NVME_REQ_CANCELLED = (1 << 0),
bb06ec31 151 NVME_REQ_USERCMD = (1 << 1),
d49187e9
CH
152};
153
154static inline struct nvme_request *nvme_req(struct request *req)
155{
156 return blk_mq_rq_to_pdu(req);
157}
158
5d87eb94
KB
159static inline u16 nvme_req_qid(struct request *req)
160{
161 if (!req->rq_disk)
162 return 0;
163 return blk_mq_unique_tag_to_hwq(blk_mq_unique_tag(req)) + 1;
164}
165
54adc010
GP
166/* The below value is the specific amount of delay needed before checking
167 * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
168 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
169 * found empirically.
170 */
8c97eecc 171#define NVME_QUIRK_DELAY_AMOUNT 2300
54adc010 172
bb8d261e
CH
173enum nvme_ctrl_state {
174 NVME_CTRL_NEW,
175 NVME_CTRL_LIVE,
176 NVME_CTRL_RESETTING,
ad6a0a52 177 NVME_CTRL_CONNECTING,
bb8d261e 178 NVME_CTRL_DELETING,
0ff9d4e1 179 NVME_CTRL_DEAD,
bb8d261e
CH
180};
181
a3646451
AM
182struct nvme_fault_inject {
183#ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
184 struct fault_attr attr;
185 struct dentry *parent;
186 bool dont_retry; /* DNR, do not retry */
187 u16 status; /* status code */
188#endif
189};
190
1c63dc66 191struct nvme_ctrl {
6e3ca03e 192 bool comp_seen;
bb8d261e 193 enum nvme_ctrl_state state;
bd4da3ab 194 bool identified;
bb8d261e 195 spinlock_t lock;
e7ad43c3 196 struct mutex scan_lock;
1c63dc66 197 const struct nvme_ctrl_ops *ops;
f11bb3e2 198 struct request_queue *admin_q;
07bfcd09 199 struct request_queue *connect_q;
e7832cb4 200 struct request_queue *fabrics_q;
f11bb3e2 201 struct device *dev;
f11bb3e2 202 int instance;
103e515e 203 int numa_node;
5bae7f73 204 struct blk_mq_tag_set *tagset;
34b6c231 205 struct blk_mq_tag_set *admin_tagset;
f11bb3e2 206 struct list_head namespaces;
765cc031 207 struct rw_semaphore namespaces_rwsem;
d22524a4 208 struct device ctrl_device;
5bae7f73 209 struct device *device; /* char device */
a6a5149b 210 struct cdev cdev;
d86c4d8e 211 struct work_struct reset_work;
c5017e85 212 struct work_struct delete_work;
c1ac9a4b 213 wait_queue_head_t state_wq;
1c63dc66 214
ab9e00cc
CH
215 struct nvme_subsystem *subsys;
216 struct list_head subsys_entry;
217
4f1244c8 218 struct opal_dev *opal_dev;
a98e58e5 219
f11bb3e2 220 char name[12];
76e3914a 221 u16 cntlid;
5fd4ce1b
CH
222
223 u32 ctrl_config;
b6dccf7f 224 u16 mtfa;
d858e5f0 225 u32 queue_count;
5fd4ce1b 226
20d0dfe6 227 u64 cap;
5fd4ce1b 228 u32 page_size;
f11bb3e2 229 u32 max_hw_sectors;
943e942e 230 u32 max_segments;
49cd84b6 231 u16 crdt[3];
f11bb3e2 232 u16 oncs;
8a9ae523 233 u16 oacs;
f5d11840
JA
234 u16 nssa;
235 u16 nr_streams;
f968688f 236 u16 sqsize;
0d0b660f 237 u32 max_namespaces;
6bf25d16 238 atomic_t abort_limit;
f11bb3e2 239 u8 vwc;
f3ca80fc 240 u32 vs;
07bfcd09 241 u32 sgls;
038bd4cb 242 u16 kas;
c5552fde
AL
243 u8 npss;
244 u8 apsta;
400b6a7b
GR
245 u16 wctemp;
246 u16 cctemp;
c0561f82 247 u32 oaes;
e3d7874d 248 u32 aen_result;
3e53ba38 249 u32 ctratt;
07fbd32a 250 unsigned int shutdown_timeout;
038bd4cb 251 unsigned int kato;
f3ca80fc 252 bool subsystem;
106198ed 253 unsigned long quirks;
c5552fde 254 struct nvme_id_power_state psd[32];
84fef62d 255 struct nvme_effects_log *effects;
5955be21 256 struct work_struct scan_work;
f866fc42 257 struct work_struct async_event_work;
038bd4cb 258 struct delayed_work ka_work;
0a34e466 259 struct nvme_command ka_cmd;
b6dccf7f 260 struct work_struct fw_act_work;
30d90964 261 unsigned long events;
ce151813 262 bool created;
07bfcd09 263
0d0b660f
CH
264#ifdef CONFIG_NVME_MULTIPATH
265 /* asymmetric namespace access: */
266 u8 anacap;
267 u8 anatt;
268 u32 anagrpmax;
269 u32 nanagrpid;
270 struct mutex ana_lock;
271 struct nvme_ana_rsp_hdr *ana_log_buf;
272 size_t ana_log_size;
273 struct timer_list anatt_timer;
274 struct work_struct ana_work;
275#endif
276
c5552fde
AL
277 /* Power saving configuration */
278 u64 ps_max_latency_us;
76a5af84 279 bool apst_enabled;
c5552fde 280
044a9df1 281 /* PCIe only: */
fe6d53c9
CH
282 u32 hmpre;
283 u32 hmmin;
044a9df1
CH
284 u32 hmminds;
285 u16 hmmaxd;
fe6d53c9 286
07bfcd09 287 /* Fabrics only */
07bfcd09
CH
288 u32 ioccsz;
289 u32 iorcsz;
290 u16 icdoff;
291 u16 maxcmd;
fdf9dfa8 292 int nr_reconnects;
07bfcd09 293 struct nvmf_ctrl_options *opts;
cb5b7262
JA
294
295 struct page *discard_page;
296 unsigned long discard_page_busy;
f79d5fda
AM
297
298 struct nvme_fault_inject fault_inject;
f11bb3e2
CH
299};
300
75c10e73
HR
301enum nvme_iopolicy {
302 NVME_IOPOLICY_NUMA,
303 NVME_IOPOLICY_RR,
304};
305
ab9e00cc
CH
306struct nvme_subsystem {
307 int instance;
308 struct device dev;
309 /*
310 * Because we unregister the device on the last put we need
311 * a separate refcount.
312 */
313 struct kref ref;
314 struct list_head entry;
315 struct mutex lock;
316 struct list_head ctrls;
ed754e5d 317 struct list_head nsheads;
ab9e00cc
CH
318 char subnqn[NVMF_NQN_SIZE];
319 char serial[20];
320 char model[40];
321 char firmware_rev[8];
322 u8 cmic;
323 u16 vendor_id;
81adb863 324 u16 awupf; /* 0's based awupf value. */
ed754e5d 325 struct ida ns_ida;
75c10e73
HR
326#ifdef CONFIG_NVME_MULTIPATH
327 enum nvme_iopolicy iopolicy;
328#endif
ab9e00cc
CH
329};
330
002fab04
CH
331/*
332 * Container structure for uniqueue namespace identifiers.
333 */
334struct nvme_ns_ids {
335 u8 eui64[8];
336 u8 nguid[16];
337 uuid_t uuid;
338};
339
ed754e5d
CH
340/*
341 * Anchor structure for namespaces. There is one for each namespace in a
342 * NVMe subsystem that any of our controllers can see, and the namespace
343 * structure for each controller is chained of it. For private namespaces
344 * there is a 1:1 relation to our namespace structures, that is ->list
345 * only ever has a single entry for private namespaces.
346 */
347struct nvme_ns_head {
348 struct list_head list;
349 struct srcu_struct srcu;
350 struct nvme_subsystem *subsys;
351 unsigned ns_id;
352 struct nvme_ns_ids ids;
353 struct list_head entry;
354 struct kref ref;
0c284db7 355 bool shared;
ed754e5d 356 int instance;
f3334447
CH
357#ifdef CONFIG_NVME_MULTIPATH
358 struct gendisk *disk;
359 struct bio_list requeue_list;
360 spinlock_t requeue_lock;
361 struct work_struct requeue_work;
362 struct mutex lock;
363 struct nvme_ns __rcu *current_path[];
364#endif
ed754e5d
CH
365};
366
f11bb3e2
CH
367struct nvme_ns {
368 struct list_head list;
369
1c63dc66 370 struct nvme_ctrl *ctrl;
f11bb3e2
CH
371 struct request_queue *queue;
372 struct gendisk *disk;
0d0b660f
CH
373#ifdef CONFIG_NVME_MULTIPATH
374 enum nvme_ana_state ana_state;
375 u32 ana_grpid;
376#endif
ed754e5d 377 struct list_head siblings;
b0b4e09c 378 struct nvm_dev *ndev;
f11bb3e2 379 struct kref kref;
ed754e5d 380 struct nvme_ns_head *head;
f11bb3e2 381
f11bb3e2
CH
382 int lba_shift;
383 u16 ms;
f5d11840
JA
384 u16 sgs;
385 u32 sws;
f11bb3e2
CH
386 bool ext;
387 u8 pi_type;
646017a6 388 unsigned long flags;
0d0b660f
CH
389#define NVME_NS_REMOVING 0
390#define NVME_NS_DEAD 1
391#define NVME_NS_ANA_PENDING 2
b9e03857 392
b9e03857 393 struct nvme_fault_inject fault_inject;
b9e03857 394
f11bb3e2
CH
395};
396
1c63dc66 397struct nvme_ctrl_ops {
1a353d85 398 const char *name;
e439bb12 399 struct module *module;
d3d5b87d
CH
400 unsigned int flags;
401#define NVME_F_FABRICS (1 << 0)
c81bfba9 402#define NVME_F_METADATA_SUPPORTED (1 << 1)
e0596ab2 403#define NVME_F_PCI_P2PDMA (1 << 2)
1c63dc66 404 int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val);
5fd4ce1b 405 int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val);
7fd8930f 406 int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val);
1673f1f0 407 void (*free_ctrl)(struct nvme_ctrl *ctrl);
ad22c355 408 void (*submit_async_event)(struct nvme_ctrl *ctrl);
c5017e85 409 void (*delete_ctrl)(struct nvme_ctrl *ctrl);
1a353d85 410 int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size);
f11bb3e2
CH
411};
412
b9e03857 413#ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
a3646451
AM
414void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj,
415 const char *dev_name);
416void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inject);
b9e03857
TT
417void nvme_should_fail(struct request *req);
418#else
a3646451
AM
419static inline void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj,
420 const char *dev_name)
421{
422}
423static inline void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inj)
424{
425}
b9e03857
TT
426static inline void nvme_should_fail(struct request *req) {}
427#endif
428
f3ca80fc
CH
429static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
430{
431 if (!ctrl->subsystem)
432 return -ENOTTY;
433 return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
434}
435
314d48dd
DLM
436/*
437 * Convert a 512B sector number to a device logical block number.
438 */
439static inline u64 nvme_sect_to_lba(struct nvme_ns *ns, sector_t sector)
f11bb3e2 440{
314d48dd 441 return sector >> (ns->lba_shift - SECTOR_SHIFT);
f11bb3e2
CH
442}
443
e08f2ae8
DLM
444/*
445 * Convert a device logical block number to a 512B sector number.
446 */
447static inline sector_t nvme_lba_to_sect(struct nvme_ns *ns, u64 lba)
f11bb3e2 448{
e08f2ae8 449 return lba << (ns->lba_shift - SECTOR_SHIFT);
f11bb3e2
CH
450}
451
71fb90eb
KB
452/*
453 * Convert byte length to nvme's 0-based num dwords
454 */
455static inline u32 nvme_bytes_to_numd(size_t len)
456{
457 return (len >> 2) - 1;
458}
459
27fa9bc5
CH
460static inline void nvme_end_request(struct request *req, __le16 status,
461 union nvme_result result)
15a190f7 462{
27fa9bc5 463 struct nvme_request *rq = nvme_req(req);
15a190f7 464
27fa9bc5
CH
465 rq->status = le16_to_cpu(status) >> 1;
466 rq->result = result;
b9e03857
TT
467 /* inject error when permitted by fault injection framework */
468 nvme_should_fail(req);
08e0029a 469 blk_mq_complete_request(req);
7688faa6
CH
470}
471
d22524a4
CH
472static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl)
473{
474 get_device(ctrl->device);
475}
476
477static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl)
478{
479 put_device(ctrl->device);
480}
481
58a8df67
IR
482static inline bool nvme_is_aen_req(u16 qid, __u16 command_id)
483{
484 return !qid && command_id >= NVME_AQ_BLK_MQ_DEPTH;
485}
486
77f02a7a 487void nvme_complete_rq(struct request *req);
7baa8572 488bool nvme_cancel_request(struct request *req, void *data, bool reserved);
bb8d261e
CH
489bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
490 enum nvme_ctrl_state new_state);
c1ac9a4b 491bool nvme_wait_reset(struct nvme_ctrl *ctrl);
b5b05048 492int nvme_disable_ctrl(struct nvme_ctrl *ctrl);
c0f2f45b 493int nvme_enable_ctrl(struct nvme_ctrl *ctrl);
5fd4ce1b 494int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
f3ca80fc
CH
495int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
496 const struct nvme_ctrl_ops *ops, unsigned long quirks);
53029b04 497void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
d09f2b45
SG
498void nvme_start_ctrl(struct nvme_ctrl *ctrl);
499void nvme_stop_ctrl(struct nvme_ctrl *ctrl);
7fd8930f 500int nvme_init_identify(struct nvme_ctrl *ctrl);
5bae7f73 501
5bae7f73 502void nvme_remove_namespaces(struct nvme_ctrl *ctrl);
1673f1f0 503
4f1244c8
CH
504int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
505 bool send);
a98e58e5 506
7bf58533 507void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
287a63eb 508 volatile union nvme_result *res);
f866fc42 509
25646264
KB
510void nvme_stop_queues(struct nvme_ctrl *ctrl);
511void nvme_start_queues(struct nvme_ctrl *ctrl);
69d9a99c 512void nvme_kill_queues(struct nvme_ctrl *ctrl);
d6135c3a 513void nvme_sync_queues(struct nvme_ctrl *ctrl);
302ad8cc
KB
514void nvme_unfreeze(struct nvme_ctrl *ctrl);
515void nvme_wait_freeze(struct nvme_ctrl *ctrl);
516void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
517void nvme_start_freeze(struct nvme_ctrl *ctrl);
363c9aac 518
eb71f435 519#define NVME_QID_ANY -1
4160982e 520struct request *nvme_alloc_request(struct request_queue *q,
9a95e4ef 521 struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid);
f7f1fc36 522void nvme_cleanup_cmd(struct request *req);
fc17b653 523blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
8093f7ca 524 struct nvme_command *cmd);
f11bb3e2
CH
525int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
526 void *buf, unsigned bufflen);
527int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 528 union nvme_result *result, void *buffer, unsigned bufflen,
9a95e4ef 529 unsigned timeout, int qid, int at_head,
6287b51c 530 blk_mq_req_flags_t flags, bool poll);
1a87ee65
KB
531int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid,
532 unsigned int dword11, void *buffer, size_t buflen,
533 u32 *result);
534int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid,
535 unsigned int dword11, void *buffer, size_t buflen,
536 u32 *result);
9a0be7ab 537int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);
038bd4cb 538void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
d86c4d8e 539int nvme_reset_ctrl(struct nvme_ctrl *ctrl);
79c48ccf 540int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl);
c1ac9a4b 541int nvme_try_sched_reset(struct nvme_ctrl *ctrl);
c5017e85 542int nvme_delete_ctrl(struct nvme_ctrl *ctrl);
f11bb3e2 543
0e98719b
CH
544int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp,
545 void *log, size_t size, u64 offset);
d558fb51 546
33b14f67 547extern const struct attribute_group *nvme_ns_id_attr_groups[];
32acab31
CH
548extern const struct block_device_operations nvme_ns_head_ops;
549
550#ifdef CONFIG_NVME_MULTIPATH
66b20ac0
MR
551static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl)
552{
553 return ctrl->ana_log_buf != NULL;
554}
555
b9156dae
SG
556void nvme_mpath_unfreeze(struct nvme_subsystem *subsys);
557void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys);
558void nvme_mpath_start_freeze(struct nvme_subsystem *subsys);
a785dbcc
KB
559void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns,
560 struct nvme_ctrl *ctrl, int *flags);
764e9332 561bool nvme_failover_req(struct request *req);
32acab31
CH
562void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl);
563int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,struct nvme_ns_head *head);
0d0b660f 564void nvme_mpath_add_disk(struct nvme_ns *ns, struct nvme_id_ns *id);
32acab31 565void nvme_mpath_remove_disk(struct nvme_ns_head *head);
0d0b660f
CH
566int nvme_mpath_init(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id);
567void nvme_mpath_uninit(struct nvme_ctrl *ctrl);
568void nvme_mpath_stop(struct nvme_ctrl *ctrl);
0157ec8d
SG
569bool nvme_mpath_clear_current_path(struct nvme_ns *ns);
570void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl);
32acab31 571struct nvme_ns *nvme_find_path(struct nvme_ns_head *head);
479a322f
SG
572
573static inline void nvme_mpath_check_last_path(struct nvme_ns *ns)
574{
575 struct nvme_ns_head *head = ns->head;
576
577 if (head->disk && list_empty(&head->list))
578 kblockd_schedule_work(&head->requeue_work);
579}
580
35fe0d12
HR
581static inline void nvme_trace_bio_complete(struct request *req,
582 blk_status_t status)
583{
584 struct nvme_ns *ns = req->q->queuedata;
585
586 if (req->cmd_flags & REQ_NVME_MPATH)
587 trace_block_bio_complete(ns->head->disk->queue,
588 req->bio, status);
589}
590
0d0b660f
CH
591extern struct device_attribute dev_attr_ana_grpid;
592extern struct device_attribute dev_attr_ana_state;
75c10e73 593extern struct device_attribute subsys_attr_iopolicy;
0d0b660f 594
32acab31 595#else
0d0b660f
CH
596static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl)
597{
598 return false;
599}
a785dbcc
KB
600/*
601 * Without the multipath code enabled, multiple controller per subsystems are
602 * visible as devices and thus we cannot use the subsystem instance.
603 */
604static inline void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns,
605 struct nvme_ctrl *ctrl, int *flags)
606{
607 sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->head->instance);
608}
609
764e9332 610static inline bool nvme_failover_req(struct request *req)
32acab31 611{
764e9332 612 return false;
32acab31 613}
32acab31
CH
614static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl)
615{
616}
617static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,
618 struct nvme_ns_head *head)
619{
620 return 0;
621}
0d0b660f
CH
622static inline void nvme_mpath_add_disk(struct nvme_ns *ns,
623 struct nvme_id_ns *id)
32acab31
CH
624{
625}
626static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head)
627{
628}
0157ec8d
SG
629static inline bool nvme_mpath_clear_current_path(struct nvme_ns *ns)
630{
631 return false;
632}
633static inline void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl)
479a322f
SG
634{
635}
636static inline void nvme_mpath_check_last_path(struct nvme_ns *ns)
32acab31
CH
637{
638}
35fe0d12
HR
639static inline void nvme_trace_bio_complete(struct request *req,
640 blk_status_t status)
641{
642}
0d0b660f
CH
643static inline int nvme_mpath_init(struct nvme_ctrl *ctrl,
644 struct nvme_id_ctrl *id)
645{
14a1336e
CH
646 if (ctrl->subsys->cmic & (1 << 3))
647 dev_warn(ctrl->device,
648"Please enable CONFIG_NVME_MULTIPATH for full support of multi-port devices.\n");
0d0b660f
CH
649 return 0;
650}
651static inline void nvme_mpath_uninit(struct nvme_ctrl *ctrl)
652{
653}
654static inline void nvme_mpath_stop(struct nvme_ctrl *ctrl)
655{
656}
b9156dae
SG
657static inline void nvme_mpath_unfreeze(struct nvme_subsystem *subsys)
658{
659}
660static inline void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys)
661{
662}
663static inline void nvme_mpath_start_freeze(struct nvme_subsystem *subsys)
664{
665}
32acab31
CH
666#endif /* CONFIG_NVME_MULTIPATH */
667
c4699e70 668#ifdef CONFIG_NVM
3dc87dd0 669int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node);
b0b4e09c 670void nvme_nvm_unregister(struct nvme_ns *ns);
33b14f67 671extern const struct attribute_group nvme_nvm_attr_group;
84d4add7 672int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg);
c4699e70 673#else
b0b4e09c 674static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name,
3dc87dd0 675 int node)
c4699e70
KB
676{
677 return 0;
678}
679
b0b4e09c 680static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
84d4add7
MB
681static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
682 unsigned long arg)
683{
684 return -ENOTTY;
685}
3dc87dd0
MB
686#endif /* CONFIG_NVM */
687
40267efd
SL
688static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev)
689{
690 return dev_to_disk(dev)->private_data;
691}
ca064085 692
400b6a7b
GR
693#ifdef CONFIG_NVME_HWMON
694void nvme_hwmon_init(struct nvme_ctrl *ctrl);
695#else
696static inline void nvme_hwmon_init(struct nvme_ctrl *ctrl) { }
697#endif
698
f11bb3e2 699#endif /* _NVME_H */