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f11bb3e2 CH |
1 | /* |
2 | * Copyright (c) 2011-2014, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | */ | |
13 | ||
14 | #ifndef _NVME_H | |
15 | #define _NVME_H | |
16 | ||
17 | #include <linux/nvme.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/kref.h> | |
20 | #include <linux/blk-mq.h> | |
b0b4e09c | 21 | #include <linux/lightnvm.h> |
a98e58e5 | 22 | #include <linux/sed-opal.h> |
f11bb3e2 CH |
23 | |
24 | extern unsigned char nvme_io_timeout; | |
25 | #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) | |
26 | ||
21d34711 CH |
27 | extern unsigned char admin_timeout; |
28 | #define ADMIN_TIMEOUT (admin_timeout * HZ) | |
29 | ||
5fd4ce1b CH |
30 | extern unsigned char shutdown_timeout; |
31 | #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ) | |
32 | ||
038bd4cb SG |
33 | #define NVME_DEFAULT_KATO 5 |
34 | #define NVME_KATO_GRACE 10 | |
35 | ||
ca064085 MB |
36 | enum { |
37 | NVME_NS_LBA = 0, | |
38 | NVME_NS_LIGHTNVM = 1, | |
39 | }; | |
40 | ||
f11bb3e2 | 41 | /* |
106198ed CH |
42 | * List of workarounds for devices that required behavior not specified in |
43 | * the standard. | |
f11bb3e2 | 44 | */ |
106198ed CH |
45 | enum nvme_quirks { |
46 | /* | |
47 | * Prefers I/O aligned to a stripe size specified in a vendor | |
48 | * specific Identify field. | |
49 | */ | |
50 | NVME_QUIRK_STRIPE_SIZE = (1 << 0), | |
540c801c KB |
51 | |
52 | /* | |
53 | * The controller doesn't handle Identify value others than 0 or 1 | |
54 | * correctly. | |
55 | */ | |
56 | NVME_QUIRK_IDENTIFY_CNS = (1 << 1), | |
08095e70 KB |
57 | |
58 | /* | |
e850fd16 CH |
59 | * The controller deterministically returns O's on reads to |
60 | * logical blocks that deallocate was called on. | |
08095e70 | 61 | */ |
e850fd16 | 62 | NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2), |
54adc010 GP |
63 | |
64 | /* | |
65 | * The controller needs a delay before starts checking the device | |
66 | * readiness, which is done by reading the NVME_CSTS_RDY bit. | |
67 | */ | |
68 | NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), | |
c5552fde AL |
69 | |
70 | /* | |
71 | * APST should not be used. | |
72 | */ | |
73 | NVME_QUIRK_NO_APST = (1 << 4), | |
ff5350a8 AL |
74 | |
75 | /* | |
76 | * The deepest sleep state should not be used. | |
77 | */ | |
78 | NVME_QUIRK_NO_DEEPEST_PS = (1 << 5), | |
106198ed CH |
79 | }; |
80 | ||
d49187e9 CH |
81 | /* |
82 | * Common request structure for NVMe passthrough. All drivers must have | |
83 | * this structure as the first member of their request-private data. | |
84 | */ | |
85 | struct nvme_request { | |
86 | struct nvme_command *cmd; | |
87 | union nvme_result result; | |
44e44b29 | 88 | u8 retries; |
27fa9bc5 CH |
89 | u8 flags; |
90 | u16 status; | |
91 | }; | |
92 | ||
93 | enum { | |
94 | NVME_REQ_CANCELLED = (1 << 0), | |
d49187e9 CH |
95 | }; |
96 | ||
97 | static inline struct nvme_request *nvme_req(struct request *req) | |
98 | { | |
99 | return blk_mq_rq_to_pdu(req); | |
100 | } | |
101 | ||
54adc010 GP |
102 | /* The below value is the specific amount of delay needed before checking |
103 | * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the | |
104 | * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was | |
105 | * found empirically. | |
106 | */ | |
107 | #define NVME_QUIRK_DELAY_AMOUNT 2000 | |
108 | ||
bb8d261e CH |
109 | enum nvme_ctrl_state { |
110 | NVME_CTRL_NEW, | |
111 | NVME_CTRL_LIVE, | |
112 | NVME_CTRL_RESETTING, | |
def61eca | 113 | NVME_CTRL_RECONNECTING, |
bb8d261e | 114 | NVME_CTRL_DELETING, |
0ff9d4e1 | 115 | NVME_CTRL_DEAD, |
bb8d261e CH |
116 | }; |
117 | ||
1c63dc66 | 118 | struct nvme_ctrl { |
bb8d261e | 119 | enum nvme_ctrl_state state; |
bd4da3ab | 120 | bool identified; |
bb8d261e | 121 | spinlock_t lock; |
1c63dc66 | 122 | const struct nvme_ctrl_ops *ops; |
f11bb3e2 | 123 | struct request_queue *admin_q; |
07bfcd09 | 124 | struct request_queue *connect_q; |
f11bb3e2 | 125 | struct device *dev; |
1673f1f0 | 126 | struct kref kref; |
f11bb3e2 | 127 | int instance; |
5bae7f73 | 128 | struct blk_mq_tag_set *tagset; |
f11bb3e2 | 129 | struct list_head namespaces; |
69d3b8ac | 130 | struct mutex namespaces_mutex; |
5bae7f73 | 131 | struct device *device; /* char device */ |
f3ca80fc | 132 | struct list_head node; |
075790eb | 133 | struct ida ns_ida; |
1c63dc66 | 134 | |
4f1244c8 | 135 | struct opal_dev *opal_dev; |
a98e58e5 | 136 | |
f11bb3e2 CH |
137 | char name[12]; |
138 | char serial[20]; | |
139 | char model[40]; | |
140 | char firmware_rev[8]; | |
76e3914a | 141 | u16 cntlid; |
5fd4ce1b CH |
142 | |
143 | u32 ctrl_config; | |
144 | ||
145 | u32 page_size; | |
f11bb3e2 | 146 | u32 max_hw_sectors; |
f11bb3e2 | 147 | u16 oncs; |
118472ab | 148 | u16 vid; |
8a9ae523 | 149 | u16 oacs; |
6bf25d16 | 150 | atomic_t abort_limit; |
f11bb3e2 CH |
151 | u8 event_limit; |
152 | u8 vwc; | |
f3ca80fc | 153 | u32 vs; |
07bfcd09 | 154 | u32 sgls; |
038bd4cb | 155 | u16 kas; |
c5552fde AL |
156 | u8 npss; |
157 | u8 apsta; | |
038bd4cb | 158 | unsigned int kato; |
f3ca80fc | 159 | bool subsystem; |
106198ed | 160 | unsigned long quirks; |
c5552fde | 161 | struct nvme_id_power_state psd[32]; |
5955be21 | 162 | struct work_struct scan_work; |
f866fc42 | 163 | struct work_struct async_event_work; |
038bd4cb | 164 | struct delayed_work ka_work; |
07bfcd09 | 165 | |
c5552fde AL |
166 | /* Power saving configuration */ |
167 | u64 ps_max_latency_us; | |
168 | ||
fe6d53c9 CH |
169 | u32 hmpre; |
170 | u32 hmmin; | |
171 | ||
07bfcd09 CH |
172 | /* Fabrics only */ |
173 | u16 sqsize; | |
174 | u32 ioccsz; | |
175 | u32 iorcsz; | |
176 | u16 icdoff; | |
177 | u16 maxcmd; | |
178 | struct nvmf_ctrl_options *opts; | |
f11bb3e2 CH |
179 | }; |
180 | ||
181 | /* | |
182 | * An NVM Express namespace is equivalent to a SCSI LUN | |
183 | */ | |
184 | struct nvme_ns { | |
185 | struct list_head list; | |
186 | ||
1c63dc66 | 187 | struct nvme_ctrl *ctrl; |
f11bb3e2 CH |
188 | struct request_queue *queue; |
189 | struct gendisk *disk; | |
b0b4e09c | 190 | struct nvm_dev *ndev; |
f11bb3e2 | 191 | struct kref kref; |
075790eb | 192 | int instance; |
f11bb3e2 | 193 | |
2b9b6e86 KB |
194 | u8 eui[8]; |
195 | u8 uuid[16]; | |
196 | ||
f11bb3e2 CH |
197 | unsigned ns_id; |
198 | int lba_shift; | |
199 | u16 ms; | |
200 | bool ext; | |
201 | u8 pi_type; | |
646017a6 KB |
202 | unsigned long flags; |
203 | ||
204 | #define NVME_NS_REMOVING 0 | |
69d9a99c | 205 | #define NVME_NS_DEAD 1 |
646017a6 | 206 | |
f11bb3e2 CH |
207 | u64 mode_select_num_blocks; |
208 | u32 mode_select_block_len; | |
209 | }; | |
210 | ||
1c63dc66 | 211 | struct nvme_ctrl_ops { |
1a353d85 | 212 | const char *name; |
e439bb12 | 213 | struct module *module; |
d3d5b87d CH |
214 | unsigned int flags; |
215 | #define NVME_F_FABRICS (1 << 0) | |
c81bfba9 | 216 | #define NVME_F_METADATA_SUPPORTED (1 << 1) |
1c63dc66 | 217 | int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); |
5fd4ce1b | 218 | int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); |
7fd8930f | 219 | int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); |
f3ca80fc | 220 | int (*reset_ctrl)(struct nvme_ctrl *ctrl); |
1673f1f0 | 221 | void (*free_ctrl)(struct nvme_ctrl *ctrl); |
f866fc42 | 222 | void (*submit_async_event)(struct nvme_ctrl *ctrl, int aer_idx); |
1a353d85 ML |
223 | int (*delete_ctrl)(struct nvme_ctrl *ctrl); |
224 | const char *(*get_subsysnqn)(struct nvme_ctrl *ctrl); | |
225 | int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); | |
f11bb3e2 CH |
226 | }; |
227 | ||
1c63dc66 CH |
228 | static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl) |
229 | { | |
230 | u32 val = 0; | |
231 | ||
232 | if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val)) | |
233 | return false; | |
234 | return val & NVME_CSTS_RDY; | |
235 | } | |
236 | ||
f3ca80fc CH |
237 | static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) |
238 | { | |
239 | if (!ctrl->subsystem) | |
240 | return -ENOTTY; | |
241 | return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); | |
242 | } | |
243 | ||
f11bb3e2 CH |
244 | static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector) |
245 | { | |
246 | return (sector >> (ns->lba_shift - 9)); | |
247 | } | |
248 | ||
6904242d ML |
249 | static inline void nvme_cleanup_cmd(struct request *req) |
250 | { | |
f9d03f96 CH |
251 | if (req->rq_flags & RQF_SPECIAL_PAYLOAD) { |
252 | kfree(page_address(req->special_vec.bv_page) + | |
253 | req->special_vec.bv_offset); | |
254 | } | |
6904242d ML |
255 | } |
256 | ||
27fa9bc5 CH |
257 | static inline void nvme_end_request(struct request *req, __le16 status, |
258 | union nvme_result result) | |
15a190f7 | 259 | { |
27fa9bc5 | 260 | struct nvme_request *rq = nvme_req(req); |
15a190f7 | 261 | |
27fa9bc5 CH |
262 | rq->status = le16_to_cpu(status) >> 1; |
263 | rq->result = result; | |
08e0029a | 264 | blk_mq_complete_request(req); |
7688faa6 CH |
265 | } |
266 | ||
77f02a7a | 267 | void nvme_complete_rq(struct request *req); |
c55a2fd4 | 268 | void nvme_cancel_request(struct request *req, void *data, bool reserved); |
bb8d261e CH |
269 | bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, |
270 | enum nvme_ctrl_state new_state); | |
5fd4ce1b CH |
271 | int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap); |
272 | int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap); | |
273 | int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl); | |
f3ca80fc CH |
274 | int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, |
275 | const struct nvme_ctrl_ops *ops, unsigned long quirks); | |
53029b04 | 276 | void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); |
1673f1f0 | 277 | void nvme_put_ctrl(struct nvme_ctrl *ctrl); |
7fd8930f | 278 | int nvme_init_identify(struct nvme_ctrl *ctrl); |
5bae7f73 | 279 | |
5955be21 | 280 | void nvme_queue_scan(struct nvme_ctrl *ctrl); |
5bae7f73 | 281 | void nvme_remove_namespaces(struct nvme_ctrl *ctrl); |
1673f1f0 | 282 | |
4f1244c8 CH |
283 | int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len, |
284 | bool send); | |
a98e58e5 | 285 | |
f866fc42 | 286 | #define NVME_NR_AERS 1 |
7bf58533 CH |
287 | void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, |
288 | union nvme_result *res); | |
f866fc42 CH |
289 | void nvme_queue_async_events(struct nvme_ctrl *ctrl); |
290 | ||
25646264 KB |
291 | void nvme_stop_queues(struct nvme_ctrl *ctrl); |
292 | void nvme_start_queues(struct nvme_ctrl *ctrl); | |
69d9a99c | 293 | void nvme_kill_queues(struct nvme_ctrl *ctrl); |
302ad8cc KB |
294 | void nvme_unfreeze(struct nvme_ctrl *ctrl); |
295 | void nvme_wait_freeze(struct nvme_ctrl *ctrl); | |
296 | void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout); | |
297 | void nvme_start_freeze(struct nvme_ctrl *ctrl); | |
363c9aac | 298 | |
eb71f435 | 299 | #define NVME_QID_ANY -1 |
4160982e | 300 | struct request *nvme_alloc_request(struct request_queue *q, |
eb71f435 | 301 | struct nvme_command *cmd, unsigned int flags, int qid); |
fc17b653 | 302 | blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req, |
8093f7ca | 303 | struct nvme_command *cmd); |
f11bb3e2 CH |
304 | int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
305 | void *buf, unsigned bufflen); | |
306 | int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, | |
d49187e9 | 307 | union nvme_result *result, void *buffer, unsigned bufflen, |
eb71f435 | 308 | unsigned timeout, int qid, int at_head, int flags); |
4160982e CH |
309 | int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd, |
310 | void __user *ubuffer, unsigned bufflen, u32 *result, | |
311 | unsigned timeout); | |
0b7f1f26 KB |
312 | int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd, |
313 | void __user *ubuffer, unsigned bufflen, | |
314 | void __user *meta_buffer, unsigned meta_len, u32 meta_seed, | |
f11bb3e2 | 315 | u32 *result, unsigned timeout); |
1c63dc66 CH |
316 | int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id); |
317 | int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid, | |
f11bb3e2 | 318 | struct nvme_id_ns **id); |
1c63dc66 CH |
319 | int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log); |
320 | int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid, | |
1a6fe74d | 321 | void *buffer, size_t buflen, u32 *result); |
1c63dc66 | 322 | int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11, |
1a6fe74d | 323 | void *buffer, size_t buflen, u32 *result); |
9a0be7ab | 324 | int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); |
038bd4cb SG |
325 | void nvme_start_keep_alive(struct nvme_ctrl *ctrl); |
326 | void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); | |
f11bb3e2 CH |
327 | |
328 | struct sg_io_hdr; | |
329 | ||
330 | int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr); | |
331 | int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg); | |
332 | int nvme_sg_get_version_num(int __user *ip); | |
333 | ||
c4699e70 | 334 | #ifdef CONFIG_NVM |
ca064085 | 335 | int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id); |
3dc87dd0 | 336 | int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node); |
b0b4e09c | 337 | void nvme_nvm_unregister(struct nvme_ns *ns); |
3dc87dd0 MB |
338 | int nvme_nvm_register_sysfs(struct nvme_ns *ns); |
339 | void nvme_nvm_unregister_sysfs(struct nvme_ns *ns); | |
84d4add7 | 340 | int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg); |
c4699e70 | 341 | #else |
b0b4e09c | 342 | static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, |
3dc87dd0 | 343 | int node) |
c4699e70 KB |
344 | { |
345 | return 0; | |
346 | } | |
347 | ||
b0b4e09c | 348 | static inline void nvme_nvm_unregister(struct nvme_ns *ns) {}; |
3dc87dd0 MB |
349 | static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns) |
350 | { | |
351 | return 0; | |
352 | } | |
353 | static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {}; | |
c4699e70 KB |
354 | static inline int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id) |
355 | { | |
356 | return 0; | |
357 | } | |
84d4add7 MB |
358 | static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, |
359 | unsigned long arg) | |
360 | { | |
361 | return -ENOTTY; | |
362 | } | |
3dc87dd0 MB |
363 | #endif /* CONFIG_NVM */ |
364 | ||
40267efd SL |
365 | static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev) |
366 | { | |
367 | return dev_to_disk(dev)->private_data; | |
368 | } | |
ca064085 | 369 | |
5bae7f73 CH |
370 | int __init nvme_core_init(void); |
371 | void nvme_core_exit(void); | |
372 | ||
f11bb3e2 | 373 | #endif /* _NVME_H */ |