[mirror_ubuntu-bionic-kernel.git] / drivers / nvme / host / nvme.h

/*
 * Copyright (c) 2011-2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef _NVME_H
#define _NVME_H

#include <linux/nvme.h>
#include <linux/pci.h>
#include <linux/kref.h>
#include <linux/blk-mq.h>
#include <linux/lightnvm.h>
#include <linux/sed-opal.h>

extern unsigned char nvme_io_timeout;
#define NVME_IO_TIMEOUT	(nvme_io_timeout * HZ)

extern unsigned char admin_timeout;
#define ADMIN_TIMEOUT	(admin_timeout * HZ)

extern unsigned char shutdown_timeout;
#define SHUTDOWN_TIMEOUT	(shutdown_timeout * HZ)

#define NVME_DEFAULT_KATO	5
#define NVME_KATO_GRACE		10

extern struct workqueue_struct *nvme_wq;

enum {
	NVME_NS_LBA		= 0,
	NVME_NS_LIGHTNVM	= 1,
};

/*
 * List of workarounds for devices that required behavior not specified in
 * the standard.
 */
enum nvme_quirks {
	/*
	 * Prefers I/O aligned to a stripe size specified in a vendor
	 * specific Identify field.
	 */
	NVME_QUIRK_STRIPE_SIZE			= (1 << 0),

	/*
	 * The controller doesn't handle Identify value others than 0 or 1
	 * correctly.
	 */
	NVME_QUIRK_IDENTIFY_CNS			= (1 << 1),

	/*
	 * The controller deterministically returns O's on reads to
	 * logical blocks that deallocate was called on.
	 */
	NVME_QUIRK_DEALLOCATE_ZEROES		= (1 << 2),

	/*
	 * The controller needs a delay before starts checking the device
	 * readiness, which is done by reading the NVME_CSTS_RDY bit.
	 */
	NVME_QUIRK_DELAY_BEFORE_CHK_RDY		= (1 << 3),

	/*
	 * APST should not be used.
	 */
	NVME_QUIRK_NO_APST			= (1 << 4),

	/*
	 * The deepest sleep state should not be used.
	 */
	NVME_QUIRK_NO_DEEPEST_PS		= (1 << 5),
};

/*
 * Common request structure for NVMe passthrough.  All drivers must have
 * this structure as the first member of their request-private data.
 */
struct nvme_request {
	struct nvme_command	*cmd;
	union nvme_result	result;
	u8			retries;
	u8			flags;
	u16			status;
};

enum {
	NVME_REQ_CANCELLED		= (1 << 0),
};

static inline struct nvme_request *nvme_req(struct request *req)
{
	return blk_mq_rq_to_pdu(req);
}

/* The below value is the specific amount of delay needed before checking
 * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
 * found empirically.
 */
#define NVME_QUIRK_DELAY_AMOUNT		2000

enum nvme_ctrl_state {
	NVME_CTRL_NEW,
	NVME_CTRL_LIVE,
	NVME_CTRL_RESETTING,
	NVME_CTRL_RECONNECTING,
	NVME_CTRL_DELETING,
	NVME_CTRL_DEAD,
};

struct nvme_ctrl {
	enum nvme_ctrl_state state;
	bool identified;
	spinlock_t lock;
	const struct nvme_ctrl_ops *ops;
	struct request_queue *admin_q;
	struct request_queue *connect_q;
	struct device *dev;
	struct kref kref;
	int instance;
	struct blk_mq_tag_set *tagset;
	struct list_head namespaces;
	struct mutex namespaces_mutex;
	struct device *device;	/* char device */
	struct list_head node;
	struct ida ns_ida;

	struct opal_dev *opal_dev;

	char name[12];
	char serial[20];
	char model[40];
	char firmware_rev[8];
	u16 cntlid;

	u32 ctrl_config;

	u32 page_size;
	u32 max_hw_sectors;
	u16 oncs;
	u16 vid;
	u16 oacs;
	atomic_t abort_limit;
	u8 event_limit;
	u8 vwc;
	u32 vs;
	u32 sgls;
	u16 kas;
	u8 npss;
	u8 apsta;
	unsigned int kato;
	bool subsystem;
	unsigned long quirks;
	struct nvme_id_power_state psd[32];
	struct work_struct scan_work;
	struct work_struct async_event_work;
	struct delayed_work ka_work;

	/* Power saving configuration */
	u64 ps_max_latency_us;

	u32 hmpre;
	u32 hmmin;

	/* Fabrics only */
	u16 sqsize;
	u32 ioccsz;
	u32 iorcsz;
	u16 icdoff;
	u16 maxcmd;
	struct nvmf_ctrl_options *opts;
};

/*
 * An NVM Express namespace is equivalent to a SCSI LUN
 */
struct nvme_ns {
	struct list_head list;

	struct nvme_ctrl *ctrl;
	struct request_queue *queue;
	struct gendisk *disk;
	struct nvm_dev *ndev;
	struct kref kref;
	int instance;

	u8 eui[8];
	u8 uuid[16];

	unsigned ns_id;
	int lba_shift;
	u16 ms;
	bool ext;
	u8 pi_type;
	unsigned long flags;

#define NVME_NS_REMOVING 0
#define NVME_NS_DEAD     1

	u64 mode_select_num_blocks;
	u32 mode_select_block_len;
};

struct nvme_ctrl_ops {
	const char *name;
	struct module *module;
	unsigned int flags;
#define NVME_F_FABRICS			(1 << 0)
#define NVME_F_METADATA_SUPPORTED	(1 << 1)
	int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val);
	int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val);
	int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val);
	int (*reset_ctrl)(struct nvme_ctrl *ctrl);
	void (*free_ctrl)(struct nvme_ctrl *ctrl);
	void (*submit_async_event)(struct nvme_ctrl *ctrl, int aer_idx);
	int (*delete_ctrl)(struct nvme_ctrl *ctrl);
	const char *(*get_subsysnqn)(struct nvme_ctrl *ctrl);
	int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size);
};

static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
{
	u32 val = 0;

	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
		return false;
	return val & NVME_CSTS_RDY;
}

static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
{
	if (!ctrl->subsystem)
		return -ENOTTY;
	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
}

static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
{
	return (sector >> (ns->lba_shift - 9));
}

static inline void nvme_cleanup_cmd(struct request *req)
{
	if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
		kfree(page_address(req->special_vec.bv_page) +
		      req->special_vec.bv_offset);
	}
}

static inline void nvme_end_request(struct request *req, __le16 status,
		union nvme_result result)
{
	struct nvme_request *rq = nvme_req(req);

	rq->status = le16_to_cpu(status) >> 1;
	rq->result = result;
	blk_mq_complete_request(req);
}

void nvme_complete_rq(struct request *req);
void nvme_cancel_request(struct request *req, void *data, bool reserved);
bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
		enum nvme_ctrl_state new_state);
int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
		const struct nvme_ctrl_ops *ops, unsigned long quirks);
void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
void nvme_put_ctrl(struct nvme_ctrl *ctrl);
int nvme_init_identify(struct nvme_ctrl *ctrl);

void nvme_queue_scan(struct nvme_ctrl *ctrl);
void nvme_remove_namespaces(struct nvme_ctrl *ctrl);

int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
		bool send);

#define NVME_NR_AERS	1
void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
		union nvme_result *res);
void nvme_queue_async_events(struct nvme_ctrl *ctrl);

void nvme_stop_queues(struct nvme_ctrl *ctrl);
void nvme_start_queues(struct nvme_ctrl *ctrl);
void nvme_kill_queues(struct nvme_ctrl *ctrl);
void nvme_unfreeze(struct nvme_ctrl *ctrl);
void nvme_wait_freeze(struct nvme_ctrl *ctrl);
void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
void nvme_start_freeze(struct nvme_ctrl *ctrl);

#define NVME_QID_ANY -1
struct request *nvme_alloc_request(struct request_queue *q,
		struct nvme_command *cmd, unsigned int flags, int qid);
blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
		struct nvme_command *cmd);
int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		void *buf, unsigned bufflen);
int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		union nvme_result *result, void *buffer, unsigned bufflen,
		unsigned timeout, int qid, int at_head, int flags);
int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
		void __user *ubuffer, unsigned bufflen, u32 *result,
		unsigned timeout);
int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
		void __user *ubuffer, unsigned bufflen,
		void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
		u32 *result, unsigned timeout);
int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id);
int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
		struct nvme_id_ns **id);
int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log);
int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
		      void *buffer, size_t buflen, u32 *result);
int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
		      void *buffer, size_t buflen, u32 *result);
int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);
void nvme_start_keep_alive(struct nvme_ctrl *ctrl);
void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);

struct sg_io_hdr;

int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr);
int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
int nvme_sg_get_version_num(int __user *ip);

#ifdef CONFIG_NVM
int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id);
int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node);
void nvme_nvm_unregister(struct nvme_ns *ns);
int nvme_nvm_register_sysfs(struct nvme_ns *ns);
void nvme_nvm_unregister_sysfs(struct nvme_ns *ns);
int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg);
#else
static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name,
				    int node)
{
	return 0;
}

static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns)
{
	return 0;
}
static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {};
static inline int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id)
{
	return 0;
}
static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
							unsigned long arg)
{
	return -ENOTTY;
}
#endif /* CONFIG_NVM */

static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev)
{
	return dev_to_disk(dev)->private_data;
}

int __init nvme_core_init(void);
void nvme_core_exit(void);

#endif /* _NVME_H */
Commit	Line	Data
f11bb3e2 CH	1	/*
	2	* Copyright (c) 2011-2014, Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*/
	13
	14	#ifndef _NVME_H
	15	#define _NVME_H
	16
	17	#include <linux/nvme.h>
	18	#include <linux/pci.h>
	19	#include <linux/kref.h>
	20	#include <linux/blk-mq.h>
b0b4e09c	21	#include <linux/lightnvm.h>
a98e58e5	22	#include <linux/sed-opal.h>
f11bb3e2 CH	23
	24	extern unsigned char nvme_io_timeout;
	25	#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
	26
21d34711 CH	27	extern unsigned char admin_timeout;
	28	#define ADMIN_TIMEOUT (admin_timeout * HZ)
	29
5fd4ce1b CH	30	extern unsigned char shutdown_timeout;
	31	#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
	32
038bd4cb SG	33	#define NVME_DEFAULT_KATO 5
	34	#define NVME_KATO_GRACE 10
	35
9a6327d2 SG	36	extern struct workqueue_struct *nvme_wq;
9a6327d2 SG	37
ca064085 MB	38	enum {
	39	NVME_NS_LBA = 0,
	40	NVME_NS_LIGHTNVM = 1,
	41	};
	42
f11bb3e2	43	/*
106198ed CH	44	* List of workarounds for devices that required behavior not specified in
106198ed CH	45	* the standard.
f11bb3e2	46	*/
106198ed CH	47	enum nvme_quirks {
	48	/*
	49	* Prefers I/O aligned to a stripe size specified in a vendor
	50	* specific Identify field.
	51	*/
	52	NVME_QUIRK_STRIPE_SIZE = (1 << 0),
540c801c KB	53
	54	/*
	55	* The controller doesn't handle Identify value others than 0 or 1
	56	* correctly.
	57	*/
	58	NVME_QUIRK_IDENTIFY_CNS = (1 << 1),
08095e70 KB	59
08095e70 KB	60	/*
e850fd16 CH	61	* The controller deterministically returns O's on reads to
e850fd16 CH	62	* logical blocks that deallocate was called on.
08095e70	63	*/
e850fd16	64	NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2),
54adc010 GP	65
	66	/*
	67	* The controller needs a delay before starts checking the device
	68	* readiness, which is done by reading the NVME_CSTS_RDY bit.
	69	*/
	70	NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3),
c5552fde AL	71
	72	/*
	73	* APST should not be used.
	74	*/
	75	NVME_QUIRK_NO_APST = (1 << 4),
ff5350a8 AL	76
	77	/*
	78	* The deepest sleep state should not be used.
	79	*/
	80	NVME_QUIRK_NO_DEEPEST_PS = (1 << 5),
106198ed CH	81	};
106198ed CH	82
d49187e9 CH	83	/*
	84	* Common request structure for NVMe passthrough. All drivers must have
	85	* this structure as the first member of their request-private data.
	86	*/
	87	struct nvme_request {
	88	struct nvme_command *cmd;
	89	union nvme_result result;
44e44b29	90	u8 retries;
27fa9bc5 CH	91	u8 flags;
	92	u16 status;
	93	};
	94
	95	enum {
	96	NVME_REQ_CANCELLED = (1 << 0),
d49187e9 CH	97	};
	98
	99	static inline struct nvme_request nvme_req(struct request req)
	100	{
	101	return blk_mq_rq_to_pdu(req);
	102	}
	103
54adc010 GP	104	/* The below value is the specific amount of delay needed before checking
	105	* readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
	106	* NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
	107	* found empirically.
	108	*/
	109	#define NVME_QUIRK_DELAY_AMOUNT 2000
	110
bb8d261e CH	111	enum nvme_ctrl_state {
	112	NVME_CTRL_NEW,
	113	NVME_CTRL_LIVE,
	114	NVME_CTRL_RESETTING,
def61eca	115	NVME_CTRL_RECONNECTING,
bb8d261e	116	NVME_CTRL_DELETING,
0ff9d4e1	117	NVME_CTRL_DEAD,
bb8d261e CH	118	};
bb8d261e CH	119
1c63dc66	120	struct nvme_ctrl {
bb8d261e	121	enum nvme_ctrl_state state;
bd4da3ab	122	bool identified;
bb8d261e	123	spinlock_t lock;
1c63dc66	124	const struct nvme_ctrl_ops *ops;
f11bb3e2	125	struct request_queue *admin_q;
07bfcd09	126	struct request_queue *connect_q;
f11bb3e2	127	struct device *dev;
1673f1f0	128	struct kref kref;
f11bb3e2	129	int instance;
5bae7f73	130	struct blk_mq_tag_set *tagset;
f11bb3e2	131	struct list_head namespaces;
69d3b8ac	132	struct mutex namespaces_mutex;
5bae7f73	133	struct device device; / char device */
f3ca80fc	134	struct list_head node;
075790eb	135	struct ida ns_ida;
1c63dc66	136
4f1244c8	137	struct opal_dev *opal_dev;
a98e58e5	138
f11bb3e2 CH	139	char name[12];
	140	char serial[20];
	141	char model[40];
	142	char firmware_rev[8];
76e3914a	143	u16 cntlid;
5fd4ce1b CH	144
	145	u32 ctrl_config;
	146
	147	u32 page_size;
f11bb3e2	148	u32 max_hw_sectors;
f11bb3e2	149	u16 oncs;
118472ab	150	u16 vid;
8a9ae523	151	u16 oacs;
6bf25d16	152	atomic_t abort_limit;
f11bb3e2 CH	153	u8 event_limit;
f11bb3e2 CH	154	u8 vwc;
f3ca80fc	155	u32 vs;
07bfcd09	156	u32 sgls;
038bd4cb	157	u16 kas;
c5552fde AL	158	u8 npss;
c5552fde AL	159	u8 apsta;
038bd4cb	160	unsigned int kato;
f3ca80fc	161	bool subsystem;
106198ed	162	unsigned long quirks;
c5552fde	163	struct nvme_id_power_state psd[32];
5955be21	164	struct work_struct scan_work;
f866fc42	165	struct work_struct async_event_work;
038bd4cb	166	struct delayed_work ka_work;
07bfcd09	167
c5552fde AL	168	/* Power saving configuration */
	169	u64 ps_max_latency_us;
	170
fe6d53c9 CH	171	u32 hmpre;
	172	u32 hmmin;
	173
07bfcd09 CH	174	/* Fabrics only */
	175	u16 sqsize;
	176	u32 ioccsz;
	177	u32 iorcsz;
	178	u16 icdoff;
	179	u16 maxcmd;
	180	struct nvmf_ctrl_options *opts;
f11bb3e2 CH	181	};
	182
	183	/*
	184	* An NVM Express namespace is equivalent to a SCSI LUN
	185	*/
	186	struct nvme_ns {
	187	struct list_head list;
	188
1c63dc66	189	struct nvme_ctrl *ctrl;
f11bb3e2 CH	190	struct request_queue *queue;
f11bb3e2 CH	191	struct gendisk *disk;
b0b4e09c	192	struct nvm_dev *ndev;
f11bb3e2	193	struct kref kref;
075790eb	194	int instance;
f11bb3e2	195
2b9b6e86 KB	196	u8 eui[8];
	197	u8 uuid[16];
	198
f11bb3e2 CH	199	unsigned ns_id;
	200	int lba_shift;
	201	u16 ms;
	202	bool ext;
	203	u8 pi_type;
646017a6 KB	204	unsigned long flags;
	205
	206	#define NVME_NS_REMOVING 0
69d9a99c	207	#define NVME_NS_DEAD 1
646017a6	208
f11bb3e2 CH	209	u64 mode_select_num_blocks;
	210	u32 mode_select_block_len;
	211	};
	212
1c63dc66	213	struct nvme_ctrl_ops {
1a353d85	214	const char *name;
e439bb12	215	struct module *module;
d3d5b87d CH	216	unsigned int flags;
d3d5b87d CH	217	#define NVME_F_FABRICS (1 << 0)
c81bfba9	218	#define NVME_F_METADATA_SUPPORTED (1 << 1)
1c63dc66	219	int (reg_read32)(struct nvme_ctrl ctrl, u32 off, u32 *val);
5fd4ce1b	220	int (reg_write32)(struct nvme_ctrl ctrl, u32 off, u32 val);
7fd8930f	221	int (reg_read64)(struct nvme_ctrl ctrl, u32 off, u64 *val);
f3ca80fc	222	int (reset_ctrl)(struct nvme_ctrl ctrl);
1673f1f0	223	void (free_ctrl)(struct nvme_ctrl ctrl);
f866fc42	224	void (submit_async_event)(struct nvme_ctrl ctrl, int aer_idx);
1a353d85 ML	225	int (delete_ctrl)(struct nvme_ctrl ctrl);
	226	const char (get_subsysnqn)(struct nvme_ctrl *ctrl);
	227	int (get_address)(struct nvme_ctrl ctrl, char *buf, int size);
f11bb3e2 CH	228	};
f11bb3e2 CH	229
1c63dc66 CH	230	static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
	231	{
	232	u32 val = 0;
	233
	234	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
	235	return false;
	236	return val & NVME_CSTS_RDY;
	237	}
	238
f3ca80fc CH	239	static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
	240	{
	241	if (!ctrl->subsystem)
	242	return -ENOTTY;
	243	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
	244	}
	245
f11bb3e2 CH	246	static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
	247	{
	248	return (sector >> (ns->lba_shift - 9));
	249	}
	250
6904242d ML	251	static inline void nvme_cleanup_cmd(struct request *req)
6904242d ML	252	{
f9d03f96 CH	253	if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
	254	kfree(page_address(req->special_vec.bv_page) +
	255	req->special_vec.bv_offset);
	256	}
6904242d ML	257	}
6904242d ML	258
27fa9bc5 CH	259	static inline void nvme_end_request(struct request *req, __le16 status,
27fa9bc5 CH	260	union nvme_result result)
15a190f7	261	{
27fa9bc5	262	struct nvme_request *rq = nvme_req(req);
15a190f7	263
27fa9bc5 CH	264	rq->status = le16_to_cpu(status) >> 1;
27fa9bc5 CH	265	rq->result = result;
08e0029a	266	blk_mq_complete_request(req);
7688faa6 CH	267	}
7688faa6 CH	268
77f02a7a	269	void nvme_complete_rq(struct request *req);
c55a2fd4	270	void nvme_cancel_request(struct request req, void data, bool reserved);
bb8d261e CH	271	bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
bb8d261e CH	272	enum nvme_ctrl_state new_state);
5fd4ce1b CH	273	int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	274	int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	275	int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
f3ca80fc CH	276	int nvme_init_ctrl(struct nvme_ctrl ctrl, struct device dev,
f3ca80fc CH	277	const struct nvme_ctrl_ops *ops, unsigned long quirks);
53029b04	278	void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
1673f1f0	279	void nvme_put_ctrl(struct nvme_ctrl *ctrl);
7fd8930f	280	int nvme_init_identify(struct nvme_ctrl *ctrl);
5bae7f73	281
5955be21	282	void nvme_queue_scan(struct nvme_ctrl *ctrl);
5bae7f73	283	void nvme_remove_namespaces(struct nvme_ctrl *ctrl);
1673f1f0	284
4f1244c8 CH	285	int nvme_sec_submit(void data, u16 spsp, u8 secp, void buffer, size_t len,
4f1244c8 CH	286	bool send);
a98e58e5	287
f866fc42	288	#define NVME_NR_AERS 1
7bf58533 CH	289	void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
7bf58533 CH	290	union nvme_result *res);
f866fc42 CH	291	void nvme_queue_async_events(struct nvme_ctrl *ctrl);
f866fc42 CH	292
25646264 KB	293	void nvme_stop_queues(struct nvme_ctrl *ctrl);
25646264 KB	294	void nvme_start_queues(struct nvme_ctrl *ctrl);
69d9a99c	295	void nvme_kill_queues(struct nvme_ctrl *ctrl);
302ad8cc KB	296	void nvme_unfreeze(struct nvme_ctrl *ctrl);
	297	void nvme_wait_freeze(struct nvme_ctrl *ctrl);
	298	void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
	299	void nvme_start_freeze(struct nvme_ctrl *ctrl);
363c9aac	300
eb71f435	301	#define NVME_QID_ANY -1
4160982e	302	struct request nvme_alloc_request(struct request_queue q,
eb71f435	303	struct nvme_command *cmd, unsigned int flags, int qid);
fc17b653	304	blk_status_t nvme_setup_cmd(struct nvme_ns ns, struct request req,
8093f7ca	305	struct nvme_command *cmd);
f11bb3e2 CH	306	int nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
	307	void *buf, unsigned bufflen);
	308	int __nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
d49187e9	309	union nvme_result result, void buffer, unsigned bufflen,
eb71f435	310	unsigned timeout, int qid, int at_head, int flags);
4160982e CH	311	int nvme_submit_user_cmd(struct request_queue q, struct nvme_command cmd,
	312	void __user ubuffer, unsigned bufflen, u32 result,
	313	unsigned timeout);
0b7f1f26 KB	314	int __nvme_submit_user_cmd(struct request_queue q, struct nvme_command cmd,
	315	void __user *ubuffer, unsigned bufflen,
	316	void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
f11bb3e2	317	u32 *result, unsigned timeout);
1c63dc66 CH	318	int nvme_identify_ctrl(struct nvme_ctrl dev, struct nvme_id_ctrl *id);
1c63dc66 CH	319	int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
f11bb3e2	320	struct nvme_id_ns **id);
1c63dc66 CH	321	int nvme_get_log_page(struct nvme_ctrl dev, struct nvme_smart_log *log);
1c63dc66 CH	322	int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
1a6fe74d	323	void buffer, size_t buflen, u32 result);
1c63dc66	324	int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
1a6fe74d	325	void buffer, size_t buflen, u32 result);
9a0be7ab	326	int nvme_set_queue_count(struct nvme_ctrl ctrl, int count);
038bd4cb SG	327	void nvme_start_keep_alive(struct nvme_ctrl *ctrl);
038bd4cb SG	328	void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
f11bb3e2 CH	329
	330	struct sg_io_hdr;
	331
	332	int nvme_sg_io(struct nvme_ns ns, struct sg_io_hdr __user u_hdr);
	333	int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
	334	int nvme_sg_get_version_num(int __user *ip);
	335
c4699e70	336	#ifdef CONFIG_NVM
ca064085	337	int nvme_nvm_ns_supported(struct nvme_ns ns, struct nvme_id_ns id);
3dc87dd0	338	int nvme_nvm_register(struct nvme_ns ns, char disk_name, int node);
b0b4e09c	339	void nvme_nvm_unregister(struct nvme_ns *ns);
3dc87dd0 MB	340	int nvme_nvm_register_sysfs(struct nvme_ns *ns);
3dc87dd0 MB	341	void nvme_nvm_unregister_sysfs(struct nvme_ns *ns);
84d4add7	342	int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg);
c4699e70	343	#else
b0b4e09c	344	static inline int nvme_nvm_register(struct nvme_ns ns, char disk_name,
3dc87dd0	345	int node)
c4699e70 KB	346	{
	347	return 0;
	348	}
	349
b0b4e09c	350	static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
3dc87dd0 MB	351	static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns)
	352	{
	353	return 0;
	354	}
	355	static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {};
c4699e70 KB	356	static inline int nvme_nvm_ns_supported(struct nvme_ns ns, struct nvme_id_ns id)
	357	{
	358	return 0;
	359	}
84d4add7 MB	360	static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
	361	unsigned long arg)
	362	{
	363	return -ENOTTY;
	364	}
3dc87dd0 MB	365	#endif /* CONFIG_NVM */
3dc87dd0 MB	366
40267efd SL	367	static inline struct nvme_ns nvme_get_ns_from_dev(struct device dev)
	368	{
	369	return dev_to_disk(dev)->private_data;
	370	}
ca064085	371
5bae7f73 CH	372	int __init nvme_core_init(void);
	373	void nvme_core_exit(void);
	374
f11bb3e2	375	#endif /* _NVME_H */