[mirror_ubuntu-hirsute-kernel.git] / drivers / nvme / host / nvme.h

/*
 * Copyright (c) 2011-2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef _NVME_H
#define _NVME_H

#include <linux/nvme.h>
#include <linux/pci.h>
#include <linux/kref.h>
#include <linux/blk-mq.h>
#include <linux/lightnvm.h>
#include <linux/sed-opal.h>

enum {
	/*
	 * Driver internal status code for commands that were cancelled due
	 * to timeouts or controller shutdown.  The value is negative so
	 * that it a) doesn't overlap with the unsigned hardware error codes,
	 * and b) can easily be tested for.
	 */
	NVME_SC_CANCELLED		= -EINTR,
};

extern unsigned char nvme_io_timeout;
#define NVME_IO_TIMEOUT	(nvme_io_timeout * HZ)

extern unsigned char admin_timeout;
#define ADMIN_TIMEOUT	(admin_timeout * HZ)

extern unsigned char shutdown_timeout;
#define SHUTDOWN_TIMEOUT	(shutdown_timeout * HZ)

#define NVME_DEFAULT_KATO	5
#define NVME_KATO_GRACE		10

enum {
	NVME_NS_LBA		= 0,
	NVME_NS_LIGHTNVM	= 1,
};

/*
 * List of workarounds for devices that required behavior not specified in
 * the standard.
 */
enum nvme_quirks {
	/*
	 * Prefers I/O aligned to a stripe size specified in a vendor
	 * specific Identify field.
	 */
	NVME_QUIRK_STRIPE_SIZE			= (1 << 0),

	/*
	 * The controller doesn't handle Identify value others than 0 or 1
	 * correctly.
	 */
	NVME_QUIRK_IDENTIFY_CNS			= (1 << 1),

	/*
	 * The controller deterministically returns O's on reads to
	 * logical blocks that deallocate was called on.
	 */
	NVME_QUIRK_DEALLOCATE_ZEROES		= (1 << 2),

	/*
	 * The controller needs a delay before starts checking the device
	 * readiness, which is done by reading the NVME_CSTS_RDY bit.
	 */
	NVME_QUIRK_DELAY_BEFORE_CHK_RDY		= (1 << 3),

	/*
	 * APST should not be used.
	 */
	NVME_QUIRK_NO_APST			= (1 << 4),
};

/*
 * Common request structure for NVMe passthrough.  All drivers must have
 * this structure as the first member of their request-private data.
 */
struct nvme_request {
	struct nvme_command	*cmd;
	union nvme_result	result;
	u8			retries;
};

static inline struct nvme_request *nvme_req(struct request *req)
{
	return blk_mq_rq_to_pdu(req);
}

/* The below value is the specific amount of delay needed before checking
 * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
 * found empirically.
 */
#define NVME_QUIRK_DELAY_AMOUNT		2000

enum nvme_ctrl_state {
	NVME_CTRL_NEW,
	NVME_CTRL_LIVE,
	NVME_CTRL_RESETTING,
	NVME_CTRL_RECONNECTING,
	NVME_CTRL_DELETING,
	NVME_CTRL_DEAD,
};

struct nvme_ctrl {
	enum nvme_ctrl_state state;
	bool identified;
	spinlock_t lock;
	const struct nvme_ctrl_ops *ops;
	struct request_queue *admin_q;
	struct request_queue *connect_q;
	struct device *dev;
	struct kref kref;
	int instance;
	struct blk_mq_tag_set *tagset;
	struct list_head namespaces;
	struct mutex namespaces_mutex;
	struct device *device;	/* char device */
	struct list_head node;
	struct ida ns_ida;

	struct opal_dev *opal_dev;

	char name[12];
	char serial[20];
	char model[40];
	char firmware_rev[8];
	u16 cntlid;

	u32 ctrl_config;

	u32 page_size;
	u32 max_hw_sectors;
	u16 oncs;
	u16 vid;
	u16 oacs;
	atomic_t abort_limit;
	u8 event_limit;
	u8 vwc;
	u32 vs;
	u32 sgls;
	u16 kas;
	u8 npss;
	u8 apsta;
	unsigned int kato;
	bool subsystem;
	unsigned long quirks;
	struct nvme_id_power_state psd[32];
	struct work_struct scan_work;
	struct work_struct async_event_work;
	struct delayed_work ka_work;

	/* Power saving configuration */
	u64 ps_max_latency_us;

	/* Fabrics only */
	u16 sqsize;
	u32 ioccsz;
	u32 iorcsz;
	u16 icdoff;
	u16 maxcmd;
	struct nvmf_ctrl_options *opts;
};

/*
 * An NVM Express namespace is equivalent to a SCSI LUN
 */
struct nvme_ns {
	struct list_head list;

	struct nvme_ctrl *ctrl;
	struct request_queue *queue;
	struct gendisk *disk;
	struct nvm_dev *ndev;
	struct kref kref;
	int instance;

	u8 eui[8];
	u8 uuid[16];

	unsigned ns_id;
	int lba_shift;
	u16 ms;
	bool ext;
	u8 pi_type;
	unsigned long flags;

#define NVME_NS_REMOVING 0
#define NVME_NS_DEAD     1

	u64 mode_select_num_blocks;
	u32 mode_select_block_len;
};

struct nvme_ctrl_ops {
	const char *name;
	struct module *module;
	bool is_fabrics;
	int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val);
	int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val);
	int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val);
	int (*reset_ctrl)(struct nvme_ctrl *ctrl);
	void (*free_ctrl)(struct nvme_ctrl *ctrl);
	void (*submit_async_event)(struct nvme_ctrl *ctrl, int aer_idx);
	int (*delete_ctrl)(struct nvme_ctrl *ctrl);
	const char *(*get_subsysnqn)(struct nvme_ctrl *ctrl);
	int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size);
};

static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
{
	u32 val = 0;

	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
		return false;
	return val & NVME_CSTS_RDY;
}

static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
{
	if (!ctrl->subsystem)
		return -ENOTTY;
	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
}

static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
{
	return (sector >> (ns->lba_shift - 9));
}

static inline void nvme_cleanup_cmd(struct request *req)
{
	if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
		kfree(page_address(req->special_vec.bv_page) +
		      req->special_vec.bv_offset);
	}
}

static inline int nvme_error_status(u16 status)
{
	switch (status & 0x7ff) {
	case NVME_SC_SUCCESS:
		return 0;
	case NVME_SC_CAP_EXCEEDED:
		return -ENOSPC;
	default:
		return -EIO;
	}
}

void nvme_complete_rq(struct request *req);
void nvme_cancel_request(struct request *req, void *data, bool reserved);
bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
		enum nvme_ctrl_state new_state);
int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
		const struct nvme_ctrl_ops *ops, unsigned long quirks);
void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
void nvme_put_ctrl(struct nvme_ctrl *ctrl);
int nvme_init_identify(struct nvme_ctrl *ctrl);

void nvme_queue_scan(struct nvme_ctrl *ctrl);
void nvme_remove_namespaces(struct nvme_ctrl *ctrl);

int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
		bool send);

#define NVME_NR_AERS	1
void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
		union nvme_result *res);
void nvme_queue_async_events(struct nvme_ctrl *ctrl);

void nvme_stop_queues(struct nvme_ctrl *ctrl);
void nvme_start_queues(struct nvme_ctrl *ctrl);
void nvme_kill_queues(struct nvme_ctrl *ctrl);
void nvme_unfreeze(struct nvme_ctrl *ctrl);
void nvme_wait_freeze(struct nvme_ctrl *ctrl);
void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
void nvme_start_freeze(struct nvme_ctrl *ctrl);

#define NVME_QID_ANY -1
struct request *nvme_alloc_request(struct request_queue *q,
		struct nvme_command *cmd, unsigned int flags, int qid);
int nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
		struct nvme_command *cmd);
int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		void *buf, unsigned bufflen);
int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		union nvme_result *result, void *buffer, unsigned bufflen,
		unsigned timeout, int qid, int at_head, int flags);
int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
		void __user *ubuffer, unsigned bufflen, u32 *result,
		unsigned timeout);
int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
		void __user *ubuffer, unsigned bufflen,
		void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
		u32 *result, unsigned timeout);
int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id);
int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
		struct nvme_id_ns **id);
int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log);
int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
		      void *buffer, size_t buflen, u32 *result);
int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
		      void *buffer, size_t buflen, u32 *result);
int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);
void nvme_start_keep_alive(struct nvme_ctrl *ctrl);
void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);

struct sg_io_hdr;

int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr);
int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
int nvme_sg_get_version_num(int __user *ip);

#ifdef CONFIG_NVM
int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id);
int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node);
void nvme_nvm_unregister(struct nvme_ns *ns);
int nvme_nvm_register_sysfs(struct nvme_ns *ns);
void nvme_nvm_unregister_sysfs(struct nvme_ns *ns);
int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg);
#else
static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name,
				    int node)
{
	return 0;
}

static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns)
{
	return 0;
}
static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {};
static inline int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id)
{
	return 0;
}
static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
							unsigned long arg)
{
	return -ENOTTY;
}
#endif /* CONFIG_NVM */

static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev)
{
	return dev_to_disk(dev)->private_data;
}

int __init nvme_core_init(void);
void nvme_core_exit(void);

#endif /* _NVME_H */
Commit	Line	Data
f11bb3e2 CH	1	/*
	2	* Copyright (c) 2011-2014, Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*/
	13
	14	#ifndef _NVME_H
	15	#define _NVME_H
	16
	17	#include <linux/nvme.h>
	18	#include <linux/pci.h>
	19	#include <linux/kref.h>
	20	#include <linux/blk-mq.h>
b0b4e09c	21	#include <linux/lightnvm.h>
a98e58e5	22	#include <linux/sed-opal.h>
f11bb3e2	23
297465c8 CH	24	enum {
	25	/*
	26	* Driver internal status code for commands that were cancelled due
	27	* to timeouts or controller shutdown. The value is negative so
	28	* that it a) doesn't overlap with the unsigned hardware error codes,
	29	* and b) can easily be tested for.
	30	*/
	31	NVME_SC_CANCELLED = -EINTR,
	32	};
	33
f11bb3e2 CH	34	extern unsigned char nvme_io_timeout;
	35	#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
	36
21d34711 CH	37	extern unsigned char admin_timeout;
	38	#define ADMIN_TIMEOUT (admin_timeout * HZ)
	39
5fd4ce1b CH	40	extern unsigned char shutdown_timeout;
	41	#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
	42
038bd4cb SG	43	#define NVME_DEFAULT_KATO 5
	44	#define NVME_KATO_GRACE 10
	45
ca064085 MB	46	enum {
	47	NVME_NS_LBA = 0,
	48	NVME_NS_LIGHTNVM = 1,
	49	};
	50
f11bb3e2	51	/*
106198ed CH	52	* List of workarounds for devices that required behavior not specified in
106198ed CH	53	* the standard.
f11bb3e2	54	*/
106198ed CH	55	enum nvme_quirks {
	56	/*
	57	* Prefers I/O aligned to a stripe size specified in a vendor
	58	* specific Identify field.
	59	*/
	60	NVME_QUIRK_STRIPE_SIZE = (1 << 0),
540c801c KB	61
	62	/*
	63	* The controller doesn't handle Identify value others than 0 or 1
	64	* correctly.
	65	*/
	66	NVME_QUIRK_IDENTIFY_CNS = (1 << 1),
08095e70 KB	67
08095e70 KB	68	/*
e850fd16 CH	69	* The controller deterministically returns O's on reads to
e850fd16 CH	70	* logical blocks that deallocate was called on.
08095e70	71	*/
e850fd16	72	NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2),
54adc010 GP	73
	74	/*
	75	* The controller needs a delay before starts checking the device
	76	* readiness, which is done by reading the NVME_CSTS_RDY bit.
	77	*/
	78	NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3),
c5552fde AL	79
	80	/*
	81	* APST should not be used.
	82	*/
	83	NVME_QUIRK_NO_APST = (1 << 4),
106198ed CH	84	};
106198ed CH	85
d49187e9 CH	86	/*
	87	* Common request structure for NVMe passthrough. All drivers must have
	88	* this structure as the first member of their request-private data.
	89	*/
	90	struct nvme_request {
	91	struct nvme_command *cmd;
	92	union nvme_result result;
44e44b29	93	u8 retries;
d49187e9 CH	94	};
	95
	96	static inline struct nvme_request nvme_req(struct request req)
	97	{
	98	return blk_mq_rq_to_pdu(req);
	99	}
	100
54adc010 GP	101	/* The below value is the specific amount of delay needed before checking
	102	* readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
	103	* NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
	104	* found empirically.
	105	*/
	106	#define NVME_QUIRK_DELAY_AMOUNT 2000
	107
bb8d261e CH	108	enum nvme_ctrl_state {
	109	NVME_CTRL_NEW,
	110	NVME_CTRL_LIVE,
	111	NVME_CTRL_RESETTING,
def61eca	112	NVME_CTRL_RECONNECTING,
bb8d261e	113	NVME_CTRL_DELETING,
0ff9d4e1	114	NVME_CTRL_DEAD,
bb8d261e CH	115	};
bb8d261e CH	116
1c63dc66	117	struct nvme_ctrl {
bb8d261e	118	enum nvme_ctrl_state state;
bd4da3ab	119	bool identified;
bb8d261e	120	spinlock_t lock;
1c63dc66	121	const struct nvme_ctrl_ops *ops;
f11bb3e2	122	struct request_queue *admin_q;
07bfcd09	123	struct request_queue *connect_q;
f11bb3e2	124	struct device *dev;
1673f1f0	125	struct kref kref;
f11bb3e2	126	int instance;
5bae7f73	127	struct blk_mq_tag_set *tagset;
f11bb3e2	128	struct list_head namespaces;
69d3b8ac	129	struct mutex namespaces_mutex;
5bae7f73	130	struct device device; / char device */
f3ca80fc	131	struct list_head node;
075790eb	132	struct ida ns_ida;
1c63dc66	133
4f1244c8	134	struct opal_dev *opal_dev;
a98e58e5	135
f11bb3e2 CH	136	char name[12];
	137	char serial[20];
	138	char model[40];
	139	char firmware_rev[8];
76e3914a	140	u16 cntlid;
5fd4ce1b CH	141
	142	u32 ctrl_config;
	143
	144	u32 page_size;
f11bb3e2	145	u32 max_hw_sectors;
f11bb3e2	146	u16 oncs;
118472ab	147	u16 vid;
8a9ae523	148	u16 oacs;
6bf25d16	149	atomic_t abort_limit;
f11bb3e2 CH	150	u8 event_limit;
f11bb3e2 CH	151	u8 vwc;
f3ca80fc	152	u32 vs;
07bfcd09	153	u32 sgls;
038bd4cb	154	u16 kas;
c5552fde AL	155	u8 npss;
c5552fde AL	156	u8 apsta;
038bd4cb	157	unsigned int kato;
f3ca80fc	158	bool subsystem;
106198ed	159	unsigned long quirks;
c5552fde	160	struct nvme_id_power_state psd[32];
5955be21	161	struct work_struct scan_work;
f866fc42	162	struct work_struct async_event_work;
038bd4cb	163	struct delayed_work ka_work;
07bfcd09	164
c5552fde AL	165	/* Power saving configuration */
	166	u64 ps_max_latency_us;
	167
07bfcd09 CH	168	/* Fabrics only */
	169	u16 sqsize;
	170	u32 ioccsz;
	171	u32 iorcsz;
	172	u16 icdoff;
	173	u16 maxcmd;
	174	struct nvmf_ctrl_options *opts;
f11bb3e2 CH	175	};
	176
	177	/*
	178	* An NVM Express namespace is equivalent to a SCSI LUN
	179	*/
	180	struct nvme_ns {
	181	struct list_head list;
	182
1c63dc66	183	struct nvme_ctrl *ctrl;
f11bb3e2 CH	184	struct request_queue *queue;
f11bb3e2 CH	185	struct gendisk *disk;
b0b4e09c	186	struct nvm_dev *ndev;
f11bb3e2	187	struct kref kref;
075790eb	188	int instance;
f11bb3e2	189
2b9b6e86 KB	190	u8 eui[8];
	191	u8 uuid[16];
	192
f11bb3e2 CH	193	unsigned ns_id;
	194	int lba_shift;
	195	u16 ms;
	196	bool ext;
	197	u8 pi_type;
646017a6 KB	198	unsigned long flags;
	199
	200	#define NVME_NS_REMOVING 0
69d9a99c	201	#define NVME_NS_DEAD 1
646017a6	202
f11bb3e2 CH	203	u64 mode_select_num_blocks;
	204	u32 mode_select_block_len;
	205	};
	206
1c63dc66	207	struct nvme_ctrl_ops {
1a353d85	208	const char *name;
e439bb12	209	struct module *module;
07bfcd09	210	bool is_fabrics;
1c63dc66	211	int (reg_read32)(struct nvme_ctrl ctrl, u32 off, u32 *val);
5fd4ce1b	212	int (reg_write32)(struct nvme_ctrl ctrl, u32 off, u32 val);
7fd8930f	213	int (reg_read64)(struct nvme_ctrl ctrl, u32 off, u64 *val);
f3ca80fc	214	int (reset_ctrl)(struct nvme_ctrl ctrl);
1673f1f0	215	void (free_ctrl)(struct nvme_ctrl ctrl);
f866fc42	216	void (submit_async_event)(struct nvme_ctrl ctrl, int aer_idx);
1a353d85 ML	217	int (delete_ctrl)(struct nvme_ctrl ctrl);
	218	const char (get_subsysnqn)(struct nvme_ctrl *ctrl);
	219	int (get_address)(struct nvme_ctrl ctrl, char *buf, int size);
f11bb3e2 CH	220	};
f11bb3e2 CH	221
1c63dc66 CH	222	static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
	223	{
	224	u32 val = 0;
	225
	226	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
	227	return false;
	228	return val & NVME_CSTS_RDY;
	229	}
	230
f3ca80fc CH	231	static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
	232	{
	233	if (!ctrl->subsystem)
	234	return -ENOTTY;
	235	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
	236	}
	237
f11bb3e2 CH	238	static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
	239	{
	240	return (sector >> (ns->lba_shift - 9));
	241	}
	242
6904242d ML	243	static inline void nvme_cleanup_cmd(struct request *req)
6904242d ML	244	{
f9d03f96 CH	245	if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
	246	kfree(page_address(req->special_vec.bv_page) +
	247	req->special_vec.bv_offset);
	248	}
6904242d ML	249	}
6904242d ML	250
15a190f7 CH	251	static inline int nvme_error_status(u16 status)
	252	{
	253	switch (status & 0x7ff) {
	254	case NVME_SC_SUCCESS:
	255	return 0;
	256	case NVME_SC_CAP_EXCEEDED:
	257	return -ENOSPC;
	258	default:
	259	return -EIO;
	260	}
	261	}
	262
77f02a7a	263	void nvme_complete_rq(struct request *req);
c55a2fd4	264	void nvme_cancel_request(struct request req, void data, bool reserved);
bb8d261e CH	265	bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
bb8d261e CH	266	enum nvme_ctrl_state new_state);
5fd4ce1b CH	267	int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	268	int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	269	int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
f3ca80fc CH	270	int nvme_init_ctrl(struct nvme_ctrl ctrl, struct device dev,
f3ca80fc CH	271	const struct nvme_ctrl_ops *ops, unsigned long quirks);
53029b04	272	void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
1673f1f0	273	void nvme_put_ctrl(struct nvme_ctrl *ctrl);
7fd8930f	274	int nvme_init_identify(struct nvme_ctrl *ctrl);
5bae7f73	275
5955be21	276	void nvme_queue_scan(struct nvme_ctrl *ctrl);
5bae7f73	277	void nvme_remove_namespaces(struct nvme_ctrl *ctrl);
1673f1f0	278
4f1244c8 CH	279	int nvme_sec_submit(void data, u16 spsp, u8 secp, void buffer, size_t len,
4f1244c8 CH	280	bool send);
a98e58e5	281
f866fc42	282	#define NVME_NR_AERS 1
7bf58533 CH	283	void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
7bf58533 CH	284	union nvme_result *res);
f866fc42 CH	285	void nvme_queue_async_events(struct nvme_ctrl *ctrl);
f866fc42 CH	286
25646264 KB	287	void nvme_stop_queues(struct nvme_ctrl *ctrl);
25646264 KB	288	void nvme_start_queues(struct nvme_ctrl *ctrl);
69d9a99c	289	void nvme_kill_queues(struct nvme_ctrl *ctrl);
302ad8cc KB	290	void nvme_unfreeze(struct nvme_ctrl *ctrl);
	291	void nvme_wait_freeze(struct nvme_ctrl *ctrl);
	292	void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
	293	void nvme_start_freeze(struct nvme_ctrl *ctrl);
363c9aac	294
eb71f435	295	#define NVME_QID_ANY -1
4160982e	296	struct request nvme_alloc_request(struct request_queue q,
eb71f435	297	struct nvme_command *cmd, unsigned int flags, int qid);
8093f7ca ML	298	int nvme_setup_cmd(struct nvme_ns ns, struct request req,
8093f7ca ML	299	struct nvme_command *cmd);
f11bb3e2 CH	300	int nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
	301	void *buf, unsigned bufflen);
	302	int __nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
d49187e9	303	union nvme_result result, void buffer, unsigned bufflen,
eb71f435	304	unsigned timeout, int qid, int at_head, int flags);
4160982e CH	305	int nvme_submit_user_cmd(struct request_queue q, struct nvme_command cmd,
	306	void __user ubuffer, unsigned bufflen, u32 result,
	307	unsigned timeout);
0b7f1f26 KB	308	int __nvme_submit_user_cmd(struct request_queue q, struct nvme_command cmd,
	309	void __user *ubuffer, unsigned bufflen,
	310	void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
f11bb3e2	311	u32 *result, unsigned timeout);
1c63dc66 CH	312	int nvme_identify_ctrl(struct nvme_ctrl dev, struct nvme_id_ctrl *id);
1c63dc66 CH	313	int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
f11bb3e2	314	struct nvme_id_ns **id);
1c63dc66 CH	315	int nvme_get_log_page(struct nvme_ctrl dev, struct nvme_smart_log *log);
1c63dc66 CH	316	int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
1a6fe74d	317	void buffer, size_t buflen, u32 result);
1c63dc66	318	int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
1a6fe74d	319	void buffer, size_t buflen, u32 result);
9a0be7ab	320	int nvme_set_queue_count(struct nvme_ctrl ctrl, int count);
038bd4cb SG	321	void nvme_start_keep_alive(struct nvme_ctrl *ctrl);
038bd4cb SG	322	void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
f11bb3e2 CH	323
	324	struct sg_io_hdr;
	325
	326	int nvme_sg_io(struct nvme_ns ns, struct sg_io_hdr __user u_hdr);
	327	int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
	328	int nvme_sg_get_version_num(int __user *ip);
	329
c4699e70	330	#ifdef CONFIG_NVM
ca064085	331	int nvme_nvm_ns_supported(struct nvme_ns ns, struct nvme_id_ns id);
3dc87dd0	332	int nvme_nvm_register(struct nvme_ns ns, char disk_name, int node);
b0b4e09c	333	void nvme_nvm_unregister(struct nvme_ns *ns);
3dc87dd0 MB	334	int nvme_nvm_register_sysfs(struct nvme_ns *ns);
3dc87dd0 MB	335	void nvme_nvm_unregister_sysfs(struct nvme_ns *ns);
84d4add7	336	int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg);
c4699e70	337	#else
b0b4e09c	338	static inline int nvme_nvm_register(struct nvme_ns ns, char disk_name,
3dc87dd0	339	int node)
c4699e70 KB	340	{
	341	return 0;
	342	}
	343
b0b4e09c	344	static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
3dc87dd0 MB	345	static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns)
	346	{
	347	return 0;
	348	}
	349	static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {};
c4699e70 KB	350	static inline int nvme_nvm_ns_supported(struct nvme_ns ns, struct nvme_id_ns id)
	351	{
	352	return 0;
	353	}
84d4add7 MB	354	static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
	355	unsigned long arg)
	356	{
	357	return -ENOTTY;
	358	}
3dc87dd0 MB	359	#endif /* CONFIG_NVM */
3dc87dd0 MB	360
40267efd SL	361	static inline struct nvme_ns nvme_get_ns_from_dev(struct device dev)
	362	{
	363	return dev_to_disk(dev)->private_data;
	364	}
ca064085	365
5bae7f73 CH	366	int __init nvme_core_init(void);
	367	void nvme_core_exit(void);
	368
f11bb3e2	369	#endif /* _NVME_H */