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f11bb3e2 CH |
1 | /* |
2 | * Copyright (c) 2011-2014, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | */ | |
13 | ||
14 | #ifndef _NVME_H | |
15 | #define _NVME_H | |
16 | ||
17 | #include <linux/nvme.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/kref.h> | |
20 | #include <linux/blk-mq.h> | |
21 | ||
22 | extern unsigned char nvme_io_timeout; | |
23 | #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) | |
24 | ||
21d34711 CH |
25 | extern unsigned char admin_timeout; |
26 | #define ADMIN_TIMEOUT (admin_timeout * HZ) | |
27 | ||
5fd4ce1b CH |
28 | extern unsigned char shutdown_timeout; |
29 | #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ) | |
30 | ||
ca064085 MB |
31 | enum { |
32 | NVME_NS_LBA = 0, | |
33 | NVME_NS_LIGHTNVM = 1, | |
34 | }; | |
35 | ||
106198ed CH |
36 | /* |
37 | * List of workarounds for devices that required behavior not specified in | |
38 | * the standard. | |
39 | */ | |
40 | enum nvme_quirks { | |
41 | /* | |
42 | * Prefers I/O aligned to a stripe size specified in a vendor | |
43 | * specific Identify field. | |
44 | */ | |
45 | NVME_QUIRK_STRIPE_SIZE = (1 << 0), | |
46 | }; | |
47 | ||
1c63dc66 CH |
48 | struct nvme_ctrl { |
49 | const struct nvme_ctrl_ops *ops; | |
f11bb3e2 | 50 | struct request_queue *admin_q; |
f11bb3e2 | 51 | struct device *dev; |
1673f1f0 | 52 | struct kref kref; |
f11bb3e2 | 53 | int instance; |
5bae7f73 CH |
54 | struct blk_mq_tag_set *tagset; |
55 | struct list_head namespaces; | |
56 | struct device *device; /* char device */ | |
f3ca80fc | 57 | struct list_head node; |
1c63dc66 | 58 | |
f11bb3e2 CH |
59 | char name[12]; |
60 | char serial[20]; | |
61 | char model[40]; | |
62 | char firmware_rev[8]; | |
5fd4ce1b CH |
63 | |
64 | u32 ctrl_config; | |
65 | ||
66 | u32 page_size; | |
7fd8930f CH |
67 | u32 max_hw_sectors; |
68 | u32 stripe_size; | |
f11bb3e2 CH |
69 | u16 oncs; |
70 | u16 abort_limit; | |
71 | u8 event_limit; | |
72 | u8 vwc; | |
f3ca80fc CH |
73 | u32 vs; |
74 | bool subsystem; | |
106198ed | 75 | unsigned long quirks; |
f11bb3e2 CH |
76 | }; |
77 | ||
78 | /* | |
79 | * An NVM Express namespace is equivalent to a SCSI LUN | |
80 | */ | |
81 | struct nvme_ns { | |
82 | struct list_head list; | |
83 | ||
1c63dc66 | 84 | struct nvme_ctrl *ctrl; |
f11bb3e2 CH |
85 | struct request_queue *queue; |
86 | struct gendisk *disk; | |
87 | struct kref kref; | |
88 | ||
89 | unsigned ns_id; | |
90 | int lba_shift; | |
91 | u16 ms; | |
92 | bool ext; | |
93 | u8 pi_type; | |
ca064085 | 94 | int type; |
f11bb3e2 CH |
95 | u64 mode_select_num_blocks; |
96 | u32 mode_select_block_len; | |
97 | }; | |
98 | ||
1c63dc66 CH |
99 | struct nvme_ctrl_ops { |
100 | int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); | |
5fd4ce1b | 101 | int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); |
7fd8930f | 102 | int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); |
5bae7f73 | 103 | bool (*io_incapable)(struct nvme_ctrl *ctrl); |
f3ca80fc | 104 | int (*reset_ctrl)(struct nvme_ctrl *ctrl); |
1673f1f0 | 105 | void (*free_ctrl)(struct nvme_ctrl *ctrl); |
1c63dc66 CH |
106 | }; |
107 | ||
108 | static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl) | |
109 | { | |
110 | u32 val = 0; | |
111 | ||
112 | if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val)) | |
113 | return false; | |
114 | return val & NVME_CSTS_RDY; | |
115 | } | |
116 | ||
5bae7f73 CH |
117 | static inline bool nvme_io_incapable(struct nvme_ctrl *ctrl) |
118 | { | |
119 | u32 val = 0; | |
120 | ||
121 | if (ctrl->ops->io_incapable(ctrl)) | |
122 | return false; | |
123 | if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val)) | |
124 | return false; | |
125 | return val & NVME_CSTS_CFS; | |
126 | } | |
127 | ||
f3ca80fc CH |
128 | static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) |
129 | { | |
130 | if (!ctrl->subsystem) | |
131 | return -ENOTTY; | |
132 | return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); | |
133 | } | |
134 | ||
f11bb3e2 CH |
135 | static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector) |
136 | { | |
137 | return (sector >> (ns->lba_shift - 9)); | |
138 | } | |
139 | ||
22944e99 CH |
140 | static inline void nvme_setup_flush(struct nvme_ns *ns, |
141 | struct nvme_command *cmnd) | |
142 | { | |
143 | memset(cmnd, 0, sizeof(*cmnd)); | |
144 | cmnd->common.opcode = nvme_cmd_flush; | |
145 | cmnd->common.nsid = cpu_to_le32(ns->ns_id); | |
146 | } | |
147 | ||
148 | static inline void nvme_setup_rw(struct nvme_ns *ns, struct request *req, | |
149 | struct nvme_command *cmnd) | |
150 | { | |
151 | u16 control = 0; | |
152 | u32 dsmgmt = 0; | |
153 | ||
154 | if (req->cmd_flags & REQ_FUA) | |
155 | control |= NVME_RW_FUA; | |
156 | if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD)) | |
157 | control |= NVME_RW_LR; | |
158 | ||
159 | if (req->cmd_flags & REQ_RAHEAD) | |
160 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; | |
161 | ||
162 | memset(cmnd, 0, sizeof(*cmnd)); | |
163 | cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read); | |
164 | cmnd->rw.command_id = req->tag; | |
165 | cmnd->rw.nsid = cpu_to_le32(ns->ns_id); | |
166 | cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
167 | cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1); | |
168 | ||
169 | if (ns->ms) { | |
170 | switch (ns->pi_type) { | |
171 | case NVME_NS_DPS_PI_TYPE3: | |
172 | control |= NVME_RW_PRINFO_PRCHK_GUARD; | |
173 | break; | |
174 | case NVME_NS_DPS_PI_TYPE1: | |
175 | case NVME_NS_DPS_PI_TYPE2: | |
176 | control |= NVME_RW_PRINFO_PRCHK_GUARD | | |
177 | NVME_RW_PRINFO_PRCHK_REF; | |
178 | cmnd->rw.reftag = cpu_to_le32( | |
179 | nvme_block_nr(ns, blk_rq_pos(req))); | |
180 | break; | |
181 | } | |
182 | if (!blk_integrity_rq(req)) | |
183 | control |= NVME_RW_PRINFO_PRACT; | |
184 | } | |
185 | ||
186 | cmnd->rw.control = cpu_to_le16(control); | |
187 | cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); | |
188 | } | |
189 | ||
190 | ||
15a190f7 CH |
191 | static inline int nvme_error_status(u16 status) |
192 | { | |
193 | switch (status & 0x7ff) { | |
194 | case NVME_SC_SUCCESS: | |
195 | return 0; | |
196 | case NVME_SC_CAP_EXCEEDED: | |
197 | return -ENOSPC; | |
198 | default: | |
199 | return -EIO; | |
200 | } | |
201 | } | |
202 | ||
5fd4ce1b CH |
203 | int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap); |
204 | int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap); | |
205 | int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl); | |
f3ca80fc CH |
206 | int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, |
207 | const struct nvme_ctrl_ops *ops, unsigned long quirks); | |
1673f1f0 | 208 | void nvme_put_ctrl(struct nvme_ctrl *ctrl); |
7fd8930f | 209 | int nvme_init_identify(struct nvme_ctrl *ctrl); |
5bae7f73 CH |
210 | |
211 | void nvme_scan_namespaces(struct nvme_ctrl *ctrl); | |
212 | void nvme_remove_namespaces(struct nvme_ctrl *ctrl); | |
1673f1f0 | 213 | |
4160982e CH |
214 | struct request *nvme_alloc_request(struct request_queue *q, |
215 | struct nvme_command *cmd, unsigned int flags); | |
f11bb3e2 CH |
216 | int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
217 | void *buf, unsigned bufflen); | |
218 | int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, | |
4160982e CH |
219 | void *buffer, unsigned bufflen, u32 *result, unsigned timeout); |
220 | int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd, | |
221 | void __user *ubuffer, unsigned bufflen, u32 *result, | |
222 | unsigned timeout); | |
0b7f1f26 KB |
223 | int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd, |
224 | void __user *ubuffer, unsigned bufflen, | |
225 | void __user *meta_buffer, unsigned meta_len, u32 meta_seed, | |
226 | u32 *result, unsigned timeout); | |
1c63dc66 CH |
227 | int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id); |
228 | int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid, | |
f11bb3e2 | 229 | struct nvme_id_ns **id); |
1c63dc66 CH |
230 | int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log); |
231 | int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid, | |
f11bb3e2 | 232 | dma_addr_t dma_addr, u32 *result); |
1c63dc66 | 233 | int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11, |
f11bb3e2 CH |
234 | dma_addr_t dma_addr, u32 *result); |
235 | ||
1673f1f0 CH |
236 | extern spinlock_t dev_list_lock; |
237 | ||
f11bb3e2 CH |
238 | struct sg_io_hdr; |
239 | ||
240 | int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr); | |
241 | int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg); | |
242 | int nvme_sg_get_version_num(int __user *ip); | |
243 | ||
ca064085 MB |
244 | int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id); |
245 | int nvme_nvm_register(struct request_queue *q, char *disk_name); | |
246 | void nvme_nvm_unregister(struct request_queue *q, char *disk_name); | |
247 | ||
5bae7f73 CH |
248 | int __init nvme_core_init(void); |
249 | void nvme_core_exit(void); | |
250 | ||
f11bb3e2 | 251 | #endif /* _NVME_H */ |