[mirror_ubuntu-jammy-kernel.git] / drivers / nvme / host / nvme.h

/*
 * Copyright (c) 2011-2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef _NVME_H
#define _NVME_H

#include <linux/nvme.h>
#include <linux/pci.h>
#include <linux/kref.h>
#include <linux/blk-mq.h>
#include <linux/lightnvm.h>
#include <linux/sed-opal.h>

enum {
	/*
	 * Driver internal status code for commands that were cancelled due
	 * to timeouts or controller shutdown.  The value is negative so
	 * that it a) doesn't overlap with the unsigned hardware error codes,
	 * and b) can easily be tested for.
	 */
	NVME_SC_CANCELLED		= -EINTR,
};

extern unsigned char nvme_io_timeout;
#define NVME_IO_TIMEOUT	(nvme_io_timeout * HZ)

extern unsigned char admin_timeout;
#define ADMIN_TIMEOUT	(admin_timeout * HZ)

extern unsigned char shutdown_timeout;
#define SHUTDOWN_TIMEOUT	(shutdown_timeout * HZ)

#define NVME_DEFAULT_KATO	5
#define NVME_KATO_GRACE		10

extern unsigned int nvme_max_retries;

enum {
	NVME_NS_LBA		= 0,
	NVME_NS_LIGHTNVM	= 1,
};

/*
 * List of workarounds for devices that required behavior not specified in
 * the standard.
 */
enum nvme_quirks {
	/*
	 * Prefers I/O aligned to a stripe size specified in a vendor
	 * specific Identify field.
	 */
	NVME_QUIRK_STRIPE_SIZE			= (1 << 0),

	/*
	 * The controller doesn't handle Identify value others than 0 or 1
	 * correctly.
	 */
	NVME_QUIRK_IDENTIFY_CNS			= (1 << 1),

	/*
	 * The controller deterministically returns O's on reads to discarded
	 * logical blocks.
	 */
	NVME_QUIRK_DISCARD_ZEROES		= (1 << 2),

	/*
	 * The controller needs a delay before starts checking the device
	 * readiness, which is done by reading the NVME_CSTS_RDY bit.
	 */
	NVME_QUIRK_DELAY_BEFORE_CHK_RDY		= (1 << 3),
};

/*
 * Common request structure for NVMe passthrough.  All drivers must have
 * this structure as the first member of their request-private data.
 */
struct nvme_request {
	struct nvme_command	*cmd;
	union nvme_result	result;
};

static inline struct nvme_request *nvme_req(struct request *req)
{
	return blk_mq_rq_to_pdu(req);
}

/* The below value is the specific amount of delay needed before checking
 * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
 * found empirically.
 */
#define NVME_QUIRK_DELAY_AMOUNT		2000

enum nvme_ctrl_state {
	NVME_CTRL_NEW,
	NVME_CTRL_LIVE,
	NVME_CTRL_RESETTING,
	NVME_CTRL_RECONNECTING,
	NVME_CTRL_DELETING,
	NVME_CTRL_DEAD,
};

struct nvme_ctrl {
	enum nvme_ctrl_state state;
	spinlock_t lock;
	const struct nvme_ctrl_ops *ops;
	struct request_queue *admin_q;
	struct request_queue *connect_q;
	struct device *dev;
	struct kref kref;
	int instance;
	struct blk_mq_tag_set *tagset;
	struct list_head namespaces;
	struct mutex namespaces_mutex;
	struct device *device;	/* char device */
	struct list_head node;
	struct ida ns_ida;

	struct opal_dev opal_dev;

	char name[12];
	char serial[20];
	char model[40];
	char firmware_rev[8];
	u16 cntlid;

	u32 ctrl_config;

	u32 page_size;
	u32 max_hw_sectors;
	u16 oncs;
	u16 vid;
	atomic_t abort_limit;
	u8 event_limit;
	u8 vwc;
	u32 vs;
	u32 sgls;
	u16 kas;
	unsigned int kato;
	bool subsystem;
	unsigned long quirks;
	struct work_struct scan_work;
	struct work_struct async_event_work;
	struct delayed_work ka_work;

	/* Fabrics only */
	u16 sqsize;
	u32 ioccsz;
	u32 iorcsz;
	u16 icdoff;
	u16 maxcmd;
	struct nvmf_ctrl_options *opts;
};

/*
 * An NVM Express namespace is equivalent to a SCSI LUN
 */
struct nvme_ns {
	struct list_head list;

	struct nvme_ctrl *ctrl;
	struct request_queue *queue;
	struct gendisk *disk;
	struct nvm_dev *ndev;
	struct kref kref;
	int instance;

	u8 eui[8];
	u8 uuid[16];

	unsigned ns_id;
	int lba_shift;
	u16 ms;
	bool ext;
	u8 pi_type;
	unsigned long flags;

#define NVME_NS_REMOVING 0
#define NVME_NS_DEAD     1

	u64 mode_select_num_blocks;
	u32 mode_select_block_len;
};

struct nvme_ctrl_ops {
	const char *name;
	struct module *module;
	bool is_fabrics;
	int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val);
	int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val);
	int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val);
	int (*reset_ctrl)(struct nvme_ctrl *ctrl);
	void (*free_ctrl)(struct nvme_ctrl *ctrl);
	void (*submit_async_event)(struct nvme_ctrl *ctrl, int aer_idx);
	int (*delete_ctrl)(struct nvme_ctrl *ctrl);
	const char *(*get_subsysnqn)(struct nvme_ctrl *ctrl);
	int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size);
};

static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
{
	u32 val = 0;

	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
		return false;
	return val & NVME_CSTS_RDY;
}

static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
{
	if (!ctrl->subsystem)
		return -ENOTTY;
	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
}

static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
{
	return (sector >> (ns->lba_shift - 9));
}

static inline unsigned nvme_map_len(struct request *rq)
{
	if (req_op(rq) == REQ_OP_DISCARD)
		return sizeof(struct nvme_dsm_range);
	else
		return blk_rq_bytes(rq);
}

static inline void nvme_cleanup_cmd(struct request *req)
{
	if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
		kfree(page_address(req->special_vec.bv_page) +
		      req->special_vec.bv_offset);
	}
}

static inline int nvme_error_status(u16 status)
{
	switch (status & 0x7ff) {
	case NVME_SC_SUCCESS:
		return 0;
	case NVME_SC_CAP_EXCEEDED:
		return -ENOSPC;
	default:
		return -EIO;
	}
}

static inline bool nvme_req_needs_retry(struct request *req, u16 status)
{
	return !(status & NVME_SC_DNR || blk_noretry_request(req)) &&
		(jiffies - req->start_time) < req->timeout &&
		req->retries < nvme_max_retries;
}

void nvme_cancel_request(struct request *req, void *data, bool reserved);
bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
		enum nvme_ctrl_state new_state);
int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
		const struct nvme_ctrl_ops *ops, unsigned long quirks);
void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
void nvme_put_ctrl(struct nvme_ctrl *ctrl);
int nvme_init_identify(struct nvme_ctrl *ctrl);

void nvme_queue_scan(struct nvme_ctrl *ctrl);
void nvme_remove_namespaces(struct nvme_ctrl *ctrl);

#ifdef CONFIG_BLK_SED_OPAL
int nvme_sec_submit(struct opal_dev *dev, u16 spsp, u8 secp,
		    void *buffer, size_t len, bool send);
#else
static inline int nvme_sec_submit(struct opal_dev *dev, u16 spsp, u8 secp,
				  void *buffer, size_t len, bool send)
{
	return 0;
}
#endif /* CONFIG_BLK_DEV_SED_OPAL */

#define NVME_NR_AERS	1
void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
		union nvme_result *res);
void nvme_queue_async_events(struct nvme_ctrl *ctrl);

void nvme_stop_queues(struct nvme_ctrl *ctrl);
void nvme_start_queues(struct nvme_ctrl *ctrl);
void nvme_kill_queues(struct nvme_ctrl *ctrl);

#define NVME_QID_ANY -1
struct request *nvme_alloc_request(struct request_queue *q,
		struct nvme_command *cmd, unsigned int flags, int qid);
void nvme_requeue_req(struct request *req);
int nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
		struct nvme_command *cmd);
int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		void *buf, unsigned bufflen);
int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		union nvme_result *result, void *buffer, unsigned bufflen,
		unsigned timeout, int qid, int at_head, int flags);
int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
		void __user *ubuffer, unsigned bufflen, u32 *result,
		unsigned timeout);
int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
		void __user *ubuffer, unsigned bufflen,
		void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
		u32 *result, unsigned timeout);
int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id);
int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
		struct nvme_id_ns **id);
int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log);
int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
		      void *buffer, size_t buflen, u32 *result);
int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
		      void *buffer, size_t buflen, u32 *result);
int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);
void nvme_start_keep_alive(struct nvme_ctrl *ctrl);
void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);

struct sg_io_hdr;

int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr);
int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
int nvme_sg_get_version_num(int __user *ip);

#ifdef CONFIG_NVM
int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id);
int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node);
void nvme_nvm_unregister(struct nvme_ns *ns);
int nvme_nvm_register_sysfs(struct nvme_ns *ns);
void nvme_nvm_unregister_sysfs(struct nvme_ns *ns);
int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg);
#else
static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name,
				    int node)
{
	return 0;
}

static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns)
{
	return 0;
}
static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {};
static inline int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id)
{
	return 0;
}
static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
							unsigned long arg)
{
	return -ENOTTY;
}
#endif /* CONFIG_NVM */

static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev)
{
	return dev_to_disk(dev)->private_data;
}

int __init nvme_core_init(void);
void nvme_core_exit(void);

#endif /* _NVME_H */
Commit	Line	Data
f11bb3e2 CH	1	/*
	2	* Copyright (c) 2011-2014, Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*/
	13
	14	#ifndef _NVME_H
	15	#define _NVME_H
	16
	17	#include <linux/nvme.h>
	18	#include <linux/pci.h>
	19	#include <linux/kref.h>
	20	#include <linux/blk-mq.h>
b0b4e09c	21	#include <linux/lightnvm.h>
a98e58e5	22	#include <linux/sed-opal.h>
f11bb3e2	23
297465c8 CH	24	enum {
	25	/*
	26	* Driver internal status code for commands that were cancelled due
	27	* to timeouts or controller shutdown. The value is negative so
	28	* that it a) doesn't overlap with the unsigned hardware error codes,
	29	* and b) can easily be tested for.
	30	*/
	31	NVME_SC_CANCELLED = -EINTR,
	32	};
	33
f11bb3e2 CH	34	extern unsigned char nvme_io_timeout;
	35	#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
	36
21d34711 CH	37	extern unsigned char admin_timeout;
	38	#define ADMIN_TIMEOUT (admin_timeout * HZ)
	39
5fd4ce1b CH	40	extern unsigned char shutdown_timeout;
	41	#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
	42
038bd4cb SG	43	#define NVME_DEFAULT_KATO 5
	44	#define NVME_KATO_GRACE 10
	45
f80ec966 KB	46	extern unsigned int nvme_max_retries;
f80ec966 KB	47
ca064085 MB	48	enum {
	49	NVME_NS_LBA = 0,
	50	NVME_NS_LIGHTNVM = 1,
	51	};
	52
f11bb3e2	53	/*
106198ed CH	54	* List of workarounds for devices that required behavior not specified in
106198ed CH	55	* the standard.
f11bb3e2	56	*/
106198ed CH	57	enum nvme_quirks {
	58	/*
	59	* Prefers I/O aligned to a stripe size specified in a vendor
	60	* specific Identify field.
	61	*/
	62	NVME_QUIRK_STRIPE_SIZE = (1 << 0),
540c801c KB	63
	64	/*
	65	* The controller doesn't handle Identify value others than 0 or 1
	66	* correctly.
	67	*/
	68	NVME_QUIRK_IDENTIFY_CNS = (1 << 1),
08095e70 KB	69
	70	/*
	71	* The controller deterministically returns O's on reads to discarded
	72	* logical blocks.
	73	*/
	74	NVME_QUIRK_DISCARD_ZEROES = (1 << 2),
54adc010 GP	75
	76	/*
	77	* The controller needs a delay before starts checking the device
	78	* readiness, which is done by reading the NVME_CSTS_RDY bit.
	79	*/
	80	NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3),
106198ed CH	81	};
106198ed CH	82
d49187e9 CH	83	/*
	84	* Common request structure for NVMe passthrough. All drivers must have
	85	* this structure as the first member of their request-private data.
	86	*/
	87	struct nvme_request {
	88	struct nvme_command *cmd;
	89	union nvme_result result;
	90	};
	91
	92	static inline struct nvme_request nvme_req(struct request req)
	93	{
	94	return blk_mq_rq_to_pdu(req);
	95	}
	96
54adc010 GP	97	/* The below value is the specific amount of delay needed before checking
	98	* readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
	99	* NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
	100	* found empirically.
	101	*/
	102	#define NVME_QUIRK_DELAY_AMOUNT 2000
	103
bb8d261e CH	104	enum nvme_ctrl_state {
	105	NVME_CTRL_NEW,
	106	NVME_CTRL_LIVE,
	107	NVME_CTRL_RESETTING,
def61eca	108	NVME_CTRL_RECONNECTING,
bb8d261e	109	NVME_CTRL_DELETING,
0ff9d4e1	110	NVME_CTRL_DEAD,
bb8d261e CH	111	};
bb8d261e CH	112
1c63dc66	113	struct nvme_ctrl {
bb8d261e CH	114	enum nvme_ctrl_state state;
bb8d261e CH	115	spinlock_t lock;
1c63dc66	116	const struct nvme_ctrl_ops *ops;
f11bb3e2	117	struct request_queue *admin_q;
07bfcd09	118	struct request_queue *connect_q;
f11bb3e2	119	struct device *dev;
1673f1f0	120	struct kref kref;
f11bb3e2	121	int instance;
5bae7f73	122	struct blk_mq_tag_set *tagset;
f11bb3e2	123	struct list_head namespaces;
69d3b8ac	124	struct mutex namespaces_mutex;
5bae7f73	125	struct device device; / char device */
f3ca80fc	126	struct list_head node;
075790eb	127	struct ida ns_ida;
1c63dc66	128
a98e58e5 SB	129	struct opal_dev opal_dev;
a98e58e5 SB	130
f11bb3e2 CH	131	char name[12];
	132	char serial[20];
	133	char model[40];
	134	char firmware_rev[8];
76e3914a	135	u16 cntlid;
5fd4ce1b CH	136
	137	u32 ctrl_config;
	138
	139	u32 page_size;
f11bb3e2	140	u32 max_hw_sectors;
f11bb3e2	141	u16 oncs;
118472ab	142	u16 vid;
6bf25d16	143	atomic_t abort_limit;
f11bb3e2 CH	144	u8 event_limit;
f11bb3e2 CH	145	u8 vwc;
f3ca80fc	146	u32 vs;
07bfcd09	147	u32 sgls;
038bd4cb SG	148	u16 kas;
038bd4cb SG	149	unsigned int kato;
f3ca80fc	150	bool subsystem;
106198ed	151	unsigned long quirks;
5955be21	152	struct work_struct scan_work;
f866fc42	153	struct work_struct async_event_work;
038bd4cb	154	struct delayed_work ka_work;
07bfcd09 CH	155
	156	/* Fabrics only */
	157	u16 sqsize;
	158	u32 ioccsz;
	159	u32 iorcsz;
	160	u16 icdoff;
	161	u16 maxcmd;
	162	struct nvmf_ctrl_options *opts;
f11bb3e2 CH	163	};
	164
	165	/*
	166	* An NVM Express namespace is equivalent to a SCSI LUN
	167	*/
	168	struct nvme_ns {
	169	struct list_head list;
	170
1c63dc66	171	struct nvme_ctrl *ctrl;
f11bb3e2 CH	172	struct request_queue *queue;
f11bb3e2 CH	173	struct gendisk *disk;
b0b4e09c	174	struct nvm_dev *ndev;
f11bb3e2	175	struct kref kref;
075790eb	176	int instance;
f11bb3e2	177
2b9b6e86 KB	178	u8 eui[8];
	179	u8 uuid[16];
	180
f11bb3e2 CH	181	unsigned ns_id;
	182	int lba_shift;
	183	u16 ms;
	184	bool ext;
	185	u8 pi_type;
646017a6 KB	186	unsigned long flags;
	187
	188	#define NVME_NS_REMOVING 0
69d9a99c	189	#define NVME_NS_DEAD 1
646017a6	190
f11bb3e2 CH	191	u64 mode_select_num_blocks;
	192	u32 mode_select_block_len;
	193	};
	194
1c63dc66	195	struct nvme_ctrl_ops {
1a353d85	196	const char *name;
e439bb12	197	struct module *module;
07bfcd09	198	bool is_fabrics;
1c63dc66	199	int (reg_read32)(struct nvme_ctrl ctrl, u32 off, u32 *val);
5fd4ce1b	200	int (reg_write32)(struct nvme_ctrl ctrl, u32 off, u32 val);
7fd8930f	201	int (reg_read64)(struct nvme_ctrl ctrl, u32 off, u64 *val);
f3ca80fc	202	int (reset_ctrl)(struct nvme_ctrl ctrl);
1673f1f0	203	void (free_ctrl)(struct nvme_ctrl ctrl);
f866fc42	204	void (submit_async_event)(struct nvme_ctrl ctrl, int aer_idx);
1a353d85 ML	205	int (delete_ctrl)(struct nvme_ctrl ctrl);
	206	const char (get_subsysnqn)(struct nvme_ctrl *ctrl);
	207	int (get_address)(struct nvme_ctrl ctrl, char *buf, int size);
f11bb3e2 CH	208	};
f11bb3e2 CH	209
1c63dc66 CH	210	static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
	211	{
	212	u32 val = 0;
	213
	214	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
	215	return false;
	216	return val & NVME_CSTS_RDY;
	217	}
	218
f3ca80fc CH	219	static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
	220	{
	221	if (!ctrl->subsystem)
	222	return -ENOTTY;
	223	return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
	224	}
	225
f11bb3e2 CH	226	static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
	227	{
	228	return (sector >> (ns->lba_shift - 9));
	229	}
	230
58b45602 ML	231	static inline unsigned nvme_map_len(struct request *rq)
58b45602 ML	232	{
c2df40df	233	if (req_op(rq) == REQ_OP_DISCARD)
58b45602 ML	234	return sizeof(struct nvme_dsm_range);
	235	else
	236	return blk_rq_bytes(rq);
	237	}
	238
6904242d ML	239	static inline void nvme_cleanup_cmd(struct request *req)
6904242d ML	240	{
f9d03f96 CH	241	if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
	242	kfree(page_address(req->special_vec.bv_page) +
	243	req->special_vec.bv_offset);
	244	}
6904242d ML	245	}
6904242d ML	246
15a190f7 CH	247	static inline int nvme_error_status(u16 status)
	248	{
	249	switch (status & 0x7ff) {
	250	case NVME_SC_SUCCESS:
	251	return 0;
	252	case NVME_SC_CAP_EXCEEDED:
	253	return -ENOSPC;
	254	default:
	255	return -EIO;
	256	}
	257	}
	258
7688faa6 CH	259	static inline bool nvme_req_needs_retry(struct request *req, u16 status)
	260	{
	261	return !(status & NVME_SC_DNR \|\| blk_noretry_request(req)) &&
f80ec966 KB	262	(jiffies - req->start_time) < req->timeout &&
f80ec966 KB	263	req->retries < nvme_max_retries;
7688faa6 CH	264	}
7688faa6 CH	265
c55a2fd4	266	void nvme_cancel_request(struct request req, void data, bool reserved);
bb8d261e CH	267	bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
bb8d261e CH	268	enum nvme_ctrl_state new_state);
5fd4ce1b CH	269	int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	270	int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	271	int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
f3ca80fc CH	272	int nvme_init_ctrl(struct nvme_ctrl ctrl, struct device dev,
f3ca80fc CH	273	const struct nvme_ctrl_ops *ops, unsigned long quirks);
53029b04	274	void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
1673f1f0	275	void nvme_put_ctrl(struct nvme_ctrl *ctrl);
7fd8930f	276	int nvme_init_identify(struct nvme_ctrl *ctrl);
5bae7f73	277
5955be21	278	void nvme_queue_scan(struct nvme_ctrl *ctrl);
5bae7f73	279	void nvme_remove_namespaces(struct nvme_ctrl *ctrl);
1673f1f0	280
a98e58e5 SB	281	#ifdef CONFIG_BLK_SED_OPAL
	282	int nvme_sec_submit(struct opal_dev *dev, u16 spsp, u8 secp,
	283	void *buffer, size_t len, bool send);
	284	#else
	285	static inline int nvme_sec_submit(struct opal_dev *dev, u16 spsp, u8 secp,
	286	void *buffer, size_t len, bool send)
	287	{
	288	return 0;
	289	}
	290	#endif /* CONFIG_BLK_DEV_SED_OPAL */
	291
f866fc42	292	#define NVME_NR_AERS 1
7bf58533 CH	293	void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
7bf58533 CH	294	union nvme_result *res);
f866fc42 CH	295	void nvme_queue_async_events(struct nvme_ctrl *ctrl);
f866fc42 CH	296
25646264 KB	297	void nvme_stop_queues(struct nvme_ctrl *ctrl);
25646264 KB	298	void nvme_start_queues(struct nvme_ctrl *ctrl);
69d9a99c	299	void nvme_kill_queues(struct nvme_ctrl *ctrl);
363c9aac	300
eb71f435	301	#define NVME_QID_ANY -1
4160982e	302	struct request nvme_alloc_request(struct request_queue q,
eb71f435	303	struct nvme_command *cmd, unsigned int flags, int qid);
7688faa6	304	void nvme_requeue_req(struct request *req);
8093f7ca ML	305	int nvme_setup_cmd(struct nvme_ns ns, struct request req,
8093f7ca ML	306	struct nvme_command *cmd);
f11bb3e2 CH	307	int nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
	308	void *buf, unsigned bufflen);
	309	int __nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
d49187e9	310	union nvme_result result, void buffer, unsigned bufflen,
eb71f435	311	unsigned timeout, int qid, int at_head, int flags);
4160982e CH	312	int nvme_submit_user_cmd(struct request_queue q, struct nvme_command cmd,
	313	void __user ubuffer, unsigned bufflen, u32 result,
	314	unsigned timeout);
0b7f1f26 KB	315	int __nvme_submit_user_cmd(struct request_queue q, struct nvme_command cmd,
	316	void __user *ubuffer, unsigned bufflen,
	317	void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
f11bb3e2	318	u32 *result, unsigned timeout);
1c63dc66 CH	319	int nvme_identify_ctrl(struct nvme_ctrl dev, struct nvme_id_ctrl *id);
1c63dc66 CH	320	int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
f11bb3e2	321	struct nvme_id_ns **id);
1c63dc66 CH	322	int nvme_get_log_page(struct nvme_ctrl dev, struct nvme_smart_log *log);
1c63dc66 CH	323	int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
1a6fe74d	324	void buffer, size_t buflen, u32 result);
1c63dc66	325	int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
1a6fe74d	326	void buffer, size_t buflen, u32 result);
9a0be7ab	327	int nvme_set_queue_count(struct nvme_ctrl ctrl, int count);
038bd4cb SG	328	void nvme_start_keep_alive(struct nvme_ctrl *ctrl);
038bd4cb SG	329	void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
f11bb3e2 CH	330
	331	struct sg_io_hdr;
	332
	333	int nvme_sg_io(struct nvme_ns ns, struct sg_io_hdr __user u_hdr);
	334	int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
	335	int nvme_sg_get_version_num(int __user *ip);
	336
c4699e70	337	#ifdef CONFIG_NVM
ca064085	338	int nvme_nvm_ns_supported(struct nvme_ns ns, struct nvme_id_ns id);
3dc87dd0	339	int nvme_nvm_register(struct nvme_ns ns, char disk_name, int node);
b0b4e09c	340	void nvme_nvm_unregister(struct nvme_ns *ns);
3dc87dd0 MB	341	int nvme_nvm_register_sysfs(struct nvme_ns *ns);
3dc87dd0 MB	342	void nvme_nvm_unregister_sysfs(struct nvme_ns *ns);
84d4add7	343	int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg);
c4699e70	344	#else
b0b4e09c	345	static inline int nvme_nvm_register(struct nvme_ns ns, char disk_name,
3dc87dd0	346	int node)
c4699e70 KB	347	{
	348	return 0;
	349	}
	350
b0b4e09c	351	static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
3dc87dd0 MB	352	static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns)
	353	{
	354	return 0;
	355	}
	356	static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {};
c4699e70 KB	357	static inline int nvme_nvm_ns_supported(struct nvme_ns ns, struct nvme_id_ns id)
	358	{
	359	return 0;
	360	}
84d4add7 MB	361	static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
	362	unsigned long arg)
	363	{
	364	return -ENOTTY;
	365	}
3dc87dd0 MB	366	#endif /* CONFIG_NVM */
3dc87dd0 MB	367
40267efd SL	368	static inline struct nvme_ns nvme_get_ns_from_dev(struct device dev)
	369	{
	370	return dev_to_disk(dev)->private_data;
	371	}
ca064085	372
5bae7f73 CH	373	int __init nvme_core_init(void);
	374	void nvme_core_exit(void);
	375
f11bb3e2	376	#endif /* _NVME_H */