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Commit | Line | Data |
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f11bb3e2 CH |
1 | /* |
2 | * Copyright (c) 2011-2014, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | */ | |
13 | ||
14 | #ifndef _NVME_H | |
15 | #define _NVME_H | |
16 | ||
17 | #include <linux/nvme.h> | |
a6a5149b | 18 | #include <linux/cdev.h> |
f11bb3e2 CH |
19 | #include <linux/pci.h> |
20 | #include <linux/kref.h> | |
21 | #include <linux/blk-mq.h> | |
b0b4e09c | 22 | #include <linux/lightnvm.h> |
a98e58e5 | 23 | #include <linux/sed-opal.h> |
b9e03857 | 24 | #include <linux/fault-inject.h> |
978628ec | 25 | #include <linux/rcupdate.h> |
f11bb3e2 | 26 | |
8ae4e447 | 27 | extern unsigned int nvme_io_timeout; |
f11bb3e2 CH |
28 | #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) |
29 | ||
8ae4e447 | 30 | extern unsigned int admin_timeout; |
21d34711 CH |
31 | #define ADMIN_TIMEOUT (admin_timeout * HZ) |
32 | ||
038bd4cb SG |
33 | #define NVME_DEFAULT_KATO 5 |
34 | #define NVME_KATO_GRACE 10 | |
35 | ||
9a6327d2 | 36 | extern struct workqueue_struct *nvme_wq; |
b227c59b RS |
37 | extern struct workqueue_struct *nvme_reset_wq; |
38 | extern struct workqueue_struct *nvme_delete_wq; | |
9a6327d2 | 39 | |
ca064085 MB |
40 | enum { |
41 | NVME_NS_LBA = 0, | |
42 | NVME_NS_LIGHTNVM = 1, | |
43 | }; | |
44 | ||
f11bb3e2 | 45 | /* |
106198ed CH |
46 | * List of workarounds for devices that required behavior not specified in |
47 | * the standard. | |
f11bb3e2 | 48 | */ |
106198ed CH |
49 | enum nvme_quirks { |
50 | /* | |
51 | * Prefers I/O aligned to a stripe size specified in a vendor | |
52 | * specific Identify field. | |
53 | */ | |
54 | NVME_QUIRK_STRIPE_SIZE = (1 << 0), | |
540c801c KB |
55 | |
56 | /* | |
57 | * The controller doesn't handle Identify value others than 0 or 1 | |
58 | * correctly. | |
59 | */ | |
60 | NVME_QUIRK_IDENTIFY_CNS = (1 << 1), | |
08095e70 KB |
61 | |
62 | /* | |
e850fd16 CH |
63 | * The controller deterministically returns O's on reads to |
64 | * logical blocks that deallocate was called on. | |
08095e70 | 65 | */ |
e850fd16 | 66 | NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2), |
54adc010 GP |
67 | |
68 | /* | |
69 | * The controller needs a delay before starts checking the device | |
70 | * readiness, which is done by reading the NVME_CSTS_RDY bit. | |
71 | */ | |
72 | NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), | |
c5552fde AL |
73 | |
74 | /* | |
75 | * APST should not be used. | |
76 | */ | |
77 | NVME_QUIRK_NO_APST = (1 << 4), | |
ff5350a8 AL |
78 | |
79 | /* | |
80 | * The deepest sleep state should not be used. | |
81 | */ | |
82 | NVME_QUIRK_NO_DEEPEST_PS = (1 << 5), | |
608cc4b1 CH |
83 | |
84 | /* | |
85 | * Supports the LighNVM command set if indicated in vs[1]. | |
86 | */ | |
87 | NVME_QUIRK_LIGHTNVM = (1 << 6), | |
9abd68ef JA |
88 | |
89 | /* | |
90 | * Set MEDIUM priority on SQ creation | |
91 | */ | |
92 | NVME_QUIRK_MEDIUM_PRIO_SQ = (1 << 7), | |
106198ed CH |
93 | }; |
94 | ||
d49187e9 CH |
95 | /* |
96 | * Common request structure for NVMe passthrough. All drivers must have | |
97 | * this structure as the first member of their request-private data. | |
98 | */ | |
99 | struct nvme_request { | |
100 | struct nvme_command *cmd; | |
101 | union nvme_result result; | |
44e44b29 | 102 | u8 retries; |
27fa9bc5 CH |
103 | u8 flags; |
104 | u16 status; | |
59e29ce6 | 105 | struct nvme_ctrl *ctrl; |
27fa9bc5 CH |
106 | }; |
107 | ||
32acab31 CH |
108 | /* |
109 | * Mark a bio as coming in through the mpath node. | |
110 | */ | |
111 | #define REQ_NVME_MPATH REQ_DRV | |
112 | ||
27fa9bc5 CH |
113 | enum { |
114 | NVME_REQ_CANCELLED = (1 << 0), | |
bb06ec31 | 115 | NVME_REQ_USERCMD = (1 << 1), |
d49187e9 CH |
116 | }; |
117 | ||
118 | static inline struct nvme_request *nvme_req(struct request *req) | |
119 | { | |
120 | return blk_mq_rq_to_pdu(req); | |
121 | } | |
122 | ||
5d87eb94 KB |
123 | static inline u16 nvme_req_qid(struct request *req) |
124 | { | |
125 | if (!req->rq_disk) | |
126 | return 0; | |
127 | return blk_mq_unique_tag_to_hwq(blk_mq_unique_tag(req)) + 1; | |
128 | } | |
129 | ||
54adc010 GP |
130 | /* The below value is the specific amount of delay needed before checking |
131 | * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the | |
132 | * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was | |
133 | * found empirically. | |
134 | */ | |
8c97eecc | 135 | #define NVME_QUIRK_DELAY_AMOUNT 2300 |
54adc010 | 136 | |
bb8d261e CH |
137 | enum nvme_ctrl_state { |
138 | NVME_CTRL_NEW, | |
139 | NVME_CTRL_LIVE, | |
2b1b7e78 | 140 | NVME_CTRL_ADMIN_ONLY, /* Only admin queue live */ |
bb8d261e | 141 | NVME_CTRL_RESETTING, |
ad6a0a52 | 142 | NVME_CTRL_CONNECTING, |
bb8d261e | 143 | NVME_CTRL_DELETING, |
0ff9d4e1 | 144 | NVME_CTRL_DEAD, |
bb8d261e CH |
145 | }; |
146 | ||
1c63dc66 | 147 | struct nvme_ctrl { |
bb8d261e | 148 | enum nvme_ctrl_state state; |
bd4da3ab | 149 | bool identified; |
bb8d261e | 150 | spinlock_t lock; |
1c63dc66 | 151 | const struct nvme_ctrl_ops *ops; |
f11bb3e2 | 152 | struct request_queue *admin_q; |
07bfcd09 | 153 | struct request_queue *connect_q; |
f11bb3e2 | 154 | struct device *dev; |
f11bb3e2 | 155 | int instance; |
5bae7f73 | 156 | struct blk_mq_tag_set *tagset; |
34b6c231 | 157 | struct blk_mq_tag_set *admin_tagset; |
f11bb3e2 | 158 | struct list_head namespaces; |
765cc031 | 159 | struct rw_semaphore namespaces_rwsem; |
d22524a4 | 160 | struct device ctrl_device; |
5bae7f73 | 161 | struct device *device; /* char device */ |
a6a5149b | 162 | struct cdev cdev; |
d86c4d8e | 163 | struct work_struct reset_work; |
c5017e85 | 164 | struct work_struct delete_work; |
1c63dc66 | 165 | |
ab9e00cc CH |
166 | struct nvme_subsystem *subsys; |
167 | struct list_head subsys_entry; | |
168 | ||
4f1244c8 | 169 | struct opal_dev *opal_dev; |
a98e58e5 | 170 | |
f11bb3e2 | 171 | char name[12]; |
76e3914a | 172 | u16 cntlid; |
5fd4ce1b CH |
173 | |
174 | u32 ctrl_config; | |
b6dccf7f | 175 | u16 mtfa; |
d858e5f0 | 176 | u32 queue_count; |
5fd4ce1b | 177 | |
20d0dfe6 | 178 | u64 cap; |
5fd4ce1b | 179 | u32 page_size; |
f11bb3e2 | 180 | u32 max_hw_sectors; |
943e942e | 181 | u32 max_segments; |
f11bb3e2 | 182 | u16 oncs; |
8a9ae523 | 183 | u16 oacs; |
f5d11840 JA |
184 | u16 nssa; |
185 | u16 nr_streams; | |
0d0b660f | 186 | u32 max_namespaces; |
6bf25d16 | 187 | atomic_t abort_limit; |
f11bb3e2 | 188 | u8 vwc; |
f3ca80fc | 189 | u32 vs; |
07bfcd09 | 190 | u32 sgls; |
038bd4cb | 191 | u16 kas; |
c5552fde AL |
192 | u8 npss; |
193 | u8 apsta; | |
c0561f82 | 194 | u32 oaes; |
e3d7874d | 195 | u32 aen_result; |
07fbd32a | 196 | unsigned int shutdown_timeout; |
038bd4cb | 197 | unsigned int kato; |
f3ca80fc | 198 | bool subsystem; |
106198ed | 199 | unsigned long quirks; |
c5552fde | 200 | struct nvme_id_power_state psd[32]; |
84fef62d | 201 | struct nvme_effects_log *effects; |
5955be21 | 202 | struct work_struct scan_work; |
f866fc42 | 203 | struct work_struct async_event_work; |
038bd4cb | 204 | struct delayed_work ka_work; |
0a34e466 | 205 | struct nvme_command ka_cmd; |
b6dccf7f | 206 | struct work_struct fw_act_work; |
30d90964 | 207 | unsigned long events; |
07bfcd09 | 208 | |
0d0b660f CH |
209 | #ifdef CONFIG_NVME_MULTIPATH |
210 | /* asymmetric namespace access: */ | |
211 | u8 anacap; | |
212 | u8 anatt; | |
213 | u32 anagrpmax; | |
214 | u32 nanagrpid; | |
215 | struct mutex ana_lock; | |
216 | struct nvme_ana_rsp_hdr *ana_log_buf; | |
217 | size_t ana_log_size; | |
218 | struct timer_list anatt_timer; | |
219 | struct work_struct ana_work; | |
220 | #endif | |
221 | ||
c5552fde AL |
222 | /* Power saving configuration */ |
223 | u64 ps_max_latency_us; | |
76a5af84 | 224 | bool apst_enabled; |
c5552fde | 225 | |
044a9df1 | 226 | /* PCIe only: */ |
fe6d53c9 CH |
227 | u32 hmpre; |
228 | u32 hmmin; | |
044a9df1 CH |
229 | u32 hmminds; |
230 | u16 hmmaxd; | |
fe6d53c9 | 231 | |
07bfcd09 CH |
232 | /* Fabrics only */ |
233 | u16 sqsize; | |
234 | u32 ioccsz; | |
235 | u32 iorcsz; | |
236 | u16 icdoff; | |
237 | u16 maxcmd; | |
fdf9dfa8 | 238 | int nr_reconnects; |
07bfcd09 | 239 | struct nvmf_ctrl_options *opts; |
f11bb3e2 CH |
240 | }; |
241 | ||
ab9e00cc CH |
242 | struct nvme_subsystem { |
243 | int instance; | |
244 | struct device dev; | |
245 | /* | |
246 | * Because we unregister the device on the last put we need | |
247 | * a separate refcount. | |
248 | */ | |
249 | struct kref ref; | |
250 | struct list_head entry; | |
251 | struct mutex lock; | |
252 | struct list_head ctrls; | |
ed754e5d | 253 | struct list_head nsheads; |
ab9e00cc CH |
254 | char subnqn[NVMF_NQN_SIZE]; |
255 | char serial[20]; | |
256 | char model[40]; | |
257 | char firmware_rev[8]; | |
258 | u8 cmic; | |
259 | u16 vendor_id; | |
ed754e5d | 260 | struct ida ns_ida; |
ab9e00cc CH |
261 | }; |
262 | ||
002fab04 CH |
263 | /* |
264 | * Container structure for uniqueue namespace identifiers. | |
265 | */ | |
266 | struct nvme_ns_ids { | |
267 | u8 eui64[8]; | |
268 | u8 nguid[16]; | |
269 | uuid_t uuid; | |
270 | }; | |
271 | ||
ed754e5d CH |
272 | /* |
273 | * Anchor structure for namespaces. There is one for each namespace in a | |
274 | * NVMe subsystem that any of our controllers can see, and the namespace | |
275 | * structure for each controller is chained of it. For private namespaces | |
276 | * there is a 1:1 relation to our namespace structures, that is ->list | |
277 | * only ever has a single entry for private namespaces. | |
278 | */ | |
279 | struct nvme_ns_head { | |
32acab31 CH |
280 | #ifdef CONFIG_NVME_MULTIPATH |
281 | struct gendisk *disk; | |
282 | struct nvme_ns __rcu *current_path; | |
283 | struct bio_list requeue_list; | |
284 | spinlock_t requeue_lock; | |
285 | struct work_struct requeue_work; | |
0d0b660f | 286 | struct mutex lock; |
32acab31 | 287 | #endif |
ed754e5d CH |
288 | struct list_head list; |
289 | struct srcu_struct srcu; | |
290 | struct nvme_subsystem *subsys; | |
291 | unsigned ns_id; | |
292 | struct nvme_ns_ids ids; | |
293 | struct list_head entry; | |
294 | struct kref ref; | |
295 | int instance; | |
296 | }; | |
297 | ||
b9e03857 TT |
298 | #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS |
299 | struct nvme_fault_inject { | |
300 | struct fault_attr attr; | |
301 | struct dentry *parent; | |
302 | bool dont_retry; /* DNR, do not retry */ | |
303 | u16 status; /* status code */ | |
304 | }; | |
305 | #endif | |
306 | ||
f11bb3e2 CH |
307 | struct nvme_ns { |
308 | struct list_head list; | |
309 | ||
1c63dc66 | 310 | struct nvme_ctrl *ctrl; |
f11bb3e2 CH |
311 | struct request_queue *queue; |
312 | struct gendisk *disk; | |
0d0b660f CH |
313 | #ifdef CONFIG_NVME_MULTIPATH |
314 | enum nvme_ana_state ana_state; | |
315 | u32 ana_grpid; | |
316 | #endif | |
ed754e5d | 317 | struct list_head siblings; |
b0b4e09c | 318 | struct nvm_dev *ndev; |
f11bb3e2 | 319 | struct kref kref; |
ed754e5d | 320 | struct nvme_ns_head *head; |
f11bb3e2 | 321 | |
f11bb3e2 CH |
322 | int lba_shift; |
323 | u16 ms; | |
f5d11840 JA |
324 | u16 sgs; |
325 | u32 sws; | |
f11bb3e2 CH |
326 | bool ext; |
327 | u8 pi_type; | |
646017a6 | 328 | unsigned long flags; |
0d0b660f CH |
329 | #define NVME_NS_REMOVING 0 |
330 | #define NVME_NS_DEAD 1 | |
331 | #define NVME_NS_ANA_PENDING 2 | |
57eeaf8e | 332 | u16 noiob; |
b9e03857 TT |
333 | |
334 | #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS | |
335 | struct nvme_fault_inject fault_inject; | |
336 | #endif | |
337 | ||
f11bb3e2 CH |
338 | }; |
339 | ||
1c63dc66 | 340 | struct nvme_ctrl_ops { |
1a353d85 | 341 | const char *name; |
e439bb12 | 342 | struct module *module; |
d3d5b87d CH |
343 | unsigned int flags; |
344 | #define NVME_F_FABRICS (1 << 0) | |
c81bfba9 | 345 | #define NVME_F_METADATA_SUPPORTED (1 << 1) |
1c63dc66 | 346 | int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); |
5fd4ce1b | 347 | int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); |
7fd8930f | 348 | int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); |
1673f1f0 | 349 | void (*free_ctrl)(struct nvme_ctrl *ctrl); |
ad22c355 | 350 | void (*submit_async_event)(struct nvme_ctrl *ctrl); |
c5017e85 | 351 | void (*delete_ctrl)(struct nvme_ctrl *ctrl); |
1a353d85 | 352 | int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); |
b435ecea | 353 | void (*stop_ctrl)(struct nvme_ctrl *ctrl); |
f11bb3e2 CH |
354 | }; |
355 | ||
b9e03857 TT |
356 | #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS |
357 | void nvme_fault_inject_init(struct nvme_ns *ns); | |
358 | void nvme_fault_inject_fini(struct nvme_ns *ns); | |
359 | void nvme_should_fail(struct request *req); | |
360 | #else | |
361 | static inline void nvme_fault_inject_init(struct nvme_ns *ns) {} | |
362 | static inline void nvme_fault_inject_fini(struct nvme_ns *ns) {} | |
363 | static inline void nvme_should_fail(struct request *req) {} | |
364 | #endif | |
365 | ||
1c63dc66 CH |
366 | static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl) |
367 | { | |
368 | u32 val = 0; | |
369 | ||
370 | if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val)) | |
371 | return false; | |
372 | return val & NVME_CSTS_RDY; | |
373 | } | |
374 | ||
f3ca80fc CH |
375 | static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) |
376 | { | |
377 | if (!ctrl->subsystem) | |
378 | return -ENOTTY; | |
379 | return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); | |
380 | } | |
381 | ||
f11bb3e2 CH |
382 | static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector) |
383 | { | |
384 | return (sector >> (ns->lba_shift - 9)); | |
385 | } | |
386 | ||
27fa9bc5 CH |
387 | static inline void nvme_end_request(struct request *req, __le16 status, |
388 | union nvme_result result) | |
15a190f7 | 389 | { |
27fa9bc5 | 390 | struct nvme_request *rq = nvme_req(req); |
15a190f7 | 391 | |
27fa9bc5 CH |
392 | rq->status = le16_to_cpu(status) >> 1; |
393 | rq->result = result; | |
b9e03857 TT |
394 | /* inject error when permitted by fault injection framework */ |
395 | nvme_should_fail(req); | |
08e0029a | 396 | blk_mq_complete_request(req); |
7688faa6 CH |
397 | } |
398 | ||
d22524a4 CH |
399 | static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl) |
400 | { | |
401 | get_device(ctrl->device); | |
402 | } | |
403 | ||
404 | static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl) | |
405 | { | |
406 | put_device(ctrl->device); | |
407 | } | |
408 | ||
77f02a7a | 409 | void nvme_complete_rq(struct request *req); |
c55a2fd4 | 410 | void nvme_cancel_request(struct request *req, void *data, bool reserved); |
bb8d261e CH |
411 | bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, |
412 | enum nvme_ctrl_state new_state); | |
5fd4ce1b CH |
413 | int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap); |
414 | int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap); | |
415 | int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl); | |
f3ca80fc CH |
416 | int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, |
417 | const struct nvme_ctrl_ops *ops, unsigned long quirks); | |
53029b04 | 418 | void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); |
d09f2b45 SG |
419 | void nvme_start_ctrl(struct nvme_ctrl *ctrl); |
420 | void nvme_stop_ctrl(struct nvme_ctrl *ctrl); | |
1673f1f0 | 421 | void nvme_put_ctrl(struct nvme_ctrl *ctrl); |
7fd8930f | 422 | int nvme_init_identify(struct nvme_ctrl *ctrl); |
5bae7f73 | 423 | |
5bae7f73 | 424 | void nvme_remove_namespaces(struct nvme_ctrl *ctrl); |
1673f1f0 | 425 | |
4f1244c8 CH |
426 | int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len, |
427 | bool send); | |
a98e58e5 | 428 | |
7bf58533 | 429 | void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, |
287a63eb | 430 | volatile union nvme_result *res); |
f866fc42 | 431 | |
25646264 KB |
432 | void nvme_stop_queues(struct nvme_ctrl *ctrl); |
433 | void nvme_start_queues(struct nvme_ctrl *ctrl); | |
69d9a99c | 434 | void nvme_kill_queues(struct nvme_ctrl *ctrl); |
302ad8cc KB |
435 | void nvme_unfreeze(struct nvme_ctrl *ctrl); |
436 | void nvme_wait_freeze(struct nvme_ctrl *ctrl); | |
437 | void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout); | |
438 | void nvme_start_freeze(struct nvme_ctrl *ctrl); | |
363c9aac | 439 | |
eb71f435 | 440 | #define NVME_QID_ANY -1 |
4160982e | 441 | struct request *nvme_alloc_request(struct request_queue *q, |
9a95e4ef | 442 | struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid); |
f7f1fc36 | 443 | void nvme_cleanup_cmd(struct request *req); |
fc17b653 | 444 | blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req, |
8093f7ca | 445 | struct nvme_command *cmd); |
f11bb3e2 CH |
446 | int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
447 | void *buf, unsigned bufflen); | |
448 | int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, | |
d49187e9 | 449 | union nvme_result *result, void *buffer, unsigned bufflen, |
9a95e4ef BVA |
450 | unsigned timeout, int qid, int at_head, |
451 | blk_mq_req_flags_t flags); | |
9a0be7ab | 452 | int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); |
038bd4cb | 453 | void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); |
d86c4d8e | 454 | int nvme_reset_ctrl(struct nvme_ctrl *ctrl); |
79c48ccf | 455 | int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl); |
c5017e85 CH |
456 | int nvme_delete_ctrl(struct nvme_ctrl *ctrl); |
457 | int nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl); | |
f11bb3e2 | 458 | |
0e98719b CH |
459 | int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, |
460 | void *log, size_t size, u64 offset); | |
d558fb51 | 461 | |
5b85b826 | 462 | extern const struct attribute_group nvme_ns_id_attr_group; |
32acab31 CH |
463 | extern const struct block_device_operations nvme_ns_head_ops; |
464 | ||
465 | #ifdef CONFIG_NVME_MULTIPATH | |
0d0b660f | 466 | bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl); |
a785dbcc KB |
467 | void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns, |
468 | struct nvme_ctrl *ctrl, int *flags); | |
32acab31 | 469 | void nvme_failover_req(struct request *req); |
32acab31 CH |
470 | void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl); |
471 | int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,struct nvme_ns_head *head); | |
0d0b660f | 472 | void nvme_mpath_add_disk(struct nvme_ns *ns, struct nvme_id_ns *id); |
32acab31 | 473 | void nvme_mpath_remove_disk(struct nvme_ns_head *head); |
0d0b660f CH |
474 | int nvme_mpath_init(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id); |
475 | void nvme_mpath_uninit(struct nvme_ctrl *ctrl); | |
476 | void nvme_mpath_stop(struct nvme_ctrl *ctrl); | |
32acab31 CH |
477 | |
478 | static inline void nvme_mpath_clear_current_path(struct nvme_ns *ns) | |
479 | { | |
480 | struct nvme_ns_head *head = ns->head; | |
481 | ||
978628ec | 482 | if (head && ns == rcu_access_pointer(head->current_path)) |
32acab31 CH |
483 | rcu_assign_pointer(head->current_path, NULL); |
484 | } | |
485 | struct nvme_ns *nvme_find_path(struct nvme_ns_head *head); | |
479a322f SG |
486 | |
487 | static inline void nvme_mpath_check_last_path(struct nvme_ns *ns) | |
488 | { | |
489 | struct nvme_ns_head *head = ns->head; | |
490 | ||
491 | if (head->disk && list_empty(&head->list)) | |
492 | kblockd_schedule_work(&head->requeue_work); | |
493 | } | |
494 | ||
0d0b660f CH |
495 | extern struct device_attribute dev_attr_ana_grpid; |
496 | extern struct device_attribute dev_attr_ana_state; | |
497 | ||
32acab31 | 498 | #else |
0d0b660f CH |
499 | static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) |
500 | { | |
501 | return false; | |
502 | } | |
a785dbcc KB |
503 | /* |
504 | * Without the multipath code enabled, multiple controller per subsystems are | |
505 | * visible as devices and thus we cannot use the subsystem instance. | |
506 | */ | |
507 | static inline void nvme_set_disk_name(char *disk_name, struct nvme_ns *ns, | |
508 | struct nvme_ctrl *ctrl, int *flags) | |
509 | { | |
510 | sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->head->instance); | |
511 | } | |
512 | ||
32acab31 CH |
513 | static inline void nvme_failover_req(struct request *req) |
514 | { | |
515 | } | |
32acab31 CH |
516 | static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl) |
517 | { | |
518 | } | |
519 | static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl, | |
520 | struct nvme_ns_head *head) | |
521 | { | |
522 | return 0; | |
523 | } | |
0d0b660f CH |
524 | static inline void nvme_mpath_add_disk(struct nvme_ns *ns, |
525 | struct nvme_id_ns *id) | |
32acab31 CH |
526 | { |
527 | } | |
528 | static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head) | |
529 | { | |
530 | } | |
531 | static inline void nvme_mpath_clear_current_path(struct nvme_ns *ns) | |
479a322f SG |
532 | { |
533 | } | |
534 | static inline void nvme_mpath_check_last_path(struct nvme_ns *ns) | |
32acab31 CH |
535 | { |
536 | } | |
0d0b660f CH |
537 | static inline int nvme_mpath_init(struct nvme_ctrl *ctrl, |
538 | struct nvme_id_ctrl *id) | |
539 | { | |
540 | return 0; | |
541 | } | |
542 | static inline void nvme_mpath_uninit(struct nvme_ctrl *ctrl) | |
543 | { | |
544 | } | |
545 | static inline void nvme_mpath_stop(struct nvme_ctrl *ctrl) | |
546 | { | |
547 | } | |
32acab31 CH |
548 | #endif /* CONFIG_NVME_MULTIPATH */ |
549 | ||
c4699e70 | 550 | #ifdef CONFIG_NVM |
96257a8a | 551 | void nvme_nvm_update_nvm_info(struct nvme_ns *ns); |
3dc87dd0 | 552 | int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node); |
b0b4e09c | 553 | void nvme_nvm_unregister(struct nvme_ns *ns); |
3dc87dd0 MB |
554 | int nvme_nvm_register_sysfs(struct nvme_ns *ns); |
555 | void nvme_nvm_unregister_sysfs(struct nvme_ns *ns); | |
84d4add7 | 556 | int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg); |
c4699e70 | 557 | #else |
96257a8a | 558 | static inline void nvme_nvm_update_nvm_info(struct nvme_ns *ns) {}; |
b0b4e09c | 559 | static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, |
3dc87dd0 | 560 | int node) |
c4699e70 KB |
561 | { |
562 | return 0; | |
563 | } | |
564 | ||
b0b4e09c | 565 | static inline void nvme_nvm_unregister(struct nvme_ns *ns) {}; |
3dc87dd0 MB |
566 | static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns) |
567 | { | |
568 | return 0; | |
569 | } | |
570 | static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {}; | |
84d4add7 MB |
571 | static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, |
572 | unsigned long arg) | |
573 | { | |
574 | return -ENOTTY; | |
575 | } | |
3dc87dd0 MB |
576 | #endif /* CONFIG_NVM */ |
577 | ||
40267efd SL |
578 | static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev) |
579 | { | |
580 | return dev_to_disk(dev)->private_data; | |
581 | } | |
ca064085 | 582 | |
5bae7f73 CH |
583 | int __init nvme_core_init(void); |
584 | void nvme_core_exit(void); | |
585 | ||
f11bb3e2 | 586 | #endif /* _NVME_H */ |