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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
8de05535 | 15 | #include <linux/bitops.h> |
b60503ba | 16 | #include <linux/blkdev.h> |
a4aea562 | 17 | #include <linux/blk-mq.h> |
42f61420 | 18 | #include <linux/cpu.h> |
fd63e9ce | 19 | #include <linux/delay.h> |
b60503ba MW |
20 | #include <linux/errno.h> |
21 | #include <linux/fs.h> | |
22 | #include <linux/genhd.h> | |
4cc09e2d | 23 | #include <linux/hdreg.h> |
5aff9382 | 24 | #include <linux/idr.h> |
b60503ba MW |
25 | #include <linux/init.h> |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/kdev_t.h> | |
1fa6aead | 29 | #include <linux/kthread.h> |
b60503ba | 30 | #include <linux/kernel.h> |
a5768aa8 | 31 | #include <linux/list_sort.h> |
b60503ba MW |
32 | #include <linux/mm.h> |
33 | #include <linux/module.h> | |
34 | #include <linux/moduleparam.h> | |
35 | #include <linux/pci.h> | |
be7b6275 | 36 | #include <linux/poison.h> |
c3bfe717 | 37 | #include <linux/ptrace.h> |
b60503ba MW |
38 | #include <linux/sched.h> |
39 | #include <linux/slab.h> | |
e1e5e564 | 40 | #include <linux/t10-pi.h> |
b60503ba | 41 | #include <linux/types.h> |
1d277a63 | 42 | #include <linux/pr.h> |
5d0f6131 | 43 | #include <scsi/sg.h> |
2f8e2c87 | 44 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 45 | #include <asm/unaligned.h> |
797a796a | 46 | |
9d99a8dd | 47 | #include <uapi/linux/nvme_ioctl.h> |
f11bb3e2 CH |
48 | #include "nvme.h" |
49 | ||
b3fffdef | 50 | #define NVME_MINORS (1U << MINORBITS) |
9d43cf64 | 51 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 52 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
53 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
54 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
2484f407 | 55 | #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ) |
9d43cf64 | 56 | |
21d34711 | 57 | unsigned char admin_timeout = 60; |
9d43cf64 KB |
58 | module_param(admin_timeout, byte, 0644); |
59 | MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands"); | |
b60503ba | 60 | |
bd67608a MW |
61 | unsigned char nvme_io_timeout = 30; |
62 | module_param_named(io_timeout, nvme_io_timeout, byte, 0644); | |
b355084a | 63 | MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); |
b60503ba | 64 | |
2484f407 DM |
65 | static unsigned char shutdown_timeout = 5; |
66 | module_param(shutdown_timeout, byte, 0644); | |
67 | MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown"); | |
68 | ||
b60503ba MW |
69 | static int nvme_major; |
70 | module_param(nvme_major, int, 0); | |
71 | ||
b3fffdef KB |
72 | static int nvme_char_major; |
73 | module_param(nvme_char_major, int, 0); | |
74 | ||
58ffacb5 MW |
75 | static int use_threaded_interrupts; |
76 | module_param(use_threaded_interrupts, int, 0); | |
77 | ||
8ffaadf7 JD |
78 | static bool use_cmb_sqes = true; |
79 | module_param(use_cmb_sqes, bool, 0644); | |
80 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
81 | ||
1fa6aead MW |
82 | static DEFINE_SPINLOCK(dev_list_lock); |
83 | static LIST_HEAD(dev_list); | |
84 | static struct task_struct *nvme_thread; | |
9a6b9458 | 85 | static struct workqueue_struct *nvme_workq; |
b9afca3e | 86 | static wait_queue_head_t nvme_kthread_wait; |
1fa6aead | 87 | |
b3fffdef KB |
88 | static struct class *nvme_class; |
89 | ||
1c63dc66 CH |
90 | struct nvme_dev; |
91 | struct nvme_queue; | |
d4f6c3ab | 92 | struct nvme_iod; |
1c63dc66 | 93 | |
90667892 | 94 | static int __nvme_reset(struct nvme_dev *dev); |
4cc06521 | 95 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 96 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
d4f6c3ab | 97 | static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod); |
3cf519b5 | 98 | static void nvme_dead_ctrl(struct nvme_dev *dev); |
d4b4ff8e | 99 | |
4d115420 KB |
100 | struct async_cmd_info { |
101 | struct kthread_work work; | |
102 | struct kthread_worker *worker; | |
a4aea562 | 103 | struct request *req; |
4d115420 KB |
104 | u32 result; |
105 | int status; | |
106 | void *ctx; | |
107 | }; | |
1fa6aead | 108 | |
1c63dc66 CH |
109 | /* |
110 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
111 | */ | |
112 | struct nvme_dev { | |
113 | struct list_head node; | |
114 | struct nvme_queue **queues; | |
115 | struct blk_mq_tag_set tagset; | |
116 | struct blk_mq_tag_set admin_tagset; | |
117 | u32 __iomem *dbs; | |
118 | struct device *dev; | |
119 | struct dma_pool *prp_page_pool; | |
120 | struct dma_pool *prp_small_pool; | |
121 | unsigned queue_count; | |
122 | unsigned online_queues; | |
123 | unsigned max_qid; | |
124 | int q_depth; | |
125 | u32 db_stride; | |
126 | u32 ctrl_config; | |
127 | struct msix_entry *entry; | |
128 | void __iomem *bar; | |
129 | struct list_head namespaces; | |
130 | struct kref kref; | |
131 | struct device *device; | |
132 | struct work_struct reset_work; | |
133 | struct work_struct probe_work; | |
134 | struct work_struct scan_work; | |
135 | bool subsystem; | |
136 | u32 max_hw_sectors; | |
137 | u32 stripe_size; | |
138 | u32 page_size; | |
139 | void __iomem *cmb; | |
140 | dma_addr_t cmb_dma_addr; | |
141 | u64 cmb_size; | |
142 | u32 cmbsz; | |
143 | ||
144 | struct nvme_ctrl ctrl; | |
145 | }; | |
146 | ||
147 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) | |
148 | { | |
149 | return container_of(ctrl, struct nvme_dev, ctrl); | |
150 | } | |
151 | ||
b60503ba MW |
152 | /* |
153 | * An NVM Express queue. Each device has at least two (one for admin | |
154 | * commands and one for I/O commands). | |
155 | */ | |
156 | struct nvme_queue { | |
157 | struct device *q_dmadev; | |
091b6092 | 158 | struct nvme_dev *dev; |
3193f07b | 159 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
160 | spinlock_t q_lock; |
161 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 162 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 163 | volatile struct nvme_completion *cqes; |
42483228 | 164 | struct blk_mq_tags **tags; |
b60503ba MW |
165 | dma_addr_t sq_dma_addr; |
166 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
167 | u32 __iomem *q_db; |
168 | u16 q_depth; | |
6222d172 | 169 | s16 cq_vector; |
b60503ba MW |
170 | u16 sq_head; |
171 | u16 sq_tail; | |
172 | u16 cq_head; | |
c30341dc | 173 | u16 qid; |
e9539f47 MW |
174 | u8 cq_phase; |
175 | u8 cqe_seen; | |
4d115420 | 176 | struct async_cmd_info cmdinfo; |
b60503ba MW |
177 | }; |
178 | ||
71bd150c CH |
179 | /* |
180 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
181 | * entries. You can't see it in this data structure because C doesn't let | |
182 | * me express that. Use nvme_alloc_iod to ensure there's enough space | |
183 | * allocated to store the PRP list. | |
184 | */ | |
185 | struct nvme_iod { | |
186 | unsigned long private; /* For the use of the submitter of the I/O */ | |
187 | int npages; /* In the PRP list. 0 means small pool in use */ | |
188 | int offset; /* Of PRP list */ | |
189 | int nents; /* Used in scatterlist */ | |
190 | int length; /* Of data, in bytes */ | |
191 | dma_addr_t first_dma; | |
192 | struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */ | |
193 | struct scatterlist sg[0]; | |
194 | }; | |
195 | ||
b60503ba MW |
196 | /* |
197 | * Check we didin't inadvertently grow the command struct | |
198 | */ | |
199 | static inline void _nvme_check_size(void) | |
200 | { | |
201 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
202 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
203 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
204 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
205 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 206 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 207 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
208 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
209 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
210 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
211 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 212 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
213 | } |
214 | ||
edd10d33 | 215 | typedef void (*nvme_completion_fn)(struct nvme_queue *, void *, |
c2f5b650 MW |
216 | struct nvme_completion *); |
217 | ||
e85248e5 | 218 | struct nvme_cmd_info { |
c2f5b650 MW |
219 | nvme_completion_fn fn; |
220 | void *ctx; | |
c30341dc | 221 | int aborted; |
a4aea562 | 222 | struct nvme_queue *nvmeq; |
ac3dd5bd | 223 | struct nvme_iod iod[0]; |
e85248e5 MW |
224 | }; |
225 | ||
ac3dd5bd JA |
226 | /* |
227 | * Max size of iod being embedded in the request payload | |
228 | */ | |
229 | #define NVME_INT_PAGES 2 | |
230 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size) | |
fda631ff | 231 | #define NVME_INT_MASK 0x01 |
ac3dd5bd JA |
232 | |
233 | /* | |
234 | * Will slightly overestimate the number of pages needed. This is OK | |
235 | * as it only leads to a small amount of wasted memory for the lifetime of | |
236 | * the I/O. | |
237 | */ | |
238 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
239 | { | |
240 | unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size); | |
241 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); | |
242 | } | |
243 | ||
244 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) | |
245 | { | |
246 | unsigned int ret = sizeof(struct nvme_cmd_info); | |
247 | ||
248 | ret += sizeof(struct nvme_iod); | |
249 | ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev); | |
250 | ret += sizeof(struct scatterlist) * NVME_INT_PAGES; | |
251 | ||
252 | return ret; | |
253 | } | |
254 | ||
a4aea562 MB |
255 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
256 | unsigned int hctx_idx) | |
e85248e5 | 257 | { |
a4aea562 MB |
258 | struct nvme_dev *dev = data; |
259 | struct nvme_queue *nvmeq = dev->queues[0]; | |
260 | ||
42483228 KB |
261 | WARN_ON(hctx_idx != 0); |
262 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
263 | WARN_ON(nvmeq->tags); | |
264 | ||
a4aea562 | 265 | hctx->driver_data = nvmeq; |
42483228 | 266 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 267 | return 0; |
e85248e5 MW |
268 | } |
269 | ||
4af0e21c KB |
270 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
271 | { | |
272 | struct nvme_queue *nvmeq = hctx->driver_data; | |
273 | ||
274 | nvmeq->tags = NULL; | |
275 | } | |
276 | ||
a4aea562 MB |
277 | static int nvme_admin_init_request(void *data, struct request *req, |
278 | unsigned int hctx_idx, unsigned int rq_idx, | |
279 | unsigned int numa_node) | |
22404274 | 280 | { |
a4aea562 MB |
281 | struct nvme_dev *dev = data; |
282 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
283 | struct nvme_queue *nvmeq = dev->queues[0]; | |
284 | ||
285 | BUG_ON(!nvmeq); | |
286 | cmd->nvmeq = nvmeq; | |
287 | return 0; | |
22404274 KB |
288 | } |
289 | ||
a4aea562 MB |
290 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
291 | unsigned int hctx_idx) | |
b60503ba | 292 | { |
a4aea562 | 293 | struct nvme_dev *dev = data; |
42483228 | 294 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 295 | |
42483228 KB |
296 | if (!nvmeq->tags) |
297 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 298 | |
42483228 | 299 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
300 | hctx->driver_data = nvmeq; |
301 | return 0; | |
b60503ba MW |
302 | } |
303 | ||
a4aea562 MB |
304 | static int nvme_init_request(void *data, struct request *req, |
305 | unsigned int hctx_idx, unsigned int rq_idx, | |
306 | unsigned int numa_node) | |
b60503ba | 307 | { |
a4aea562 MB |
308 | struct nvme_dev *dev = data; |
309 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
310 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; | |
311 | ||
312 | BUG_ON(!nvmeq); | |
313 | cmd->nvmeq = nvmeq; | |
314 | return 0; | |
315 | } | |
316 | ||
317 | static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx, | |
318 | nvme_completion_fn handler) | |
319 | { | |
320 | cmd->fn = handler; | |
321 | cmd->ctx = ctx; | |
322 | cmd->aborted = 0; | |
c917dfe5 | 323 | blk_mq_start_request(blk_mq_rq_from_pdu(cmd)); |
b60503ba MW |
324 | } |
325 | ||
ac3dd5bd JA |
326 | static void *iod_get_private(struct nvme_iod *iod) |
327 | { | |
328 | return (void *) (iod->private & ~0x1UL); | |
329 | } | |
330 | ||
331 | /* | |
332 | * If bit 0 is set, the iod is embedded in the request payload. | |
333 | */ | |
334 | static bool iod_should_kfree(struct nvme_iod *iod) | |
335 | { | |
fda631ff | 336 | return (iod->private & NVME_INT_MASK) == 0; |
ac3dd5bd JA |
337 | } |
338 | ||
c2f5b650 MW |
339 | /* Special values must be less than 0x1000 */ |
340 | #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA) | |
d2d87034 MW |
341 | #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) |
342 | #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) | |
343 | #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) | |
be7b6275 | 344 | |
edd10d33 | 345 | static void special_completion(struct nvme_queue *nvmeq, void *ctx, |
c2f5b650 MW |
346 | struct nvme_completion *cqe) |
347 | { | |
348 | if (ctx == CMD_CTX_CANCELLED) | |
349 | return; | |
c2f5b650 | 350 | if (ctx == CMD_CTX_COMPLETED) { |
edd10d33 | 351 | dev_warn(nvmeq->q_dmadev, |
c2f5b650 MW |
352 | "completed id %d twice on queue %d\n", |
353 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
354 | return; | |
355 | } | |
356 | if (ctx == CMD_CTX_INVALID) { | |
edd10d33 | 357 | dev_warn(nvmeq->q_dmadev, |
c2f5b650 MW |
358 | "invalid id %d completed on queue %d\n", |
359 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
360 | return; | |
361 | } | |
edd10d33 | 362 | dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx); |
c2f5b650 MW |
363 | } |
364 | ||
a4aea562 | 365 | static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn) |
b60503ba | 366 | { |
c2f5b650 | 367 | void *ctx; |
b60503ba | 368 | |
859361a2 | 369 | if (fn) |
a4aea562 MB |
370 | *fn = cmd->fn; |
371 | ctx = cmd->ctx; | |
372 | cmd->fn = special_completion; | |
373 | cmd->ctx = CMD_CTX_CANCELLED; | |
c2f5b650 | 374 | return ctx; |
b60503ba MW |
375 | } |
376 | ||
a4aea562 MB |
377 | static void async_req_completion(struct nvme_queue *nvmeq, void *ctx, |
378 | struct nvme_completion *cqe) | |
3c0cf138 | 379 | { |
a4aea562 MB |
380 | u32 result = le32_to_cpup(&cqe->result); |
381 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
382 | ||
383 | if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) | |
1c63dc66 | 384 | ++nvmeq->dev->ctrl.event_limit; |
a5768aa8 KB |
385 | if (status != NVME_SC_SUCCESS) |
386 | return; | |
387 | ||
388 | switch (result & 0xff07) { | |
389 | case NVME_AER_NOTICE_NS_CHANGED: | |
390 | dev_info(nvmeq->q_dmadev, "rescanning\n"); | |
391 | schedule_work(&nvmeq->dev->scan_work); | |
392 | default: | |
393 | dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result); | |
394 | } | |
b60503ba MW |
395 | } |
396 | ||
a4aea562 MB |
397 | static void abort_completion(struct nvme_queue *nvmeq, void *ctx, |
398 | struct nvme_completion *cqe) | |
5a92e700 | 399 | { |
a4aea562 MB |
400 | struct request *req = ctx; |
401 | ||
402 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
403 | u32 result = le32_to_cpup(&cqe->result); | |
a51afb54 | 404 | |
42483228 | 405 | blk_mq_free_request(req); |
a51afb54 | 406 | |
a4aea562 | 407 | dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result); |
1c63dc66 | 408 | ++nvmeq->dev->ctrl.abort_limit; |
5a92e700 KB |
409 | } |
410 | ||
a4aea562 MB |
411 | static void async_completion(struct nvme_queue *nvmeq, void *ctx, |
412 | struct nvme_completion *cqe) | |
b60503ba | 413 | { |
a4aea562 MB |
414 | struct async_cmd_info *cmdinfo = ctx; |
415 | cmdinfo->result = le32_to_cpup(&cqe->result); | |
416 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
417 | queue_kthread_work(cmdinfo->worker, &cmdinfo->work); | |
42483228 | 418 | blk_mq_free_request(cmdinfo->req); |
b60503ba MW |
419 | } |
420 | ||
a4aea562 MB |
421 | static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq, |
422 | unsigned int tag) | |
b60503ba | 423 | { |
42483228 | 424 | struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag); |
a51afb54 | 425 | |
a4aea562 | 426 | return blk_mq_rq_to_pdu(req); |
4f5099af KB |
427 | } |
428 | ||
a4aea562 MB |
429 | /* |
430 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
431 | */ | |
432 | static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag, | |
433 | nvme_completion_fn *fn) | |
4f5099af | 434 | { |
a4aea562 MB |
435 | struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag); |
436 | void *ctx; | |
437 | if (tag >= nvmeq->q_depth) { | |
438 | *fn = special_completion; | |
439 | return CMD_CTX_INVALID; | |
440 | } | |
441 | if (fn) | |
442 | *fn = cmd->fn; | |
443 | ctx = cmd->ctx; | |
444 | cmd->fn = special_completion; | |
445 | cmd->ctx = CMD_CTX_COMPLETED; | |
446 | return ctx; | |
b60503ba MW |
447 | } |
448 | ||
449 | /** | |
714a7a22 | 450 | * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
451 | * @nvmeq: The queue to use |
452 | * @cmd: The command to send | |
453 | * | |
454 | * Safe to use from interrupt context | |
455 | */ | |
e3f879bf SB |
456 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
457 | struct nvme_command *cmd) | |
b60503ba | 458 | { |
a4aea562 MB |
459 | u16 tail = nvmeq->sq_tail; |
460 | ||
8ffaadf7 JD |
461 | if (nvmeq->sq_cmds_io) |
462 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
463 | else | |
464 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
465 | ||
b60503ba MW |
466 | if (++tail == nvmeq->q_depth) |
467 | tail = 0; | |
7547881d | 468 | writel(tail, nvmeq->q_db); |
b60503ba | 469 | nvmeq->sq_tail = tail; |
b60503ba MW |
470 | } |
471 | ||
e3f879bf | 472 | static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) |
a4aea562 MB |
473 | { |
474 | unsigned long flags; | |
a4aea562 | 475 | spin_lock_irqsave(&nvmeq->q_lock, flags); |
e3f879bf | 476 | __nvme_submit_cmd(nvmeq, cmd); |
a4aea562 | 477 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); |
a4aea562 MB |
478 | } |
479 | ||
eca18b23 | 480 | static __le64 **iod_list(struct nvme_iod *iod) |
e025344c | 481 | { |
eca18b23 | 482 | return ((void *)iod) + iod->offset; |
e025344c SMM |
483 | } |
484 | ||
ac3dd5bd JA |
485 | static inline void iod_init(struct nvme_iod *iod, unsigned nbytes, |
486 | unsigned nseg, unsigned long private) | |
eca18b23 | 487 | { |
ac3dd5bd JA |
488 | iod->private = private; |
489 | iod->offset = offsetof(struct nvme_iod, sg[nseg]); | |
490 | iod->npages = -1; | |
491 | iod->length = nbytes; | |
492 | iod->nents = 0; | |
eca18b23 | 493 | } |
b60503ba | 494 | |
eca18b23 | 495 | static struct nvme_iod * |
ac3dd5bd JA |
496 | __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev, |
497 | unsigned long priv, gfp_t gfp) | |
b60503ba | 498 | { |
eca18b23 | 499 | struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) + |
ac3dd5bd | 500 | sizeof(__le64 *) * nvme_npages(bytes, dev) + |
eca18b23 MW |
501 | sizeof(struct scatterlist) * nseg, gfp); |
502 | ||
ac3dd5bd JA |
503 | if (iod) |
504 | iod_init(iod, bytes, nseg, priv); | |
eca18b23 MW |
505 | |
506 | return iod; | |
b60503ba MW |
507 | } |
508 | ||
ac3dd5bd JA |
509 | static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev, |
510 | gfp_t gfp) | |
511 | { | |
512 | unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) : | |
513 | sizeof(struct nvme_dsm_range); | |
ac3dd5bd JA |
514 | struct nvme_iod *iod; |
515 | ||
516 | if (rq->nr_phys_segments <= NVME_INT_PAGES && | |
517 | size <= NVME_INT_BYTES(dev)) { | |
518 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq); | |
519 | ||
520 | iod = cmd->iod; | |
ac3dd5bd | 521 | iod_init(iod, size, rq->nr_phys_segments, |
fda631ff | 522 | (unsigned long) rq | NVME_INT_MASK); |
ac3dd5bd JA |
523 | return iod; |
524 | } | |
525 | ||
526 | return __nvme_alloc_iod(rq->nr_phys_segments, size, dev, | |
527 | (unsigned long) rq, gfp); | |
528 | } | |
529 | ||
d29ec824 | 530 | static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) |
b60503ba | 531 | { |
1d090624 | 532 | const int last_prp = dev->page_size / 8 - 1; |
eca18b23 MW |
533 | int i; |
534 | __le64 **list = iod_list(iod); | |
535 | dma_addr_t prp_dma = iod->first_dma; | |
536 | ||
537 | if (iod->npages == 0) | |
538 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
539 | for (i = 0; i < iod->npages; i++) { | |
540 | __le64 *prp_list = list[i]; | |
541 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
542 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
543 | prp_dma = next_prp_dma; | |
544 | } | |
ac3dd5bd JA |
545 | |
546 | if (iod_should_kfree(iod)) | |
547 | kfree(iod); | |
b60503ba MW |
548 | } |
549 | ||
52b68d7e | 550 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
551 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
552 | { | |
553 | if (be32_to_cpu(pi->ref_tag) == v) | |
554 | pi->ref_tag = cpu_to_be32(p); | |
555 | } | |
556 | ||
557 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
558 | { | |
559 | if (be32_to_cpu(pi->ref_tag) == p) | |
560 | pi->ref_tag = cpu_to_be32(v); | |
561 | } | |
562 | ||
563 | /** | |
564 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
565 | * | |
566 | * The virtual start sector is the one that was originally submitted by the | |
567 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
568 | * start sector may be different. Remap protection information to match the | |
569 | * physical LBA on writes, and back to the original seed on reads. | |
570 | * | |
571 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
572 | */ | |
573 | static void nvme_dif_remap(struct request *req, | |
574 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
575 | { | |
576 | struct nvme_ns *ns = req->rq_disk->private_data; | |
577 | struct bio_integrity_payload *bip; | |
578 | struct t10_pi_tuple *pi; | |
579 | void *p, *pmap; | |
580 | u32 i, nlb, ts, phys, virt; | |
581 | ||
582 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
583 | return; | |
584 | ||
585 | bip = bio_integrity(req->bio); | |
586 | if (!bip) | |
587 | return; | |
588 | ||
589 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
590 | |
591 | p = pmap; | |
592 | virt = bip_get_seed(bip); | |
593 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
594 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 595 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
596 | |
597 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
598 | pi = (struct t10_pi_tuple *)p; | |
599 | dif_swap(phys, virt, pi); | |
600 | p += ts; | |
601 | } | |
602 | kunmap_atomic(pmap); | |
603 | } | |
604 | ||
52b68d7e KB |
605 | static void nvme_init_integrity(struct nvme_ns *ns) |
606 | { | |
607 | struct blk_integrity integrity; | |
608 | ||
609 | switch (ns->pi_type) { | |
610 | case NVME_NS_DPS_PI_TYPE3: | |
0f8087ec | 611 | integrity.profile = &t10_pi_type3_crc; |
52b68d7e KB |
612 | break; |
613 | case NVME_NS_DPS_PI_TYPE1: | |
614 | case NVME_NS_DPS_PI_TYPE2: | |
0f8087ec | 615 | integrity.profile = &t10_pi_type1_crc; |
52b68d7e KB |
616 | break; |
617 | default: | |
4125a09b | 618 | integrity.profile = NULL; |
52b68d7e KB |
619 | break; |
620 | } | |
621 | integrity.tuple_size = ns->ms; | |
622 | blk_integrity_register(ns->disk, &integrity); | |
623 | blk_queue_max_integrity_segments(ns->queue, 1); | |
624 | } | |
625 | #else /* CONFIG_BLK_DEV_INTEGRITY */ | |
626 | static void nvme_dif_remap(struct request *req, | |
627 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
628 | { | |
629 | } | |
630 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
631 | { | |
632 | } | |
633 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
634 | { | |
635 | } | |
636 | static void nvme_init_integrity(struct nvme_ns *ns) | |
637 | { | |
638 | } | |
639 | #endif | |
640 | ||
a4aea562 | 641 | static void req_completion(struct nvme_queue *nvmeq, void *ctx, |
b60503ba MW |
642 | struct nvme_completion *cqe) |
643 | { | |
eca18b23 | 644 | struct nvme_iod *iod = ctx; |
ac3dd5bd | 645 | struct request *req = iod_get_private(iod); |
a4aea562 | 646 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
b60503ba | 647 | u16 status = le16_to_cpup(&cqe->status) >> 1; |
81c04b94 | 648 | int error = 0; |
b60503ba | 649 | |
edd10d33 | 650 | if (unlikely(status)) { |
a4aea562 MB |
651 | if (!(status & NVME_SC_DNR || blk_noretry_request(req)) |
652 | && (jiffies - req->start_time) < req->timeout) { | |
c9d3bf88 KB |
653 | unsigned long flags; |
654 | ||
d4f6c3ab CH |
655 | nvme_unmap_data(nvmeq->dev, iod); |
656 | ||
a4aea562 | 657 | blk_mq_requeue_request(req); |
c9d3bf88 KB |
658 | spin_lock_irqsave(req->q->queue_lock, flags); |
659 | if (!blk_queue_stopped(req->q)) | |
660 | blk_mq_kick_requeue_list(req->q); | |
661 | spin_unlock_irqrestore(req->q->queue_lock, flags); | |
d4f6c3ab | 662 | return; |
edd10d33 | 663 | } |
f4829a9b | 664 | |
d29ec824 | 665 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) { |
17188bb4 | 666 | if (cmd_rq->ctx == CMD_CTX_CANCELLED) |
81c04b94 CH |
667 | error = -EINTR; |
668 | else | |
669 | error = status; | |
d29ec824 | 670 | } else { |
81c04b94 | 671 | error = nvme_error_status(status); |
d29ec824 | 672 | } |
f4829a9b CH |
673 | } |
674 | ||
a0a931d6 KB |
675 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) { |
676 | u32 result = le32_to_cpup(&cqe->result); | |
677 | req->special = (void *)(uintptr_t)result; | |
678 | } | |
a4aea562 MB |
679 | |
680 | if (cmd_rq->aborted) | |
e75ec752 | 681 | dev_warn(nvmeq->dev->dev, |
a4aea562 | 682 | "completing aborted command with status:%04x\n", |
81c04b94 | 683 | error); |
a4aea562 | 684 | |
d4f6c3ab CH |
685 | nvme_unmap_data(nvmeq->dev, iod); |
686 | blk_mq_complete_request(req, error); | |
b60503ba MW |
687 | } |
688 | ||
69d2b571 CH |
689 | static bool nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, |
690 | int total_len) | |
ff22b54f | 691 | { |
99802a7a | 692 | struct dma_pool *pool; |
eca18b23 MW |
693 | int length = total_len; |
694 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
695 | int dma_len = sg_dma_len(sg); |
696 | u64 dma_addr = sg_dma_address(sg); | |
f137e0f1 MI |
697 | u32 page_size = dev->page_size; |
698 | int offset = dma_addr & (page_size - 1); | |
e025344c | 699 | __le64 *prp_list; |
eca18b23 | 700 | __le64 **list = iod_list(iod); |
e025344c | 701 | dma_addr_t prp_dma; |
eca18b23 | 702 | int nprps, i; |
ff22b54f | 703 | |
1d090624 | 704 | length -= (page_size - offset); |
ff22b54f | 705 | if (length <= 0) |
69d2b571 | 706 | return true; |
ff22b54f | 707 | |
1d090624 | 708 | dma_len -= (page_size - offset); |
ff22b54f | 709 | if (dma_len) { |
1d090624 | 710 | dma_addr += (page_size - offset); |
ff22b54f MW |
711 | } else { |
712 | sg = sg_next(sg); | |
713 | dma_addr = sg_dma_address(sg); | |
714 | dma_len = sg_dma_len(sg); | |
715 | } | |
716 | ||
1d090624 | 717 | if (length <= page_size) { |
edd10d33 | 718 | iod->first_dma = dma_addr; |
69d2b571 | 719 | return true; |
e025344c SMM |
720 | } |
721 | ||
1d090624 | 722 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
723 | if (nprps <= (256 / 8)) { |
724 | pool = dev->prp_small_pool; | |
eca18b23 | 725 | iod->npages = 0; |
99802a7a MW |
726 | } else { |
727 | pool = dev->prp_page_pool; | |
eca18b23 | 728 | iod->npages = 1; |
99802a7a MW |
729 | } |
730 | ||
69d2b571 | 731 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 732 | if (!prp_list) { |
edd10d33 | 733 | iod->first_dma = dma_addr; |
eca18b23 | 734 | iod->npages = -1; |
69d2b571 | 735 | return false; |
b77954cb | 736 | } |
eca18b23 MW |
737 | list[0] = prp_list; |
738 | iod->first_dma = prp_dma; | |
e025344c SMM |
739 | i = 0; |
740 | for (;;) { | |
1d090624 | 741 | if (i == page_size >> 3) { |
e025344c | 742 | __le64 *old_prp_list = prp_list; |
69d2b571 | 743 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 744 | if (!prp_list) |
69d2b571 | 745 | return false; |
eca18b23 | 746 | list[iod->npages++] = prp_list; |
7523d834 MW |
747 | prp_list[0] = old_prp_list[i - 1]; |
748 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
749 | i = 1; | |
e025344c SMM |
750 | } |
751 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
752 | dma_len -= page_size; |
753 | dma_addr += page_size; | |
754 | length -= page_size; | |
e025344c SMM |
755 | if (length <= 0) |
756 | break; | |
757 | if (dma_len > 0) | |
758 | continue; | |
759 | BUG_ON(dma_len < 0); | |
760 | sg = sg_next(sg); | |
761 | dma_addr = sg_dma_address(sg); | |
762 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
763 | } |
764 | ||
69d2b571 | 765 | return true; |
ff22b54f MW |
766 | } |
767 | ||
ba1ca37e CH |
768 | static int nvme_map_data(struct nvme_dev *dev, struct nvme_iod *iod, |
769 | struct nvme_command *cmnd) | |
d29ec824 | 770 | { |
ba1ca37e CH |
771 | struct request *req = iod_get_private(iod); |
772 | struct request_queue *q = req->q; | |
773 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
774 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
775 | int ret = BLK_MQ_RQ_QUEUE_ERROR; | |
776 | ||
777 | sg_init_table(iod->sg, req->nr_phys_segments); | |
778 | iod->nents = blk_rq_map_sg(q, req, iod->sg); | |
779 | if (!iod->nents) | |
780 | goto out; | |
781 | ||
782 | ret = BLK_MQ_RQ_QUEUE_BUSY; | |
783 | if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir)) | |
784 | goto out; | |
785 | ||
786 | if (!nvme_setup_prps(dev, iod, blk_rq_bytes(req))) | |
787 | goto out_unmap; | |
788 | ||
789 | ret = BLK_MQ_RQ_QUEUE_ERROR; | |
790 | if (blk_integrity_rq(req)) { | |
791 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
792 | goto out_unmap; | |
793 | ||
794 | sg_init_table(iod->meta_sg, 1); | |
795 | if (blk_rq_map_integrity_sg(q, req->bio, iod->meta_sg) != 1) | |
796 | goto out_unmap; | |
d29ec824 | 797 | |
ba1ca37e CH |
798 | if (rq_data_dir(req)) |
799 | nvme_dif_remap(req, nvme_dif_prep); | |
800 | ||
801 | if (!dma_map_sg(dev->dev, iod->meta_sg, 1, dma_dir)) | |
802 | goto out_unmap; | |
d29ec824 CH |
803 | } |
804 | ||
ba1ca37e CH |
805 | cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
806 | cmnd->rw.prp2 = cpu_to_le64(iod->first_dma); | |
807 | if (blk_integrity_rq(req)) | |
808 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg)); | |
809 | return BLK_MQ_RQ_QUEUE_OK; | |
810 | ||
811 | out_unmap: | |
812 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
813 | out: | |
814 | return ret; | |
d29ec824 CH |
815 | } |
816 | ||
d4f6c3ab CH |
817 | static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod) |
818 | { | |
819 | struct request *req = iod_get_private(iod); | |
820 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
821 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
822 | ||
823 | if (iod->nents) { | |
824 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
825 | if (blk_integrity_rq(req)) { | |
826 | if (!rq_data_dir(req)) | |
827 | nvme_dif_remap(req, nvme_dif_complete); | |
828 | dma_unmap_sg(dev->dev, iod->meta_sg, 1, dma_dir); | |
829 | } | |
830 | } | |
831 | ||
832 | nvme_free_iod(dev, iod); | |
833 | } | |
834 | ||
a4aea562 MB |
835 | /* |
836 | * We reuse the small pool to allocate the 16-byte range here as it is not | |
837 | * worth having a special pool for these or additional cases to handle freeing | |
838 | * the iod. | |
839 | */ | |
ba1ca37e CH |
840 | static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
841 | struct nvme_iod *iod, struct nvme_command *cmnd) | |
0e5e4f0e | 842 | { |
ba1ca37e CH |
843 | struct request *req = iod_get_private(iod); |
844 | struct nvme_dsm_range *range; | |
845 | ||
846 | range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC, | |
847 | &iod->first_dma); | |
848 | if (!range) | |
849 | return BLK_MQ_RQ_QUEUE_BUSY; | |
850 | iod_list(iod)[0] = (__le64 *)range; | |
851 | iod->npages = 0; | |
0e5e4f0e | 852 | |
0e5e4f0e | 853 | range->cattr = cpu_to_le32(0); |
a4aea562 MB |
854 | range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift); |
855 | range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
0e5e4f0e | 856 | |
ba1ca37e CH |
857 | memset(cmnd, 0, sizeof(*cmnd)); |
858 | cmnd->dsm.opcode = nvme_cmd_dsm; | |
859 | cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); | |
860 | cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); | |
861 | cmnd->dsm.nr = 0; | |
862 | cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); | |
863 | return BLK_MQ_RQ_QUEUE_OK; | |
0e5e4f0e KB |
864 | } |
865 | ||
d29ec824 CH |
866 | /* |
867 | * NOTE: ns is NULL when called on the admin queue. | |
868 | */ | |
a4aea562 MB |
869 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
870 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 871 | { |
a4aea562 MB |
872 | struct nvme_ns *ns = hctx->queue->queuedata; |
873 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 874 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 MB |
875 | struct request *req = bd->rq; |
876 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
edd10d33 | 877 | struct nvme_iod *iod; |
ba1ca37e CH |
878 | struct nvme_command cmnd; |
879 | int ret = BLK_MQ_RQ_QUEUE_OK; | |
edd10d33 | 880 | |
e1e5e564 KB |
881 | /* |
882 | * If formated with metadata, require the block layer provide a buffer | |
883 | * unless this namespace is formated such that the metadata can be | |
884 | * stripped/generated by the controller with PRACT=1. | |
885 | */ | |
d29ec824 | 886 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 KB |
887 | if (!(ns->pi_type && ns->ms == 8) && |
888 | req->cmd_type != REQ_TYPE_DRV_PRIV) { | |
f4829a9b | 889 | blk_mq_complete_request(req, -EFAULT); |
e1e5e564 KB |
890 | return BLK_MQ_RQ_QUEUE_OK; |
891 | } | |
892 | } | |
893 | ||
d29ec824 | 894 | iod = nvme_alloc_iod(req, dev, GFP_ATOMIC); |
edd10d33 | 895 | if (!iod) |
fe54303e | 896 | return BLK_MQ_RQ_QUEUE_BUSY; |
a4aea562 | 897 | |
a4aea562 | 898 | if (req->cmd_flags & REQ_DISCARD) { |
ba1ca37e CH |
899 | ret = nvme_setup_discard(nvmeq, ns, iod, &cmnd); |
900 | } else { | |
901 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) | |
902 | memcpy(&cmnd, req->cmd, sizeof(cmnd)); | |
903 | else if (req->cmd_flags & REQ_FLUSH) | |
904 | nvme_setup_flush(ns, &cmnd); | |
905 | else | |
906 | nvme_setup_rw(ns, req, &cmnd); | |
a4aea562 | 907 | |
ba1ca37e CH |
908 | if (req->nr_phys_segments) |
909 | ret = nvme_map_data(dev, iod, &cmnd); | |
edd10d33 | 910 | } |
1974b1ae | 911 | |
ba1ca37e CH |
912 | if (ret) |
913 | goto out; | |
914 | ||
915 | cmnd.common.command_id = req->tag; | |
9af8785a | 916 | nvme_set_info(cmd, iod, req_completion); |
a4aea562 | 917 | |
ba1ca37e CH |
918 | spin_lock_irq(&nvmeq->q_lock); |
919 | __nvme_submit_cmd(nvmeq, &cmnd); | |
a4aea562 MB |
920 | nvme_process_cq(nvmeq); |
921 | spin_unlock_irq(&nvmeq->q_lock); | |
922 | return BLK_MQ_RQ_QUEUE_OK; | |
ba1ca37e | 923 | out: |
d29ec824 | 924 | nvme_free_iod(dev, iod); |
ba1ca37e | 925 | return ret; |
b60503ba MW |
926 | } |
927 | ||
a0fa9647 | 928 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 929 | { |
82123460 | 930 | u16 head, phase; |
b60503ba | 931 | |
b60503ba | 932 | head = nvmeq->cq_head; |
82123460 | 933 | phase = nvmeq->cq_phase; |
b60503ba MW |
934 | |
935 | for (;;) { | |
c2f5b650 MW |
936 | void *ctx; |
937 | nvme_completion_fn fn; | |
b60503ba | 938 | struct nvme_completion cqe = nvmeq->cqes[head]; |
82123460 | 939 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
940 | break; |
941 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
942 | if (++head == nvmeq->q_depth) { | |
943 | head = 0; | |
82123460 | 944 | phase = !phase; |
b60503ba | 945 | } |
a0fa9647 JA |
946 | if (tag && *tag == cqe.command_id) |
947 | *tag = -1; | |
a4aea562 | 948 | ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn); |
edd10d33 | 949 | fn(nvmeq, ctx, &cqe); |
b60503ba MW |
950 | } |
951 | ||
952 | /* If the controller ignores the cq head doorbell and continuously | |
953 | * writes to the queue, it is theoretically possible to wrap around | |
954 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
955 | * requires that 0.1% of your interrupts are handled, so this isn't | |
956 | * a big problem. | |
957 | */ | |
82123460 | 958 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 959 | return; |
b60503ba | 960 | |
604e8c8d KB |
961 | if (likely(nvmeq->cq_vector >= 0)) |
962 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 963 | nvmeq->cq_head = head; |
82123460 | 964 | nvmeq->cq_phase = phase; |
b60503ba | 965 | |
e9539f47 | 966 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
967 | } |
968 | ||
969 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
970 | { | |
971 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
972 | } |
973 | ||
974 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
975 | { |
976 | irqreturn_t result; | |
977 | struct nvme_queue *nvmeq = data; | |
978 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
979 | nvme_process_cq(nvmeq); |
980 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
981 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
982 | spin_unlock(&nvmeq->q_lock); |
983 | return result; | |
984 | } | |
985 | ||
986 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
987 | { | |
988 | struct nvme_queue *nvmeq = data; | |
989 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
990 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
991 | return IRQ_NONE; | |
992 | return IRQ_WAKE_THREAD; | |
993 | } | |
994 | ||
a0fa9647 JA |
995 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
996 | { | |
997 | struct nvme_queue *nvmeq = hctx->driver_data; | |
998 | ||
999 | if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == | |
1000 | nvmeq->cq_phase) { | |
1001 | spin_lock_irq(&nvmeq->q_lock); | |
1002 | __nvme_process_cq(nvmeq, &tag); | |
1003 | spin_unlock_irq(&nvmeq->q_lock); | |
1004 | ||
1005 | if (tag == -1) | |
1006 | return 1; | |
1007 | } | |
1008 | ||
1009 | return 0; | |
1010 | } | |
1011 | ||
a4aea562 MB |
1012 | static int nvme_submit_async_admin_req(struct nvme_dev *dev) |
1013 | { | |
1014 | struct nvme_queue *nvmeq = dev->queues[0]; | |
1015 | struct nvme_command c; | |
1016 | struct nvme_cmd_info *cmd_info; | |
1017 | struct request *req; | |
1018 | ||
1c63dc66 | 1019 | req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, |
6f3b0e8b | 1020 | BLK_MQ_REQ_NOWAIT | BLK_MQ_REQ_RESERVED); |
9f173b33 DC |
1021 | if (IS_ERR(req)) |
1022 | return PTR_ERR(req); | |
a4aea562 | 1023 | |
c917dfe5 | 1024 | req->cmd_flags |= REQ_NO_TIMEOUT; |
a4aea562 | 1025 | cmd_info = blk_mq_rq_to_pdu(req); |
1efccc9d | 1026 | nvme_set_info(cmd_info, NULL, async_req_completion); |
a4aea562 MB |
1027 | |
1028 | memset(&c, 0, sizeof(c)); | |
1029 | c.common.opcode = nvme_admin_async_event; | |
1030 | c.common.command_id = req->tag; | |
1031 | ||
42483228 | 1032 | blk_mq_free_request(req); |
e3f879bf SB |
1033 | __nvme_submit_cmd(nvmeq, &c); |
1034 | return 0; | |
a4aea562 MB |
1035 | } |
1036 | ||
1037 | static int nvme_submit_admin_async_cmd(struct nvme_dev *dev, | |
4d115420 KB |
1038 | struct nvme_command *cmd, |
1039 | struct async_cmd_info *cmdinfo, unsigned timeout) | |
1040 | { | |
a4aea562 MB |
1041 | struct nvme_queue *nvmeq = dev->queues[0]; |
1042 | struct request *req; | |
1043 | struct nvme_cmd_info *cmd_rq; | |
4d115420 | 1044 | |
1c63dc66 | 1045 | req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, 0); |
9f173b33 DC |
1046 | if (IS_ERR(req)) |
1047 | return PTR_ERR(req); | |
a4aea562 MB |
1048 | |
1049 | req->timeout = timeout; | |
1050 | cmd_rq = blk_mq_rq_to_pdu(req); | |
1051 | cmdinfo->req = req; | |
1052 | nvme_set_info(cmd_rq, cmdinfo, async_completion); | |
4d115420 | 1053 | cmdinfo->status = -EINTR; |
a4aea562 MB |
1054 | |
1055 | cmd->common.command_id = req->tag; | |
1056 | ||
e3f879bf SB |
1057 | nvme_submit_cmd(nvmeq, cmd); |
1058 | return 0; | |
4d115420 KB |
1059 | } |
1060 | ||
b60503ba MW |
1061 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
1062 | { | |
b60503ba MW |
1063 | struct nvme_command c; |
1064 | ||
1065 | memset(&c, 0, sizeof(c)); | |
1066 | c.delete_queue.opcode = opcode; | |
1067 | c.delete_queue.qid = cpu_to_le16(id); | |
1068 | ||
1c63dc66 | 1069 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1070 | } |
1071 | ||
1072 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
1073 | struct nvme_queue *nvmeq) | |
1074 | { | |
b60503ba MW |
1075 | struct nvme_command c; |
1076 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
1077 | ||
d29ec824 CH |
1078 | /* |
1079 | * Note: we (ab)use the fact the the prp fields survive if no data | |
1080 | * is attached to the request. | |
1081 | */ | |
b60503ba MW |
1082 | memset(&c, 0, sizeof(c)); |
1083 | c.create_cq.opcode = nvme_admin_create_cq; | |
1084 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
1085 | c.create_cq.cqid = cpu_to_le16(qid); | |
1086 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1087 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
1088 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
1089 | ||
1c63dc66 | 1090 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1091 | } |
1092 | ||
1093 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
1094 | struct nvme_queue *nvmeq) | |
1095 | { | |
b60503ba MW |
1096 | struct nvme_command c; |
1097 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
1098 | ||
d29ec824 CH |
1099 | /* |
1100 | * Note: we (ab)use the fact the the prp fields survive if no data | |
1101 | * is attached to the request. | |
1102 | */ | |
b60503ba MW |
1103 | memset(&c, 0, sizeof(c)); |
1104 | c.create_sq.opcode = nvme_admin_create_sq; | |
1105 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
1106 | c.create_sq.sqid = cpu_to_le16(qid); | |
1107 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1108 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
1109 | c.create_sq.cqid = cpu_to_le16(qid); | |
1110 | ||
1c63dc66 | 1111 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1112 | } |
1113 | ||
1114 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
1115 | { | |
1116 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
1117 | } | |
1118 | ||
1119 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
1120 | { | |
1121 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
1122 | } | |
1123 | ||
c30341dc | 1124 | /** |
a4aea562 | 1125 | * nvme_abort_req - Attempt aborting a request |
c30341dc KB |
1126 | * |
1127 | * Schedule controller reset if the command was already aborted once before and | |
1128 | * still hasn't been returned to the driver, or if this is the admin queue. | |
1129 | */ | |
a4aea562 | 1130 | static void nvme_abort_req(struct request *req) |
c30341dc | 1131 | { |
a4aea562 MB |
1132 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
1133 | struct nvme_queue *nvmeq = cmd_rq->nvmeq; | |
c30341dc | 1134 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 MB |
1135 | struct request *abort_req; |
1136 | struct nvme_cmd_info *abort_cmd; | |
1137 | struct nvme_command cmd; | |
c30341dc | 1138 | |
a4aea562 | 1139 | if (!nvmeq->qid || cmd_rq->aborted) { |
90667892 CH |
1140 | spin_lock(&dev_list_lock); |
1141 | if (!__nvme_reset(dev)) { | |
1142 | dev_warn(dev->dev, | |
1143 | "I/O %d QID %d timeout, reset controller\n", | |
1144 | req->tag, nvmeq->qid); | |
1145 | } | |
1146 | spin_unlock(&dev_list_lock); | |
c30341dc KB |
1147 | return; |
1148 | } | |
1149 | ||
1c63dc66 | 1150 | if (!dev->ctrl.abort_limit) |
c30341dc KB |
1151 | return; |
1152 | ||
1c63dc66 | 1153 | abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, |
6f3b0e8b | 1154 | BLK_MQ_REQ_NOWAIT); |
9f173b33 | 1155 | if (IS_ERR(abort_req)) |
c30341dc KB |
1156 | return; |
1157 | ||
a4aea562 MB |
1158 | abort_cmd = blk_mq_rq_to_pdu(abort_req); |
1159 | nvme_set_info(abort_cmd, abort_req, abort_completion); | |
1160 | ||
c30341dc KB |
1161 | memset(&cmd, 0, sizeof(cmd)); |
1162 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 1163 | cmd.abort.cid = req->tag; |
c30341dc | 1164 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
a4aea562 | 1165 | cmd.abort.command_id = abort_req->tag; |
c30341dc | 1166 | |
1c63dc66 | 1167 | --dev->ctrl.abort_limit; |
a4aea562 | 1168 | cmd_rq->aborted = 1; |
c30341dc | 1169 | |
a4aea562 | 1170 | dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag, |
c30341dc | 1171 | nvmeq->qid); |
e3f879bf | 1172 | nvme_submit_cmd(dev->queues[0], &cmd); |
c30341dc KB |
1173 | } |
1174 | ||
42483228 | 1175 | static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved) |
a09115b2 | 1176 | { |
a4aea562 MB |
1177 | struct nvme_queue *nvmeq = data; |
1178 | void *ctx; | |
1179 | nvme_completion_fn fn; | |
1180 | struct nvme_cmd_info *cmd; | |
cef6a948 KB |
1181 | struct nvme_completion cqe; |
1182 | ||
1183 | if (!blk_mq_request_started(req)) | |
1184 | return; | |
a09115b2 | 1185 | |
a4aea562 | 1186 | cmd = blk_mq_rq_to_pdu(req); |
a09115b2 | 1187 | |
a4aea562 MB |
1188 | if (cmd->ctx == CMD_CTX_CANCELLED) |
1189 | return; | |
1190 | ||
cef6a948 KB |
1191 | if (blk_queue_dying(req->q)) |
1192 | cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1); | |
1193 | else | |
1194 | cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1); | |
1195 | ||
1196 | ||
a4aea562 MB |
1197 | dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", |
1198 | req->tag, nvmeq->qid); | |
1199 | ctx = cancel_cmd_info(cmd, &fn); | |
1200 | fn(nvmeq, ctx, &cqe); | |
a09115b2 MW |
1201 | } |
1202 | ||
a4aea562 | 1203 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
9e866774 | 1204 | { |
a4aea562 MB |
1205 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); |
1206 | struct nvme_queue *nvmeq = cmd->nvmeq; | |
1207 | ||
1208 | dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag, | |
1209 | nvmeq->qid); | |
7a509a6b | 1210 | spin_lock_irq(&nvmeq->q_lock); |
07836e65 | 1211 | nvme_abort_req(req); |
7a509a6b | 1212 | spin_unlock_irq(&nvmeq->q_lock); |
a4aea562 | 1213 | |
07836e65 KB |
1214 | /* |
1215 | * The aborted req will be completed on receiving the abort req. | |
1216 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1217 | * as the device then is in a faulty state. | |
1218 | */ | |
1219 | return BLK_EH_RESET_TIMER; | |
a4aea562 | 1220 | } |
22404274 | 1221 | |
a4aea562 MB |
1222 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1223 | { | |
9e866774 MW |
1224 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1225 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1226 | if (nvmeq->sq_cmds) |
1227 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1228 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1229 | kfree(nvmeq); | |
1230 | } | |
1231 | ||
a1a5ef99 | 1232 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1233 | { |
1234 | int i; | |
1235 | ||
a1a5ef99 | 1236 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1237 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1238 | dev->queue_count--; |
a4aea562 | 1239 | dev->queues[i] = NULL; |
f435c282 | 1240 | nvme_free_queue(nvmeq); |
121c7ad4 | 1241 | } |
22404274 KB |
1242 | } |
1243 | ||
4d115420 KB |
1244 | /** |
1245 | * nvme_suspend_queue - put queue into suspended state | |
1246 | * @nvmeq - queue to suspend | |
4d115420 KB |
1247 | */ |
1248 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1249 | { |
2b25d981 | 1250 | int vector; |
b60503ba | 1251 | |
a09115b2 | 1252 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1253 | if (nvmeq->cq_vector == -1) { |
1254 | spin_unlock_irq(&nvmeq->q_lock); | |
1255 | return 1; | |
1256 | } | |
1257 | vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; | |
42f61420 | 1258 | nvmeq->dev->online_queues--; |
2b25d981 | 1259 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1260 | spin_unlock_irq(&nvmeq->q_lock); |
1261 | ||
1c63dc66 CH |
1262 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
1263 | blk_mq_freeze_queue_start(nvmeq->dev->ctrl.admin_q); | |
6df3dbc8 | 1264 | |
aba2080f MW |
1265 | irq_set_affinity_hint(vector, NULL); |
1266 | free_irq(vector, nvmeq); | |
b60503ba | 1267 | |
4d115420 KB |
1268 | return 0; |
1269 | } | |
b60503ba | 1270 | |
4d115420 KB |
1271 | static void nvme_clear_queue(struct nvme_queue *nvmeq) |
1272 | { | |
22404274 | 1273 | spin_lock_irq(&nvmeq->q_lock); |
42483228 KB |
1274 | if (nvmeq->tags && *nvmeq->tags) |
1275 | blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq); | |
22404274 | 1276 | spin_unlock_irq(&nvmeq->q_lock); |
b60503ba MW |
1277 | } |
1278 | ||
4d115420 KB |
1279 | static void nvme_disable_queue(struct nvme_dev *dev, int qid) |
1280 | { | |
a4aea562 | 1281 | struct nvme_queue *nvmeq = dev->queues[qid]; |
4d115420 KB |
1282 | |
1283 | if (!nvmeq) | |
1284 | return; | |
1285 | if (nvme_suspend_queue(nvmeq)) | |
1286 | return; | |
1287 | ||
0e53d180 KB |
1288 | /* Don't tell the adapter to delete the admin queue. |
1289 | * Don't tell a removed adapter to delete IO queues. */ | |
7a67cbea | 1290 | if (qid && readl(dev->bar + NVME_REG_CSTS) != -1) { |
b60503ba MW |
1291 | adapter_delete_sq(dev, qid); |
1292 | adapter_delete_cq(dev, qid); | |
1293 | } | |
07836e65 KB |
1294 | |
1295 | spin_lock_irq(&nvmeq->q_lock); | |
1296 | nvme_process_cq(nvmeq); | |
1297 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1298 | } |
1299 | ||
8ffaadf7 JD |
1300 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1301 | int entry_size) | |
1302 | { | |
1303 | int q_depth = dev->q_depth; | |
1304 | unsigned q_size_aligned = roundup(q_depth * entry_size, dev->page_size); | |
1305 | ||
1306 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 JD |
1307 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
1308 | mem_per_q = round_down(mem_per_q, dev->page_size); | |
1309 | q_depth = div_u64(mem_per_q, entry_size); | |
8ffaadf7 JD |
1310 | |
1311 | /* | |
1312 | * Ensure the reduced q_depth is above some threshold where it | |
1313 | * would be better to map queues in system memory with the | |
1314 | * original depth | |
1315 | */ | |
1316 | if (q_depth < 64) | |
1317 | return -ENOMEM; | |
1318 | } | |
1319 | ||
1320 | return q_depth; | |
1321 | } | |
1322 | ||
1323 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1324 | int qid, int depth) | |
1325 | { | |
1326 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
1327 | unsigned offset = (qid - 1) * | |
1328 | roundup(SQ_SIZE(depth), dev->page_size); | |
1329 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; | |
1330 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1331 | } else { | |
1332 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1333 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1334 | if (!nvmeq->sq_cmds) | |
1335 | return -ENOMEM; | |
1336 | } | |
1337 | ||
1338 | return 0; | |
1339 | } | |
1340 | ||
b60503ba | 1341 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
2b25d981 | 1342 | int depth) |
b60503ba | 1343 | { |
a4aea562 | 1344 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1345 | if (!nvmeq) |
1346 | return NULL; | |
1347 | ||
e75ec752 | 1348 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1349 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1350 | if (!nvmeq->cqes) |
1351 | goto free_nvmeq; | |
b60503ba | 1352 | |
8ffaadf7 | 1353 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1354 | goto free_cqdma; |
1355 | ||
e75ec752 | 1356 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1357 | nvmeq->dev = dev; |
3193f07b | 1358 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1c63dc66 | 1359 | dev->ctrl.instance, qid); |
b60503ba MW |
1360 | spin_lock_init(&nvmeq->q_lock); |
1361 | nvmeq->cq_head = 0; | |
82123460 | 1362 | nvmeq->cq_phase = 1; |
b80d5ccc | 1363 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1364 | nvmeq->q_depth = depth; |
c30341dc | 1365 | nvmeq->qid = qid; |
758dd7fd | 1366 | nvmeq->cq_vector = -1; |
a4aea562 | 1367 | dev->queues[qid] = nvmeq; |
b60503ba | 1368 | |
36a7e993 JD |
1369 | /* make sure queue descriptor is set before queue count, for kthread */ |
1370 | mb(); | |
1371 | dev->queue_count++; | |
1372 | ||
b60503ba MW |
1373 | return nvmeq; |
1374 | ||
1375 | free_cqdma: | |
e75ec752 | 1376 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1377 | nvmeq->cq_dma_addr); |
1378 | free_nvmeq: | |
1379 | kfree(nvmeq); | |
1380 | return NULL; | |
1381 | } | |
1382 | ||
3001082c MW |
1383 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1384 | const char *name) | |
1385 | { | |
58ffacb5 MW |
1386 | if (use_threaded_interrupts) |
1387 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
481e5bad | 1388 | nvme_irq_check, nvme_irq, IRQF_SHARED, |
58ffacb5 | 1389 | name, nvmeq); |
3001082c | 1390 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
481e5bad | 1391 | IRQF_SHARED, name, nvmeq); |
3001082c MW |
1392 | } |
1393 | ||
22404274 | 1394 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1395 | { |
22404274 | 1396 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1397 | |
7be50e93 | 1398 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1399 | nvmeq->sq_tail = 0; |
1400 | nvmeq->cq_head = 0; | |
1401 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1402 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1403 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1404 | dev->online_queues++; |
7be50e93 | 1405 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1406 | } |
1407 | ||
1408 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1409 | { | |
1410 | struct nvme_dev *dev = nvmeq->dev; | |
1411 | int result; | |
3f85d50b | 1412 | |
2b25d981 | 1413 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1414 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1415 | if (result < 0) | |
22404274 | 1416 | return result; |
b60503ba MW |
1417 | |
1418 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1419 | if (result < 0) | |
1420 | goto release_cq; | |
1421 | ||
3193f07b | 1422 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
b60503ba MW |
1423 | if (result < 0) |
1424 | goto release_sq; | |
1425 | ||
22404274 | 1426 | nvme_init_queue(nvmeq, qid); |
22404274 | 1427 | return result; |
b60503ba MW |
1428 | |
1429 | release_sq: | |
1430 | adapter_delete_sq(dev, qid); | |
1431 | release_cq: | |
1432 | adapter_delete_cq(dev, qid); | |
22404274 | 1433 | return result; |
b60503ba MW |
1434 | } |
1435 | ||
ba47e386 MW |
1436 | static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled) |
1437 | { | |
1438 | unsigned long timeout; | |
1439 | u32 bit = enabled ? NVME_CSTS_RDY : 0; | |
1440 | ||
1441 | timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; | |
1442 | ||
7a67cbea | 1443 | while ((readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_RDY) != bit) { |
ba47e386 MW |
1444 | msleep(100); |
1445 | if (fatal_signal_pending(current)) | |
1446 | return -EINTR; | |
1447 | if (time_after(jiffies, timeout)) { | |
e75ec752 | 1448 | dev_err(dev->dev, |
27e8166c MW |
1449 | "Device not ready; aborting %s\n", enabled ? |
1450 | "initialisation" : "reset"); | |
ba47e386 MW |
1451 | return -ENODEV; |
1452 | } | |
1453 | } | |
1454 | ||
1455 | return 0; | |
1456 | } | |
1457 | ||
1458 | /* | |
1459 | * If the device has been passed off to us in an enabled state, just clear | |
1460 | * the enabled bit. The spec says we should set the 'shutdown notification | |
1461 | * bits', but doing so may cause the device to complete commands to the | |
1462 | * admin queue ... and we don't know what memory that might be pointing at! | |
1463 | */ | |
1464 | static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap) | |
1465 | { | |
01079522 DM |
1466 | dev->ctrl_config &= ~NVME_CC_SHN_MASK; |
1467 | dev->ctrl_config &= ~NVME_CC_ENABLE; | |
7a67cbea | 1468 | writel(dev->ctrl_config, dev->bar + NVME_REG_CC); |
44af146a | 1469 | |
ba47e386 MW |
1470 | return nvme_wait_ready(dev, cap, false); |
1471 | } | |
1472 | ||
1473 | static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap) | |
1474 | { | |
01079522 DM |
1475 | dev->ctrl_config &= ~NVME_CC_SHN_MASK; |
1476 | dev->ctrl_config |= NVME_CC_ENABLE; | |
7a67cbea | 1477 | writel(dev->ctrl_config, dev->bar + NVME_REG_CC); |
01079522 | 1478 | |
ba47e386 MW |
1479 | return nvme_wait_ready(dev, cap, true); |
1480 | } | |
1481 | ||
1894d8f1 KB |
1482 | static int nvme_shutdown_ctrl(struct nvme_dev *dev) |
1483 | { | |
1484 | unsigned long timeout; | |
1894d8f1 | 1485 | |
01079522 DM |
1486 | dev->ctrl_config &= ~NVME_CC_SHN_MASK; |
1487 | dev->ctrl_config |= NVME_CC_SHN_NORMAL; | |
1488 | ||
7a67cbea | 1489 | writel(dev->ctrl_config, dev->bar + NVME_REG_CC); |
1894d8f1 | 1490 | |
2484f407 | 1491 | timeout = SHUTDOWN_TIMEOUT + jiffies; |
7a67cbea | 1492 | while ((readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_SHST_MASK) != |
1894d8f1 KB |
1493 | NVME_CSTS_SHST_CMPLT) { |
1494 | msleep(100); | |
1495 | if (fatal_signal_pending(current)) | |
1496 | return -EINTR; | |
1497 | if (time_after(jiffies, timeout)) { | |
e75ec752 | 1498 | dev_err(dev->dev, |
1894d8f1 KB |
1499 | "Device shutdown incomplete; abort shutdown\n"); |
1500 | return -ENODEV; | |
1501 | } | |
1502 | } | |
1503 | ||
1504 | return 0; | |
1505 | } | |
1506 | ||
a4aea562 | 1507 | static struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1508 | .queue_rq = nvme_queue_rq, |
a4aea562 MB |
1509 | .map_queue = blk_mq_map_queue, |
1510 | .init_hctx = nvme_admin_init_hctx, | |
4af0e21c | 1511 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1512 | .init_request = nvme_admin_init_request, |
1513 | .timeout = nvme_timeout, | |
1514 | }; | |
1515 | ||
1516 | static struct blk_mq_ops nvme_mq_ops = { | |
1517 | .queue_rq = nvme_queue_rq, | |
1518 | .map_queue = blk_mq_map_queue, | |
1519 | .init_hctx = nvme_init_hctx, | |
1520 | .init_request = nvme_init_request, | |
1521 | .timeout = nvme_timeout, | |
a0fa9647 | 1522 | .poll = nvme_poll, |
a4aea562 MB |
1523 | }; |
1524 | ||
ea191d2f KB |
1525 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1526 | { | |
1c63dc66 CH |
1527 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
1528 | blk_cleanup_queue(dev->ctrl.admin_q); | |
ea191d2f KB |
1529 | blk_mq_free_tag_set(&dev->admin_tagset); |
1530 | } | |
1531 | } | |
1532 | ||
a4aea562 MB |
1533 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1534 | { | |
1c63dc66 | 1535 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1536 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1537 | dev->admin_tagset.nr_hw_queues = 1; | |
1538 | dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1; | |
1efccc9d | 1539 | dev->admin_tagset.reserved_tags = 1; |
a4aea562 | 1540 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1541 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1542 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1543 | dev->admin_tagset.driver_data = dev; |
1544 | ||
1545 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1546 | return -ENOMEM; | |
1547 | ||
1c63dc66 CH |
1548 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1549 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1550 | blk_mq_free_tag_set(&dev->admin_tagset); |
1551 | return -ENOMEM; | |
1552 | } | |
1c63dc66 | 1553 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1554 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1555 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1556 | return -ENODEV; |
1557 | } | |
0fb59cbc | 1558 | } else |
1c63dc66 | 1559 | blk_mq_unfreeze_queue(dev->ctrl.admin_q); |
a4aea562 MB |
1560 | |
1561 | return 0; | |
1562 | } | |
1563 | ||
8d85fce7 | 1564 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1565 | { |
ba47e386 | 1566 | int result; |
b60503ba | 1567 | u32 aqa; |
7a67cbea | 1568 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba | 1569 | struct nvme_queue *nvmeq; |
c5c9f25b NA |
1570 | /* |
1571 | * default to a 4K page size, with the intention to update this | |
1572 | * path in the future to accomodate architectures with differing | |
1573 | * kernel and IO page sizes. | |
1574 | */ | |
1575 | unsigned page_shift = 12; | |
1d090624 | 1576 | unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12; |
1d090624 KB |
1577 | |
1578 | if (page_shift < dev_page_min) { | |
e75ec752 | 1579 | dev_err(dev->dev, |
1d090624 KB |
1580 | "Minimum device page size (%u) too large for " |
1581 | "host (%u)\n", 1 << dev_page_min, | |
1582 | 1 << page_shift); | |
1583 | return -ENODEV; | |
1584 | } | |
b60503ba | 1585 | |
7a67cbea | 1586 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ? |
dfbac8c7 KB |
1587 | NVME_CAP_NSSRC(cap) : 0; |
1588 | ||
7a67cbea CH |
1589 | if (dev->subsystem && |
1590 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1591 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1592 | |
ba47e386 MW |
1593 | result = nvme_disable_ctrl(dev, cap); |
1594 | if (result < 0) | |
1595 | return result; | |
b60503ba | 1596 | |
a4aea562 | 1597 | nvmeq = dev->queues[0]; |
cd638946 | 1598 | if (!nvmeq) { |
2b25d981 | 1599 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1600 | if (!nvmeq) |
1601 | return -ENOMEM; | |
cd638946 | 1602 | } |
b60503ba MW |
1603 | |
1604 | aqa = nvmeq->q_depth - 1; | |
1605 | aqa |= aqa << 16; | |
1606 | ||
1d090624 KB |
1607 | dev->page_size = 1 << page_shift; |
1608 | ||
01079522 | 1609 | dev->ctrl_config = NVME_CC_CSS_NVM; |
1d090624 | 1610 | dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT; |
b60503ba | 1611 | dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE; |
7f53f9d2 | 1612 | dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; |
b60503ba | 1613 | |
7a67cbea CH |
1614 | writel(aqa, dev->bar + NVME_REG_AQA); |
1615 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1616 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1617 | |
ba47e386 | 1618 | result = nvme_enable_ctrl(dev, cap); |
025c557a | 1619 | if (result) |
a4aea562 MB |
1620 | goto free_nvmeq; |
1621 | ||
2b25d981 | 1622 | nvmeq->cq_vector = 0; |
3193f07b | 1623 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
758dd7fd JD |
1624 | if (result) { |
1625 | nvmeq->cq_vector = -1; | |
0fb59cbc | 1626 | goto free_nvmeq; |
758dd7fd | 1627 | } |
025c557a | 1628 | |
b60503ba | 1629 | return result; |
a4aea562 | 1630 | |
a4aea562 MB |
1631 | free_nvmeq: |
1632 | nvme_free_queues(dev, 0); | |
1633 | return result; | |
b60503ba MW |
1634 | } |
1635 | ||
a53295b6 MW |
1636 | static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio) |
1637 | { | |
a53295b6 MW |
1638 | struct nvme_user_io io; |
1639 | struct nvme_command c; | |
d29ec824 | 1640 | unsigned length, meta_len; |
fec558b5 | 1641 | void __user *metadata; |
a53295b6 MW |
1642 | |
1643 | if (copy_from_user(&io, uio, sizeof(io))) | |
1644 | return -EFAULT; | |
6c7d4945 MW |
1645 | |
1646 | switch (io.opcode) { | |
1647 | case nvme_cmd_write: | |
1648 | case nvme_cmd_read: | |
6bbf1acd | 1649 | case nvme_cmd_compare: |
6413214c | 1650 | break; |
6c7d4945 | 1651 | default: |
6bbf1acd | 1652 | return -EINVAL; |
6c7d4945 MW |
1653 | } |
1654 | ||
d29ec824 CH |
1655 | length = (io.nblocks + 1) << ns->lba_shift; |
1656 | meta_len = (io.nblocks + 1) * ns->ms; | |
835da3f9 | 1657 | metadata = (void __user *)(uintptr_t)io.metadata; |
a53295b6 | 1658 | |
71feb364 KB |
1659 | if (ns->ext) { |
1660 | length += meta_len; | |
1661 | meta_len = 0; | |
0b7f1f26 KB |
1662 | } else if (meta_len) { |
1663 | if ((io.metadata & 3) || !io.metadata) | |
d29ec824 | 1664 | return -EINVAL; |
a67a9513 KB |
1665 | } |
1666 | ||
a53295b6 MW |
1667 | memset(&c, 0, sizeof(c)); |
1668 | c.rw.opcode = io.opcode; | |
1669 | c.rw.flags = io.flags; | |
6c7d4945 | 1670 | c.rw.nsid = cpu_to_le32(ns->ns_id); |
a53295b6 | 1671 | c.rw.slba = cpu_to_le64(io.slba); |
6c7d4945 | 1672 | c.rw.length = cpu_to_le16(io.nblocks); |
a53295b6 | 1673 | c.rw.control = cpu_to_le16(io.control); |
1c9b5265 MW |
1674 | c.rw.dsmgmt = cpu_to_le32(io.dsmgmt); |
1675 | c.rw.reftag = cpu_to_le32(io.reftag); | |
1676 | c.rw.apptag = cpu_to_le16(io.apptag); | |
1677 | c.rw.appmask = cpu_to_le16(io.appmask); | |
0b7f1f26 KB |
1678 | |
1679 | return __nvme_submit_user_cmd(ns->queue, &c, | |
1680 | (void __user *)(uintptr_t)io.addr, length, | |
1681 | metadata, meta_len, io.slba, NULL, 0); | |
a53295b6 MW |
1682 | } |
1683 | ||
1c63dc66 | 1684 | static int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns, |
a4aea562 | 1685 | struct nvme_passthru_cmd __user *ucmd) |
6ee44cdc | 1686 | { |
7963e521 | 1687 | struct nvme_passthru_cmd cmd; |
6ee44cdc | 1688 | struct nvme_command c; |
d29ec824 CH |
1689 | unsigned timeout = 0; |
1690 | int status; | |
6ee44cdc | 1691 | |
6bbf1acd MW |
1692 | if (!capable(CAP_SYS_ADMIN)) |
1693 | return -EACCES; | |
1694 | if (copy_from_user(&cmd, ucmd, sizeof(cmd))) | |
6ee44cdc | 1695 | return -EFAULT; |
6ee44cdc MW |
1696 | |
1697 | memset(&c, 0, sizeof(c)); | |
6bbf1acd MW |
1698 | c.common.opcode = cmd.opcode; |
1699 | c.common.flags = cmd.flags; | |
1700 | c.common.nsid = cpu_to_le32(cmd.nsid); | |
1701 | c.common.cdw2[0] = cpu_to_le32(cmd.cdw2); | |
1702 | c.common.cdw2[1] = cpu_to_le32(cmd.cdw3); | |
1703 | c.common.cdw10[0] = cpu_to_le32(cmd.cdw10); | |
1704 | c.common.cdw10[1] = cpu_to_le32(cmd.cdw11); | |
1705 | c.common.cdw10[2] = cpu_to_le32(cmd.cdw12); | |
1706 | c.common.cdw10[3] = cpu_to_le32(cmd.cdw13); | |
1707 | c.common.cdw10[4] = cpu_to_le32(cmd.cdw14); | |
1708 | c.common.cdw10[5] = cpu_to_le32(cmd.cdw15); | |
1709 | ||
d29ec824 CH |
1710 | if (cmd.timeout_ms) |
1711 | timeout = msecs_to_jiffies(cmd.timeout_ms); | |
eca18b23 | 1712 | |
4160982e CH |
1713 | status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c, |
1714 | (void __user *)(uintptr_t)cmd.addr, cmd.data_len, | |
d29ec824 CH |
1715 | &cmd.result, timeout); |
1716 | if (status >= 0) { | |
1717 | if (put_user(cmd.result, &ucmd->result)) | |
1718 | return -EFAULT; | |
6bbf1acd | 1719 | } |
f4f117f6 | 1720 | |
6ee44cdc MW |
1721 | return status; |
1722 | } | |
1723 | ||
81f03fed JD |
1724 | static int nvme_subsys_reset(struct nvme_dev *dev) |
1725 | { | |
1726 | if (!dev->subsystem) | |
1727 | return -ENOTTY; | |
1728 | ||
7a67cbea | 1729 | writel(0x4E564D65, dev->bar + NVME_REG_NSSR); /* "NVMe" */ |
81f03fed JD |
1730 | return 0; |
1731 | } | |
1732 | ||
b60503ba MW |
1733 | static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, |
1734 | unsigned long arg) | |
1735 | { | |
1736 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
1737 | ||
1738 | switch (cmd) { | |
6bbf1acd | 1739 | case NVME_IOCTL_ID: |
c3bfe717 | 1740 | force_successful_syscall_return(); |
6bbf1acd MW |
1741 | return ns->ns_id; |
1742 | case NVME_IOCTL_ADMIN_CMD: | |
1c63dc66 | 1743 | return nvme_user_cmd(ns->ctrl, NULL, (void __user *)arg); |
7963e521 | 1744 | case NVME_IOCTL_IO_CMD: |
1c63dc66 | 1745 | return nvme_user_cmd(ns->ctrl, ns, (void __user *)arg); |
a53295b6 MW |
1746 | case NVME_IOCTL_SUBMIT_IO: |
1747 | return nvme_submit_io(ns, (void __user *)arg); | |
5d0f6131 VV |
1748 | case SG_GET_VERSION_NUM: |
1749 | return nvme_sg_get_version_num((void __user *)arg); | |
1750 | case SG_IO: | |
1751 | return nvme_sg_io(ns, (void __user *)arg); | |
b60503ba MW |
1752 | default: |
1753 | return -ENOTTY; | |
1754 | } | |
1755 | } | |
1756 | ||
320a3827 KB |
1757 | #ifdef CONFIG_COMPAT |
1758 | static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode, | |
1759 | unsigned int cmd, unsigned long arg) | |
1760 | { | |
320a3827 KB |
1761 | switch (cmd) { |
1762 | case SG_IO: | |
e179729a | 1763 | return -ENOIOCTLCMD; |
320a3827 KB |
1764 | } |
1765 | return nvme_ioctl(bdev, mode, cmd, arg); | |
1766 | } | |
1767 | #else | |
1768 | #define nvme_compat_ioctl NULL | |
1769 | #endif | |
1770 | ||
5105aa55 | 1771 | static void nvme_free_dev(struct kref *kref); |
188c3568 KB |
1772 | static void nvme_free_ns(struct kref *kref) |
1773 | { | |
1774 | struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref); | |
1c63dc66 | 1775 | struct nvme_dev *dev = to_nvme_dev(ns->ctrl); |
188c3568 | 1776 | |
ca064085 MB |
1777 | if (ns->type == NVME_NS_LIGHTNVM) |
1778 | nvme_nvm_unregister(ns->queue, ns->disk->disk_name); | |
1779 | ||
188c3568 KB |
1780 | spin_lock(&dev_list_lock); |
1781 | ns->disk->private_data = NULL; | |
1782 | spin_unlock(&dev_list_lock); | |
1783 | ||
1c63dc66 | 1784 | kref_put(&dev->kref, nvme_free_dev); |
188c3568 KB |
1785 | put_disk(ns->disk); |
1786 | kfree(ns); | |
1787 | } | |
1788 | ||
9ac27090 KB |
1789 | static int nvme_open(struct block_device *bdev, fmode_t mode) |
1790 | { | |
9e60352c KB |
1791 | int ret = 0; |
1792 | struct nvme_ns *ns; | |
9ac27090 | 1793 | |
9e60352c KB |
1794 | spin_lock(&dev_list_lock); |
1795 | ns = bdev->bd_disk->private_data; | |
1796 | if (!ns) | |
1797 | ret = -ENXIO; | |
188c3568 | 1798 | else if (!kref_get_unless_zero(&ns->kref)) |
9e60352c KB |
1799 | ret = -ENXIO; |
1800 | spin_unlock(&dev_list_lock); | |
1801 | ||
1802 | return ret; | |
9ac27090 KB |
1803 | } |
1804 | ||
9ac27090 KB |
1805 | static void nvme_release(struct gendisk *disk, fmode_t mode) |
1806 | { | |
1807 | struct nvme_ns *ns = disk->private_data; | |
188c3568 | 1808 | kref_put(&ns->kref, nvme_free_ns); |
9ac27090 KB |
1809 | } |
1810 | ||
4cc09e2d KB |
1811 | static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo) |
1812 | { | |
1813 | /* some standard values */ | |
1814 | geo->heads = 1 << 6; | |
1815 | geo->sectors = 1 << 5; | |
1816 | geo->cylinders = get_capacity(bd->bd_disk) >> 11; | |
1817 | return 0; | |
1818 | } | |
1819 | ||
e1e5e564 KB |
1820 | static void nvme_config_discard(struct nvme_ns *ns) |
1821 | { | |
1822 | u32 logical_block_size = queue_logical_block_size(ns->queue); | |
1823 | ns->queue->limits.discard_zeroes_data = 0; | |
1824 | ns->queue->limits.discard_alignment = logical_block_size; | |
1825 | ns->queue->limits.discard_granularity = logical_block_size; | |
2bb4cd5c | 1826 | blk_queue_max_discard_sectors(ns->queue, 0xffffffff); |
e1e5e564 KB |
1827 | queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); |
1828 | } | |
1829 | ||
1b9dbf7f KB |
1830 | static int nvme_revalidate_disk(struct gendisk *disk) |
1831 | { | |
1832 | struct nvme_ns *ns = disk->private_data; | |
1c63dc66 | 1833 | struct nvme_dev *dev = to_nvme_dev(ns->ctrl); |
1b9dbf7f | 1834 | struct nvme_id_ns *id; |
a67a9513 KB |
1835 | u8 lbaf, pi_type; |
1836 | u16 old_ms; | |
e1e5e564 | 1837 | unsigned short bs; |
1b9dbf7f | 1838 | |
1c63dc66 | 1839 | if (nvme_identify_ns(&dev->ctrl, ns->ns_id, &id)) { |
a5768aa8 | 1840 | dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__, |
1c63dc66 | 1841 | dev->ctrl.instance, ns->ns_id); |
a5768aa8 | 1842 | return -ENODEV; |
1b9dbf7f | 1843 | } |
a5768aa8 KB |
1844 | if (id->ncap == 0) { |
1845 | kfree(id); | |
1846 | return -ENODEV; | |
e1e5e564 | 1847 | } |
1b9dbf7f | 1848 | |
ca064085 MB |
1849 | if (nvme_nvm_ns_supported(ns, id) && ns->type != NVME_NS_LIGHTNVM) { |
1850 | if (nvme_nvm_register(ns->queue, disk->disk_name)) { | |
1851 | dev_warn(dev->dev, | |
1852 | "%s: LightNVM init failure\n", __func__); | |
1853 | kfree(id); | |
1854 | return -ENODEV; | |
1855 | } | |
1856 | ns->type = NVME_NS_LIGHTNVM; | |
1857 | } | |
1858 | ||
e1e5e564 KB |
1859 | old_ms = ns->ms; |
1860 | lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK; | |
1b9dbf7f | 1861 | ns->lba_shift = id->lbaf[lbaf].ds; |
e1e5e564 | 1862 | ns->ms = le16_to_cpu(id->lbaf[lbaf].ms); |
a67a9513 | 1863 | ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT); |
e1e5e564 KB |
1864 | |
1865 | /* | |
1866 | * If identify namespace failed, use default 512 byte block size so | |
1867 | * block layer can use before failing read/write for 0 capacity. | |
1868 | */ | |
1869 | if (ns->lba_shift == 0) | |
1870 | ns->lba_shift = 9; | |
1871 | bs = 1 << ns->lba_shift; | |
1872 | ||
1873 | /* XXX: PI implementation requires metadata equal t10 pi tuple size */ | |
1874 | pi_type = ns->ms == sizeof(struct t10_pi_tuple) ? | |
1875 | id->dps & NVME_NS_DPS_PI_MASK : 0; | |
1876 | ||
4cfc766e | 1877 | blk_mq_freeze_queue(disk->queue); |
52b68d7e KB |
1878 | if (blk_get_integrity(disk) && (ns->pi_type != pi_type || |
1879 | ns->ms != old_ms || | |
e1e5e564 | 1880 | bs != queue_logical_block_size(disk->queue) || |
a67a9513 | 1881 | (ns->ms && ns->ext))) |
e1e5e564 KB |
1882 | blk_integrity_unregister(disk); |
1883 | ||
1884 | ns->pi_type = pi_type; | |
1885 | blk_queue_logical_block_size(ns->queue, bs); | |
1886 | ||
25520d55 | 1887 | if (ns->ms && !ns->ext) |
e1e5e564 KB |
1888 | nvme_init_integrity(ns); |
1889 | ||
ca064085 MB |
1890 | if ((ns->ms && !(ns->ms == 8 && ns->pi_type) && |
1891 | !blk_get_integrity(disk)) || | |
1892 | ns->type == NVME_NS_LIGHTNVM) | |
e1e5e564 KB |
1893 | set_capacity(disk, 0); |
1894 | else | |
1895 | set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9)); | |
1896 | ||
1c63dc66 | 1897 | if (dev->ctrl.oncs & NVME_CTRL_ONCS_DSM) |
e1e5e564 | 1898 | nvme_config_discard(ns); |
4cfc766e | 1899 | blk_mq_unfreeze_queue(disk->queue); |
1b9dbf7f | 1900 | |
d29ec824 | 1901 | kfree(id); |
1b9dbf7f KB |
1902 | return 0; |
1903 | } | |
1904 | ||
1d277a63 KB |
1905 | static char nvme_pr_type(enum pr_type type) |
1906 | { | |
1907 | switch (type) { | |
1908 | case PR_WRITE_EXCLUSIVE: | |
1909 | return 1; | |
1910 | case PR_EXCLUSIVE_ACCESS: | |
1911 | return 2; | |
1912 | case PR_WRITE_EXCLUSIVE_REG_ONLY: | |
1913 | return 3; | |
1914 | case PR_EXCLUSIVE_ACCESS_REG_ONLY: | |
1915 | return 4; | |
1916 | case PR_WRITE_EXCLUSIVE_ALL_REGS: | |
1917 | return 5; | |
1918 | case PR_EXCLUSIVE_ACCESS_ALL_REGS: | |
1919 | return 6; | |
1920 | default: | |
1921 | return 0; | |
1922 | } | |
1923 | }; | |
1924 | ||
1925 | static int nvme_pr_command(struct block_device *bdev, u32 cdw10, | |
1926 | u64 key, u64 sa_key, u8 op) | |
1927 | { | |
1928 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
1929 | struct nvme_command c; | |
1930 | u8 data[16] = { 0, }; | |
1931 | ||
1932 | put_unaligned_le64(key, &data[0]); | |
1933 | put_unaligned_le64(sa_key, &data[8]); | |
1934 | ||
1935 | memset(&c, 0, sizeof(c)); | |
1936 | c.common.opcode = op; | |
a6dd1020 CH |
1937 | c.common.nsid = cpu_to_le32(ns->ns_id); |
1938 | c.common.cdw10[0] = cpu_to_le32(cdw10); | |
1d277a63 KB |
1939 | |
1940 | return nvme_submit_sync_cmd(ns->queue, &c, data, 16); | |
1941 | } | |
1942 | ||
1943 | static int nvme_pr_register(struct block_device *bdev, u64 old, | |
1944 | u64 new, unsigned flags) | |
1945 | { | |
1946 | u32 cdw10; | |
1947 | ||
1948 | if (flags & ~PR_FL_IGNORE_KEY) | |
1949 | return -EOPNOTSUPP; | |
1950 | ||
1951 | cdw10 = old ? 2 : 0; | |
1952 | cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0; | |
1953 | cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */ | |
1954 | return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register); | |
1955 | } | |
1956 | ||
1957 | static int nvme_pr_reserve(struct block_device *bdev, u64 key, | |
1958 | enum pr_type type, unsigned flags) | |
1959 | { | |
1960 | u32 cdw10; | |
1961 | ||
1962 | if (flags & ~PR_FL_IGNORE_KEY) | |
1963 | return -EOPNOTSUPP; | |
1964 | ||
1965 | cdw10 = nvme_pr_type(type) << 8; | |
1966 | cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0); | |
1967 | return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire); | |
1968 | } | |
1969 | ||
1970 | static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new, | |
1971 | enum pr_type type, bool abort) | |
1972 | { | |
1973 | u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1; | |
1974 | return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire); | |
1975 | } | |
1976 | ||
1977 | static int nvme_pr_clear(struct block_device *bdev, u64 key) | |
1978 | { | |
73fcf4e2 | 1979 | u32 cdw10 = 1 | (key ? 1 << 3 : 0); |
1d277a63 KB |
1980 | return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register); |
1981 | } | |
1982 | ||
1983 | static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type) | |
1984 | { | |
1985 | u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0; | |
1986 | return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release); | |
1987 | } | |
1988 | ||
1989 | static const struct pr_ops nvme_pr_ops = { | |
1990 | .pr_register = nvme_pr_register, | |
1991 | .pr_reserve = nvme_pr_reserve, | |
1992 | .pr_release = nvme_pr_release, | |
1993 | .pr_preempt = nvme_pr_preempt, | |
1994 | .pr_clear = nvme_pr_clear, | |
1995 | }; | |
1996 | ||
b60503ba MW |
1997 | static const struct block_device_operations nvme_fops = { |
1998 | .owner = THIS_MODULE, | |
1999 | .ioctl = nvme_ioctl, | |
320a3827 | 2000 | .compat_ioctl = nvme_compat_ioctl, |
9ac27090 KB |
2001 | .open = nvme_open, |
2002 | .release = nvme_release, | |
4cc09e2d | 2003 | .getgeo = nvme_getgeo, |
1b9dbf7f | 2004 | .revalidate_disk= nvme_revalidate_disk, |
1d277a63 | 2005 | .pr_ops = &nvme_pr_ops, |
b60503ba MW |
2006 | }; |
2007 | ||
1fa6aead MW |
2008 | static int nvme_kthread(void *data) |
2009 | { | |
d4b4ff8e | 2010 | struct nvme_dev *dev, *next; |
1fa6aead MW |
2011 | |
2012 | while (!kthread_should_stop()) { | |
564a232c | 2013 | set_current_state(TASK_INTERRUPTIBLE); |
1fa6aead | 2014 | spin_lock(&dev_list_lock); |
d4b4ff8e | 2015 | list_for_each_entry_safe(dev, next, &dev_list, node) { |
1fa6aead | 2016 | int i; |
7a67cbea | 2017 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
dfbac8c7 KB |
2018 | |
2019 | if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) || | |
2020 | csts & NVME_CSTS_CFS) { | |
90667892 CH |
2021 | if (!__nvme_reset(dev)) { |
2022 | dev_warn(dev->dev, | |
2023 | "Failed status: %x, reset controller\n", | |
7a67cbea | 2024 | readl(dev->bar + NVME_REG_CSTS)); |
90667892 | 2025 | } |
d4b4ff8e KB |
2026 | continue; |
2027 | } | |
1fa6aead | 2028 | for (i = 0; i < dev->queue_count; i++) { |
a4aea562 | 2029 | struct nvme_queue *nvmeq = dev->queues[i]; |
740216fc MW |
2030 | if (!nvmeq) |
2031 | continue; | |
1fa6aead | 2032 | spin_lock_irq(&nvmeq->q_lock); |
bc57a0f7 | 2033 | nvme_process_cq(nvmeq); |
6fccf938 | 2034 | |
1c63dc66 | 2035 | while (i == 0 && dev->ctrl.event_limit > 0) { |
a4aea562 | 2036 | if (nvme_submit_async_admin_req(dev)) |
6fccf938 | 2037 | break; |
1c63dc66 | 2038 | dev->ctrl.event_limit--; |
6fccf938 | 2039 | } |
1fa6aead MW |
2040 | spin_unlock_irq(&nvmeq->q_lock); |
2041 | } | |
2042 | } | |
2043 | spin_unlock(&dev_list_lock); | |
acb7aa0d | 2044 | schedule_timeout(round_jiffies_relative(HZ)); |
1fa6aead MW |
2045 | } |
2046 | return 0; | |
2047 | } | |
2048 | ||
e1e5e564 | 2049 | static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid) |
b60503ba MW |
2050 | { |
2051 | struct nvme_ns *ns; | |
2052 | struct gendisk *disk; | |
e75ec752 | 2053 | int node = dev_to_node(dev->dev); |
b60503ba | 2054 | |
a4aea562 | 2055 | ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node); |
b60503ba | 2056 | if (!ns) |
e1e5e564 KB |
2057 | return; |
2058 | ||
a4aea562 | 2059 | ns->queue = blk_mq_init_queue(&dev->tagset); |
9f173b33 | 2060 | if (IS_ERR(ns->queue)) |
b60503ba | 2061 | goto out_free_ns; |
4eeb9215 MW |
2062 | queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue); |
2063 | queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue); | |
1c63dc66 | 2064 | ns->ctrl = &dev->ctrl; |
b60503ba MW |
2065 | ns->queue->queuedata = ns; |
2066 | ||
a4aea562 | 2067 | disk = alloc_disk_node(0, node); |
b60503ba MW |
2068 | if (!disk) |
2069 | goto out_free_queue; | |
a4aea562 | 2070 | |
188c3568 | 2071 | kref_init(&ns->kref); |
5aff9382 | 2072 | ns->ns_id = nsid; |
b60503ba | 2073 | ns->disk = disk; |
e1e5e564 KB |
2074 | ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */ |
2075 | list_add_tail(&ns->list, &dev->namespaces); | |
2076 | ||
e9ef4636 | 2077 | blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift); |
e824410f | 2078 | if (dev->max_hw_sectors) { |
8fc23e03 | 2079 | blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors); |
e824410f | 2080 | blk_queue_max_segments(ns->queue, |
6824c5ef | 2081 | (dev->max_hw_sectors / (dev->page_size >> 9)) + 1); |
e824410f | 2082 | } |
a4aea562 MB |
2083 | if (dev->stripe_size) |
2084 | blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9); | |
1c63dc66 | 2085 | if (dev->ctrl.vwc & NVME_CTRL_VWC_PRESENT) |
a7d2ce28 | 2086 | blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA); |
03100aad | 2087 | blk_queue_virt_boundary(ns->queue, dev->page_size - 1); |
b60503ba MW |
2088 | |
2089 | disk->major = nvme_major; | |
469071a3 | 2090 | disk->first_minor = 0; |
b60503ba MW |
2091 | disk->fops = &nvme_fops; |
2092 | disk->private_data = ns; | |
2093 | disk->queue = ns->queue; | |
b3fffdef | 2094 | disk->driverfs_dev = dev->device; |
469071a3 | 2095 | disk->flags = GENHD_FL_EXT_DEVT; |
1c63dc66 | 2096 | sprintf(disk->disk_name, "nvme%dn%d", dev->ctrl.instance, nsid); |
b60503ba | 2097 | |
e1e5e564 KB |
2098 | /* |
2099 | * Initialize capacity to 0 until we establish the namespace format and | |
2100 | * setup integrity extentions if necessary. The revalidate_disk after | |
2101 | * add_disk allows the driver to register with integrity if the format | |
2102 | * requires it. | |
2103 | */ | |
2104 | set_capacity(disk, 0); | |
a5768aa8 KB |
2105 | if (nvme_revalidate_disk(ns->disk)) |
2106 | goto out_free_disk; | |
2107 | ||
5105aa55 | 2108 | kref_get(&dev->kref); |
ca064085 MB |
2109 | if (ns->type != NVME_NS_LIGHTNVM) { |
2110 | add_disk(ns->disk); | |
2111 | if (ns->ms) { | |
2112 | struct block_device *bd = bdget_disk(ns->disk, 0); | |
2113 | if (!bd) | |
2114 | return; | |
2115 | if (blkdev_get(bd, FMODE_READ, NULL)) { | |
2116 | bdput(bd); | |
2117 | return; | |
2118 | } | |
2119 | blkdev_reread_part(bd); | |
2120 | blkdev_put(bd, FMODE_READ); | |
7bee6074 | 2121 | } |
7bee6074 | 2122 | } |
e1e5e564 | 2123 | return; |
a5768aa8 KB |
2124 | out_free_disk: |
2125 | kfree(disk); | |
2126 | list_del(&ns->list); | |
b60503ba MW |
2127 | out_free_queue: |
2128 | blk_cleanup_queue(ns->queue); | |
2129 | out_free_ns: | |
2130 | kfree(ns); | |
b60503ba MW |
2131 | } |
2132 | ||
2659e57b CH |
2133 | /* |
2134 | * Create I/O queues. Failing to create an I/O queue is not an issue, | |
2135 | * we can continue with less than the desired amount of queues, and | |
2136 | * even a controller without I/O queues an still be used to issue | |
2137 | * admin commands. This might be useful to upgrade a buggy firmware | |
2138 | * for example. | |
2139 | */ | |
42f61420 KB |
2140 | static void nvme_create_io_queues(struct nvme_dev *dev) |
2141 | { | |
a4aea562 | 2142 | unsigned i; |
42f61420 | 2143 | |
a4aea562 | 2144 | for (i = dev->queue_count; i <= dev->max_qid; i++) |
2b25d981 | 2145 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) |
42f61420 KB |
2146 | break; |
2147 | ||
a4aea562 | 2148 | for (i = dev->online_queues; i <= dev->queue_count - 1; i++) |
2659e57b CH |
2149 | if (nvme_create_queue(dev->queues[i], i)) { |
2150 | nvme_free_queues(dev, i); | |
42f61420 | 2151 | break; |
2659e57b | 2152 | } |
42f61420 KB |
2153 | } |
2154 | ||
b3b06812 | 2155 | static int set_queue_count(struct nvme_dev *dev, int count) |
b60503ba MW |
2156 | { |
2157 | int status; | |
2158 | u32 result; | |
b3b06812 | 2159 | u32 q_count = (count - 1) | ((count - 1) << 16); |
b60503ba | 2160 | |
1c63dc66 | 2161 | status = nvme_set_features(&dev->ctrl, NVME_FEAT_NUM_QUEUES, q_count, 0, |
bc5fc7e4 | 2162 | &result); |
27e8166c MW |
2163 | if (status < 0) |
2164 | return status; | |
2165 | if (status > 0) { | |
e75ec752 | 2166 | dev_err(dev->dev, "Could not set queue count (%d)\n", status); |
badc34d4 | 2167 | return 0; |
27e8166c | 2168 | } |
b60503ba MW |
2169 | return min(result & 0xffff, result >> 16) + 1; |
2170 | } | |
2171 | ||
8ffaadf7 JD |
2172 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
2173 | { | |
2174 | u64 szu, size, offset; | |
2175 | u32 cmbloc; | |
2176 | resource_size_t bar_size; | |
2177 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
2178 | void __iomem *cmb; | |
2179 | dma_addr_t dma_addr; | |
2180 | ||
2181 | if (!use_cmb_sqes) | |
2182 | return NULL; | |
2183 | ||
7a67cbea | 2184 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
2185 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
2186 | return NULL; | |
2187 | ||
7a67cbea | 2188 | cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 JD |
2189 | |
2190 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
2191 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
2192 | offset = szu * NVME_CMB_OFST(cmbloc); | |
2193 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); | |
2194 | ||
2195 | if (offset > bar_size) | |
2196 | return NULL; | |
2197 | ||
2198 | /* | |
2199 | * Controllers may support a CMB size larger than their BAR, | |
2200 | * for example, due to being behind a bridge. Reduce the CMB to | |
2201 | * the reported size of the BAR | |
2202 | */ | |
2203 | if (size > bar_size - offset) | |
2204 | size = bar_size - offset; | |
2205 | ||
2206 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; | |
2207 | cmb = ioremap_wc(dma_addr, size); | |
2208 | if (!cmb) | |
2209 | return NULL; | |
2210 | ||
2211 | dev->cmb_dma_addr = dma_addr; | |
2212 | dev->cmb_size = size; | |
2213 | return cmb; | |
2214 | } | |
2215 | ||
2216 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
2217 | { | |
2218 | if (dev->cmb) { | |
2219 | iounmap(dev->cmb); | |
2220 | dev->cmb = NULL; | |
2221 | } | |
2222 | } | |
2223 | ||
9d713c2b KB |
2224 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
2225 | { | |
b80d5ccc | 2226 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
2227 | } |
2228 | ||
8d85fce7 | 2229 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 2230 | { |
a4aea562 | 2231 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 2232 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
42f61420 | 2233 | int result, i, vecs, nr_io_queues, size; |
b60503ba | 2234 | |
42f61420 | 2235 | nr_io_queues = num_possible_cpus(); |
b348b7d5 | 2236 | result = set_queue_count(dev, nr_io_queues); |
badc34d4 | 2237 | if (result <= 0) |
1b23484b | 2238 | return result; |
b348b7d5 MW |
2239 | if (result < nr_io_queues) |
2240 | nr_io_queues = result; | |
b60503ba | 2241 | |
8ffaadf7 JD |
2242 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
2243 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
2244 | sizeof(struct nvme_command)); | |
2245 | if (result > 0) | |
2246 | dev->q_depth = result; | |
2247 | else | |
2248 | nvme_release_cmb(dev); | |
2249 | } | |
2250 | ||
9d713c2b KB |
2251 | size = db_bar_size(dev, nr_io_queues); |
2252 | if (size > 8192) { | |
f1938f6e | 2253 | iounmap(dev->bar); |
9d713c2b KB |
2254 | do { |
2255 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
2256 | if (dev->bar) | |
2257 | break; | |
2258 | if (!--nr_io_queues) | |
2259 | return -ENOMEM; | |
2260 | size = db_bar_size(dev, nr_io_queues); | |
2261 | } while (1); | |
7a67cbea | 2262 | dev->dbs = dev->bar + 4096; |
5a92e700 | 2263 | adminq->q_db = dev->dbs; |
f1938f6e MW |
2264 | } |
2265 | ||
9d713c2b | 2266 | /* Deregister the admin queue's interrupt */ |
3193f07b | 2267 | free_irq(dev->entry[0].vector, adminq); |
9d713c2b | 2268 | |
e32efbfc JA |
2269 | /* |
2270 | * If we enable msix early due to not intx, disable it again before | |
2271 | * setting up the full range we need. | |
2272 | */ | |
2273 | if (!pdev->irq) | |
2274 | pci_disable_msix(pdev); | |
2275 | ||
be577fab | 2276 | for (i = 0; i < nr_io_queues; i++) |
1b23484b | 2277 | dev->entry[i].entry = i; |
be577fab AG |
2278 | vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); |
2279 | if (vecs < 0) { | |
2280 | vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); | |
2281 | if (vecs < 0) { | |
2282 | vecs = 1; | |
2283 | } else { | |
2284 | for (i = 0; i < vecs; i++) | |
2285 | dev->entry[i].vector = i + pdev->irq; | |
fa08a396 RRG |
2286 | } |
2287 | } | |
2288 | ||
063a8096 MW |
2289 | /* |
2290 | * Should investigate if there's a performance win from allocating | |
2291 | * more queues than interrupt vectors; it might allow the submission | |
2292 | * path to scale better, even if the receive path is limited by the | |
2293 | * number of interrupts. | |
2294 | */ | |
2295 | nr_io_queues = vecs; | |
42f61420 | 2296 | dev->max_qid = nr_io_queues; |
063a8096 | 2297 | |
3193f07b | 2298 | result = queue_request_irq(dev, adminq, adminq->irqname); |
758dd7fd JD |
2299 | if (result) { |
2300 | adminq->cq_vector = -1; | |
22404274 | 2301 | goto free_queues; |
758dd7fd | 2302 | } |
1b23484b | 2303 | |
cd638946 | 2304 | /* Free previously allocated queues that are no longer usable */ |
42f61420 | 2305 | nvme_free_queues(dev, nr_io_queues + 1); |
a4aea562 | 2306 | nvme_create_io_queues(dev); |
9ecdc946 | 2307 | |
22404274 | 2308 | return 0; |
b60503ba | 2309 | |
22404274 | 2310 | free_queues: |
a1a5ef99 | 2311 | nvme_free_queues(dev, 1); |
22404274 | 2312 | return result; |
b60503ba MW |
2313 | } |
2314 | ||
a5768aa8 KB |
2315 | static int ns_cmp(void *priv, struct list_head *a, struct list_head *b) |
2316 | { | |
2317 | struct nvme_ns *nsa = container_of(a, struct nvme_ns, list); | |
2318 | struct nvme_ns *nsb = container_of(b, struct nvme_ns, list); | |
2319 | ||
2320 | return nsa->ns_id - nsb->ns_id; | |
2321 | } | |
2322 | ||
2323 | static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid) | |
2324 | { | |
2325 | struct nvme_ns *ns; | |
2326 | ||
2327 | list_for_each_entry(ns, &dev->namespaces, list) { | |
2328 | if (ns->ns_id == nsid) | |
2329 | return ns; | |
2330 | if (ns->ns_id > nsid) | |
2331 | break; | |
2332 | } | |
2333 | return NULL; | |
2334 | } | |
2335 | ||
2336 | static inline bool nvme_io_incapable(struct nvme_dev *dev) | |
2337 | { | |
7a67cbea CH |
2338 | return (!dev->bar || |
2339 | readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_CFS || | |
2340 | dev->online_queues < 2); | |
a5768aa8 KB |
2341 | } |
2342 | ||
2343 | static void nvme_ns_remove(struct nvme_ns *ns) | |
2344 | { | |
1c63dc66 CH |
2345 | bool kill = nvme_io_incapable(to_nvme_dev(ns->ctrl)) && |
2346 | !blk_queue_dying(ns->queue); | |
a5768aa8 KB |
2347 | |
2348 | if (kill) | |
2349 | blk_set_queue_dying(ns->queue); | |
9609b994 | 2350 | if (ns->disk->flags & GENHD_FL_UP) |
a5768aa8 | 2351 | del_gendisk(ns->disk); |
a5768aa8 KB |
2352 | if (kill || !blk_queue_dying(ns->queue)) { |
2353 | blk_mq_abort_requeue_list(ns->queue); | |
2354 | blk_cleanup_queue(ns->queue); | |
5105aa55 KB |
2355 | } |
2356 | list_del_init(&ns->list); | |
2357 | kref_put(&ns->kref, nvme_free_ns); | |
a5768aa8 KB |
2358 | } |
2359 | ||
2360 | static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn) | |
2361 | { | |
2362 | struct nvme_ns *ns, *next; | |
2363 | unsigned i; | |
2364 | ||
2365 | for (i = 1; i <= nn; i++) { | |
2366 | ns = nvme_find_ns(dev, i); | |
2367 | if (ns) { | |
5105aa55 | 2368 | if (revalidate_disk(ns->disk)) |
a5768aa8 | 2369 | nvme_ns_remove(ns); |
a5768aa8 KB |
2370 | } else |
2371 | nvme_alloc_ns(dev, i); | |
2372 | } | |
2373 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
5105aa55 | 2374 | if (ns->ns_id > nn) |
a5768aa8 | 2375 | nvme_ns_remove(ns); |
a5768aa8 KB |
2376 | } |
2377 | list_sort(NULL, &dev->namespaces, ns_cmp); | |
2378 | } | |
2379 | ||
bda4e0fb KB |
2380 | static void nvme_set_irq_hints(struct nvme_dev *dev) |
2381 | { | |
2382 | struct nvme_queue *nvmeq; | |
2383 | int i; | |
2384 | ||
2385 | for (i = 0; i < dev->online_queues; i++) { | |
2386 | nvmeq = dev->queues[i]; | |
2387 | ||
2388 | if (!nvmeq->tags || !(*nvmeq->tags)) | |
2389 | continue; | |
2390 | ||
2391 | irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, | |
2392 | blk_mq_tags_cpumask(*nvmeq->tags)); | |
2393 | } | |
2394 | } | |
2395 | ||
a5768aa8 KB |
2396 | static void nvme_dev_scan(struct work_struct *work) |
2397 | { | |
2398 | struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work); | |
2399 | struct nvme_id_ctrl *ctrl; | |
2400 | ||
2401 | if (!dev->tagset.tags) | |
2402 | return; | |
1c63dc66 | 2403 | if (nvme_identify_ctrl(&dev->ctrl, &ctrl)) |
a5768aa8 KB |
2404 | return; |
2405 | nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn)); | |
2406 | kfree(ctrl); | |
bda4e0fb | 2407 | nvme_set_irq_hints(dev); |
a5768aa8 KB |
2408 | } |
2409 | ||
422ef0c7 MW |
2410 | /* |
2411 | * Return: error value if an error occurred setting up the queues or calling | |
2412 | * Identify Device. 0 if these succeeded, even if adding some of the | |
2413 | * namespaces failed. At the moment, these failures are silent. TBD which | |
2414 | * failures should be reported. | |
2415 | */ | |
8d85fce7 | 2416 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 2417 | { |
e75ec752 | 2418 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
c3bfe717 | 2419 | int res; |
51814232 | 2420 | struct nvme_id_ctrl *ctrl; |
7a67cbea | 2421 | int shift = NVME_CAP_MPSMIN(lo_hi_readq(dev->bar + NVME_REG_CAP)) + 12; |
b60503ba | 2422 | |
1c63dc66 | 2423 | res = nvme_identify_ctrl(&dev->ctrl, &ctrl); |
b60503ba | 2424 | if (res) { |
e75ec752 | 2425 | dev_err(dev->dev, "Identify Controller failed (%d)\n", res); |
e1e5e564 | 2426 | return -EIO; |
b60503ba MW |
2427 | } |
2428 | ||
1c63dc66 CH |
2429 | dev->ctrl.oncs = le16_to_cpup(&ctrl->oncs); |
2430 | dev->ctrl.abort_limit = ctrl->acl + 1; | |
2431 | dev->ctrl.vwc = ctrl->vwc; | |
2432 | memcpy(dev->ctrl.serial, ctrl->sn, sizeof(ctrl->sn)); | |
2433 | memcpy(dev->ctrl.model, ctrl->mn, sizeof(ctrl->mn)); | |
2434 | memcpy(dev->ctrl.firmware_rev, ctrl->fr, sizeof(ctrl->fr)); | |
159b67d7 | 2435 | if (ctrl->mdts) |
8fc23e03 | 2436 | dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9); |
b12363d0 S |
2437 | else |
2438 | dev->max_hw_sectors = UINT_MAX; | |
68608c26 | 2439 | if ((pdev->vendor == PCI_VENDOR_ID_INTEL) && |
a4aea562 MB |
2440 | (pdev->device == 0x0953) && ctrl->vs[3]) { |
2441 | unsigned int max_hw_sectors; | |
2442 | ||
159b67d7 | 2443 | dev->stripe_size = 1 << (ctrl->vs[3] + shift); |
a4aea562 MB |
2444 | max_hw_sectors = dev->stripe_size >> (shift - 9); |
2445 | if (dev->max_hw_sectors) { | |
2446 | dev->max_hw_sectors = min(max_hw_sectors, | |
2447 | dev->max_hw_sectors); | |
2448 | } else | |
2449 | dev->max_hw_sectors = max_hw_sectors; | |
2450 | } | |
d29ec824 | 2451 | kfree(ctrl); |
a4aea562 | 2452 | |
ffe7704d KB |
2453 | if (!dev->tagset.tags) { |
2454 | dev->tagset.ops = &nvme_mq_ops; | |
2455 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
2456 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
2457 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
2458 | dev->tagset.queue_depth = | |
a4aea562 | 2459 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
2460 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
2461 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
2462 | dev->tagset.driver_data = dev; | |
b60503ba | 2463 | |
ffe7704d KB |
2464 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
2465 | return 0; | |
2466 | } | |
a5768aa8 | 2467 | schedule_work(&dev->scan_work); |
e1e5e564 | 2468 | return 0; |
b60503ba MW |
2469 | } |
2470 | ||
0877cb0d KB |
2471 | static int nvme_dev_map(struct nvme_dev *dev) |
2472 | { | |
42f61420 | 2473 | u64 cap; |
0877cb0d | 2474 | int bars, result = -ENOMEM; |
e75ec752 | 2475 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
2476 | |
2477 | if (pci_enable_device_mem(pdev)) | |
2478 | return result; | |
2479 | ||
2480 | dev->entry[0].vector = pdev->irq; | |
2481 | pci_set_master(pdev); | |
2482 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
be7837e8 JA |
2483 | if (!bars) |
2484 | goto disable_pci; | |
2485 | ||
0877cb0d KB |
2486 | if (pci_request_selected_regions(pdev, bars, "nvme")) |
2487 | goto disable_pci; | |
2488 | ||
e75ec752 CH |
2489 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
2490 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 2491 | goto disable; |
0877cb0d | 2492 | |
0877cb0d KB |
2493 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
2494 | if (!dev->bar) | |
2495 | goto disable; | |
e32efbfc | 2496 | |
7a67cbea | 2497 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 KB |
2498 | result = -ENODEV; |
2499 | goto unmap; | |
2500 | } | |
e32efbfc JA |
2501 | |
2502 | /* | |
2503 | * Some devices don't advertse INTx interrupts, pre-enable a single | |
2504 | * MSIX vec for setup. We'll adjust this later. | |
2505 | */ | |
2506 | if (!pdev->irq) { | |
2507 | result = pci_enable_msix(pdev, dev->entry, 1); | |
2508 | if (result < 0) | |
2509 | goto unmap; | |
2510 | } | |
2511 | ||
7a67cbea CH |
2512 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
2513 | ||
42f61420 KB |
2514 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
2515 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea CH |
2516 | dev->dbs = dev->bar + 4096; |
2517 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2)) | |
8ffaadf7 | 2518 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d KB |
2519 | |
2520 | return 0; | |
2521 | ||
0e53d180 KB |
2522 | unmap: |
2523 | iounmap(dev->bar); | |
2524 | dev->bar = NULL; | |
0877cb0d KB |
2525 | disable: |
2526 | pci_release_regions(pdev); | |
2527 | disable_pci: | |
2528 | pci_disable_device(pdev); | |
2529 | return result; | |
2530 | } | |
2531 | ||
2532 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
2533 | { | |
e75ec752 CH |
2534 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2535 | ||
2536 | if (pdev->msi_enabled) | |
2537 | pci_disable_msi(pdev); | |
2538 | else if (pdev->msix_enabled) | |
2539 | pci_disable_msix(pdev); | |
0877cb0d KB |
2540 | |
2541 | if (dev->bar) { | |
2542 | iounmap(dev->bar); | |
2543 | dev->bar = NULL; | |
e75ec752 | 2544 | pci_release_regions(pdev); |
0877cb0d KB |
2545 | } |
2546 | ||
e75ec752 CH |
2547 | if (pci_is_enabled(pdev)) |
2548 | pci_disable_device(pdev); | |
0877cb0d KB |
2549 | } |
2550 | ||
4d115420 KB |
2551 | struct nvme_delq_ctx { |
2552 | struct task_struct *waiter; | |
2553 | struct kthread_worker *worker; | |
2554 | atomic_t refcount; | |
2555 | }; | |
2556 | ||
2557 | static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev) | |
2558 | { | |
2559 | dq->waiter = current; | |
2560 | mb(); | |
2561 | ||
2562 | for (;;) { | |
2563 | set_current_state(TASK_KILLABLE); | |
2564 | if (!atomic_read(&dq->refcount)) | |
2565 | break; | |
2566 | if (!schedule_timeout(ADMIN_TIMEOUT) || | |
2567 | fatal_signal_pending(current)) { | |
0fb59cbc KB |
2568 | /* |
2569 | * Disable the controller first since we can't trust it | |
2570 | * at this point, but leave the admin queue enabled | |
2571 | * until all queue deletion requests are flushed. | |
2572 | * FIXME: This may take a while if there are more h/w | |
2573 | * queues than admin tags. | |
2574 | */ | |
4d115420 | 2575 | set_current_state(TASK_RUNNING); |
7a67cbea CH |
2576 | nvme_disable_ctrl(dev, |
2577 | lo_hi_readq(dev->bar + NVME_REG_CAP)); | |
0fb59cbc | 2578 | nvme_clear_queue(dev->queues[0]); |
4d115420 | 2579 | flush_kthread_worker(dq->worker); |
0fb59cbc | 2580 | nvme_disable_queue(dev, 0); |
4d115420 KB |
2581 | return; |
2582 | } | |
2583 | } | |
2584 | set_current_state(TASK_RUNNING); | |
2585 | } | |
2586 | ||
2587 | static void nvme_put_dq(struct nvme_delq_ctx *dq) | |
2588 | { | |
2589 | atomic_dec(&dq->refcount); | |
2590 | if (dq->waiter) | |
2591 | wake_up_process(dq->waiter); | |
2592 | } | |
2593 | ||
2594 | static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq) | |
2595 | { | |
2596 | atomic_inc(&dq->refcount); | |
2597 | return dq; | |
2598 | } | |
2599 | ||
2600 | static void nvme_del_queue_end(struct nvme_queue *nvmeq) | |
2601 | { | |
2602 | struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx; | |
4d115420 | 2603 | nvme_put_dq(dq); |
604e8c8d KB |
2604 | |
2605 | spin_lock_irq(&nvmeq->q_lock); | |
2606 | nvme_process_cq(nvmeq); | |
2607 | spin_unlock_irq(&nvmeq->q_lock); | |
4d115420 KB |
2608 | } |
2609 | ||
2610 | static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode, | |
2611 | kthread_work_func_t fn) | |
2612 | { | |
2613 | struct nvme_command c; | |
2614 | ||
2615 | memset(&c, 0, sizeof(c)); | |
2616 | c.delete_queue.opcode = opcode; | |
2617 | c.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
2618 | ||
2619 | init_kthread_work(&nvmeq->cmdinfo.work, fn); | |
a4aea562 MB |
2620 | return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo, |
2621 | ADMIN_TIMEOUT); | |
4d115420 KB |
2622 | } |
2623 | ||
2624 | static void nvme_del_cq_work_handler(struct kthread_work *work) | |
2625 | { | |
2626 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2627 | cmdinfo.work); | |
2628 | nvme_del_queue_end(nvmeq); | |
2629 | } | |
2630 | ||
2631 | static int nvme_delete_cq(struct nvme_queue *nvmeq) | |
2632 | { | |
2633 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq, | |
2634 | nvme_del_cq_work_handler); | |
2635 | } | |
2636 | ||
2637 | static void nvme_del_sq_work_handler(struct kthread_work *work) | |
2638 | { | |
2639 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2640 | cmdinfo.work); | |
2641 | int status = nvmeq->cmdinfo.status; | |
2642 | ||
2643 | if (!status) | |
2644 | status = nvme_delete_cq(nvmeq); | |
2645 | if (status) | |
2646 | nvme_del_queue_end(nvmeq); | |
2647 | } | |
2648 | ||
2649 | static int nvme_delete_sq(struct nvme_queue *nvmeq) | |
2650 | { | |
2651 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq, | |
2652 | nvme_del_sq_work_handler); | |
2653 | } | |
2654 | ||
2655 | static void nvme_del_queue_start(struct kthread_work *work) | |
2656 | { | |
2657 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2658 | cmdinfo.work); | |
4d115420 KB |
2659 | if (nvme_delete_sq(nvmeq)) |
2660 | nvme_del_queue_end(nvmeq); | |
2661 | } | |
2662 | ||
2663 | static void nvme_disable_io_queues(struct nvme_dev *dev) | |
2664 | { | |
2665 | int i; | |
2666 | DEFINE_KTHREAD_WORKER_ONSTACK(worker); | |
2667 | struct nvme_delq_ctx dq; | |
2668 | struct task_struct *kworker_task = kthread_run(kthread_worker_fn, | |
1c63dc66 | 2669 | &worker, "nvme%d", dev->ctrl.instance); |
4d115420 KB |
2670 | |
2671 | if (IS_ERR(kworker_task)) { | |
e75ec752 | 2672 | dev_err(dev->dev, |
4d115420 KB |
2673 | "Failed to create queue del task\n"); |
2674 | for (i = dev->queue_count - 1; i > 0; i--) | |
2675 | nvme_disable_queue(dev, i); | |
2676 | return; | |
2677 | } | |
2678 | ||
2679 | dq.waiter = NULL; | |
2680 | atomic_set(&dq.refcount, 0); | |
2681 | dq.worker = &worker; | |
2682 | for (i = dev->queue_count - 1; i > 0; i--) { | |
a4aea562 | 2683 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 KB |
2684 | |
2685 | if (nvme_suspend_queue(nvmeq)) | |
2686 | continue; | |
2687 | nvmeq->cmdinfo.ctx = nvme_get_dq(&dq); | |
2688 | nvmeq->cmdinfo.worker = dq.worker; | |
2689 | init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start); | |
2690 | queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work); | |
2691 | } | |
2692 | nvme_wait_dq(&dq, dev); | |
2693 | kthread_stop(kworker_task); | |
2694 | } | |
2695 | ||
b9afca3e DM |
2696 | /* |
2697 | * Remove the node from the device list and check | |
2698 | * for whether or not we need to stop the nvme_thread. | |
2699 | */ | |
2700 | static void nvme_dev_list_remove(struct nvme_dev *dev) | |
2701 | { | |
2702 | struct task_struct *tmp = NULL; | |
2703 | ||
2704 | spin_lock(&dev_list_lock); | |
2705 | list_del_init(&dev->node); | |
2706 | if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) { | |
2707 | tmp = nvme_thread; | |
2708 | nvme_thread = NULL; | |
2709 | } | |
2710 | spin_unlock(&dev_list_lock); | |
2711 | ||
2712 | if (tmp) | |
2713 | kthread_stop(tmp); | |
2714 | } | |
2715 | ||
c9d3bf88 KB |
2716 | static void nvme_freeze_queues(struct nvme_dev *dev) |
2717 | { | |
2718 | struct nvme_ns *ns; | |
2719 | ||
2720 | list_for_each_entry(ns, &dev->namespaces, list) { | |
2721 | blk_mq_freeze_queue_start(ns->queue); | |
2722 | ||
cddcd72b | 2723 | spin_lock_irq(ns->queue->queue_lock); |
c9d3bf88 | 2724 | queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue); |
cddcd72b | 2725 | spin_unlock_irq(ns->queue->queue_lock); |
c9d3bf88 KB |
2726 | |
2727 | blk_mq_cancel_requeue_work(ns->queue); | |
2728 | blk_mq_stop_hw_queues(ns->queue); | |
2729 | } | |
2730 | } | |
2731 | ||
2732 | static void nvme_unfreeze_queues(struct nvme_dev *dev) | |
2733 | { | |
2734 | struct nvme_ns *ns; | |
2735 | ||
2736 | list_for_each_entry(ns, &dev->namespaces, list) { | |
2737 | queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue); | |
2738 | blk_mq_unfreeze_queue(ns->queue); | |
2739 | blk_mq_start_stopped_hw_queues(ns->queue, true); | |
2740 | blk_mq_kick_requeue_list(ns->queue); | |
2741 | } | |
2742 | } | |
2743 | ||
f0b50732 | 2744 | static void nvme_dev_shutdown(struct nvme_dev *dev) |
b60503ba | 2745 | { |
22404274 | 2746 | int i; |
7c1b2450 | 2747 | u32 csts = -1; |
22404274 | 2748 | |
b9afca3e | 2749 | nvme_dev_list_remove(dev); |
1fa6aead | 2750 | |
c9d3bf88 KB |
2751 | if (dev->bar) { |
2752 | nvme_freeze_queues(dev); | |
7a67cbea | 2753 | csts = readl(dev->bar + NVME_REG_CSTS); |
c9d3bf88 | 2754 | } |
7c1b2450 | 2755 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
4d115420 | 2756 | for (i = dev->queue_count - 1; i >= 0; i--) { |
a4aea562 | 2757 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 | 2758 | nvme_suspend_queue(nvmeq); |
4d115420 KB |
2759 | } |
2760 | } else { | |
2761 | nvme_disable_io_queues(dev); | |
1894d8f1 | 2762 | nvme_shutdown_ctrl(dev); |
4d115420 KB |
2763 | nvme_disable_queue(dev, 0); |
2764 | } | |
f0b50732 | 2765 | nvme_dev_unmap(dev); |
07836e65 KB |
2766 | |
2767 | for (i = dev->queue_count - 1; i >= 0; i--) | |
2768 | nvme_clear_queue(dev->queues[i]); | |
f0b50732 KB |
2769 | } |
2770 | ||
2771 | static void nvme_dev_remove(struct nvme_dev *dev) | |
2772 | { | |
5105aa55 | 2773 | struct nvme_ns *ns, *next; |
f0b50732 | 2774 | |
5105aa55 | 2775 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) |
a5768aa8 | 2776 | nvme_ns_remove(ns); |
b60503ba MW |
2777 | } |
2778 | ||
091b6092 MW |
2779 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2780 | { | |
e75ec752 | 2781 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
2782 | PAGE_SIZE, PAGE_SIZE, 0); |
2783 | if (!dev->prp_page_pool) | |
2784 | return -ENOMEM; | |
2785 | ||
99802a7a | 2786 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 2787 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
2788 | 256, 256, 0); |
2789 | if (!dev->prp_small_pool) { | |
2790 | dma_pool_destroy(dev->prp_page_pool); | |
2791 | return -ENOMEM; | |
2792 | } | |
091b6092 MW |
2793 | return 0; |
2794 | } | |
2795 | ||
2796 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2797 | { | |
2798 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2799 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2800 | } |
2801 | ||
cd58ad7d QSA |
2802 | static DEFINE_IDA(nvme_instance_ida); |
2803 | ||
2804 | static int nvme_set_instance(struct nvme_dev *dev) | |
b60503ba | 2805 | { |
cd58ad7d QSA |
2806 | int instance, error; |
2807 | ||
2808 | do { | |
2809 | if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL)) | |
2810 | return -ENODEV; | |
2811 | ||
2812 | spin_lock(&dev_list_lock); | |
2813 | error = ida_get_new(&nvme_instance_ida, &instance); | |
2814 | spin_unlock(&dev_list_lock); | |
2815 | } while (error == -EAGAIN); | |
2816 | ||
2817 | if (error) | |
2818 | return -ENODEV; | |
2819 | ||
1c63dc66 | 2820 | dev->ctrl.instance = instance; |
cd58ad7d | 2821 | return 0; |
b60503ba MW |
2822 | } |
2823 | ||
2824 | static void nvme_release_instance(struct nvme_dev *dev) | |
2825 | { | |
cd58ad7d | 2826 | spin_lock(&dev_list_lock); |
1c63dc66 | 2827 | ida_remove(&nvme_instance_ida, dev->ctrl.instance); |
cd58ad7d | 2828 | spin_unlock(&dev_list_lock); |
b60503ba MW |
2829 | } |
2830 | ||
5e82e952 KB |
2831 | static void nvme_free_dev(struct kref *kref) |
2832 | { | |
2833 | struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref); | |
9ac27090 | 2834 | |
e75ec752 | 2835 | put_device(dev->dev); |
b3fffdef | 2836 | put_device(dev->device); |
285dffc9 | 2837 | nvme_release_instance(dev); |
4af0e21c KB |
2838 | if (dev->tagset.tags) |
2839 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
2840 | if (dev->ctrl.admin_q) |
2841 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 KB |
2842 | kfree(dev->queues); |
2843 | kfree(dev->entry); | |
2844 | kfree(dev); | |
2845 | } | |
2846 | ||
2847 | static int nvme_dev_open(struct inode *inode, struct file *f) | |
2848 | { | |
b3fffdef KB |
2849 | struct nvme_dev *dev; |
2850 | int instance = iminor(inode); | |
2851 | int ret = -ENODEV; | |
2852 | ||
2853 | spin_lock(&dev_list_lock); | |
2854 | list_for_each_entry(dev, &dev_list, node) { | |
1c63dc66 CH |
2855 | if (dev->ctrl.instance == instance) { |
2856 | if (!dev->ctrl.admin_q) { | |
2e1d8448 KB |
2857 | ret = -EWOULDBLOCK; |
2858 | break; | |
2859 | } | |
b3fffdef KB |
2860 | if (!kref_get_unless_zero(&dev->kref)) |
2861 | break; | |
2862 | f->private_data = dev; | |
2863 | ret = 0; | |
2864 | break; | |
2865 | } | |
2866 | } | |
2867 | spin_unlock(&dev_list_lock); | |
2868 | ||
2869 | return ret; | |
5e82e952 KB |
2870 | } |
2871 | ||
2872 | static int nvme_dev_release(struct inode *inode, struct file *f) | |
2873 | { | |
2874 | struct nvme_dev *dev = f->private_data; | |
2875 | kref_put(&dev->kref, nvme_free_dev); | |
2876 | return 0; | |
2877 | } | |
2878 | ||
2879 | static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg) | |
2880 | { | |
2881 | struct nvme_dev *dev = f->private_data; | |
a4aea562 MB |
2882 | struct nvme_ns *ns; |
2883 | ||
5e82e952 KB |
2884 | switch (cmd) { |
2885 | case NVME_IOCTL_ADMIN_CMD: | |
1c63dc66 | 2886 | return nvme_user_cmd(&dev->ctrl, NULL, (void __user *)arg); |
7963e521 | 2887 | case NVME_IOCTL_IO_CMD: |
a4aea562 MB |
2888 | if (list_empty(&dev->namespaces)) |
2889 | return -ENOTTY; | |
2890 | ns = list_first_entry(&dev->namespaces, struct nvme_ns, list); | |
1c63dc66 | 2891 | return nvme_user_cmd(&dev->ctrl, ns, (void __user *)arg); |
4cc06521 KB |
2892 | case NVME_IOCTL_RESET: |
2893 | dev_warn(dev->dev, "resetting controller\n"); | |
2894 | return nvme_reset(dev); | |
81f03fed JD |
2895 | case NVME_IOCTL_SUBSYS_RESET: |
2896 | return nvme_subsys_reset(dev); | |
5e82e952 KB |
2897 | default: |
2898 | return -ENOTTY; | |
2899 | } | |
2900 | } | |
2901 | ||
2902 | static const struct file_operations nvme_dev_fops = { | |
2903 | .owner = THIS_MODULE, | |
2904 | .open = nvme_dev_open, | |
2905 | .release = nvme_dev_release, | |
2906 | .unlocked_ioctl = nvme_dev_ioctl, | |
2907 | .compat_ioctl = nvme_dev_ioctl, | |
2908 | }; | |
2909 | ||
3cf519b5 | 2910 | static void nvme_probe_work(struct work_struct *work) |
f0b50732 | 2911 | { |
3cf519b5 | 2912 | struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work); |
b9afca3e | 2913 | bool start_thread = false; |
3cf519b5 | 2914 | int result; |
f0b50732 KB |
2915 | |
2916 | result = nvme_dev_map(dev); | |
2917 | if (result) | |
3cf519b5 | 2918 | goto out; |
f0b50732 KB |
2919 | |
2920 | result = nvme_configure_admin_queue(dev); | |
2921 | if (result) | |
2922 | goto unmap; | |
2923 | ||
2924 | spin_lock(&dev_list_lock); | |
b9afca3e DM |
2925 | if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) { |
2926 | start_thread = true; | |
2927 | nvme_thread = NULL; | |
2928 | } | |
f0b50732 KB |
2929 | list_add(&dev->node, &dev_list); |
2930 | spin_unlock(&dev_list_lock); | |
2931 | ||
b9afca3e DM |
2932 | if (start_thread) { |
2933 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
387caa5a | 2934 | wake_up_all(&nvme_kthread_wait); |
b9afca3e DM |
2935 | } else |
2936 | wait_event_killable(nvme_kthread_wait, nvme_thread); | |
2937 | ||
2938 | if (IS_ERR_OR_NULL(nvme_thread)) { | |
2939 | result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR; | |
2940 | goto disable; | |
2941 | } | |
a4aea562 MB |
2942 | |
2943 | nvme_init_queue(dev->queues[0], 0); | |
0fb59cbc KB |
2944 | result = nvme_alloc_admin_tags(dev); |
2945 | if (result) | |
2946 | goto disable; | |
b9afca3e | 2947 | |
f0b50732 | 2948 | result = nvme_setup_io_queues(dev); |
badc34d4 | 2949 | if (result) |
0fb59cbc | 2950 | goto free_tags; |
f0b50732 | 2951 | |
1c63dc66 | 2952 | dev->ctrl.event_limit = 1; |
3cf519b5 | 2953 | |
2659e57b CH |
2954 | /* |
2955 | * Keep the controller around but remove all namespaces if we don't have | |
2956 | * any working I/O queue. | |
2957 | */ | |
3cf519b5 CH |
2958 | if (dev->online_queues < 2) { |
2959 | dev_warn(dev->dev, "IO queues not created\n"); | |
3cf519b5 CH |
2960 | nvme_dev_remove(dev); |
2961 | } else { | |
2962 | nvme_unfreeze_queues(dev); | |
2963 | nvme_dev_add(dev); | |
2964 | } | |
2965 | ||
2966 | return; | |
f0b50732 | 2967 | |
0fb59cbc KB |
2968 | free_tags: |
2969 | nvme_dev_remove_admin(dev); | |
1c63dc66 CH |
2970 | blk_put_queue(dev->ctrl.admin_q); |
2971 | dev->ctrl.admin_q = NULL; | |
4af0e21c | 2972 | dev->queues[0]->tags = NULL; |
f0b50732 | 2973 | disable: |
a1a5ef99 | 2974 | nvme_disable_queue(dev, 0); |
b9afca3e | 2975 | nvme_dev_list_remove(dev); |
f0b50732 KB |
2976 | unmap: |
2977 | nvme_dev_unmap(dev); | |
3cf519b5 CH |
2978 | out: |
2979 | if (!work_busy(&dev->reset_work)) | |
2980 | nvme_dead_ctrl(dev); | |
f0b50732 KB |
2981 | } |
2982 | ||
9a6b9458 KB |
2983 | static int nvme_remove_dead_ctrl(void *arg) |
2984 | { | |
2985 | struct nvme_dev *dev = (struct nvme_dev *)arg; | |
e75ec752 | 2986 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 KB |
2987 | |
2988 | if (pci_get_drvdata(pdev)) | |
c81f4975 | 2989 | pci_stop_and_remove_bus_device_locked(pdev); |
9a6b9458 KB |
2990 | kref_put(&dev->kref, nvme_free_dev); |
2991 | return 0; | |
2992 | } | |
2993 | ||
de3eff2b KB |
2994 | static void nvme_dead_ctrl(struct nvme_dev *dev) |
2995 | { | |
2996 | dev_warn(dev->dev, "Device failed to resume\n"); | |
2997 | kref_get(&dev->kref); | |
2998 | if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d", | |
1c63dc66 | 2999 | dev->ctrl.instance))) { |
de3eff2b KB |
3000 | dev_err(dev->dev, |
3001 | "Failed to start controller remove task\n"); | |
3002 | kref_put(&dev->kref, nvme_free_dev); | |
3003 | } | |
3004 | } | |
3005 | ||
77b50d9e | 3006 | static void nvme_reset_work(struct work_struct *ws) |
9a6b9458 | 3007 | { |
77b50d9e | 3008 | struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work); |
ffe7704d KB |
3009 | bool in_probe = work_busy(&dev->probe_work); |
3010 | ||
9a6b9458 | 3011 | nvme_dev_shutdown(dev); |
ffe7704d KB |
3012 | |
3013 | /* Synchronize with device probe so that work will see failure status | |
3014 | * and exit gracefully without trying to schedule another reset */ | |
3015 | flush_work(&dev->probe_work); | |
3016 | ||
3017 | /* Fail this device if reset occured during probe to avoid | |
3018 | * infinite initialization loops. */ | |
3019 | if (in_probe) { | |
de3eff2b | 3020 | nvme_dead_ctrl(dev); |
ffe7704d | 3021 | return; |
9a6b9458 | 3022 | } |
ffe7704d KB |
3023 | /* Schedule device resume asynchronously so the reset work is available |
3024 | * to cleanup errors that may occur during reinitialization */ | |
3025 | schedule_work(&dev->probe_work); | |
9a6b9458 KB |
3026 | } |
3027 | ||
90667892 | 3028 | static int __nvme_reset(struct nvme_dev *dev) |
9ca97374 | 3029 | { |
90667892 CH |
3030 | if (work_pending(&dev->reset_work)) |
3031 | return -EBUSY; | |
3032 | list_del_init(&dev->node); | |
3033 | queue_work(nvme_workq, &dev->reset_work); | |
3034 | return 0; | |
9ca97374 TH |
3035 | } |
3036 | ||
4cc06521 KB |
3037 | static int nvme_reset(struct nvme_dev *dev) |
3038 | { | |
90667892 | 3039 | int ret; |
4cc06521 | 3040 | |
1c63dc66 | 3041 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 KB |
3042 | return -ENODEV; |
3043 | ||
3044 | spin_lock(&dev_list_lock); | |
90667892 | 3045 | ret = __nvme_reset(dev); |
4cc06521 KB |
3046 | spin_unlock(&dev_list_lock); |
3047 | ||
3048 | if (!ret) { | |
3049 | flush_work(&dev->reset_work); | |
ffe7704d | 3050 | flush_work(&dev->probe_work); |
4cc06521 KB |
3051 | return 0; |
3052 | } | |
3053 | ||
3054 | return ret; | |
3055 | } | |
3056 | ||
3057 | static ssize_t nvme_sysfs_reset(struct device *dev, | |
3058 | struct device_attribute *attr, const char *buf, | |
3059 | size_t count) | |
3060 | { | |
3061 | struct nvme_dev *ndev = dev_get_drvdata(dev); | |
3062 | int ret; | |
3063 | ||
3064 | ret = nvme_reset(ndev); | |
3065 | if (ret < 0) | |
3066 | return ret; | |
3067 | ||
3068 | return count; | |
3069 | } | |
3070 | static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset); | |
3071 | ||
1c63dc66 CH |
3072 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
3073 | { | |
3074 | *val = readl(to_nvme_dev(ctrl)->bar + off); | |
3075 | return 0; | |
3076 | } | |
3077 | ||
3078 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { | |
3079 | .reg_read32 = nvme_pci_reg_read32, | |
3080 | }; | |
3081 | ||
8d85fce7 | 3082 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 3083 | { |
a4aea562 | 3084 | int node, result = -ENOMEM; |
b60503ba MW |
3085 | struct nvme_dev *dev; |
3086 | ||
a4aea562 MB |
3087 | node = dev_to_node(&pdev->dev); |
3088 | if (node == NUMA_NO_NODE) | |
3089 | set_dev_node(&pdev->dev, 0); | |
3090 | ||
3091 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
3092 | if (!dev) |
3093 | return -ENOMEM; | |
a4aea562 MB |
3094 | dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), |
3095 | GFP_KERNEL, node); | |
b60503ba MW |
3096 | if (!dev->entry) |
3097 | goto free; | |
a4aea562 MB |
3098 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
3099 | GFP_KERNEL, node); | |
b60503ba MW |
3100 | if (!dev->queues) |
3101 | goto free; | |
3102 | ||
3103 | INIT_LIST_HEAD(&dev->namespaces); | |
77b50d9e | 3104 | INIT_WORK(&dev->reset_work, nvme_reset_work); |
e75ec752 | 3105 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 3106 | pci_set_drvdata(pdev, dev); |
1c63dc66 CH |
3107 | |
3108 | dev->ctrl.ops = &nvme_pci_ctrl_ops; | |
3109 | dev->ctrl.dev = dev->dev; | |
3110 | ||
cd58ad7d QSA |
3111 | result = nvme_set_instance(dev); |
3112 | if (result) | |
a96d4f5c | 3113 | goto put_pci; |
b60503ba | 3114 | |
091b6092 MW |
3115 | result = nvme_setup_prp_pools(dev); |
3116 | if (result) | |
0877cb0d | 3117 | goto release; |
091b6092 | 3118 | |
fb35e914 | 3119 | kref_init(&dev->kref); |
b3fffdef | 3120 | dev->device = device_create(nvme_class, &pdev->dev, |
1c63dc66 CH |
3121 | MKDEV(nvme_char_major, dev->ctrl.instance), |
3122 | dev, "nvme%d", dev->ctrl.instance); | |
b3fffdef KB |
3123 | if (IS_ERR(dev->device)) { |
3124 | result = PTR_ERR(dev->device); | |
2e1d8448 | 3125 | goto release_pools; |
b3fffdef KB |
3126 | } |
3127 | get_device(dev->device); | |
4cc06521 KB |
3128 | dev_set_drvdata(dev->device, dev); |
3129 | ||
3130 | result = device_create_file(dev->device, &dev_attr_reset_controller); | |
3131 | if (result) | |
3132 | goto put_dev; | |
740216fc | 3133 | |
e6e96d73 | 3134 | INIT_LIST_HEAD(&dev->node); |
a5768aa8 | 3135 | INIT_WORK(&dev->scan_work, nvme_dev_scan); |
3cf519b5 | 3136 | INIT_WORK(&dev->probe_work, nvme_probe_work); |
2e1d8448 | 3137 | schedule_work(&dev->probe_work); |
b60503ba MW |
3138 | return 0; |
3139 | ||
4cc06521 | 3140 | put_dev: |
1c63dc66 | 3141 | device_destroy(nvme_class, MKDEV(nvme_char_major, dev->ctrl.instance)); |
4cc06521 | 3142 | put_device(dev->device); |
0877cb0d | 3143 | release_pools: |
091b6092 | 3144 | nvme_release_prp_pools(dev); |
0877cb0d KB |
3145 | release: |
3146 | nvme_release_instance(dev); | |
a96d4f5c | 3147 | put_pci: |
e75ec752 | 3148 | put_device(dev->dev); |
b60503ba MW |
3149 | free: |
3150 | kfree(dev->queues); | |
3151 | kfree(dev->entry); | |
3152 | kfree(dev); | |
3153 | return result; | |
3154 | } | |
3155 | ||
f0d54a54 KB |
3156 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
3157 | { | |
a6739479 | 3158 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 3159 | |
a6739479 KB |
3160 | if (prepare) |
3161 | nvme_dev_shutdown(dev); | |
3162 | else | |
0a7385ad | 3163 | schedule_work(&dev->probe_work); |
f0d54a54 KB |
3164 | } |
3165 | ||
09ece142 KB |
3166 | static void nvme_shutdown(struct pci_dev *pdev) |
3167 | { | |
3168 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
3169 | nvme_dev_shutdown(dev); | |
3170 | } | |
3171 | ||
8d85fce7 | 3172 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
3173 | { |
3174 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 KB |
3175 | |
3176 | spin_lock(&dev_list_lock); | |
3177 | list_del_init(&dev->node); | |
3178 | spin_unlock(&dev_list_lock); | |
3179 | ||
3180 | pci_set_drvdata(pdev, NULL); | |
2e1d8448 | 3181 | flush_work(&dev->probe_work); |
9a6b9458 | 3182 | flush_work(&dev->reset_work); |
a5768aa8 | 3183 | flush_work(&dev->scan_work); |
4cc06521 | 3184 | device_remove_file(dev->device, &dev_attr_reset_controller); |
c9d3bf88 | 3185 | nvme_dev_remove(dev); |
3399a3f7 | 3186 | nvme_dev_shutdown(dev); |
a4aea562 | 3187 | nvme_dev_remove_admin(dev); |
1c63dc66 | 3188 | device_destroy(nvme_class, MKDEV(nvme_char_major, dev->ctrl.instance)); |
a1a5ef99 | 3189 | nvme_free_queues(dev, 0); |
8ffaadf7 | 3190 | nvme_release_cmb(dev); |
9a6b9458 | 3191 | nvme_release_prp_pools(dev); |
5e82e952 | 3192 | kref_put(&dev->kref, nvme_free_dev); |
b60503ba MW |
3193 | } |
3194 | ||
3195 | /* These functions are yet to be implemented */ | |
3196 | #define nvme_error_detected NULL | |
3197 | #define nvme_dump_registers NULL | |
3198 | #define nvme_link_reset NULL | |
3199 | #define nvme_slot_reset NULL | |
3200 | #define nvme_error_resume NULL | |
cd638946 | 3201 | |
671a6018 | 3202 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
3203 | static int nvme_suspend(struct device *dev) |
3204 | { | |
3205 | struct pci_dev *pdev = to_pci_dev(dev); | |
3206 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
3207 | ||
3208 | nvme_dev_shutdown(ndev); | |
3209 | return 0; | |
3210 | } | |
3211 | ||
3212 | static int nvme_resume(struct device *dev) | |
3213 | { | |
3214 | struct pci_dev *pdev = to_pci_dev(dev); | |
3215 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 3216 | |
0a7385ad | 3217 | schedule_work(&ndev->probe_work); |
9a6b9458 | 3218 | return 0; |
cd638946 | 3219 | } |
671a6018 | 3220 | #endif |
cd638946 KB |
3221 | |
3222 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 3223 | |
1d352035 | 3224 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba MW |
3225 | .error_detected = nvme_error_detected, |
3226 | .mmio_enabled = nvme_dump_registers, | |
3227 | .link_reset = nvme_link_reset, | |
3228 | .slot_reset = nvme_slot_reset, | |
3229 | .resume = nvme_error_resume, | |
f0d54a54 | 3230 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
3231 | }; |
3232 | ||
3233 | /* Move to pci_ids.h later */ | |
3234 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
3235 | ||
6eb0d698 | 3236 | static const struct pci_device_id nvme_id_table[] = { |
b60503ba | 3237 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 3238 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
b60503ba MW |
3239 | { 0, } |
3240 | }; | |
3241 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
3242 | ||
3243 | static struct pci_driver nvme_driver = { | |
3244 | .name = "nvme", | |
3245 | .id_table = nvme_id_table, | |
3246 | .probe = nvme_probe, | |
8d85fce7 | 3247 | .remove = nvme_remove, |
09ece142 | 3248 | .shutdown = nvme_shutdown, |
cd638946 KB |
3249 | .driver = { |
3250 | .pm = &nvme_dev_pm_ops, | |
3251 | }, | |
b60503ba MW |
3252 | .err_handler = &nvme_err_handler, |
3253 | }; | |
3254 | ||
3255 | static int __init nvme_init(void) | |
3256 | { | |
0ac13140 | 3257 | int result; |
1fa6aead | 3258 | |
b9afca3e | 3259 | init_waitqueue_head(&nvme_kthread_wait); |
b60503ba | 3260 | |
9a6b9458 KB |
3261 | nvme_workq = create_singlethread_workqueue("nvme"); |
3262 | if (!nvme_workq) | |
b9afca3e | 3263 | return -ENOMEM; |
9a6b9458 | 3264 | |
5c42ea16 KB |
3265 | result = register_blkdev(nvme_major, "nvme"); |
3266 | if (result < 0) | |
9a6b9458 | 3267 | goto kill_workq; |
5c42ea16 | 3268 | else if (result > 0) |
0ac13140 | 3269 | nvme_major = result; |
b60503ba | 3270 | |
b3fffdef KB |
3271 | result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme", |
3272 | &nvme_dev_fops); | |
3273 | if (result < 0) | |
3274 | goto unregister_blkdev; | |
3275 | else if (result > 0) | |
3276 | nvme_char_major = result; | |
3277 | ||
3278 | nvme_class = class_create(THIS_MODULE, "nvme"); | |
c727040b AK |
3279 | if (IS_ERR(nvme_class)) { |
3280 | result = PTR_ERR(nvme_class); | |
b3fffdef | 3281 | goto unregister_chrdev; |
c727040b | 3282 | } |
b3fffdef | 3283 | |
f3db22fe KB |
3284 | result = pci_register_driver(&nvme_driver); |
3285 | if (result) | |
b3fffdef | 3286 | goto destroy_class; |
1fa6aead | 3287 | return 0; |
b60503ba | 3288 | |
b3fffdef KB |
3289 | destroy_class: |
3290 | class_destroy(nvme_class); | |
3291 | unregister_chrdev: | |
3292 | __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme"); | |
1fa6aead | 3293 | unregister_blkdev: |
b60503ba | 3294 | unregister_blkdev(nvme_major, "nvme"); |
9a6b9458 KB |
3295 | kill_workq: |
3296 | destroy_workqueue(nvme_workq); | |
b60503ba MW |
3297 | return result; |
3298 | } | |
3299 | ||
3300 | static void __exit nvme_exit(void) | |
3301 | { | |
3302 | pci_unregister_driver(&nvme_driver); | |
3303 | unregister_blkdev(nvme_major, "nvme"); | |
9a6b9458 | 3304 | destroy_workqueue(nvme_workq); |
b3fffdef KB |
3305 | class_destroy(nvme_class); |
3306 | __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme"); | |
b9afca3e | 3307 | BUG_ON(nvme_thread && !IS_ERR(nvme_thread)); |
21bd78bc | 3308 | _nvme_check_size(); |
b60503ba MW |
3309 | } |
3310 | ||
3311 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
3312 | MODULE_LICENSE("GPL"); | |
c78b4713 | 3313 | MODULE_VERSION("1.0"); |
b60503ba MW |
3314 | module_init(nvme_init); |
3315 | module_exit(nvme_exit); |