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Commit | Line | Data |
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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
a0a3408e | 15 | #include <linux/aer.h> |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
dca51e78 | 19 | #include <linux/blk-mq-pci.h> |
42f61420 | 20 | #include <linux/cpu.h> |
fd63e9ce | 21 | #include <linux/delay.h> |
b60503ba MW |
22 | #include <linux/errno.h> |
23 | #include <linux/fs.h> | |
24 | #include <linux/genhd.h> | |
4cc09e2d | 25 | #include <linux/hdreg.h> |
5aff9382 | 26 | #include <linux/idr.h> |
b60503ba MW |
27 | #include <linux/init.h> |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/io.h> | |
30 | #include <linux/kdev_t.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/mm.h> | |
33 | #include <linux/module.h> | |
34 | #include <linux/moduleparam.h> | |
77bf25ea | 35 | #include <linux/mutex.h> |
b60503ba | 36 | #include <linux/pci.h> |
be7b6275 | 37 | #include <linux/poison.h> |
c3bfe717 | 38 | #include <linux/ptrace.h> |
b60503ba MW |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
e1e5e564 | 41 | #include <linux/t10-pi.h> |
2d55cd5f | 42 | #include <linux/timer.h> |
b60503ba | 43 | #include <linux/types.h> |
2f8e2c87 | 44 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 45 | #include <asm/unaligned.h> |
797a796a | 46 | |
f11bb3e2 CH |
47 | #include "nvme.h" |
48 | ||
9d43cf64 | 49 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 50 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
51 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
52 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
c965809c | 53 | |
12e6f749 RN |
54 | /* Google Vendor ID is not in include/linux/pci_ids.h */ |
55 | #define PCI_VENDOR_ID_GOOGLE 0x1AE0 | |
56 | ||
adf68f21 CH |
57 | /* |
58 | * We handle AEN commands ourselves and don't even let the | |
59 | * block layer know about them. | |
60 | */ | |
f866fc42 | 61 | #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS) |
9d43cf64 | 62 | |
58ffacb5 MW |
63 | static int use_threaded_interrupts; |
64 | module_param(use_threaded_interrupts, int, 0); | |
65 | ||
8ffaadf7 JD |
66 | static bool use_cmb_sqes = true; |
67 | module_param(use_cmb_sqes, bool, 0644); | |
68 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
69 | ||
9a6b9458 | 70 | static struct workqueue_struct *nvme_workq; |
1fa6aead | 71 | |
1c63dc66 CH |
72 | struct nvme_dev; |
73 | struct nvme_queue; | |
b3fffdef | 74 | |
4cc06521 | 75 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 76 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
a5cdb68c | 77 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
d4b4ff8e | 78 | |
1c63dc66 CH |
79 | /* |
80 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
81 | */ | |
82 | struct nvme_dev { | |
1c63dc66 CH |
83 | struct nvme_queue **queues; |
84 | struct blk_mq_tag_set tagset; | |
85 | struct blk_mq_tag_set admin_tagset; | |
86 | u32 __iomem *dbs; | |
87 | struct device *dev; | |
88 | struct dma_pool *prp_page_pool; | |
89 | struct dma_pool *prp_small_pool; | |
90 | unsigned queue_count; | |
91 | unsigned online_queues; | |
92 | unsigned max_qid; | |
93 | int q_depth; | |
94 | u32 db_stride; | |
1c63dc66 | 95 | void __iomem *bar; |
1c63dc66 | 96 | struct work_struct reset_work; |
5c8809e6 | 97 | struct work_struct remove_work; |
2d55cd5f | 98 | struct timer_list watchdog_timer; |
77bf25ea | 99 | struct mutex shutdown_lock; |
1c63dc66 | 100 | bool subsystem; |
1c63dc66 CH |
101 | void __iomem *cmb; |
102 | dma_addr_t cmb_dma_addr; | |
103 | u64 cmb_size; | |
104 | u32 cmbsz; | |
202021c1 | 105 | u32 cmbloc; |
1c63dc66 | 106 | struct nvme_ctrl ctrl; |
db3cbfff | 107 | struct completion ioq_wait; |
12e6f749 RN |
108 | #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE |
109 | u32 *db_mem; | |
110 | dma_addr_t doorbell; | |
111 | u32 *ei_mem; | |
112 | dma_addr_t eventidx; | |
113 | #endif | |
4d115420 | 114 | }; |
1fa6aead | 115 | |
1c63dc66 CH |
116 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
117 | { | |
118 | return container_of(ctrl, struct nvme_dev, ctrl); | |
119 | } | |
120 | ||
b60503ba MW |
121 | /* |
122 | * An NVM Express queue. Each device has at least two (one for admin | |
123 | * commands and one for I/O commands). | |
124 | */ | |
125 | struct nvme_queue { | |
126 | struct device *q_dmadev; | |
091b6092 | 127 | struct nvme_dev *dev; |
3193f07b | 128 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
129 | spinlock_t q_lock; |
130 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 131 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 132 | volatile struct nvme_completion *cqes; |
42483228 | 133 | struct blk_mq_tags **tags; |
b60503ba MW |
134 | dma_addr_t sq_dma_addr; |
135 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
136 | u32 __iomem *q_db; |
137 | u16 q_depth; | |
6222d172 | 138 | s16 cq_vector; |
b60503ba MW |
139 | u16 sq_tail; |
140 | u16 cq_head; | |
c30341dc | 141 | u16 qid; |
e9539f47 MW |
142 | u8 cq_phase; |
143 | u8 cqe_seen; | |
12e6f749 RN |
144 | #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE |
145 | u32 *sq_doorbell_addr; | |
146 | u32 *sq_eventidx_addr; | |
147 | u32 *cq_doorbell_addr; | |
148 | u32 *cq_eventidx_addr; | |
149 | #endif | |
b60503ba MW |
150 | }; |
151 | ||
71bd150c CH |
152 | /* |
153 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
154 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 155 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
156 | * allocated to store the PRP list. |
157 | */ | |
158 | struct nvme_iod { | |
d49187e9 | 159 | struct nvme_request req; |
f4800d6d CH |
160 | struct nvme_queue *nvmeq; |
161 | int aborted; | |
71bd150c | 162 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
163 | int nents; /* Used in scatterlist */ |
164 | int length; /* Of data, in bytes */ | |
165 | dma_addr_t first_dma; | |
bf684057 | 166 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
167 | struct scatterlist *sg; |
168 | struct scatterlist inline_sg[0]; | |
b60503ba MW |
169 | }; |
170 | ||
171 | /* | |
172 | * Check we didin't inadvertently grow the command struct | |
173 | */ | |
174 | static inline void _nvme_check_size(void) | |
175 | { | |
176 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
177 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
178 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
179 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
180 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 181 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 182 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
183 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
184 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
185 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
186 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 187 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
12e6f749 RN |
188 | #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE |
189 | BUILD_BUG_ON(sizeof(struct nvme_doorbell_memory) != 64); | |
190 | #endif | |
b60503ba MW |
191 | } |
192 | ||
ac3dd5bd JA |
193 | /* |
194 | * Max size of iod being embedded in the request payload | |
195 | */ | |
196 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 197 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
198 | |
199 | /* | |
200 | * Will slightly overestimate the number of pages needed. This is OK | |
201 | * as it only leads to a small amount of wasted memory for the lifetime of | |
202 | * the I/O. | |
203 | */ | |
204 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
205 | { | |
5fd4ce1b CH |
206 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
207 | dev->ctrl.page_size); | |
ac3dd5bd JA |
208 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
209 | } | |
210 | ||
f4800d6d CH |
211 | static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, |
212 | unsigned int size, unsigned int nseg) | |
ac3dd5bd | 213 | { |
f4800d6d CH |
214 | return sizeof(__le64 *) * nvme_npages(size, dev) + |
215 | sizeof(struct scatterlist) * nseg; | |
216 | } | |
ac3dd5bd | 217 | |
f4800d6d CH |
218 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) |
219 | { | |
220 | return sizeof(struct nvme_iod) + | |
221 | nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); | |
ac3dd5bd JA |
222 | } |
223 | ||
dca51e78 CH |
224 | static int nvmeq_irq(struct nvme_queue *nvmeq) |
225 | { | |
226 | return pci_irq_vector(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector); | |
227 | } | |
228 | ||
a4aea562 MB |
229 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
230 | unsigned int hctx_idx) | |
e85248e5 | 231 | { |
a4aea562 MB |
232 | struct nvme_dev *dev = data; |
233 | struct nvme_queue *nvmeq = dev->queues[0]; | |
234 | ||
42483228 KB |
235 | WARN_ON(hctx_idx != 0); |
236 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
237 | WARN_ON(nvmeq->tags); | |
238 | ||
a4aea562 | 239 | hctx->driver_data = nvmeq; |
42483228 | 240 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 241 | return 0; |
e85248e5 MW |
242 | } |
243 | ||
4af0e21c KB |
244 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
245 | { | |
246 | struct nvme_queue *nvmeq = hctx->driver_data; | |
247 | ||
248 | nvmeq->tags = NULL; | |
249 | } | |
250 | ||
a4aea562 MB |
251 | static int nvme_admin_init_request(void *data, struct request *req, |
252 | unsigned int hctx_idx, unsigned int rq_idx, | |
253 | unsigned int numa_node) | |
22404274 | 254 | { |
a4aea562 | 255 | struct nvme_dev *dev = data; |
f4800d6d | 256 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
257 | struct nvme_queue *nvmeq = dev->queues[0]; |
258 | ||
259 | BUG_ON(!nvmeq); | |
f4800d6d | 260 | iod->nvmeq = nvmeq; |
a4aea562 | 261 | return 0; |
22404274 KB |
262 | } |
263 | ||
a4aea562 MB |
264 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
265 | unsigned int hctx_idx) | |
b60503ba | 266 | { |
a4aea562 | 267 | struct nvme_dev *dev = data; |
42483228 | 268 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 269 | |
42483228 KB |
270 | if (!nvmeq->tags) |
271 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 272 | |
42483228 | 273 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
274 | hctx->driver_data = nvmeq; |
275 | return 0; | |
b60503ba MW |
276 | } |
277 | ||
a4aea562 MB |
278 | static int nvme_init_request(void *data, struct request *req, |
279 | unsigned int hctx_idx, unsigned int rq_idx, | |
280 | unsigned int numa_node) | |
b60503ba | 281 | { |
a4aea562 | 282 | struct nvme_dev *dev = data; |
f4800d6d | 283 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
284 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
285 | ||
286 | BUG_ON(!nvmeq); | |
f4800d6d | 287 | iod->nvmeq = nvmeq; |
a4aea562 MB |
288 | return 0; |
289 | } | |
290 | ||
dca51e78 CH |
291 | static int nvme_pci_map_queues(struct blk_mq_tag_set *set) |
292 | { | |
293 | struct nvme_dev *dev = set->driver_data; | |
294 | ||
295 | return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev)); | |
296 | } | |
297 | ||
12e6f749 RN |
298 | #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE |
299 | static int nvme_vendor_memory_size(struct nvme_dev *dev) | |
300 | { | |
301 | return ((num_possible_cpus() + 1) * 8 * dev->db_stride); | |
302 | } | |
303 | ||
304 | static int nvme_set_doorbell_memory(struct nvme_dev *dev) | |
305 | { | |
306 | struct nvme_command c; | |
307 | ||
308 | memset(&c, 0, sizeof(c)); | |
309 | c.doorbell_memory.opcode = nvme_admin_doorbell_memory; | |
310 | c.doorbell_memory.prp1 = cpu_to_le64(dev->doorbell); | |
311 | c.doorbell_memory.prp2 = cpu_to_le64(dev->eventidx); | |
312 | ||
313 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); | |
314 | } | |
315 | ||
316 | static inline int nvme_ext_need_event(u16 event_idx, u16 new_idx, u16 old) | |
317 | { | |
318 | /* Borrowed from vring_need_event */ | |
319 | return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); | |
320 | } | |
321 | ||
322 | static void nvme_ext_write_doorbell(u16 value, u32 __iomem* q_db, | |
323 | u32* db_addr, volatile u32* event_idx) | |
324 | { | |
325 | u16 old_value; | |
326 | if (!db_addr) | |
327 | goto ring_doorbell; | |
328 | ||
329 | old_value = *db_addr; | |
330 | *db_addr = value; | |
331 | ||
332 | rmb(); | |
333 | if (!nvme_ext_need_event(*event_idx, value, old_value)) | |
334 | goto no_doorbell; | |
335 | ||
336 | ring_doorbell: | |
337 | writel(value, q_db); | |
338 | no_doorbell: | |
339 | return; | |
340 | } | |
341 | #endif | |
342 | ||
b60503ba | 343 | /** |
adf68f21 | 344 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
345 | * @nvmeq: The queue to use |
346 | * @cmd: The command to send | |
347 | * | |
348 | * Safe to use from interrupt context | |
349 | */ | |
e3f879bf SB |
350 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
351 | struct nvme_command *cmd) | |
b60503ba | 352 | { |
a4aea562 MB |
353 | u16 tail = nvmeq->sq_tail; |
354 | ||
8ffaadf7 JD |
355 | if (nvmeq->sq_cmds_io) |
356 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
357 | else | |
358 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
359 | ||
12e6f749 RN |
360 | #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE |
361 | if (nvmeq->sq_doorbell_addr) | |
362 | wmb(); | |
363 | #endif | |
364 | ||
b60503ba MW |
365 | if (++tail == nvmeq->q_depth) |
366 | tail = 0; | |
12e6f749 RN |
367 | #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE |
368 | nvme_ext_write_doorbell(tail, nvmeq->q_db, | |
369 | nvmeq->sq_doorbell_addr, nvmeq->sq_eventidx_addr); | |
370 | #else | |
7547881d | 371 | writel(tail, nvmeq->q_db); |
12e6f749 | 372 | #endif |
b60503ba | 373 | nvmeq->sq_tail = tail; |
b60503ba MW |
374 | } |
375 | ||
f4800d6d | 376 | static __le64 **iod_list(struct request *req) |
b60503ba | 377 | { |
f4800d6d | 378 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
f9d03f96 | 379 | return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req)); |
b60503ba MW |
380 | } |
381 | ||
b131c61d | 382 | static int nvme_init_iod(struct request *rq, struct nvme_dev *dev) |
ac3dd5bd | 383 | { |
f4800d6d | 384 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
f9d03f96 | 385 | int nseg = blk_rq_nr_phys_segments(rq); |
b131c61d | 386 | unsigned int size = blk_rq_payload_bytes(rq); |
ac3dd5bd | 387 | |
f4800d6d CH |
388 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
389 | iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); | |
390 | if (!iod->sg) | |
391 | return BLK_MQ_RQ_QUEUE_BUSY; | |
392 | } else { | |
393 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
394 | } |
395 | ||
f4800d6d CH |
396 | iod->aborted = 0; |
397 | iod->npages = -1; | |
398 | iod->nents = 0; | |
399 | iod->length = size; | |
f80ec966 | 400 | |
e8064021 | 401 | if (!(rq->rq_flags & RQF_DONTPREP)) { |
f80ec966 | 402 | rq->retries = 0; |
e8064021 | 403 | rq->rq_flags |= RQF_DONTPREP; |
f80ec966 | 404 | } |
bac0000a | 405 | return BLK_MQ_RQ_QUEUE_OK; |
ac3dd5bd JA |
406 | } |
407 | ||
f4800d6d | 408 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 409 | { |
f4800d6d | 410 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
5fd4ce1b | 411 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 | 412 | int i; |
f4800d6d | 413 | __le64 **list = iod_list(req); |
eca18b23 MW |
414 | dma_addr_t prp_dma = iod->first_dma; |
415 | ||
416 | if (iod->npages == 0) | |
417 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
418 | for (i = 0; i < iod->npages; i++) { | |
419 | __le64 *prp_list = list[i]; | |
420 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
421 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
422 | prp_dma = next_prp_dma; | |
423 | } | |
ac3dd5bd | 424 | |
f4800d6d CH |
425 | if (iod->sg != iod->inline_sg) |
426 | kfree(iod->sg); | |
b4ff9c8d KB |
427 | } |
428 | ||
52b68d7e | 429 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
430 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
431 | { | |
432 | if (be32_to_cpu(pi->ref_tag) == v) | |
433 | pi->ref_tag = cpu_to_be32(p); | |
434 | } | |
435 | ||
436 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
437 | { | |
438 | if (be32_to_cpu(pi->ref_tag) == p) | |
439 | pi->ref_tag = cpu_to_be32(v); | |
440 | } | |
441 | ||
442 | /** | |
443 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
444 | * | |
445 | * The virtual start sector is the one that was originally submitted by the | |
446 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
447 | * start sector may be different. Remap protection information to match the | |
448 | * physical LBA on writes, and back to the original seed on reads. | |
449 | * | |
450 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
451 | */ | |
452 | static void nvme_dif_remap(struct request *req, | |
453 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
454 | { | |
455 | struct nvme_ns *ns = req->rq_disk->private_data; | |
456 | struct bio_integrity_payload *bip; | |
457 | struct t10_pi_tuple *pi; | |
458 | void *p, *pmap; | |
459 | u32 i, nlb, ts, phys, virt; | |
460 | ||
461 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
462 | return; | |
463 | ||
464 | bip = bio_integrity(req->bio); | |
465 | if (!bip) | |
466 | return; | |
467 | ||
468 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
469 | |
470 | p = pmap; | |
471 | virt = bip_get_seed(bip); | |
472 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
473 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 474 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
475 | |
476 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
477 | pi = (struct t10_pi_tuple *)p; | |
478 | dif_swap(phys, virt, pi); | |
479 | p += ts; | |
480 | } | |
481 | kunmap_atomic(pmap); | |
482 | } | |
52b68d7e KB |
483 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
484 | static void nvme_dif_remap(struct request *req, | |
485 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
486 | { | |
487 | } | |
488 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
489 | { | |
490 | } | |
491 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
492 | { | |
493 | } | |
52b68d7e KB |
494 | #endif |
495 | ||
b131c61d | 496 | static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req) |
ff22b54f | 497 | { |
f4800d6d | 498 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 499 | struct dma_pool *pool; |
b131c61d | 500 | int length = blk_rq_payload_bytes(req); |
eca18b23 | 501 | struct scatterlist *sg = iod->sg; |
ff22b54f MW |
502 | int dma_len = sg_dma_len(sg); |
503 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 504 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 505 | int offset = dma_addr & (page_size - 1); |
e025344c | 506 | __le64 *prp_list; |
f4800d6d | 507 | __le64 **list = iod_list(req); |
e025344c | 508 | dma_addr_t prp_dma; |
eca18b23 | 509 | int nprps, i; |
ff22b54f | 510 | |
1d090624 | 511 | length -= (page_size - offset); |
ff22b54f | 512 | if (length <= 0) |
69d2b571 | 513 | return true; |
ff22b54f | 514 | |
1d090624 | 515 | dma_len -= (page_size - offset); |
ff22b54f | 516 | if (dma_len) { |
1d090624 | 517 | dma_addr += (page_size - offset); |
ff22b54f MW |
518 | } else { |
519 | sg = sg_next(sg); | |
520 | dma_addr = sg_dma_address(sg); | |
521 | dma_len = sg_dma_len(sg); | |
522 | } | |
523 | ||
1d090624 | 524 | if (length <= page_size) { |
edd10d33 | 525 | iod->first_dma = dma_addr; |
69d2b571 | 526 | return true; |
e025344c SMM |
527 | } |
528 | ||
1d090624 | 529 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
530 | if (nprps <= (256 / 8)) { |
531 | pool = dev->prp_small_pool; | |
eca18b23 | 532 | iod->npages = 0; |
99802a7a MW |
533 | } else { |
534 | pool = dev->prp_page_pool; | |
eca18b23 | 535 | iod->npages = 1; |
99802a7a MW |
536 | } |
537 | ||
69d2b571 | 538 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 539 | if (!prp_list) { |
edd10d33 | 540 | iod->first_dma = dma_addr; |
eca18b23 | 541 | iod->npages = -1; |
69d2b571 | 542 | return false; |
b77954cb | 543 | } |
eca18b23 MW |
544 | list[0] = prp_list; |
545 | iod->first_dma = prp_dma; | |
e025344c SMM |
546 | i = 0; |
547 | for (;;) { | |
1d090624 | 548 | if (i == page_size >> 3) { |
e025344c | 549 | __le64 *old_prp_list = prp_list; |
69d2b571 | 550 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 551 | if (!prp_list) |
69d2b571 | 552 | return false; |
eca18b23 | 553 | list[iod->npages++] = prp_list; |
7523d834 MW |
554 | prp_list[0] = old_prp_list[i - 1]; |
555 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
556 | i = 1; | |
e025344c SMM |
557 | } |
558 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
559 | dma_len -= page_size; |
560 | dma_addr += page_size; | |
561 | length -= page_size; | |
e025344c SMM |
562 | if (length <= 0) |
563 | break; | |
564 | if (dma_len > 0) | |
565 | continue; | |
566 | BUG_ON(dma_len < 0); | |
567 | sg = sg_next(sg); | |
568 | dma_addr = sg_dma_address(sg); | |
569 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
570 | } |
571 | ||
69d2b571 | 572 | return true; |
ff22b54f MW |
573 | } |
574 | ||
f4800d6d | 575 | static int nvme_map_data(struct nvme_dev *dev, struct request *req, |
b131c61d | 576 | struct nvme_command *cmnd) |
d29ec824 | 577 | { |
f4800d6d | 578 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
579 | struct request_queue *q = req->q; |
580 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
581 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
582 | int ret = BLK_MQ_RQ_QUEUE_ERROR; | |
d29ec824 | 583 | |
f9d03f96 | 584 | sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); |
ba1ca37e CH |
585 | iod->nents = blk_rq_map_sg(q, req, iod->sg); |
586 | if (!iod->nents) | |
587 | goto out; | |
d29ec824 | 588 | |
ba1ca37e | 589 | ret = BLK_MQ_RQ_QUEUE_BUSY; |
2b6b535d MFO |
590 | if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, |
591 | DMA_ATTR_NO_WARN)) | |
ba1ca37e | 592 | goto out; |
d29ec824 | 593 | |
b131c61d | 594 | if (!nvme_setup_prps(dev, req)) |
ba1ca37e | 595 | goto out_unmap; |
0e5e4f0e | 596 | |
ba1ca37e CH |
597 | ret = BLK_MQ_RQ_QUEUE_ERROR; |
598 | if (blk_integrity_rq(req)) { | |
599 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
600 | goto out_unmap; | |
0e5e4f0e | 601 | |
bf684057 CH |
602 | sg_init_table(&iod->meta_sg, 1); |
603 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 604 | goto out_unmap; |
0e5e4f0e | 605 | |
ba1ca37e CH |
606 | if (rq_data_dir(req)) |
607 | nvme_dif_remap(req, nvme_dif_prep); | |
0e5e4f0e | 608 | |
bf684057 | 609 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 610 | goto out_unmap; |
d29ec824 | 611 | } |
00df5cb4 | 612 | |
eb793e2c CH |
613 | cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
614 | cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma); | |
ba1ca37e | 615 | if (blk_integrity_rq(req)) |
bf684057 | 616 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
ba1ca37e | 617 | return BLK_MQ_RQ_QUEUE_OK; |
00df5cb4 | 618 | |
ba1ca37e CH |
619 | out_unmap: |
620 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
621 | out: | |
622 | return ret; | |
00df5cb4 MW |
623 | } |
624 | ||
f4800d6d | 625 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
b60503ba | 626 | { |
f4800d6d | 627 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
628 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
629 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
630 | ||
631 | if (iod->nents) { | |
632 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
633 | if (blk_integrity_rq(req)) { | |
634 | if (!rq_data_dir(req)) | |
635 | nvme_dif_remap(req, nvme_dif_complete); | |
bf684057 | 636 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
e1e5e564 | 637 | } |
e19b127f | 638 | } |
e1e5e564 | 639 | |
f9d03f96 | 640 | nvme_cleanup_cmd(req); |
f4800d6d | 641 | nvme_free_iod(dev, req); |
d4f6c3ab | 642 | } |
b60503ba | 643 | |
d29ec824 CH |
644 | /* |
645 | * NOTE: ns is NULL when called on the admin queue. | |
646 | */ | |
a4aea562 MB |
647 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
648 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 649 | { |
a4aea562 MB |
650 | struct nvme_ns *ns = hctx->queue->queuedata; |
651 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 652 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 653 | struct request *req = bd->rq; |
ba1ca37e CH |
654 | struct nvme_command cmnd; |
655 | int ret = BLK_MQ_RQ_QUEUE_OK; | |
edd10d33 | 656 | |
e1e5e564 KB |
657 | /* |
658 | * If formated with metadata, require the block layer provide a buffer | |
659 | * unless this namespace is formated such that the metadata can be | |
660 | * stripped/generated by the controller with PRACT=1. | |
661 | */ | |
d29ec824 | 662 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 KB |
663 | if (!(ns->pi_type && ns->ms == 8) && |
664 | req->cmd_type != REQ_TYPE_DRV_PRIV) { | |
eee417b0 | 665 | blk_mq_end_request(req, -EFAULT); |
e1e5e564 KB |
666 | return BLK_MQ_RQ_QUEUE_OK; |
667 | } | |
668 | } | |
669 | ||
f9d03f96 | 670 | ret = nvme_setup_cmd(ns, req, &cmnd); |
bac0000a | 671 | if (ret != BLK_MQ_RQ_QUEUE_OK) |
f4800d6d | 672 | return ret; |
a4aea562 | 673 | |
b131c61d | 674 | ret = nvme_init_iod(req, dev); |
bac0000a | 675 | if (ret != BLK_MQ_RQ_QUEUE_OK) |
f9d03f96 | 676 | goto out_free_cmd; |
a4aea562 | 677 | |
f9d03f96 | 678 | if (blk_rq_nr_phys_segments(req)) |
b131c61d | 679 | ret = nvme_map_data(dev, req, &cmnd); |
a4aea562 | 680 | |
bac0000a | 681 | if (ret != BLK_MQ_RQ_QUEUE_OK) |
f9d03f96 | 682 | goto out_cleanup_iod; |
a4aea562 | 683 | |
aae239e1 | 684 | blk_mq_start_request(req); |
a4aea562 | 685 | |
ba1ca37e | 686 | spin_lock_irq(&nvmeq->q_lock); |
ae1fba20 | 687 | if (unlikely(nvmeq->cq_vector < 0)) { |
69d9a99c KB |
688 | if (ns && !test_bit(NVME_NS_DEAD, &ns->flags)) |
689 | ret = BLK_MQ_RQ_QUEUE_BUSY; | |
690 | else | |
691 | ret = BLK_MQ_RQ_QUEUE_ERROR; | |
ae1fba20 | 692 | spin_unlock_irq(&nvmeq->q_lock); |
f9d03f96 | 693 | goto out_cleanup_iod; |
ae1fba20 | 694 | } |
ba1ca37e | 695 | __nvme_submit_cmd(nvmeq, &cmnd); |
a4aea562 MB |
696 | nvme_process_cq(nvmeq); |
697 | spin_unlock_irq(&nvmeq->q_lock); | |
698 | return BLK_MQ_RQ_QUEUE_OK; | |
f9d03f96 | 699 | out_cleanup_iod: |
f4800d6d | 700 | nvme_free_iod(dev, req); |
f9d03f96 CH |
701 | out_free_cmd: |
702 | nvme_cleanup_cmd(req); | |
ba1ca37e | 703 | return ret; |
b60503ba | 704 | } |
e1e5e564 | 705 | |
eee417b0 CH |
706 | static void nvme_complete_rq(struct request *req) |
707 | { | |
f4800d6d CH |
708 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
709 | struct nvme_dev *dev = iod->nvmeq->dev; | |
eee417b0 | 710 | int error = 0; |
e1e5e564 | 711 | |
f4800d6d | 712 | nvme_unmap_data(dev, req); |
e1e5e564 | 713 | |
eee417b0 CH |
714 | if (unlikely(req->errors)) { |
715 | if (nvme_req_needs_retry(req, req->errors)) { | |
f80ec966 | 716 | req->retries++; |
eee417b0 CH |
717 | nvme_requeue_req(req); |
718 | return; | |
e1e5e564 | 719 | } |
1974b1ae | 720 | |
eee417b0 CH |
721 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) |
722 | error = req->errors; | |
723 | else | |
724 | error = nvme_error_status(req->errors); | |
725 | } | |
a4aea562 | 726 | |
f4800d6d | 727 | if (unlikely(iod->aborted)) { |
1b3c47c1 | 728 | dev_warn(dev->ctrl.device, |
eee417b0 CH |
729 | "completing aborted command with status: %04x\n", |
730 | req->errors); | |
731 | } | |
a4aea562 | 732 | |
eee417b0 | 733 | blk_mq_end_request(req, error); |
b60503ba MW |
734 | } |
735 | ||
d783e0bd MR |
736 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
737 | static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, | |
738 | u16 phase) | |
739 | { | |
740 | return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; | |
741 | } | |
742 | ||
a0fa9647 | 743 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 744 | { |
82123460 | 745 | u16 head, phase; |
b60503ba | 746 | |
b60503ba | 747 | head = nvmeq->cq_head; |
82123460 | 748 | phase = nvmeq->cq_phase; |
b60503ba | 749 | |
d783e0bd | 750 | while (nvme_cqe_valid(nvmeq, head, phase)) { |
b60503ba | 751 | struct nvme_completion cqe = nvmeq->cqes[head]; |
eee417b0 | 752 | struct request *req; |
adf68f21 | 753 | |
12e6f749 RN |
754 | #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE |
755 | if (to_pci_dev(nvmeq->dev->dev)->vendor == PCI_VENDOR_ID_GOOGLE) | |
756 | rmb(); | |
757 | #endif | |
b60503ba MW |
758 | if (++head == nvmeq->q_depth) { |
759 | head = 0; | |
82123460 | 760 | phase = !phase; |
b60503ba | 761 | } |
adf68f21 | 762 | |
a0fa9647 JA |
763 | if (tag && *tag == cqe.command_id) |
764 | *tag = -1; | |
adf68f21 | 765 | |
aae239e1 | 766 | if (unlikely(cqe.command_id >= nvmeq->q_depth)) { |
1b3c47c1 | 767 | dev_warn(nvmeq->dev->ctrl.device, |
aae239e1 CH |
768 | "invalid id %d completed on queue %d\n", |
769 | cqe.command_id, le16_to_cpu(cqe.sq_id)); | |
770 | continue; | |
771 | } | |
772 | ||
adf68f21 CH |
773 | /* |
774 | * AEN requests are special as they don't time out and can | |
775 | * survive any kind of queue freeze and often don't respond to | |
776 | * aborts. We don't even bother to allocate a struct request | |
777 | * for them but rather special case them here. | |
778 | */ | |
779 | if (unlikely(nvmeq->qid == 0 && | |
780 | cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { | |
7bf58533 CH |
781 | nvme_complete_async_event(&nvmeq->dev->ctrl, |
782 | cqe.status, &cqe.result); | |
adf68f21 CH |
783 | continue; |
784 | } | |
785 | ||
eee417b0 | 786 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); |
d49187e9 | 787 | nvme_req(req)->result = cqe.result; |
d783e0bd | 788 | blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1); |
b60503ba MW |
789 | } |
790 | ||
82123460 | 791 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 792 | return; |
b60503ba | 793 | |
604e8c8d | 794 | if (likely(nvmeq->cq_vector >= 0)) |
12e6f749 RN |
795 | #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE |
796 | nvme_ext_write_doorbell(head, | |
797 | nvmeq->q_db + nvmeq->dev->db_stride, | |
798 | nvmeq->cq_doorbell_addr, | |
799 | nvmeq->cq_eventidx_addr); | |
800 | #else | |
604e8c8d | 801 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); |
12e6f749 | 802 | #endif |
b60503ba | 803 | nvmeq->cq_head = head; |
82123460 | 804 | nvmeq->cq_phase = phase; |
b60503ba | 805 | |
e9539f47 | 806 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
807 | } |
808 | ||
809 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
810 | { | |
811 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
812 | } |
813 | ||
814 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
815 | { |
816 | irqreturn_t result; | |
817 | struct nvme_queue *nvmeq = data; | |
818 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
819 | nvme_process_cq(nvmeq); |
820 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
821 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
822 | spin_unlock(&nvmeq->q_lock); |
823 | return result; | |
824 | } | |
825 | ||
826 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
827 | { | |
828 | struct nvme_queue *nvmeq = data; | |
d783e0bd MR |
829 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) |
830 | return IRQ_WAKE_THREAD; | |
831 | return IRQ_NONE; | |
58ffacb5 MW |
832 | } |
833 | ||
a0fa9647 JA |
834 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
835 | { | |
836 | struct nvme_queue *nvmeq = hctx->driver_data; | |
837 | ||
d783e0bd | 838 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { |
a0fa9647 JA |
839 | spin_lock_irq(&nvmeq->q_lock); |
840 | __nvme_process_cq(nvmeq, &tag); | |
841 | spin_unlock_irq(&nvmeq->q_lock); | |
842 | ||
843 | if (tag == -1) | |
844 | return 1; | |
845 | } | |
846 | ||
847 | return 0; | |
848 | } | |
849 | ||
f866fc42 | 850 | static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx) |
b60503ba | 851 | { |
f866fc42 | 852 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9396dec9 | 853 | struct nvme_queue *nvmeq = dev->queues[0]; |
a4aea562 | 854 | struct nvme_command c; |
b60503ba | 855 | |
a4aea562 MB |
856 | memset(&c, 0, sizeof(c)); |
857 | c.common.opcode = nvme_admin_async_event; | |
f866fc42 | 858 | c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx; |
3c0cf138 | 859 | |
9396dec9 | 860 | spin_lock_irq(&nvmeq->q_lock); |
f866fc42 | 861 | __nvme_submit_cmd(nvmeq, &c); |
9396dec9 | 862 | spin_unlock_irq(&nvmeq->q_lock); |
f705f837 CH |
863 | } |
864 | ||
b60503ba | 865 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 866 | { |
b60503ba MW |
867 | struct nvme_command c; |
868 | ||
869 | memset(&c, 0, sizeof(c)); | |
870 | c.delete_queue.opcode = opcode; | |
871 | c.delete_queue.qid = cpu_to_le16(id); | |
872 | ||
1c63dc66 | 873 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
874 | } |
875 | ||
b60503ba MW |
876 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
877 | struct nvme_queue *nvmeq) | |
878 | { | |
b60503ba MW |
879 | struct nvme_command c; |
880 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
881 | ||
d29ec824 CH |
882 | /* |
883 | * Note: we (ab)use the fact the the prp fields survive if no data | |
884 | * is attached to the request. | |
885 | */ | |
b60503ba MW |
886 | memset(&c, 0, sizeof(c)); |
887 | c.create_cq.opcode = nvme_admin_create_cq; | |
888 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
889 | c.create_cq.cqid = cpu_to_le16(qid); | |
890 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
891 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
892 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
893 | ||
1c63dc66 | 894 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
895 | } |
896 | ||
897 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
898 | struct nvme_queue *nvmeq) | |
899 | { | |
b60503ba MW |
900 | struct nvme_command c; |
901 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
902 | ||
d29ec824 CH |
903 | /* |
904 | * Note: we (ab)use the fact the the prp fields survive if no data | |
905 | * is attached to the request. | |
906 | */ | |
b60503ba MW |
907 | memset(&c, 0, sizeof(c)); |
908 | c.create_sq.opcode = nvme_admin_create_sq; | |
909 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
910 | c.create_sq.sqid = cpu_to_le16(qid); | |
911 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
912 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
913 | c.create_sq.cqid = cpu_to_le16(qid); | |
914 | ||
1c63dc66 | 915 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
916 | } |
917 | ||
918 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
919 | { | |
920 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
921 | } | |
922 | ||
923 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
924 | { | |
925 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
926 | } | |
927 | ||
e7a2a87d | 928 | static void abort_endio(struct request *req, int error) |
bc5fc7e4 | 929 | { |
f4800d6d CH |
930 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
931 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e7a2a87d | 932 | u16 status = req->errors; |
e44ac588 | 933 | |
1cb3cce5 | 934 | dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status); |
e7a2a87d | 935 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
e7a2a87d | 936 | blk_mq_free_request(req); |
bc5fc7e4 MW |
937 | } |
938 | ||
31c7c7d2 | 939 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 940 | { |
f4800d6d CH |
941 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
942 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 943 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 944 | struct request *abort_req; |
a4aea562 | 945 | struct nvme_command cmd; |
c30341dc | 946 | |
31c7c7d2 | 947 | /* |
fd634f41 CH |
948 | * Shutdown immediately if controller times out while starting. The |
949 | * reset work will see the pci device disabled when it gets the forced | |
950 | * cancellation error. All outstanding requests are completed on | |
951 | * shutdown, so we return BLK_EH_HANDLED. | |
952 | */ | |
bb8d261e | 953 | if (dev->ctrl.state == NVME_CTRL_RESETTING) { |
1b3c47c1 | 954 | dev_warn(dev->ctrl.device, |
fd634f41 CH |
955 | "I/O %d QID %d timeout, disable controller\n", |
956 | req->tag, nvmeq->qid); | |
a5cdb68c | 957 | nvme_dev_disable(dev, false); |
fd634f41 CH |
958 | req->errors = NVME_SC_CANCELLED; |
959 | return BLK_EH_HANDLED; | |
c30341dc KB |
960 | } |
961 | ||
fd634f41 CH |
962 | /* |
963 | * Shutdown the controller immediately and schedule a reset if the | |
964 | * command was already aborted once before and still hasn't been | |
965 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 966 | */ |
f4800d6d | 967 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 968 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
969 | "I/O %d QID %d timeout, reset controller\n", |
970 | req->tag, nvmeq->qid); | |
a5cdb68c | 971 | nvme_dev_disable(dev, false); |
c5f6ce97 | 972 | nvme_reset(dev); |
c30341dc | 973 | |
e1569a16 KB |
974 | /* |
975 | * Mark the request as handled, since the inline shutdown | |
976 | * forces all outstanding requests to complete. | |
977 | */ | |
978 | req->errors = NVME_SC_CANCELLED; | |
979 | return BLK_EH_HANDLED; | |
c30341dc | 980 | } |
c30341dc | 981 | |
f4800d6d | 982 | iod->aborted = 1; |
c30341dc | 983 | |
e7a2a87d | 984 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 985 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 986 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 987 | } |
a4aea562 | 988 | |
c30341dc KB |
989 | memset(&cmd, 0, sizeof(cmd)); |
990 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 991 | cmd.abort.cid = req->tag; |
c30341dc | 992 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 993 | |
1b3c47c1 SG |
994 | dev_warn(nvmeq->dev->ctrl.device, |
995 | "I/O %d QID %d timeout, aborting\n", | |
996 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
997 | |
998 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
eb71f435 | 999 | BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
e7a2a87d CH |
1000 | if (IS_ERR(abort_req)) { |
1001 | atomic_inc(&dev->ctrl.abort_limit); | |
1002 | return BLK_EH_RESET_TIMER; | |
1003 | } | |
1004 | ||
1005 | abort_req->timeout = ADMIN_TIMEOUT; | |
1006 | abort_req->end_io_data = NULL; | |
1007 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
c30341dc | 1008 | |
31c7c7d2 CH |
1009 | /* |
1010 | * The aborted req will be completed on receiving the abort req. | |
1011 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1012 | * as the device then is in a faulty state. | |
1013 | */ | |
1014 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
1015 | } |
1016 | ||
a4aea562 MB |
1017 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1018 | { | |
9e866774 MW |
1019 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1020 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1021 | if (nvmeq->sq_cmds) |
1022 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1023 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1024 | kfree(nvmeq); | |
1025 | } | |
1026 | ||
a1a5ef99 | 1027 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1028 | { |
1029 | int i; | |
1030 | ||
a1a5ef99 | 1031 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1032 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1033 | dev->queue_count--; |
a4aea562 | 1034 | dev->queues[i] = NULL; |
f435c282 | 1035 | nvme_free_queue(nvmeq); |
121c7ad4 | 1036 | } |
22404274 KB |
1037 | } |
1038 | ||
4d115420 KB |
1039 | /** |
1040 | * nvme_suspend_queue - put queue into suspended state | |
1041 | * @nvmeq - queue to suspend | |
4d115420 KB |
1042 | */ |
1043 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1044 | { |
2b25d981 | 1045 | int vector; |
b60503ba | 1046 | |
a09115b2 | 1047 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1048 | if (nvmeq->cq_vector == -1) { |
1049 | spin_unlock_irq(&nvmeq->q_lock); | |
1050 | return 1; | |
1051 | } | |
dca51e78 | 1052 | vector = nvmeq_irq(nvmeq); |
42f61420 | 1053 | nvmeq->dev->online_queues--; |
2b25d981 | 1054 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1055 | spin_unlock_irq(&nvmeq->q_lock); |
1056 | ||
1c63dc66 | 1057 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
25646264 | 1058 | blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q); |
6df3dbc8 | 1059 | |
aba2080f | 1060 | free_irq(vector, nvmeq); |
b60503ba | 1061 | |
4d115420 KB |
1062 | return 0; |
1063 | } | |
b60503ba | 1064 | |
a5cdb68c | 1065 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 1066 | { |
a5cdb68c | 1067 | struct nvme_queue *nvmeq = dev->queues[0]; |
4d115420 KB |
1068 | |
1069 | if (!nvmeq) | |
1070 | return; | |
1071 | if (nvme_suspend_queue(nvmeq)) | |
1072 | return; | |
1073 | ||
a5cdb68c KB |
1074 | if (shutdown) |
1075 | nvme_shutdown_ctrl(&dev->ctrl); | |
1076 | else | |
1077 | nvme_disable_ctrl(&dev->ctrl, lo_hi_readq( | |
1078 | dev->bar + NVME_REG_CAP)); | |
07836e65 KB |
1079 | |
1080 | spin_lock_irq(&nvmeq->q_lock); | |
1081 | nvme_process_cq(nvmeq); | |
1082 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1083 | } |
1084 | ||
8ffaadf7 JD |
1085 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1086 | int entry_size) | |
1087 | { | |
1088 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1089 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1090 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1091 | |
1092 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1093 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1094 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1095 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1096 | |
1097 | /* | |
1098 | * Ensure the reduced q_depth is above some threshold where it | |
1099 | * would be better to map queues in system memory with the | |
1100 | * original depth | |
1101 | */ | |
1102 | if (q_depth < 64) | |
1103 | return -ENOMEM; | |
1104 | } | |
1105 | ||
1106 | return q_depth; | |
1107 | } | |
1108 | ||
1109 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1110 | int qid, int depth) | |
1111 | { | |
1112 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1113 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1114 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1115 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1116 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1117 | } else { | |
1118 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1119 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1120 | if (!nvmeq->sq_cmds) | |
1121 | return -ENOMEM; | |
1122 | } | |
1123 | ||
1124 | return 0; | |
1125 | } | |
1126 | ||
b60503ba | 1127 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
2b25d981 | 1128 | int depth) |
b60503ba | 1129 | { |
a4aea562 | 1130 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1131 | if (!nvmeq) |
1132 | return NULL; | |
1133 | ||
e75ec752 | 1134 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1135 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1136 | if (!nvmeq->cqes) |
1137 | goto free_nvmeq; | |
b60503ba | 1138 | |
8ffaadf7 | 1139 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1140 | goto free_cqdma; |
1141 | ||
e75ec752 | 1142 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1143 | nvmeq->dev = dev; |
3193f07b | 1144 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1c63dc66 | 1145 | dev->ctrl.instance, qid); |
b60503ba MW |
1146 | spin_lock_init(&nvmeq->q_lock); |
1147 | nvmeq->cq_head = 0; | |
82123460 | 1148 | nvmeq->cq_phase = 1; |
b80d5ccc | 1149 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1150 | nvmeq->q_depth = depth; |
c30341dc | 1151 | nvmeq->qid = qid; |
758dd7fd | 1152 | nvmeq->cq_vector = -1; |
a4aea562 | 1153 | dev->queues[qid] = nvmeq; |
36a7e993 JD |
1154 | dev->queue_count++; |
1155 | ||
12e6f749 RN |
1156 | #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE |
1157 | if (dev->db_mem && dev->ei_mem && qid != 0) { | |
1158 | nvmeq->sq_doorbell_addr = &dev->db_mem[qid * 2 * dev->db_stride]; | |
1159 | nvmeq->cq_doorbell_addr = | |
1160 | &dev->db_mem[(qid * 2 + 1) * dev->db_stride]; | |
1161 | nvmeq->sq_eventidx_addr = &dev->ei_mem[qid * 2 * dev->db_stride]; | |
1162 | nvmeq->cq_eventidx_addr = | |
1163 | &dev->ei_mem[(qid * 2 + 1) * dev->db_stride]; | |
1164 | } | |
1165 | #endif | |
1166 | ||
b60503ba MW |
1167 | return nvmeq; |
1168 | ||
1169 | free_cqdma: | |
e75ec752 | 1170 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1171 | nvmeq->cq_dma_addr); |
1172 | free_nvmeq: | |
1173 | kfree(nvmeq); | |
1174 | return NULL; | |
1175 | } | |
1176 | ||
dca51e78 | 1177 | static int queue_request_irq(struct nvme_queue *nvmeq) |
3001082c | 1178 | { |
58ffacb5 | 1179 | if (use_threaded_interrupts) |
dca51e78 CH |
1180 | return request_threaded_irq(nvmeq_irq(nvmeq), nvme_irq_check, |
1181 | nvme_irq, IRQF_SHARED, nvmeq->irqname, nvmeq); | |
1182 | else | |
1183 | return request_irq(nvmeq_irq(nvmeq), nvme_irq, IRQF_SHARED, | |
1184 | nvmeq->irqname, nvmeq); | |
3001082c MW |
1185 | } |
1186 | ||
22404274 | 1187 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1188 | { |
22404274 | 1189 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1190 | |
7be50e93 | 1191 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1192 | nvmeq->sq_tail = 0; |
1193 | nvmeq->cq_head = 0; | |
1194 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1195 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
12e6f749 RN |
1196 | #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE |
1197 | if (to_pci_dev(dev->dev)->vendor == PCI_VENDOR_ID_GOOGLE && qid != 0) { | |
1198 | nvmeq->sq_doorbell_addr = &dev->db_mem[qid * 2 * dev->db_stride]; | |
1199 | nvmeq->cq_doorbell_addr = | |
1200 | &dev->db_mem[(qid * 2 + 1) * dev->db_stride]; | |
1201 | nvmeq->sq_eventidx_addr = &dev->ei_mem[qid * 2 * dev->db_stride]; | |
1202 | nvmeq->cq_eventidx_addr = | |
1203 | &dev->ei_mem[(qid * 2 + 1) * dev->db_stride]; | |
1204 | } | |
1205 | #endif | |
22404274 | 1206 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1207 | dev->online_queues++; |
7be50e93 | 1208 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1209 | } |
1210 | ||
1211 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1212 | { | |
1213 | struct nvme_dev *dev = nvmeq->dev; | |
1214 | int result; | |
3f85d50b | 1215 | |
2b25d981 | 1216 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1217 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1218 | if (result < 0) | |
22404274 | 1219 | return result; |
b60503ba MW |
1220 | |
1221 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1222 | if (result < 0) | |
1223 | goto release_cq; | |
1224 | ||
dca51e78 | 1225 | result = queue_request_irq(nvmeq); |
b60503ba MW |
1226 | if (result < 0) |
1227 | goto release_sq; | |
1228 | ||
22404274 | 1229 | nvme_init_queue(nvmeq, qid); |
22404274 | 1230 | return result; |
b60503ba MW |
1231 | |
1232 | release_sq: | |
1233 | adapter_delete_sq(dev, qid); | |
1234 | release_cq: | |
1235 | adapter_delete_cq(dev, qid); | |
22404274 | 1236 | return result; |
b60503ba MW |
1237 | } |
1238 | ||
a4aea562 | 1239 | static struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1240 | .queue_rq = nvme_queue_rq, |
eee417b0 | 1241 | .complete = nvme_complete_rq, |
a4aea562 | 1242 | .init_hctx = nvme_admin_init_hctx, |
4af0e21c | 1243 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1244 | .init_request = nvme_admin_init_request, |
1245 | .timeout = nvme_timeout, | |
1246 | }; | |
1247 | ||
1248 | static struct blk_mq_ops nvme_mq_ops = { | |
1249 | .queue_rq = nvme_queue_rq, | |
eee417b0 | 1250 | .complete = nvme_complete_rq, |
a4aea562 MB |
1251 | .init_hctx = nvme_init_hctx, |
1252 | .init_request = nvme_init_request, | |
dca51e78 | 1253 | .map_queues = nvme_pci_map_queues, |
a4aea562 | 1254 | .timeout = nvme_timeout, |
a0fa9647 | 1255 | .poll = nvme_poll, |
a4aea562 MB |
1256 | }; |
1257 | ||
ea191d2f KB |
1258 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1259 | { | |
1c63dc66 | 1260 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
69d9a99c KB |
1261 | /* |
1262 | * If the controller was reset during removal, it's possible | |
1263 | * user requests may be waiting on a stopped queue. Start the | |
1264 | * queue to flush these to completion. | |
1265 | */ | |
1266 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); | |
1c63dc66 | 1267 | blk_cleanup_queue(dev->ctrl.admin_q); |
ea191d2f KB |
1268 | blk_mq_free_tag_set(&dev->admin_tagset); |
1269 | } | |
1270 | } | |
1271 | ||
a4aea562 MB |
1272 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1273 | { | |
1c63dc66 | 1274 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1275 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1276 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c KB |
1277 | |
1278 | /* | |
1279 | * Subtract one to leave an empty queue entry for 'Full Queue' | |
1280 | * condition. See NVM-Express 1.2 specification, section 4.1.2. | |
1281 | */ | |
1282 | dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; | |
a4aea562 | 1283 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1284 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1285 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1286 | dev->admin_tagset.driver_data = dev; |
1287 | ||
1288 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1289 | return -ENOMEM; | |
1290 | ||
1c63dc66 CH |
1291 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1292 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1293 | blk_mq_free_tag_set(&dev->admin_tagset); |
1294 | return -ENOMEM; | |
1295 | } | |
1c63dc66 | 1296 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1297 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1298 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1299 | return -ENODEV; |
1300 | } | |
0fb59cbc | 1301 | } else |
25646264 | 1302 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); |
a4aea562 MB |
1303 | |
1304 | return 0; | |
1305 | } | |
1306 | ||
8d85fce7 | 1307 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1308 | { |
ba47e386 | 1309 | int result; |
b60503ba | 1310 | u32 aqa; |
7a67cbea | 1311 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1312 | struct nvme_queue *nvmeq; |
1313 | ||
8ef2074d | 1314 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? |
dfbac8c7 KB |
1315 | NVME_CAP_NSSRC(cap) : 0; |
1316 | ||
7a67cbea CH |
1317 | if (dev->subsystem && |
1318 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1319 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1320 | |
5fd4ce1b | 1321 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1322 | if (result < 0) |
1323 | return result; | |
b60503ba | 1324 | |
a4aea562 | 1325 | nvmeq = dev->queues[0]; |
cd638946 | 1326 | if (!nvmeq) { |
2b25d981 | 1327 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1328 | if (!nvmeq) |
1329 | return -ENOMEM; | |
cd638946 | 1330 | } |
b60503ba MW |
1331 | |
1332 | aqa = nvmeq->q_depth - 1; | |
1333 | aqa |= aqa << 16; | |
1334 | ||
7a67cbea CH |
1335 | writel(aqa, dev->bar + NVME_REG_AQA); |
1336 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1337 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1338 | |
5fd4ce1b | 1339 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1340 | if (result) |
d4875622 | 1341 | return result; |
a4aea562 | 1342 | |
2b25d981 | 1343 | nvmeq->cq_vector = 0; |
dca51e78 | 1344 | result = queue_request_irq(nvmeq); |
758dd7fd JD |
1345 | if (result) { |
1346 | nvmeq->cq_vector = -1; | |
d4875622 | 1347 | return result; |
758dd7fd | 1348 | } |
025c557a | 1349 | |
b60503ba MW |
1350 | return result; |
1351 | } | |
1352 | ||
c875a709 GP |
1353 | static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) |
1354 | { | |
1355 | ||
1356 | /* If true, indicates loss of adapter communication, possibly by a | |
1357 | * NVMe Subsystem reset. | |
1358 | */ | |
1359 | bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); | |
1360 | ||
1361 | /* If there is a reset ongoing, we shouldn't reset again. */ | |
1362 | if (work_busy(&dev->reset_work)) | |
1363 | return false; | |
1364 | ||
1365 | /* We shouldn't reset unless the controller is on fatal error state | |
1366 | * _or_ if we lost the communication with it. | |
1367 | */ | |
1368 | if (!(csts & NVME_CSTS_CFS) && !nssro) | |
1369 | return false; | |
1370 | ||
1371 | /* If PCI error recovery process is happening, we cannot reset or | |
1372 | * the recovery mechanism will surely fail. | |
1373 | */ | |
1374 | if (pci_channel_offline(to_pci_dev(dev->dev))) | |
1375 | return false; | |
1376 | ||
1377 | return true; | |
1378 | } | |
1379 | ||
d2a61918 AL |
1380 | static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) |
1381 | { | |
1382 | /* Read a config register to help see what died. */ | |
1383 | u16 pci_status; | |
1384 | int result; | |
1385 | ||
1386 | result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, | |
1387 | &pci_status); | |
1388 | if (result == PCIBIOS_SUCCESSFUL) | |
1389 | dev_warn(dev->dev, | |
1390 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", | |
1391 | csts, pci_status); | |
1392 | else | |
1393 | dev_warn(dev->dev, | |
1394 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", | |
1395 | csts, result); | |
1396 | } | |
1397 | ||
2d55cd5f | 1398 | static void nvme_watchdog_timer(unsigned long data) |
1fa6aead | 1399 | { |
2d55cd5f CH |
1400 | struct nvme_dev *dev = (struct nvme_dev *)data; |
1401 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
1fa6aead | 1402 | |
c875a709 GP |
1403 | /* Skip controllers under certain specific conditions. */ |
1404 | if (nvme_should_reset(dev, csts)) { | |
c5f6ce97 | 1405 | if (!nvme_reset(dev)) |
d2a61918 | 1406 | nvme_warn_reset(dev, csts); |
2d55cd5f | 1407 | return; |
1fa6aead | 1408 | } |
2d55cd5f CH |
1409 | |
1410 | mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); | |
1fa6aead MW |
1411 | } |
1412 | ||
749941f2 | 1413 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1414 | { |
949928c1 | 1415 | unsigned i, max; |
749941f2 | 1416 | int ret = 0; |
42f61420 | 1417 | |
749941f2 CH |
1418 | for (i = dev->queue_count; i <= dev->max_qid; i++) { |
1419 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) { | |
1420 | ret = -ENOMEM; | |
42f61420 | 1421 | break; |
749941f2 CH |
1422 | } |
1423 | } | |
42f61420 | 1424 | |
949928c1 KB |
1425 | max = min(dev->max_qid, dev->queue_count - 1); |
1426 | for (i = dev->online_queues; i <= max; i++) { | |
749941f2 | 1427 | ret = nvme_create_queue(dev->queues[i], i); |
d4875622 | 1428 | if (ret) |
42f61420 | 1429 | break; |
27e8166c | 1430 | } |
749941f2 CH |
1431 | |
1432 | /* | |
1433 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1434 | * than the desired aount of queues, and even a controller without | |
1435 | * I/O queues an still be used to issue admin commands. This might | |
1436 | * be useful to upgrade a buggy firmware for example. | |
1437 | */ | |
1438 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1439 | } |
1440 | ||
202021c1 SB |
1441 | static ssize_t nvme_cmb_show(struct device *dev, |
1442 | struct device_attribute *attr, | |
1443 | char *buf) | |
1444 | { | |
1445 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
1446 | ||
c965809c | 1447 | return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", |
202021c1 SB |
1448 | ndev->cmbloc, ndev->cmbsz); |
1449 | } | |
1450 | static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); | |
1451 | ||
8ffaadf7 JD |
1452 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1453 | { | |
1454 | u64 szu, size, offset; | |
8ffaadf7 JD |
1455 | resource_size_t bar_size; |
1456 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1457 | void __iomem *cmb; | |
1458 | dma_addr_t dma_addr; | |
1459 | ||
7a67cbea | 1460 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1461 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1462 | return NULL; | |
202021c1 | 1463 | dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 | 1464 | |
202021c1 SB |
1465 | if (!use_cmb_sqes) |
1466 | return NULL; | |
8ffaadf7 JD |
1467 | |
1468 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1469 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
202021c1 SB |
1470 | offset = szu * NVME_CMB_OFST(dev->cmbloc); |
1471 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc)); | |
8ffaadf7 JD |
1472 | |
1473 | if (offset > bar_size) | |
1474 | return NULL; | |
1475 | ||
1476 | /* | |
1477 | * Controllers may support a CMB size larger than their BAR, | |
1478 | * for example, due to being behind a bridge. Reduce the CMB to | |
1479 | * the reported size of the BAR | |
1480 | */ | |
1481 | if (size > bar_size - offset) | |
1482 | size = bar_size - offset; | |
1483 | ||
202021c1 | 1484 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset; |
8ffaadf7 JD |
1485 | cmb = ioremap_wc(dma_addr, size); |
1486 | if (!cmb) | |
1487 | return NULL; | |
1488 | ||
1489 | dev->cmb_dma_addr = dma_addr; | |
1490 | dev->cmb_size = size; | |
1491 | return cmb; | |
1492 | } | |
1493 | ||
1494 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1495 | { | |
1496 | if (dev->cmb) { | |
1497 | iounmap(dev->cmb); | |
1498 | dev->cmb = NULL; | |
1499 | } | |
1500 | } | |
1501 | ||
9d713c2b KB |
1502 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1503 | { | |
b80d5ccc | 1504 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
1505 | } |
1506 | ||
8d85fce7 | 1507 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1508 | { |
a4aea562 | 1509 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1510 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
dca51e78 | 1511 | int result, nr_io_queues, size; |
b60503ba | 1512 | |
2800b8e7 | 1513 | nr_io_queues = num_online_cpus(); |
9a0be7ab CH |
1514 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1515 | if (result < 0) | |
1b23484b | 1516 | return result; |
9a0be7ab | 1517 | |
f5fa90dc | 1518 | if (nr_io_queues == 0) |
a5229050 | 1519 | return 0; |
b60503ba | 1520 | |
8ffaadf7 JD |
1521 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1522 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1523 | sizeof(struct nvme_command)); | |
1524 | if (result > 0) | |
1525 | dev->q_depth = result; | |
1526 | else | |
1527 | nvme_release_cmb(dev); | |
1528 | } | |
1529 | ||
9d713c2b KB |
1530 | size = db_bar_size(dev, nr_io_queues); |
1531 | if (size > 8192) { | |
f1938f6e | 1532 | iounmap(dev->bar); |
9d713c2b KB |
1533 | do { |
1534 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1535 | if (dev->bar) | |
1536 | break; | |
1537 | if (!--nr_io_queues) | |
1538 | return -ENOMEM; | |
1539 | size = db_bar_size(dev, nr_io_queues); | |
1540 | } while (1); | |
7a67cbea | 1541 | dev->dbs = dev->bar + 4096; |
5a92e700 | 1542 | adminq->q_db = dev->dbs; |
f1938f6e MW |
1543 | } |
1544 | ||
9d713c2b | 1545 | /* Deregister the admin queue's interrupt */ |
dca51e78 | 1546 | free_irq(pci_irq_vector(pdev, 0), adminq); |
9d713c2b | 1547 | |
e32efbfc JA |
1548 | /* |
1549 | * If we enable msix early due to not intx, disable it again before | |
1550 | * setting up the full range we need. | |
1551 | */ | |
dca51e78 CH |
1552 | pci_free_irq_vectors(pdev); |
1553 | nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues, | |
1554 | PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY); | |
1555 | if (nr_io_queues <= 0) | |
1556 | return -EIO; | |
1557 | dev->max_qid = nr_io_queues; | |
fa08a396 | 1558 | |
063a8096 MW |
1559 | /* |
1560 | * Should investigate if there's a performance win from allocating | |
1561 | * more queues than interrupt vectors; it might allow the submission | |
1562 | * path to scale better, even if the receive path is limited by the | |
1563 | * number of interrupts. | |
1564 | */ | |
063a8096 | 1565 | |
dca51e78 | 1566 | result = queue_request_irq(adminq); |
758dd7fd JD |
1567 | if (result) { |
1568 | adminq->cq_vector = -1; | |
d4875622 | 1569 | return result; |
758dd7fd | 1570 | } |
749941f2 | 1571 | return nvme_create_io_queues(dev); |
b60503ba MW |
1572 | } |
1573 | ||
db3cbfff | 1574 | static void nvme_del_queue_end(struct request *req, int error) |
a5768aa8 | 1575 | { |
db3cbfff | 1576 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 1577 | |
db3cbfff KB |
1578 | blk_mq_free_request(req); |
1579 | complete(&nvmeq->dev->ioq_wait); | |
a5768aa8 KB |
1580 | } |
1581 | ||
db3cbfff | 1582 | static void nvme_del_cq_end(struct request *req, int error) |
a5768aa8 | 1583 | { |
db3cbfff | 1584 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 1585 | |
db3cbfff KB |
1586 | if (!error) { |
1587 | unsigned long flags; | |
1588 | ||
2e39e0f6 ML |
1589 | /* |
1590 | * We might be called with the AQ q_lock held | |
1591 | * and the I/O queue q_lock should always | |
1592 | * nest inside the AQ one. | |
1593 | */ | |
1594 | spin_lock_irqsave_nested(&nvmeq->q_lock, flags, | |
1595 | SINGLE_DEPTH_NESTING); | |
db3cbfff KB |
1596 | nvme_process_cq(nvmeq); |
1597 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
a5768aa8 | 1598 | } |
db3cbfff KB |
1599 | |
1600 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
1601 | } |
1602 | ||
db3cbfff | 1603 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 1604 | { |
db3cbfff KB |
1605 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
1606 | struct request *req; | |
1607 | struct nvme_command cmd; | |
bda4e0fb | 1608 | |
db3cbfff KB |
1609 | memset(&cmd, 0, sizeof(cmd)); |
1610 | cmd.delete_queue.opcode = opcode; | |
1611 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 1612 | |
eb71f435 | 1613 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
db3cbfff KB |
1614 | if (IS_ERR(req)) |
1615 | return PTR_ERR(req); | |
bda4e0fb | 1616 | |
db3cbfff KB |
1617 | req->timeout = ADMIN_TIMEOUT; |
1618 | req->end_io_data = nvmeq; | |
1619 | ||
1620 | blk_execute_rq_nowait(q, NULL, req, false, | |
1621 | opcode == nvme_admin_delete_cq ? | |
1622 | nvme_del_cq_end : nvme_del_queue_end); | |
1623 | return 0; | |
bda4e0fb KB |
1624 | } |
1625 | ||
70659060 | 1626 | static void nvme_disable_io_queues(struct nvme_dev *dev, int queues) |
a5768aa8 | 1627 | { |
70659060 | 1628 | int pass; |
db3cbfff KB |
1629 | unsigned long timeout; |
1630 | u8 opcode = nvme_admin_delete_sq; | |
a5768aa8 | 1631 | |
db3cbfff | 1632 | for (pass = 0; pass < 2; pass++) { |
014a0d60 | 1633 | int sent = 0, i = queues; |
db3cbfff KB |
1634 | |
1635 | reinit_completion(&dev->ioq_wait); | |
1636 | retry: | |
1637 | timeout = ADMIN_TIMEOUT; | |
c21377f8 GKB |
1638 | for (; i > 0; i--, sent++) |
1639 | if (nvme_delete_queue(dev->queues[i], opcode)) | |
db3cbfff | 1640 | break; |
c21377f8 | 1641 | |
db3cbfff KB |
1642 | while (sent--) { |
1643 | timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); | |
1644 | if (timeout == 0) | |
1645 | return; | |
1646 | if (i) | |
1647 | goto retry; | |
1648 | } | |
1649 | opcode = nvme_admin_delete_cq; | |
1650 | } | |
a5768aa8 KB |
1651 | } |
1652 | ||
422ef0c7 MW |
1653 | /* |
1654 | * Return: error value if an error occurred setting up the queues or calling | |
1655 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1656 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1657 | * failures should be reported. | |
1658 | */ | |
8d85fce7 | 1659 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1660 | { |
5bae7f73 | 1661 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1662 | dev->tagset.ops = &nvme_mq_ops; |
1663 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1664 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1665 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1666 | dev->tagset.queue_depth = | |
a4aea562 | 1667 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1668 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1669 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1670 | dev->tagset.driver_data = dev; | |
b60503ba | 1671 | |
ffe7704d KB |
1672 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1673 | return 0; | |
5bae7f73 | 1674 | dev->ctrl.tagset = &dev->tagset; |
12e6f749 RN |
1675 | |
1676 | #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE | |
1677 | if (to_pci_dev(dev->dev)->vendor == PCI_VENDOR_ID_GOOGLE) { | |
1678 | int res = nvme_set_doorbell_memory(dev); | |
1679 | if (res) { | |
1680 | // Free memory and continue on. | |
1681 | dma_free_coherent(dev->dev, 8192, dev->db_mem, dev->doorbell); | |
1682 | dma_free_coherent(dev->dev, 8192, dev->ei_mem, dev->doorbell); | |
1683 | dev->db_mem = 0; | |
1684 | dev->ei_mem = 0; | |
1685 | } | |
1686 | } | |
1687 | #endif | |
949928c1 KB |
1688 | } else { |
1689 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
1690 | ||
1691 | /* Free previously allocated queues that are no longer usable */ | |
1692 | nvme_free_queues(dev, dev->online_queues); | |
ffe7704d | 1693 | } |
949928c1 | 1694 | |
e1e5e564 | 1695 | return 0; |
b60503ba MW |
1696 | } |
1697 | ||
b00a726a | 1698 | static int nvme_pci_enable(struct nvme_dev *dev) |
0877cb0d | 1699 | { |
42f61420 | 1700 | u64 cap; |
b00a726a | 1701 | int result = -ENOMEM; |
e75ec752 | 1702 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1703 | |
1704 | if (pci_enable_device_mem(pdev)) | |
1705 | return result; | |
1706 | ||
0877cb0d | 1707 | pci_set_master(pdev); |
0877cb0d | 1708 | |
e75ec752 CH |
1709 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1710 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1711 | goto disable; |
0877cb0d | 1712 | |
7a67cbea | 1713 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 | 1714 | result = -ENODEV; |
b00a726a | 1715 | goto disable; |
0e53d180 | 1716 | } |
e32efbfc JA |
1717 | |
1718 | /* | |
a5229050 KB |
1719 | * Some devices and/or platforms don't advertise or work with INTx |
1720 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll | |
1721 | * adjust this later. | |
e32efbfc | 1722 | */ |
dca51e78 CH |
1723 | result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
1724 | if (result < 0) | |
1725 | return result; | |
e32efbfc | 1726 | |
7a67cbea CH |
1727 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1728 | ||
42f61420 KB |
1729 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1730 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea | 1731 | dev->dbs = dev->bar + 4096; |
1f390c1f SG |
1732 | |
1733 | /* | |
1734 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
1735 | * some MacBook7,1 to avoid controller resets and data loss. | |
1736 | */ | |
1737 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
1738 | dev->q_depth = 2; | |
1739 | dev_warn(dev->dev, "detected Apple NVMe controller, set " | |
1740 | "queue depth=%u to work around controller resets\n", | |
1741 | dev->q_depth); | |
1742 | } | |
1743 | ||
202021c1 SB |
1744 | /* |
1745 | * CMBs can currently only exist on >=1.2 PCIe devices. We only | |
1746 | * populate sysfs if a CMB is implemented. Note that we add the | |
1747 | * CMB attribute to the nvme_ctrl kobj which removes the need to remove | |
1748 | * it on exit. Since nvme_dev_attrs_group has no name we can pass | |
1749 | * NULL as final argument to sysfs_add_file_to_group. | |
1750 | */ | |
1751 | ||
8ef2074d | 1752 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) { |
8ffaadf7 | 1753 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d | 1754 | |
202021c1 SB |
1755 | if (dev->cmbsz) { |
1756 | if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, | |
1757 | &dev_attr_cmb.attr, NULL)) | |
1758 | dev_warn(dev->dev, | |
1759 | "failed to add sysfs attribute for CMB\n"); | |
1760 | } | |
1761 | } | |
1762 | ||
a0a3408e KB |
1763 | pci_enable_pcie_error_reporting(pdev); |
1764 | pci_save_state(pdev); | |
12e6f749 RN |
1765 | |
1766 | #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE | |
1767 | if (pdev->vendor == PCI_VENDOR_ID_GOOGLE) { | |
1768 | int mem_size = nvme_vendor_memory_size(dev); | |
1769 | dev->db_mem = dma_alloc_coherent(&pdev->dev, mem_size, &dev->doorbell, GFP_KERNEL); | |
1770 | if (!dev->db_mem) { | |
1771 | result = -ENOMEM; | |
1772 | goto disable; | |
1773 | } | |
1774 | dev->ei_mem = dma_alloc_coherent(&pdev->dev, mem_size, &dev->eventidx, GFP_KERNEL); | |
1775 | if (!dev->ei_mem) { | |
1776 | result = -ENOMEM; | |
1777 | goto dma_free; | |
1778 | } | |
1779 | } | |
1780 | #endif | |
1781 | ||
0877cb0d KB |
1782 | return 0; |
1783 | ||
12e6f749 RN |
1784 | #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE |
1785 | dma_free: | |
1786 | dma_free_coherent(&pdev->dev, nvme_vendor_memory_size(dev), dev->db_mem, dev->doorbell); | |
1787 | dev->db_mem = 0; | |
1788 | #endif | |
1789 | ||
0877cb0d | 1790 | disable: |
0877cb0d KB |
1791 | pci_disable_device(pdev); |
1792 | return result; | |
1793 | } | |
1794 | ||
1795 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
b00a726a KB |
1796 | { |
1797 | if (dev->bar) | |
1798 | iounmap(dev->bar); | |
a1f447b3 | 1799 | pci_release_mem_regions(to_pci_dev(dev->dev)); |
b00a726a KB |
1800 | } |
1801 | ||
1802 | static void nvme_pci_disable(struct nvme_dev *dev) | |
0877cb0d | 1803 | { |
e75ec752 | 1804 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
12e6f749 RN |
1805 | #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE |
1806 | int mem_size = nvme_vendor_memory_size(dev); | |
1807 | ||
1808 | if (dev->db_mem) | |
1809 | dma_free_coherent(&pdev->dev, mem_size, dev->db_mem, dev->doorbell); | |
1810 | if (dev->ei_mem) | |
1811 | dma_free_coherent(&pdev->dev, mem_size, dev->ei_mem, dev->eventidx); | |
1812 | #endif | |
e75ec752 | 1813 | |
dca51e78 | 1814 | pci_free_irq_vectors(pdev); |
0877cb0d | 1815 | |
a0a3408e KB |
1816 | if (pci_is_enabled(pdev)) { |
1817 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 1818 | pci_disable_device(pdev); |
4d115420 | 1819 | } |
4d115420 KB |
1820 | } |
1821 | ||
a5cdb68c | 1822 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 1823 | { |
70659060 | 1824 | int i, queues; |
7c1b2450 | 1825 | u32 csts = -1; |
22404274 | 1826 | |
2d55cd5f | 1827 | del_timer_sync(&dev->watchdog_timer); |
1fa6aead | 1828 | |
77bf25ea | 1829 | mutex_lock(&dev->shutdown_lock); |
b00a726a | 1830 | if (pci_is_enabled(to_pci_dev(dev->dev))) { |
25646264 | 1831 | nvme_stop_queues(&dev->ctrl); |
7a67cbea | 1832 | csts = readl(dev->bar + NVME_REG_CSTS); |
c9d3bf88 | 1833 | } |
c21377f8 | 1834 | |
70659060 | 1835 | queues = dev->online_queues - 1; |
c21377f8 GKB |
1836 | for (i = dev->queue_count - 1; i > 0; i--) |
1837 | nvme_suspend_queue(dev->queues[i]); | |
1838 | ||
7c1b2450 | 1839 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
82469c59 GKB |
1840 | /* A device might become IO incapable very soon during |
1841 | * probe, before the admin queue is configured. Thus, | |
1842 | * queue_count can be 0 here. | |
1843 | */ | |
1844 | if (dev->queue_count) | |
1845 | nvme_suspend_queue(dev->queues[0]); | |
4d115420 | 1846 | } else { |
70659060 | 1847 | nvme_disable_io_queues(dev, queues); |
a5cdb68c | 1848 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 1849 | } |
b00a726a | 1850 | nvme_pci_disable(dev); |
07836e65 | 1851 | |
e1958e65 ML |
1852 | blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); |
1853 | blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); | |
77bf25ea | 1854 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
1855 | } |
1856 | ||
091b6092 MW |
1857 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1858 | { | |
e75ec752 | 1859 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
1860 | PAGE_SIZE, PAGE_SIZE, 0); |
1861 | if (!dev->prp_page_pool) | |
1862 | return -ENOMEM; | |
1863 | ||
99802a7a | 1864 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 1865 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
1866 | 256, 256, 0); |
1867 | if (!dev->prp_small_pool) { | |
1868 | dma_pool_destroy(dev->prp_page_pool); | |
1869 | return -ENOMEM; | |
1870 | } | |
091b6092 MW |
1871 | return 0; |
1872 | } | |
1873 | ||
1874 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1875 | { | |
1876 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1877 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1878 | } |
1879 | ||
1673f1f0 | 1880 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 1881 | { |
1673f1f0 | 1882 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 1883 | |
e75ec752 | 1884 | put_device(dev->dev); |
4af0e21c KB |
1885 | if (dev->tagset.tags) |
1886 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
1887 | if (dev->ctrl.admin_q) |
1888 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 | 1889 | kfree(dev->queues); |
5e82e952 KB |
1890 | kfree(dev); |
1891 | } | |
1892 | ||
f58944e2 KB |
1893 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) |
1894 | { | |
237045fc | 1895 | dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); |
f58944e2 KB |
1896 | |
1897 | kref_get(&dev->ctrl.kref); | |
69d9a99c | 1898 | nvme_dev_disable(dev, false); |
f58944e2 KB |
1899 | if (!schedule_work(&dev->remove_work)) |
1900 | nvme_put_ctrl(&dev->ctrl); | |
1901 | } | |
1902 | ||
fd634f41 | 1903 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 1904 | { |
fd634f41 | 1905 | struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); |
f58944e2 | 1906 | int result = -ENODEV; |
5e82e952 | 1907 | |
bb8d261e | 1908 | if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING)) |
fd634f41 | 1909 | goto out; |
5e82e952 | 1910 | |
fd634f41 CH |
1911 | /* |
1912 | * If we're called to reset a live controller first shut it down before | |
1913 | * moving on. | |
1914 | */ | |
b00a726a | 1915 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
a5cdb68c | 1916 | nvme_dev_disable(dev, false); |
5e82e952 | 1917 | |
bb8d261e | 1918 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) |
9bf2b972 KB |
1919 | goto out; |
1920 | ||
b00a726a | 1921 | result = nvme_pci_enable(dev); |
f0b50732 | 1922 | if (result) |
3cf519b5 | 1923 | goto out; |
f0b50732 KB |
1924 | |
1925 | result = nvme_configure_admin_queue(dev); | |
1926 | if (result) | |
f58944e2 | 1927 | goto out; |
f0b50732 | 1928 | |
a4aea562 | 1929 | nvme_init_queue(dev->queues[0], 0); |
0fb59cbc KB |
1930 | result = nvme_alloc_admin_tags(dev); |
1931 | if (result) | |
f58944e2 | 1932 | goto out; |
b9afca3e | 1933 | |
ce4541f4 CH |
1934 | result = nvme_init_identify(&dev->ctrl); |
1935 | if (result) | |
f58944e2 | 1936 | goto out; |
ce4541f4 | 1937 | |
f0b50732 | 1938 | result = nvme_setup_io_queues(dev); |
badc34d4 | 1939 | if (result) |
f58944e2 | 1940 | goto out; |
f0b50732 | 1941 | |
21f033f7 KB |
1942 | /* |
1943 | * A controller that can not execute IO typically requires user | |
1944 | * intervention to correct. For such degraded controllers, the driver | |
1945 | * should not submit commands the user did not request, so skip | |
1946 | * registering for asynchronous event notification on this condition. | |
1947 | */ | |
f866fc42 CH |
1948 | if (dev->online_queues > 1) |
1949 | nvme_queue_async_events(&dev->ctrl); | |
3cf519b5 | 1950 | |
2d55cd5f | 1951 | mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); |
3cf519b5 | 1952 | |
2659e57b CH |
1953 | /* |
1954 | * Keep the controller around but remove all namespaces if we don't have | |
1955 | * any working I/O queue. | |
1956 | */ | |
3cf519b5 | 1957 | if (dev->online_queues < 2) { |
1b3c47c1 | 1958 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
3b24774e | 1959 | nvme_kill_queues(&dev->ctrl); |
5bae7f73 | 1960 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 | 1961 | } else { |
25646264 | 1962 | nvme_start_queues(&dev->ctrl); |
3cf519b5 CH |
1963 | nvme_dev_add(dev); |
1964 | } | |
1965 | ||
bb8d261e CH |
1966 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { |
1967 | dev_warn(dev->ctrl.device, "failed to mark controller live\n"); | |
1968 | goto out; | |
1969 | } | |
92911a55 CH |
1970 | |
1971 | if (dev->online_queues > 1) | |
5955be21 | 1972 | nvme_queue_scan(&dev->ctrl); |
3cf519b5 | 1973 | return; |
f0b50732 | 1974 | |
3cf519b5 | 1975 | out: |
f58944e2 | 1976 | nvme_remove_dead_ctrl(dev, result); |
f0b50732 KB |
1977 | } |
1978 | ||
5c8809e6 | 1979 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 1980 | { |
5c8809e6 | 1981 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 1982 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 | 1983 | |
69d9a99c | 1984 | nvme_kill_queues(&dev->ctrl); |
9a6b9458 | 1985 | if (pci_get_drvdata(pdev)) |
921920ab | 1986 | device_release_driver(&pdev->dev); |
1673f1f0 | 1987 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
1988 | } |
1989 | ||
4cc06521 | 1990 | static int nvme_reset(struct nvme_dev *dev) |
9a6b9458 | 1991 | { |
1c63dc66 | 1992 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 | 1993 | return -ENODEV; |
c5f6ce97 KB |
1994 | if (work_busy(&dev->reset_work)) |
1995 | return -ENODEV; | |
846cc05f CH |
1996 | if (!queue_work(nvme_workq, &dev->reset_work)) |
1997 | return -EBUSY; | |
846cc05f | 1998 | return 0; |
9a6b9458 KB |
1999 | } |
2000 | ||
1c63dc66 | 2001 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 2002 | { |
1c63dc66 | 2003 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 2004 | return 0; |
9ca97374 TH |
2005 | } |
2006 | ||
5fd4ce1b | 2007 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 2008 | { |
5fd4ce1b CH |
2009 | writel(val, to_nvme_dev(ctrl)->bar + off); |
2010 | return 0; | |
2011 | } | |
4cc06521 | 2012 | |
7fd8930f CH |
2013 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2014 | { | |
2015 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
2016 | return 0; | |
4cc06521 KB |
2017 | } |
2018 | ||
f3ca80fc CH |
2019 | static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) |
2020 | { | |
c5f6ce97 KB |
2021 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
2022 | int ret = nvme_reset(dev); | |
2023 | ||
2024 | if (!ret) | |
2025 | flush_work(&dev->reset_work); | |
2026 | return ret; | |
4cc06521 | 2027 | } |
f3ca80fc | 2028 | |
1c63dc66 | 2029 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
1a353d85 | 2030 | .name = "pcie", |
e439bb12 | 2031 | .module = THIS_MODULE, |
1c63dc66 | 2032 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 2033 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 2034 | .reg_read64 = nvme_pci_reg_read64, |
f3ca80fc | 2035 | .reset_ctrl = nvme_pci_reset_ctrl, |
1673f1f0 | 2036 | .free_ctrl = nvme_pci_free_ctrl, |
f866fc42 | 2037 | .submit_async_event = nvme_pci_submit_async_event, |
1c63dc66 | 2038 | }; |
4cc06521 | 2039 | |
b00a726a KB |
2040 | static int nvme_dev_map(struct nvme_dev *dev) |
2041 | { | |
b00a726a KB |
2042 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2043 | ||
a1f447b3 | 2044 | if (pci_request_mem_regions(pdev, "nvme")) |
b00a726a KB |
2045 | return -ENODEV; |
2046 | ||
2047 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); | |
2048 | if (!dev->bar) | |
2049 | goto release; | |
2050 | ||
9fa196e7 | 2051 | return 0; |
b00a726a | 2052 | release: |
9fa196e7 MG |
2053 | pci_release_mem_regions(pdev); |
2054 | return -ENODEV; | |
b00a726a KB |
2055 | } |
2056 | ||
8d85fce7 | 2057 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2058 | { |
a4aea562 | 2059 | int node, result = -ENOMEM; |
b60503ba MW |
2060 | struct nvme_dev *dev; |
2061 | ||
a4aea562 MB |
2062 | node = dev_to_node(&pdev->dev); |
2063 | if (node == NUMA_NO_NODE) | |
2fa84351 | 2064 | set_dev_node(&pdev->dev, first_memory_node); |
a4aea562 MB |
2065 | |
2066 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2067 | if (!dev) |
2068 | return -ENOMEM; | |
a4aea562 MB |
2069 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2070 | GFP_KERNEL, node); | |
b60503ba MW |
2071 | if (!dev->queues) |
2072 | goto free; | |
2073 | ||
e75ec752 | 2074 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2075 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2076 | |
b00a726a KB |
2077 | result = nvme_dev_map(dev); |
2078 | if (result) | |
2079 | goto free; | |
2080 | ||
f3ca80fc | 2081 | INIT_WORK(&dev->reset_work, nvme_reset_work); |
5c8809e6 | 2082 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
2d55cd5f CH |
2083 | setup_timer(&dev->watchdog_timer, nvme_watchdog_timer, |
2084 | (unsigned long)dev); | |
77bf25ea | 2085 | mutex_init(&dev->shutdown_lock); |
db3cbfff | 2086 | init_completion(&dev->ioq_wait); |
b60503ba | 2087 | |
091b6092 MW |
2088 | result = nvme_setup_prp_pools(dev); |
2089 | if (result) | |
a96d4f5c | 2090 | goto put_pci; |
4cc06521 | 2091 | |
f3ca80fc CH |
2092 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
2093 | id->driver_data); | |
4cc06521 | 2094 | if (result) |
2e1d8448 | 2095 | goto release_pools; |
740216fc | 2096 | |
1b3c47c1 SG |
2097 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
2098 | ||
92f7a162 | 2099 | queue_work(nvme_workq, &dev->reset_work); |
b60503ba MW |
2100 | return 0; |
2101 | ||
0877cb0d | 2102 | release_pools: |
091b6092 | 2103 | nvme_release_prp_pools(dev); |
a96d4f5c | 2104 | put_pci: |
e75ec752 | 2105 | put_device(dev->dev); |
b00a726a | 2106 | nvme_dev_unmap(dev); |
b60503ba MW |
2107 | free: |
2108 | kfree(dev->queues); | |
b60503ba MW |
2109 | kfree(dev); |
2110 | return result; | |
2111 | } | |
2112 | ||
f0d54a54 KB |
2113 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
2114 | { | |
a6739479 | 2115 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 2116 | |
a6739479 | 2117 | if (prepare) |
a5cdb68c | 2118 | nvme_dev_disable(dev, false); |
a6739479 | 2119 | else |
c5f6ce97 | 2120 | nvme_reset(dev); |
f0d54a54 KB |
2121 | } |
2122 | ||
09ece142 KB |
2123 | static void nvme_shutdown(struct pci_dev *pdev) |
2124 | { | |
2125 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
a5cdb68c | 2126 | nvme_dev_disable(dev, true); |
09ece142 KB |
2127 | } |
2128 | ||
f58944e2 KB |
2129 | /* |
2130 | * The driver's remove may be called on a device in a partially initialized | |
2131 | * state. This function must not have any dependencies on the device state in | |
2132 | * order to proceed. | |
2133 | */ | |
8d85fce7 | 2134 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2135 | { |
2136 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 2137 | |
bb8d261e CH |
2138 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
2139 | ||
9a6b9458 | 2140 | pci_set_drvdata(pdev, NULL); |
0ff9d4e1 KB |
2141 | |
2142 | if (!pci_device_is_present(pdev)) | |
2143 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); | |
2144 | ||
9bf2b972 | 2145 | flush_work(&dev->reset_work); |
53029b04 | 2146 | nvme_uninit_ctrl(&dev->ctrl); |
a5cdb68c | 2147 | nvme_dev_disable(dev, true); |
a4aea562 | 2148 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2149 | nvme_free_queues(dev, 0); |
8ffaadf7 | 2150 | nvme_release_cmb(dev); |
9a6b9458 | 2151 | nvme_release_prp_pools(dev); |
b00a726a | 2152 | nvme_dev_unmap(dev); |
1673f1f0 | 2153 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2154 | } |
2155 | ||
13880f5b KB |
2156 | static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) |
2157 | { | |
2158 | int ret = 0; | |
2159 | ||
2160 | if (numvfs == 0) { | |
2161 | if (pci_vfs_assigned(pdev)) { | |
2162 | dev_warn(&pdev->dev, | |
2163 | "Cannot disable SR-IOV VFs while assigned\n"); | |
2164 | return -EPERM; | |
2165 | } | |
2166 | pci_disable_sriov(pdev); | |
2167 | return 0; | |
2168 | } | |
2169 | ||
2170 | ret = pci_enable_sriov(pdev, numvfs); | |
2171 | return ret ? ret : numvfs; | |
2172 | } | |
2173 | ||
671a6018 | 2174 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2175 | static int nvme_suspend(struct device *dev) |
2176 | { | |
2177 | struct pci_dev *pdev = to_pci_dev(dev); | |
2178 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2179 | ||
a5cdb68c | 2180 | nvme_dev_disable(ndev, true); |
cd638946 KB |
2181 | return 0; |
2182 | } | |
2183 | ||
2184 | static int nvme_resume(struct device *dev) | |
2185 | { | |
2186 | struct pci_dev *pdev = to_pci_dev(dev); | |
2187 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2188 | |
c5f6ce97 | 2189 | nvme_reset(ndev); |
9a6b9458 | 2190 | return 0; |
cd638946 | 2191 | } |
671a6018 | 2192 | #endif |
cd638946 KB |
2193 | |
2194 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2195 | |
a0a3408e KB |
2196 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2197 | pci_channel_state_t state) | |
2198 | { | |
2199 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2200 | ||
2201 | /* | |
2202 | * A frozen channel requires a reset. When detected, this method will | |
2203 | * shutdown the controller to quiesce. The controller will be restarted | |
2204 | * after the slot reset through driver's slot_reset callback. | |
2205 | */ | |
a0a3408e KB |
2206 | switch (state) { |
2207 | case pci_channel_io_normal: | |
2208 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2209 | case pci_channel_io_frozen: | |
d011fb31 KB |
2210 | dev_warn(dev->ctrl.device, |
2211 | "frozen state error detected, reset controller\n"); | |
a5cdb68c | 2212 | nvme_dev_disable(dev, false); |
a0a3408e KB |
2213 | return PCI_ERS_RESULT_NEED_RESET; |
2214 | case pci_channel_io_perm_failure: | |
d011fb31 KB |
2215 | dev_warn(dev->ctrl.device, |
2216 | "failure state error detected, request disconnect\n"); | |
a0a3408e KB |
2217 | return PCI_ERS_RESULT_DISCONNECT; |
2218 | } | |
2219 | return PCI_ERS_RESULT_NEED_RESET; | |
2220 | } | |
2221 | ||
2222 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2223 | { | |
2224 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2225 | ||
1b3c47c1 | 2226 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e | 2227 | pci_restore_state(pdev); |
c5f6ce97 | 2228 | nvme_reset(dev); |
a0a3408e KB |
2229 | return PCI_ERS_RESULT_RECOVERED; |
2230 | } | |
2231 | ||
2232 | static void nvme_error_resume(struct pci_dev *pdev) | |
2233 | { | |
2234 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2235 | } | |
2236 | ||
1d352035 | 2237 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2238 | .error_detected = nvme_error_detected, |
b60503ba MW |
2239 | .slot_reset = nvme_slot_reset, |
2240 | .resume = nvme_error_resume, | |
f0d54a54 | 2241 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2242 | }; |
2243 | ||
6eb0d698 | 2244 | static const struct pci_device_id nvme_id_table[] = { |
106198ed | 2245 | { PCI_VDEVICE(INTEL, 0x0953), |
08095e70 KB |
2246 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
2247 | NVME_QUIRK_DISCARD_ZEROES, }, | |
99466e70 KB |
2248 | { PCI_VDEVICE(INTEL, 0x0a53), |
2249 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
2250 | NVME_QUIRK_DISCARD_ZEROES, }, | |
2251 | { PCI_VDEVICE(INTEL, 0x0a54), | |
2252 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
2253 | NVME_QUIRK_DISCARD_ZEROES, }, | |
540c801c KB |
2254 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2255 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
54adc010 GP |
2256 | { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ |
2257 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
015282c9 WW |
2258 | { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ |
2259 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
b60503ba | 2260 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2261 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
b60503ba MW |
2262 | { 0, } |
2263 | }; | |
2264 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2265 | ||
2266 | static struct pci_driver nvme_driver = { | |
2267 | .name = "nvme", | |
2268 | .id_table = nvme_id_table, | |
2269 | .probe = nvme_probe, | |
8d85fce7 | 2270 | .remove = nvme_remove, |
09ece142 | 2271 | .shutdown = nvme_shutdown, |
cd638946 KB |
2272 | .driver = { |
2273 | .pm = &nvme_dev_pm_ops, | |
2274 | }, | |
13880f5b | 2275 | .sriov_configure = nvme_pci_sriov_configure, |
b60503ba MW |
2276 | .err_handler = &nvme_err_handler, |
2277 | }; | |
2278 | ||
2279 | static int __init nvme_init(void) | |
2280 | { | |
0ac13140 | 2281 | int result; |
1fa6aead | 2282 | |
92f7a162 | 2283 | nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0); |
9a6b9458 | 2284 | if (!nvme_workq) |
b9afca3e | 2285 | return -ENOMEM; |
9a6b9458 | 2286 | |
f3db22fe KB |
2287 | result = pci_register_driver(&nvme_driver); |
2288 | if (result) | |
576d55d6 | 2289 | destroy_workqueue(nvme_workq); |
b60503ba MW |
2290 | return result; |
2291 | } | |
2292 | ||
2293 | static void __exit nvme_exit(void) | |
2294 | { | |
2295 | pci_unregister_driver(&nvme_driver); | |
9a6b9458 | 2296 | destroy_workqueue(nvme_workq); |
21bd78bc | 2297 | _nvme_check_size(); |
b60503ba MW |
2298 | } |
2299 | ||
2300 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2301 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2302 | MODULE_VERSION("1.0"); |
b60503ba MW |
2303 | module_init(nvme_init); |
2304 | module_exit(nvme_exit); |