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Commit | Line | Data |
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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
a0a3408e | 15 | #include <linux/aer.h> |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
dca51e78 | 19 | #include <linux/blk-mq-pci.h> |
42f61420 | 20 | #include <linux/cpu.h> |
fd63e9ce | 21 | #include <linux/delay.h> |
b60503ba MW |
22 | #include <linux/errno.h> |
23 | #include <linux/fs.h> | |
24 | #include <linux/genhd.h> | |
4cc09e2d | 25 | #include <linux/hdreg.h> |
5aff9382 | 26 | #include <linux/idr.h> |
b60503ba MW |
27 | #include <linux/init.h> |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/io.h> | |
30 | #include <linux/kdev_t.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/mm.h> | |
33 | #include <linux/module.h> | |
34 | #include <linux/moduleparam.h> | |
77bf25ea | 35 | #include <linux/mutex.h> |
b60503ba | 36 | #include <linux/pci.h> |
be7b6275 | 37 | #include <linux/poison.h> |
c3bfe717 | 38 | #include <linux/ptrace.h> |
b60503ba MW |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
e1e5e564 | 41 | #include <linux/t10-pi.h> |
2d55cd5f | 42 | #include <linux/timer.h> |
b60503ba | 43 | #include <linux/types.h> |
2f8e2c87 | 44 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 45 | #include <asm/unaligned.h> |
a98e58e5 | 46 | #include <linux/sed-opal.h> |
797a796a | 47 | |
f11bb3e2 CH |
48 | #include "nvme.h" |
49 | ||
9d43cf64 | 50 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 51 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
52 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
53 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
c965809c | 54 | |
adf68f21 CH |
55 | /* |
56 | * We handle AEN commands ourselves and don't even let the | |
57 | * block layer know about them. | |
58 | */ | |
f866fc42 | 59 | #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS) |
9d43cf64 | 60 | |
58ffacb5 MW |
61 | static int use_threaded_interrupts; |
62 | module_param(use_threaded_interrupts, int, 0); | |
63 | ||
8ffaadf7 JD |
64 | static bool use_cmb_sqes = true; |
65 | module_param(use_cmb_sqes, bool, 0644); | |
66 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
67 | ||
9a6b9458 | 68 | static struct workqueue_struct *nvme_workq; |
1fa6aead | 69 | |
1c63dc66 CH |
70 | struct nvme_dev; |
71 | struct nvme_queue; | |
b3fffdef | 72 | |
4cc06521 | 73 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 74 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
a5cdb68c | 75 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
d4b4ff8e | 76 | |
1c63dc66 CH |
77 | /* |
78 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
79 | */ | |
80 | struct nvme_dev { | |
1c63dc66 CH |
81 | struct nvme_queue **queues; |
82 | struct blk_mq_tag_set tagset; | |
83 | struct blk_mq_tag_set admin_tagset; | |
84 | u32 __iomem *dbs; | |
85 | struct device *dev; | |
86 | struct dma_pool *prp_page_pool; | |
87 | struct dma_pool *prp_small_pool; | |
88 | unsigned queue_count; | |
89 | unsigned online_queues; | |
90 | unsigned max_qid; | |
91 | int q_depth; | |
92 | u32 db_stride; | |
1c63dc66 | 93 | void __iomem *bar; |
1c63dc66 | 94 | struct work_struct reset_work; |
5c8809e6 | 95 | struct work_struct remove_work; |
2d55cd5f | 96 | struct timer_list watchdog_timer; |
77bf25ea | 97 | struct mutex shutdown_lock; |
1c63dc66 | 98 | bool subsystem; |
1c63dc66 CH |
99 | void __iomem *cmb; |
100 | dma_addr_t cmb_dma_addr; | |
101 | u64 cmb_size; | |
102 | u32 cmbsz; | |
202021c1 | 103 | u32 cmbloc; |
1c63dc66 | 104 | struct nvme_ctrl ctrl; |
db3cbfff | 105 | struct completion ioq_wait; |
f9f38e33 HK |
106 | u32 *dbbuf_dbs; |
107 | dma_addr_t dbbuf_dbs_dma_addr; | |
108 | u32 *dbbuf_eis; | |
109 | dma_addr_t dbbuf_eis_dma_addr; | |
4d115420 | 110 | }; |
1fa6aead | 111 | |
f9f38e33 HK |
112 | static inline unsigned int sq_idx(unsigned int qid, u32 stride) |
113 | { | |
114 | return qid * 2 * stride; | |
115 | } | |
116 | ||
117 | static inline unsigned int cq_idx(unsigned int qid, u32 stride) | |
118 | { | |
119 | return (qid * 2 + 1) * stride; | |
120 | } | |
121 | ||
1c63dc66 CH |
122 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
123 | { | |
124 | return container_of(ctrl, struct nvme_dev, ctrl); | |
125 | } | |
126 | ||
b60503ba MW |
127 | /* |
128 | * An NVM Express queue. Each device has at least two (one for admin | |
129 | * commands and one for I/O commands). | |
130 | */ | |
131 | struct nvme_queue { | |
132 | struct device *q_dmadev; | |
091b6092 | 133 | struct nvme_dev *dev; |
3193f07b | 134 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
135 | spinlock_t q_lock; |
136 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 137 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 138 | volatile struct nvme_completion *cqes; |
42483228 | 139 | struct blk_mq_tags **tags; |
b60503ba MW |
140 | dma_addr_t sq_dma_addr; |
141 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
142 | u32 __iomem *q_db; |
143 | u16 q_depth; | |
6222d172 | 144 | s16 cq_vector; |
b60503ba MW |
145 | u16 sq_tail; |
146 | u16 cq_head; | |
c30341dc | 147 | u16 qid; |
e9539f47 MW |
148 | u8 cq_phase; |
149 | u8 cqe_seen; | |
f9f38e33 HK |
150 | u32 *dbbuf_sq_db; |
151 | u32 *dbbuf_cq_db; | |
152 | u32 *dbbuf_sq_ei; | |
153 | u32 *dbbuf_cq_ei; | |
b60503ba MW |
154 | }; |
155 | ||
71bd150c CH |
156 | /* |
157 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
158 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 159 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
160 | * allocated to store the PRP list. |
161 | */ | |
162 | struct nvme_iod { | |
d49187e9 | 163 | struct nvme_request req; |
f4800d6d CH |
164 | struct nvme_queue *nvmeq; |
165 | int aborted; | |
71bd150c | 166 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
167 | int nents; /* Used in scatterlist */ |
168 | int length; /* Of data, in bytes */ | |
169 | dma_addr_t first_dma; | |
bf684057 | 170 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
171 | struct scatterlist *sg; |
172 | struct scatterlist inline_sg[0]; | |
b60503ba MW |
173 | }; |
174 | ||
175 | /* | |
176 | * Check we didin't inadvertently grow the command struct | |
177 | */ | |
178 | static inline void _nvme_check_size(void) | |
179 | { | |
180 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
181 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
182 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
183 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
184 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 185 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 186 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
187 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
188 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
189 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
190 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 191 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
f9f38e33 HK |
192 | BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); |
193 | } | |
194 | ||
195 | static inline unsigned int nvme_dbbuf_size(u32 stride) | |
196 | { | |
197 | return ((num_possible_cpus() + 1) * 8 * stride); | |
198 | } | |
199 | ||
200 | static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) | |
201 | { | |
202 | unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); | |
203 | ||
204 | if (dev->dbbuf_dbs) | |
205 | return 0; | |
206 | ||
207 | dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, | |
208 | &dev->dbbuf_dbs_dma_addr, | |
209 | GFP_KERNEL); | |
210 | if (!dev->dbbuf_dbs) | |
211 | return -ENOMEM; | |
212 | dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, | |
213 | &dev->dbbuf_eis_dma_addr, | |
214 | GFP_KERNEL); | |
215 | if (!dev->dbbuf_eis) { | |
216 | dma_free_coherent(dev->dev, mem_size, | |
217 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
218 | dev->dbbuf_dbs = NULL; | |
219 | return -ENOMEM; | |
220 | } | |
221 | ||
222 | return 0; | |
223 | } | |
224 | ||
225 | static void nvme_dbbuf_dma_free(struct nvme_dev *dev) | |
226 | { | |
227 | unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); | |
228 | ||
229 | if (dev->dbbuf_dbs) { | |
230 | dma_free_coherent(dev->dev, mem_size, | |
231 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
232 | dev->dbbuf_dbs = NULL; | |
233 | } | |
234 | if (dev->dbbuf_eis) { | |
235 | dma_free_coherent(dev->dev, mem_size, | |
236 | dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); | |
237 | dev->dbbuf_eis = NULL; | |
238 | } | |
239 | } | |
240 | ||
241 | static void nvme_dbbuf_init(struct nvme_dev *dev, | |
242 | struct nvme_queue *nvmeq, int qid) | |
243 | { | |
244 | if (!dev->dbbuf_dbs || !qid) | |
245 | return; | |
246 | ||
247 | nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; | |
248 | nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; | |
249 | nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; | |
250 | nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; | |
251 | } | |
252 | ||
253 | static void nvme_dbbuf_set(struct nvme_dev *dev) | |
254 | { | |
255 | struct nvme_command c; | |
256 | ||
257 | if (!dev->dbbuf_dbs) | |
258 | return; | |
259 | ||
260 | memset(&c, 0, sizeof(c)); | |
261 | c.dbbuf.opcode = nvme_admin_dbbuf; | |
262 | c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); | |
263 | c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); | |
264 | ||
265 | if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { | |
266 | dev_warn(dev->dev, "unable to set dbbuf\n"); | |
267 | /* Free memory and continue on */ | |
268 | nvme_dbbuf_dma_free(dev); | |
269 | } | |
270 | } | |
271 | ||
272 | static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) | |
273 | { | |
274 | return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); | |
275 | } | |
276 | ||
277 | /* Update dbbuf and return true if an MMIO is required */ | |
278 | static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, | |
279 | volatile u32 *dbbuf_ei) | |
280 | { | |
281 | if (dbbuf_db) { | |
282 | u16 old_value; | |
283 | ||
284 | /* | |
285 | * Ensure that the queue is written before updating | |
286 | * the doorbell in memory | |
287 | */ | |
288 | wmb(); | |
289 | ||
290 | old_value = *dbbuf_db; | |
291 | *dbbuf_db = value; | |
292 | ||
293 | if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) | |
294 | return false; | |
295 | } | |
296 | ||
297 | return true; | |
b60503ba MW |
298 | } |
299 | ||
ac3dd5bd JA |
300 | /* |
301 | * Max size of iod being embedded in the request payload | |
302 | */ | |
303 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 304 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
305 | |
306 | /* | |
307 | * Will slightly overestimate the number of pages needed. This is OK | |
308 | * as it only leads to a small amount of wasted memory for the lifetime of | |
309 | * the I/O. | |
310 | */ | |
311 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
312 | { | |
5fd4ce1b CH |
313 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
314 | dev->ctrl.page_size); | |
ac3dd5bd JA |
315 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
316 | } | |
317 | ||
f4800d6d CH |
318 | static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, |
319 | unsigned int size, unsigned int nseg) | |
ac3dd5bd | 320 | { |
f4800d6d CH |
321 | return sizeof(__le64 *) * nvme_npages(size, dev) + |
322 | sizeof(struct scatterlist) * nseg; | |
323 | } | |
ac3dd5bd | 324 | |
f4800d6d CH |
325 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) |
326 | { | |
327 | return sizeof(struct nvme_iod) + | |
328 | nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); | |
ac3dd5bd JA |
329 | } |
330 | ||
dca51e78 CH |
331 | static int nvmeq_irq(struct nvme_queue *nvmeq) |
332 | { | |
333 | return pci_irq_vector(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector); | |
334 | } | |
335 | ||
a4aea562 MB |
336 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
337 | unsigned int hctx_idx) | |
e85248e5 | 338 | { |
a4aea562 MB |
339 | struct nvme_dev *dev = data; |
340 | struct nvme_queue *nvmeq = dev->queues[0]; | |
341 | ||
42483228 KB |
342 | WARN_ON(hctx_idx != 0); |
343 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
344 | WARN_ON(nvmeq->tags); | |
345 | ||
a4aea562 | 346 | hctx->driver_data = nvmeq; |
42483228 | 347 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 348 | return 0; |
e85248e5 MW |
349 | } |
350 | ||
4af0e21c KB |
351 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
352 | { | |
353 | struct nvme_queue *nvmeq = hctx->driver_data; | |
354 | ||
355 | nvmeq->tags = NULL; | |
356 | } | |
357 | ||
a4aea562 MB |
358 | static int nvme_admin_init_request(void *data, struct request *req, |
359 | unsigned int hctx_idx, unsigned int rq_idx, | |
360 | unsigned int numa_node) | |
22404274 | 361 | { |
a4aea562 | 362 | struct nvme_dev *dev = data; |
f4800d6d | 363 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
364 | struct nvme_queue *nvmeq = dev->queues[0]; |
365 | ||
366 | BUG_ON(!nvmeq); | |
f4800d6d | 367 | iod->nvmeq = nvmeq; |
a4aea562 | 368 | return 0; |
22404274 KB |
369 | } |
370 | ||
a4aea562 MB |
371 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
372 | unsigned int hctx_idx) | |
b60503ba | 373 | { |
a4aea562 | 374 | struct nvme_dev *dev = data; |
42483228 | 375 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 376 | |
42483228 KB |
377 | if (!nvmeq->tags) |
378 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 379 | |
42483228 | 380 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
381 | hctx->driver_data = nvmeq; |
382 | return 0; | |
b60503ba MW |
383 | } |
384 | ||
a4aea562 MB |
385 | static int nvme_init_request(void *data, struct request *req, |
386 | unsigned int hctx_idx, unsigned int rq_idx, | |
387 | unsigned int numa_node) | |
b60503ba | 388 | { |
a4aea562 | 389 | struct nvme_dev *dev = data; |
f4800d6d | 390 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
391 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
392 | ||
393 | BUG_ON(!nvmeq); | |
f4800d6d | 394 | iod->nvmeq = nvmeq; |
a4aea562 MB |
395 | return 0; |
396 | } | |
397 | ||
dca51e78 CH |
398 | static int nvme_pci_map_queues(struct blk_mq_tag_set *set) |
399 | { | |
400 | struct nvme_dev *dev = set->driver_data; | |
401 | ||
402 | return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev)); | |
403 | } | |
404 | ||
b60503ba | 405 | /** |
adf68f21 | 406 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
407 | * @nvmeq: The queue to use |
408 | * @cmd: The command to send | |
409 | * | |
410 | * Safe to use from interrupt context | |
411 | */ | |
e3f879bf SB |
412 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
413 | struct nvme_command *cmd) | |
b60503ba | 414 | { |
a4aea562 MB |
415 | u16 tail = nvmeq->sq_tail; |
416 | ||
8ffaadf7 JD |
417 | if (nvmeq->sq_cmds_io) |
418 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
419 | else | |
420 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
421 | ||
b60503ba MW |
422 | if (++tail == nvmeq->q_depth) |
423 | tail = 0; | |
f9f38e33 HK |
424 | if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db, |
425 | nvmeq->dbbuf_sq_ei)) | |
426 | writel(tail, nvmeq->q_db); | |
b60503ba | 427 | nvmeq->sq_tail = tail; |
b60503ba MW |
428 | } |
429 | ||
f4800d6d | 430 | static __le64 **iod_list(struct request *req) |
b60503ba | 431 | { |
f4800d6d | 432 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
f9d03f96 | 433 | return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req)); |
b60503ba MW |
434 | } |
435 | ||
b131c61d | 436 | static int nvme_init_iod(struct request *rq, struct nvme_dev *dev) |
ac3dd5bd | 437 | { |
f4800d6d | 438 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
f9d03f96 | 439 | int nseg = blk_rq_nr_phys_segments(rq); |
b131c61d | 440 | unsigned int size = blk_rq_payload_bytes(rq); |
ac3dd5bd | 441 | |
f4800d6d CH |
442 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
443 | iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); | |
444 | if (!iod->sg) | |
445 | return BLK_MQ_RQ_QUEUE_BUSY; | |
446 | } else { | |
447 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
448 | } |
449 | ||
f4800d6d CH |
450 | iod->aborted = 0; |
451 | iod->npages = -1; | |
452 | iod->nents = 0; | |
453 | iod->length = size; | |
f80ec966 | 454 | |
bac0000a | 455 | return BLK_MQ_RQ_QUEUE_OK; |
ac3dd5bd JA |
456 | } |
457 | ||
f4800d6d | 458 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 459 | { |
f4800d6d | 460 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
5fd4ce1b | 461 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 | 462 | int i; |
f4800d6d | 463 | __le64 **list = iod_list(req); |
eca18b23 MW |
464 | dma_addr_t prp_dma = iod->first_dma; |
465 | ||
466 | if (iod->npages == 0) | |
467 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
468 | for (i = 0; i < iod->npages; i++) { | |
469 | __le64 *prp_list = list[i]; | |
470 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
471 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
472 | prp_dma = next_prp_dma; | |
473 | } | |
ac3dd5bd | 474 | |
f4800d6d CH |
475 | if (iod->sg != iod->inline_sg) |
476 | kfree(iod->sg); | |
b4ff9c8d KB |
477 | } |
478 | ||
52b68d7e | 479 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
480 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
481 | { | |
482 | if (be32_to_cpu(pi->ref_tag) == v) | |
483 | pi->ref_tag = cpu_to_be32(p); | |
484 | } | |
485 | ||
486 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
487 | { | |
488 | if (be32_to_cpu(pi->ref_tag) == p) | |
489 | pi->ref_tag = cpu_to_be32(v); | |
490 | } | |
491 | ||
492 | /** | |
493 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
494 | * | |
495 | * The virtual start sector is the one that was originally submitted by the | |
496 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
497 | * start sector may be different. Remap protection information to match the | |
498 | * physical LBA on writes, and back to the original seed on reads. | |
499 | * | |
500 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
501 | */ | |
502 | static void nvme_dif_remap(struct request *req, | |
503 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
504 | { | |
505 | struct nvme_ns *ns = req->rq_disk->private_data; | |
506 | struct bio_integrity_payload *bip; | |
507 | struct t10_pi_tuple *pi; | |
508 | void *p, *pmap; | |
509 | u32 i, nlb, ts, phys, virt; | |
510 | ||
511 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
512 | return; | |
513 | ||
514 | bip = bio_integrity(req->bio); | |
515 | if (!bip) | |
516 | return; | |
517 | ||
518 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
519 | |
520 | p = pmap; | |
521 | virt = bip_get_seed(bip); | |
522 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
523 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 524 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
525 | |
526 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
527 | pi = (struct t10_pi_tuple *)p; | |
528 | dif_swap(phys, virt, pi); | |
529 | p += ts; | |
530 | } | |
531 | kunmap_atomic(pmap); | |
532 | } | |
52b68d7e KB |
533 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
534 | static void nvme_dif_remap(struct request *req, | |
535 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
536 | { | |
537 | } | |
538 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
539 | { | |
540 | } | |
541 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
542 | { | |
543 | } | |
52b68d7e KB |
544 | #endif |
545 | ||
b131c61d | 546 | static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req) |
ff22b54f | 547 | { |
f4800d6d | 548 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 549 | struct dma_pool *pool; |
b131c61d | 550 | int length = blk_rq_payload_bytes(req); |
eca18b23 | 551 | struct scatterlist *sg = iod->sg; |
ff22b54f MW |
552 | int dma_len = sg_dma_len(sg); |
553 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 554 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 555 | int offset = dma_addr & (page_size - 1); |
e025344c | 556 | __le64 *prp_list; |
f4800d6d | 557 | __le64 **list = iod_list(req); |
e025344c | 558 | dma_addr_t prp_dma; |
eca18b23 | 559 | int nprps, i; |
ff22b54f | 560 | |
1d090624 | 561 | length -= (page_size - offset); |
ff22b54f | 562 | if (length <= 0) |
69d2b571 | 563 | return true; |
ff22b54f | 564 | |
1d090624 | 565 | dma_len -= (page_size - offset); |
ff22b54f | 566 | if (dma_len) { |
1d090624 | 567 | dma_addr += (page_size - offset); |
ff22b54f MW |
568 | } else { |
569 | sg = sg_next(sg); | |
570 | dma_addr = sg_dma_address(sg); | |
571 | dma_len = sg_dma_len(sg); | |
572 | } | |
573 | ||
1d090624 | 574 | if (length <= page_size) { |
edd10d33 | 575 | iod->first_dma = dma_addr; |
69d2b571 | 576 | return true; |
e025344c SMM |
577 | } |
578 | ||
1d090624 | 579 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
580 | if (nprps <= (256 / 8)) { |
581 | pool = dev->prp_small_pool; | |
eca18b23 | 582 | iod->npages = 0; |
99802a7a MW |
583 | } else { |
584 | pool = dev->prp_page_pool; | |
eca18b23 | 585 | iod->npages = 1; |
99802a7a MW |
586 | } |
587 | ||
69d2b571 | 588 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 589 | if (!prp_list) { |
edd10d33 | 590 | iod->first_dma = dma_addr; |
eca18b23 | 591 | iod->npages = -1; |
69d2b571 | 592 | return false; |
b77954cb | 593 | } |
eca18b23 MW |
594 | list[0] = prp_list; |
595 | iod->first_dma = prp_dma; | |
e025344c SMM |
596 | i = 0; |
597 | for (;;) { | |
1d090624 | 598 | if (i == page_size >> 3) { |
e025344c | 599 | __le64 *old_prp_list = prp_list; |
69d2b571 | 600 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 601 | if (!prp_list) |
69d2b571 | 602 | return false; |
eca18b23 | 603 | list[iod->npages++] = prp_list; |
7523d834 MW |
604 | prp_list[0] = old_prp_list[i - 1]; |
605 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
606 | i = 1; | |
e025344c SMM |
607 | } |
608 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
609 | dma_len -= page_size; |
610 | dma_addr += page_size; | |
611 | length -= page_size; | |
e025344c SMM |
612 | if (length <= 0) |
613 | break; | |
614 | if (dma_len > 0) | |
615 | continue; | |
616 | BUG_ON(dma_len < 0); | |
617 | sg = sg_next(sg); | |
618 | dma_addr = sg_dma_address(sg); | |
619 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
620 | } |
621 | ||
69d2b571 | 622 | return true; |
ff22b54f MW |
623 | } |
624 | ||
f4800d6d | 625 | static int nvme_map_data(struct nvme_dev *dev, struct request *req, |
b131c61d | 626 | struct nvme_command *cmnd) |
d29ec824 | 627 | { |
f4800d6d | 628 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
629 | struct request_queue *q = req->q; |
630 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
631 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
632 | int ret = BLK_MQ_RQ_QUEUE_ERROR; | |
d29ec824 | 633 | |
f9d03f96 | 634 | sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); |
ba1ca37e CH |
635 | iod->nents = blk_rq_map_sg(q, req, iod->sg); |
636 | if (!iod->nents) | |
637 | goto out; | |
d29ec824 | 638 | |
ba1ca37e | 639 | ret = BLK_MQ_RQ_QUEUE_BUSY; |
2b6b535d MFO |
640 | if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, |
641 | DMA_ATTR_NO_WARN)) | |
ba1ca37e | 642 | goto out; |
d29ec824 | 643 | |
b131c61d | 644 | if (!nvme_setup_prps(dev, req)) |
ba1ca37e | 645 | goto out_unmap; |
0e5e4f0e | 646 | |
ba1ca37e CH |
647 | ret = BLK_MQ_RQ_QUEUE_ERROR; |
648 | if (blk_integrity_rq(req)) { | |
649 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
650 | goto out_unmap; | |
0e5e4f0e | 651 | |
bf684057 CH |
652 | sg_init_table(&iod->meta_sg, 1); |
653 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 654 | goto out_unmap; |
0e5e4f0e | 655 | |
ba1ca37e CH |
656 | if (rq_data_dir(req)) |
657 | nvme_dif_remap(req, nvme_dif_prep); | |
0e5e4f0e | 658 | |
bf684057 | 659 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 660 | goto out_unmap; |
d29ec824 | 661 | } |
00df5cb4 | 662 | |
eb793e2c CH |
663 | cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
664 | cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma); | |
ba1ca37e | 665 | if (blk_integrity_rq(req)) |
bf684057 | 666 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
ba1ca37e | 667 | return BLK_MQ_RQ_QUEUE_OK; |
00df5cb4 | 668 | |
ba1ca37e CH |
669 | out_unmap: |
670 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
671 | out: | |
672 | return ret; | |
00df5cb4 MW |
673 | } |
674 | ||
f4800d6d | 675 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
b60503ba | 676 | { |
f4800d6d | 677 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
678 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
679 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
680 | ||
681 | if (iod->nents) { | |
682 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
683 | if (blk_integrity_rq(req)) { | |
684 | if (!rq_data_dir(req)) | |
685 | nvme_dif_remap(req, nvme_dif_complete); | |
bf684057 | 686 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
e1e5e564 | 687 | } |
e19b127f | 688 | } |
e1e5e564 | 689 | |
f9d03f96 | 690 | nvme_cleanup_cmd(req); |
f4800d6d | 691 | nvme_free_iod(dev, req); |
d4f6c3ab | 692 | } |
b60503ba | 693 | |
d29ec824 CH |
694 | /* |
695 | * NOTE: ns is NULL when called on the admin queue. | |
696 | */ | |
a4aea562 MB |
697 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
698 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 699 | { |
a4aea562 MB |
700 | struct nvme_ns *ns = hctx->queue->queuedata; |
701 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 702 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 703 | struct request *req = bd->rq; |
ba1ca37e CH |
704 | struct nvme_command cmnd; |
705 | int ret = BLK_MQ_RQ_QUEUE_OK; | |
edd10d33 | 706 | |
e1e5e564 KB |
707 | /* |
708 | * If formated with metadata, require the block layer provide a buffer | |
709 | * unless this namespace is formated such that the metadata can be | |
710 | * stripped/generated by the controller with PRACT=1. | |
711 | */ | |
d29ec824 | 712 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 | 713 | if (!(ns->pi_type && ns->ms == 8) && |
57292b58 | 714 | !blk_rq_is_passthrough(req)) { |
eee417b0 | 715 | blk_mq_end_request(req, -EFAULT); |
e1e5e564 KB |
716 | return BLK_MQ_RQ_QUEUE_OK; |
717 | } | |
718 | } | |
719 | ||
f9d03f96 | 720 | ret = nvme_setup_cmd(ns, req, &cmnd); |
bac0000a | 721 | if (ret != BLK_MQ_RQ_QUEUE_OK) |
f4800d6d | 722 | return ret; |
a4aea562 | 723 | |
b131c61d | 724 | ret = nvme_init_iod(req, dev); |
bac0000a | 725 | if (ret != BLK_MQ_RQ_QUEUE_OK) |
f9d03f96 | 726 | goto out_free_cmd; |
a4aea562 | 727 | |
f9d03f96 | 728 | if (blk_rq_nr_phys_segments(req)) |
b131c61d | 729 | ret = nvme_map_data(dev, req, &cmnd); |
a4aea562 | 730 | |
bac0000a | 731 | if (ret != BLK_MQ_RQ_QUEUE_OK) |
f9d03f96 | 732 | goto out_cleanup_iod; |
a4aea562 | 733 | |
aae239e1 | 734 | blk_mq_start_request(req); |
a4aea562 | 735 | |
ba1ca37e | 736 | spin_lock_irq(&nvmeq->q_lock); |
ae1fba20 | 737 | if (unlikely(nvmeq->cq_vector < 0)) { |
9ef3932e | 738 | ret = BLK_MQ_RQ_QUEUE_ERROR; |
ae1fba20 | 739 | spin_unlock_irq(&nvmeq->q_lock); |
f9d03f96 | 740 | goto out_cleanup_iod; |
ae1fba20 | 741 | } |
ba1ca37e | 742 | __nvme_submit_cmd(nvmeq, &cmnd); |
a4aea562 MB |
743 | nvme_process_cq(nvmeq); |
744 | spin_unlock_irq(&nvmeq->q_lock); | |
745 | return BLK_MQ_RQ_QUEUE_OK; | |
f9d03f96 | 746 | out_cleanup_iod: |
f4800d6d | 747 | nvme_free_iod(dev, req); |
f9d03f96 CH |
748 | out_free_cmd: |
749 | nvme_cleanup_cmd(req); | |
ba1ca37e | 750 | return ret; |
b60503ba | 751 | } |
e1e5e564 | 752 | |
77f02a7a | 753 | static void nvme_pci_complete_rq(struct request *req) |
eee417b0 | 754 | { |
f4800d6d | 755 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
e1e5e564 | 756 | |
77f02a7a CH |
757 | nvme_unmap_data(iod->nvmeq->dev, req); |
758 | nvme_complete_rq(req); | |
b60503ba MW |
759 | } |
760 | ||
d783e0bd MR |
761 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
762 | static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, | |
763 | u16 phase) | |
764 | { | |
765 | return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; | |
766 | } | |
767 | ||
a0fa9647 | 768 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 769 | { |
82123460 | 770 | u16 head, phase; |
b60503ba | 771 | |
b60503ba | 772 | head = nvmeq->cq_head; |
82123460 | 773 | phase = nvmeq->cq_phase; |
b60503ba | 774 | |
d783e0bd | 775 | while (nvme_cqe_valid(nvmeq, head, phase)) { |
b60503ba | 776 | struct nvme_completion cqe = nvmeq->cqes[head]; |
eee417b0 | 777 | struct request *req; |
adf68f21 | 778 | |
b60503ba MW |
779 | if (++head == nvmeq->q_depth) { |
780 | head = 0; | |
82123460 | 781 | phase = !phase; |
b60503ba | 782 | } |
adf68f21 | 783 | |
a0fa9647 JA |
784 | if (tag && *tag == cqe.command_id) |
785 | *tag = -1; | |
adf68f21 | 786 | |
aae239e1 | 787 | if (unlikely(cqe.command_id >= nvmeq->q_depth)) { |
1b3c47c1 | 788 | dev_warn(nvmeq->dev->ctrl.device, |
aae239e1 CH |
789 | "invalid id %d completed on queue %d\n", |
790 | cqe.command_id, le16_to_cpu(cqe.sq_id)); | |
791 | continue; | |
792 | } | |
793 | ||
adf68f21 CH |
794 | /* |
795 | * AEN requests are special as they don't time out and can | |
796 | * survive any kind of queue freeze and often don't respond to | |
797 | * aborts. We don't even bother to allocate a struct request | |
798 | * for them but rather special case them here. | |
799 | */ | |
800 | if (unlikely(nvmeq->qid == 0 && | |
801 | cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { | |
7bf58533 CH |
802 | nvme_complete_async_event(&nvmeq->dev->ctrl, |
803 | cqe.status, &cqe.result); | |
adf68f21 CH |
804 | continue; |
805 | } | |
806 | ||
eee417b0 | 807 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); |
27fa9bc5 | 808 | nvme_end_request(req, cqe.status, cqe.result); |
b60503ba MW |
809 | } |
810 | ||
82123460 | 811 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 812 | return; |
b60503ba | 813 | |
604e8c8d | 814 | if (likely(nvmeq->cq_vector >= 0)) |
f9f38e33 HK |
815 | if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, |
816 | nvmeq->dbbuf_cq_ei)) | |
817 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 818 | nvmeq->cq_head = head; |
82123460 | 819 | nvmeq->cq_phase = phase; |
b60503ba | 820 | |
e9539f47 | 821 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
822 | } |
823 | ||
824 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
825 | { | |
826 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
827 | } |
828 | ||
829 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
830 | { |
831 | irqreturn_t result; | |
832 | struct nvme_queue *nvmeq = data; | |
833 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
834 | nvme_process_cq(nvmeq); |
835 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
836 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
837 | spin_unlock(&nvmeq->q_lock); |
838 | return result; | |
839 | } | |
840 | ||
841 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
842 | { | |
843 | struct nvme_queue *nvmeq = data; | |
d783e0bd MR |
844 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) |
845 | return IRQ_WAKE_THREAD; | |
846 | return IRQ_NONE; | |
58ffacb5 MW |
847 | } |
848 | ||
a0fa9647 JA |
849 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
850 | { | |
851 | struct nvme_queue *nvmeq = hctx->driver_data; | |
852 | ||
d783e0bd | 853 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { |
a0fa9647 JA |
854 | spin_lock_irq(&nvmeq->q_lock); |
855 | __nvme_process_cq(nvmeq, &tag); | |
856 | spin_unlock_irq(&nvmeq->q_lock); | |
857 | ||
858 | if (tag == -1) | |
859 | return 1; | |
860 | } | |
861 | ||
862 | return 0; | |
863 | } | |
864 | ||
f866fc42 | 865 | static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx) |
b60503ba | 866 | { |
f866fc42 | 867 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9396dec9 | 868 | struct nvme_queue *nvmeq = dev->queues[0]; |
a4aea562 | 869 | struct nvme_command c; |
b60503ba | 870 | |
a4aea562 MB |
871 | memset(&c, 0, sizeof(c)); |
872 | c.common.opcode = nvme_admin_async_event; | |
f866fc42 | 873 | c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx; |
3c0cf138 | 874 | |
9396dec9 | 875 | spin_lock_irq(&nvmeq->q_lock); |
f866fc42 | 876 | __nvme_submit_cmd(nvmeq, &c); |
9396dec9 | 877 | spin_unlock_irq(&nvmeq->q_lock); |
f705f837 CH |
878 | } |
879 | ||
b60503ba | 880 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 881 | { |
b60503ba MW |
882 | struct nvme_command c; |
883 | ||
884 | memset(&c, 0, sizeof(c)); | |
885 | c.delete_queue.opcode = opcode; | |
886 | c.delete_queue.qid = cpu_to_le16(id); | |
887 | ||
1c63dc66 | 888 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
889 | } |
890 | ||
b60503ba MW |
891 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
892 | struct nvme_queue *nvmeq) | |
893 | { | |
b60503ba MW |
894 | struct nvme_command c; |
895 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
896 | ||
d29ec824 CH |
897 | /* |
898 | * Note: we (ab)use the fact the the prp fields survive if no data | |
899 | * is attached to the request. | |
900 | */ | |
b60503ba MW |
901 | memset(&c, 0, sizeof(c)); |
902 | c.create_cq.opcode = nvme_admin_create_cq; | |
903 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
904 | c.create_cq.cqid = cpu_to_le16(qid); | |
905 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
906 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
907 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
908 | ||
1c63dc66 | 909 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
910 | } |
911 | ||
912 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
913 | struct nvme_queue *nvmeq) | |
914 | { | |
b60503ba | 915 | struct nvme_command c; |
81c1cd98 | 916 | int flags = NVME_QUEUE_PHYS_CONTIG; |
b60503ba | 917 | |
d29ec824 CH |
918 | /* |
919 | * Note: we (ab)use the fact the the prp fields survive if no data | |
920 | * is attached to the request. | |
921 | */ | |
b60503ba MW |
922 | memset(&c, 0, sizeof(c)); |
923 | c.create_sq.opcode = nvme_admin_create_sq; | |
924 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
925 | c.create_sq.sqid = cpu_to_le16(qid); | |
926 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
927 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
928 | c.create_sq.cqid = cpu_to_le16(qid); | |
929 | ||
1c63dc66 | 930 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
931 | } |
932 | ||
933 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
934 | { | |
935 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
936 | } | |
937 | ||
938 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
939 | { | |
940 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
941 | } | |
942 | ||
e7a2a87d | 943 | static void abort_endio(struct request *req, int error) |
bc5fc7e4 | 944 | { |
f4800d6d CH |
945 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
946 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e44ac588 | 947 | |
27fa9bc5 CH |
948 | dev_warn(nvmeq->dev->ctrl.device, |
949 | "Abort status: 0x%x", nvme_req(req)->status); | |
e7a2a87d | 950 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
e7a2a87d | 951 | blk_mq_free_request(req); |
bc5fc7e4 MW |
952 | } |
953 | ||
31c7c7d2 | 954 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 955 | { |
f4800d6d CH |
956 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
957 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 958 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 959 | struct request *abort_req; |
a4aea562 | 960 | struct nvme_command cmd; |
c30341dc | 961 | |
31c7c7d2 | 962 | /* |
fd634f41 CH |
963 | * Shutdown immediately if controller times out while starting. The |
964 | * reset work will see the pci device disabled when it gets the forced | |
965 | * cancellation error. All outstanding requests are completed on | |
966 | * shutdown, so we return BLK_EH_HANDLED. | |
967 | */ | |
bb8d261e | 968 | if (dev->ctrl.state == NVME_CTRL_RESETTING) { |
1b3c47c1 | 969 | dev_warn(dev->ctrl.device, |
fd634f41 CH |
970 | "I/O %d QID %d timeout, disable controller\n", |
971 | req->tag, nvmeq->qid); | |
a5cdb68c | 972 | nvme_dev_disable(dev, false); |
27fa9bc5 | 973 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
fd634f41 | 974 | return BLK_EH_HANDLED; |
c30341dc KB |
975 | } |
976 | ||
fd634f41 CH |
977 | /* |
978 | * Shutdown the controller immediately and schedule a reset if the | |
979 | * command was already aborted once before and still hasn't been | |
980 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 981 | */ |
f4800d6d | 982 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 983 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
984 | "I/O %d QID %d timeout, reset controller\n", |
985 | req->tag, nvmeq->qid); | |
a5cdb68c | 986 | nvme_dev_disable(dev, false); |
c5f6ce97 | 987 | nvme_reset(dev); |
c30341dc | 988 | |
e1569a16 KB |
989 | /* |
990 | * Mark the request as handled, since the inline shutdown | |
991 | * forces all outstanding requests to complete. | |
992 | */ | |
27fa9bc5 | 993 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
e1569a16 | 994 | return BLK_EH_HANDLED; |
c30341dc | 995 | } |
c30341dc | 996 | |
e7a2a87d | 997 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 998 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 999 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 1000 | } |
7bf7d778 | 1001 | iod->aborted = 1; |
a4aea562 | 1002 | |
c30341dc KB |
1003 | memset(&cmd, 0, sizeof(cmd)); |
1004 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 1005 | cmd.abort.cid = req->tag; |
c30341dc | 1006 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 1007 | |
1b3c47c1 SG |
1008 | dev_warn(nvmeq->dev->ctrl.device, |
1009 | "I/O %d QID %d timeout, aborting\n", | |
1010 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
1011 | |
1012 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
eb71f435 | 1013 | BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
e7a2a87d CH |
1014 | if (IS_ERR(abort_req)) { |
1015 | atomic_inc(&dev->ctrl.abort_limit); | |
1016 | return BLK_EH_RESET_TIMER; | |
1017 | } | |
1018 | ||
1019 | abort_req->timeout = ADMIN_TIMEOUT; | |
1020 | abort_req->end_io_data = NULL; | |
1021 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
c30341dc | 1022 | |
31c7c7d2 CH |
1023 | /* |
1024 | * The aborted req will be completed on receiving the abort req. | |
1025 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1026 | * as the device then is in a faulty state. | |
1027 | */ | |
1028 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
1029 | } |
1030 | ||
a4aea562 MB |
1031 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1032 | { | |
9e866774 MW |
1033 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1034 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1035 | if (nvmeq->sq_cmds) |
1036 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1037 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1038 | kfree(nvmeq); | |
1039 | } | |
1040 | ||
a1a5ef99 | 1041 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1042 | { |
1043 | int i; | |
1044 | ||
a1a5ef99 | 1045 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1046 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1047 | dev->queue_count--; |
a4aea562 | 1048 | dev->queues[i] = NULL; |
f435c282 | 1049 | nvme_free_queue(nvmeq); |
121c7ad4 | 1050 | } |
22404274 KB |
1051 | } |
1052 | ||
4d115420 KB |
1053 | /** |
1054 | * nvme_suspend_queue - put queue into suspended state | |
1055 | * @nvmeq - queue to suspend | |
4d115420 KB |
1056 | */ |
1057 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1058 | { |
2b25d981 | 1059 | int vector; |
b60503ba | 1060 | |
a09115b2 | 1061 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1062 | if (nvmeq->cq_vector == -1) { |
1063 | spin_unlock_irq(&nvmeq->q_lock); | |
1064 | return 1; | |
1065 | } | |
dca51e78 | 1066 | vector = nvmeq_irq(nvmeq); |
42f61420 | 1067 | nvmeq->dev->online_queues--; |
2b25d981 | 1068 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1069 | spin_unlock_irq(&nvmeq->q_lock); |
1070 | ||
1c63dc66 | 1071 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
25646264 | 1072 | blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q); |
6df3dbc8 | 1073 | |
aba2080f | 1074 | free_irq(vector, nvmeq); |
b60503ba | 1075 | |
4d115420 KB |
1076 | return 0; |
1077 | } | |
b60503ba | 1078 | |
a5cdb68c | 1079 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 1080 | { |
a5cdb68c | 1081 | struct nvme_queue *nvmeq = dev->queues[0]; |
4d115420 KB |
1082 | |
1083 | if (!nvmeq) | |
1084 | return; | |
1085 | if (nvme_suspend_queue(nvmeq)) | |
1086 | return; | |
1087 | ||
a5cdb68c KB |
1088 | if (shutdown) |
1089 | nvme_shutdown_ctrl(&dev->ctrl); | |
1090 | else | |
1091 | nvme_disable_ctrl(&dev->ctrl, lo_hi_readq( | |
1092 | dev->bar + NVME_REG_CAP)); | |
07836e65 KB |
1093 | |
1094 | spin_lock_irq(&nvmeq->q_lock); | |
1095 | nvme_process_cq(nvmeq); | |
1096 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1097 | } |
1098 | ||
8ffaadf7 JD |
1099 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1100 | int entry_size) | |
1101 | { | |
1102 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1103 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1104 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1105 | |
1106 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1107 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1108 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1109 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1110 | |
1111 | /* | |
1112 | * Ensure the reduced q_depth is above some threshold where it | |
1113 | * would be better to map queues in system memory with the | |
1114 | * original depth | |
1115 | */ | |
1116 | if (q_depth < 64) | |
1117 | return -ENOMEM; | |
1118 | } | |
1119 | ||
1120 | return q_depth; | |
1121 | } | |
1122 | ||
1123 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1124 | int qid, int depth) | |
1125 | { | |
1126 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1127 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1128 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1129 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1130 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1131 | } else { | |
1132 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1133 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1134 | if (!nvmeq->sq_cmds) | |
1135 | return -ENOMEM; | |
1136 | } | |
1137 | ||
1138 | return 0; | |
1139 | } | |
1140 | ||
b60503ba | 1141 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
d3af3ecd | 1142 | int depth, int node) |
b60503ba | 1143 | { |
d3af3ecd SL |
1144 | struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL, |
1145 | node); | |
b60503ba MW |
1146 | if (!nvmeq) |
1147 | return NULL; | |
1148 | ||
e75ec752 | 1149 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1150 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1151 | if (!nvmeq->cqes) |
1152 | goto free_nvmeq; | |
b60503ba | 1153 | |
8ffaadf7 | 1154 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1155 | goto free_cqdma; |
1156 | ||
e75ec752 | 1157 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1158 | nvmeq->dev = dev; |
3193f07b | 1159 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1c63dc66 | 1160 | dev->ctrl.instance, qid); |
b60503ba MW |
1161 | spin_lock_init(&nvmeq->q_lock); |
1162 | nvmeq->cq_head = 0; | |
82123460 | 1163 | nvmeq->cq_phase = 1; |
b80d5ccc | 1164 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1165 | nvmeq->q_depth = depth; |
c30341dc | 1166 | nvmeq->qid = qid; |
758dd7fd | 1167 | nvmeq->cq_vector = -1; |
a4aea562 | 1168 | dev->queues[qid] = nvmeq; |
36a7e993 JD |
1169 | dev->queue_count++; |
1170 | ||
b60503ba MW |
1171 | return nvmeq; |
1172 | ||
1173 | free_cqdma: | |
e75ec752 | 1174 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1175 | nvmeq->cq_dma_addr); |
1176 | free_nvmeq: | |
1177 | kfree(nvmeq); | |
1178 | return NULL; | |
1179 | } | |
1180 | ||
dca51e78 | 1181 | static int queue_request_irq(struct nvme_queue *nvmeq) |
3001082c | 1182 | { |
58ffacb5 | 1183 | if (use_threaded_interrupts) |
dca51e78 CH |
1184 | return request_threaded_irq(nvmeq_irq(nvmeq), nvme_irq_check, |
1185 | nvme_irq, IRQF_SHARED, nvmeq->irqname, nvmeq); | |
1186 | else | |
1187 | return request_irq(nvmeq_irq(nvmeq), nvme_irq, IRQF_SHARED, | |
1188 | nvmeq->irqname, nvmeq); | |
3001082c MW |
1189 | } |
1190 | ||
22404274 | 1191 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1192 | { |
22404274 | 1193 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1194 | |
7be50e93 | 1195 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1196 | nvmeq->sq_tail = 0; |
1197 | nvmeq->cq_head = 0; | |
1198 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1199 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1200 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
f9f38e33 | 1201 | nvme_dbbuf_init(dev, nvmeq, qid); |
42f61420 | 1202 | dev->online_queues++; |
7be50e93 | 1203 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1204 | } |
1205 | ||
1206 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1207 | { | |
1208 | struct nvme_dev *dev = nvmeq->dev; | |
1209 | int result; | |
3f85d50b | 1210 | |
2b25d981 | 1211 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1212 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1213 | if (result < 0) | |
22404274 | 1214 | return result; |
b60503ba MW |
1215 | |
1216 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1217 | if (result < 0) | |
1218 | goto release_cq; | |
1219 | ||
dca51e78 | 1220 | result = queue_request_irq(nvmeq); |
b60503ba MW |
1221 | if (result < 0) |
1222 | goto release_sq; | |
1223 | ||
22404274 | 1224 | nvme_init_queue(nvmeq, qid); |
22404274 | 1225 | return result; |
b60503ba MW |
1226 | |
1227 | release_sq: | |
1228 | adapter_delete_sq(dev, qid); | |
1229 | release_cq: | |
1230 | adapter_delete_cq(dev, qid); | |
22404274 | 1231 | return result; |
b60503ba MW |
1232 | } |
1233 | ||
f363b089 | 1234 | static const struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1235 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1236 | .complete = nvme_pci_complete_rq, |
a4aea562 | 1237 | .init_hctx = nvme_admin_init_hctx, |
4af0e21c | 1238 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1239 | .init_request = nvme_admin_init_request, |
1240 | .timeout = nvme_timeout, | |
1241 | }; | |
1242 | ||
f363b089 | 1243 | static const struct blk_mq_ops nvme_mq_ops = { |
a4aea562 | 1244 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1245 | .complete = nvme_pci_complete_rq, |
a4aea562 MB |
1246 | .init_hctx = nvme_init_hctx, |
1247 | .init_request = nvme_init_request, | |
dca51e78 | 1248 | .map_queues = nvme_pci_map_queues, |
a4aea562 | 1249 | .timeout = nvme_timeout, |
a0fa9647 | 1250 | .poll = nvme_poll, |
a4aea562 MB |
1251 | }; |
1252 | ||
ea191d2f KB |
1253 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1254 | { | |
1c63dc66 | 1255 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
69d9a99c KB |
1256 | /* |
1257 | * If the controller was reset during removal, it's possible | |
1258 | * user requests may be waiting on a stopped queue. Start the | |
1259 | * queue to flush these to completion. | |
1260 | */ | |
1261 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); | |
1c63dc66 | 1262 | blk_cleanup_queue(dev->ctrl.admin_q); |
ea191d2f KB |
1263 | blk_mq_free_tag_set(&dev->admin_tagset); |
1264 | } | |
1265 | } | |
1266 | ||
a4aea562 MB |
1267 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1268 | { | |
1c63dc66 | 1269 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1270 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1271 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c KB |
1272 | |
1273 | /* | |
1274 | * Subtract one to leave an empty queue entry for 'Full Queue' | |
1275 | * condition. See NVM-Express 1.2 specification, section 4.1.2. | |
1276 | */ | |
1277 | dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; | |
a4aea562 | 1278 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1279 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1280 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
d3484991 | 1281 | dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; |
a4aea562 MB |
1282 | dev->admin_tagset.driver_data = dev; |
1283 | ||
1284 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1285 | return -ENOMEM; | |
1286 | ||
1c63dc66 CH |
1287 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1288 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1289 | blk_mq_free_tag_set(&dev->admin_tagset); |
1290 | return -ENOMEM; | |
1291 | } | |
1c63dc66 | 1292 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1293 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1294 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1295 | return -ENODEV; |
1296 | } | |
0fb59cbc | 1297 | } else |
25646264 | 1298 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); |
a4aea562 MB |
1299 | |
1300 | return 0; | |
1301 | } | |
1302 | ||
8d85fce7 | 1303 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1304 | { |
ba47e386 | 1305 | int result; |
b60503ba | 1306 | u32 aqa; |
7a67cbea | 1307 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1308 | struct nvme_queue *nvmeq; |
1309 | ||
8ef2074d | 1310 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? |
dfbac8c7 KB |
1311 | NVME_CAP_NSSRC(cap) : 0; |
1312 | ||
7a67cbea CH |
1313 | if (dev->subsystem && |
1314 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1315 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1316 | |
5fd4ce1b | 1317 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1318 | if (result < 0) |
1319 | return result; | |
b60503ba | 1320 | |
a4aea562 | 1321 | nvmeq = dev->queues[0]; |
cd638946 | 1322 | if (!nvmeq) { |
d3af3ecd SL |
1323 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, |
1324 | dev_to_node(dev->dev)); | |
cd638946 KB |
1325 | if (!nvmeq) |
1326 | return -ENOMEM; | |
cd638946 | 1327 | } |
b60503ba MW |
1328 | |
1329 | aqa = nvmeq->q_depth - 1; | |
1330 | aqa |= aqa << 16; | |
1331 | ||
7a67cbea CH |
1332 | writel(aqa, dev->bar + NVME_REG_AQA); |
1333 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1334 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1335 | |
5fd4ce1b | 1336 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1337 | if (result) |
d4875622 | 1338 | return result; |
a4aea562 | 1339 | |
2b25d981 | 1340 | nvmeq->cq_vector = 0; |
dca51e78 | 1341 | result = queue_request_irq(nvmeq); |
758dd7fd JD |
1342 | if (result) { |
1343 | nvmeq->cq_vector = -1; | |
d4875622 | 1344 | return result; |
758dd7fd | 1345 | } |
025c557a | 1346 | |
b60503ba MW |
1347 | return result; |
1348 | } | |
1349 | ||
c875a709 GP |
1350 | static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) |
1351 | { | |
1352 | ||
1353 | /* If true, indicates loss of adapter communication, possibly by a | |
1354 | * NVMe Subsystem reset. | |
1355 | */ | |
1356 | bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); | |
1357 | ||
1358 | /* If there is a reset ongoing, we shouldn't reset again. */ | |
1359 | if (work_busy(&dev->reset_work)) | |
1360 | return false; | |
1361 | ||
1362 | /* We shouldn't reset unless the controller is on fatal error state | |
1363 | * _or_ if we lost the communication with it. | |
1364 | */ | |
1365 | if (!(csts & NVME_CSTS_CFS) && !nssro) | |
1366 | return false; | |
1367 | ||
1368 | /* If PCI error recovery process is happening, we cannot reset or | |
1369 | * the recovery mechanism will surely fail. | |
1370 | */ | |
1371 | if (pci_channel_offline(to_pci_dev(dev->dev))) | |
1372 | return false; | |
1373 | ||
1374 | return true; | |
1375 | } | |
1376 | ||
d2a61918 AL |
1377 | static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) |
1378 | { | |
1379 | /* Read a config register to help see what died. */ | |
1380 | u16 pci_status; | |
1381 | int result; | |
1382 | ||
1383 | result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, | |
1384 | &pci_status); | |
1385 | if (result == PCIBIOS_SUCCESSFUL) | |
1386 | dev_warn(dev->dev, | |
1387 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", | |
1388 | csts, pci_status); | |
1389 | else | |
1390 | dev_warn(dev->dev, | |
1391 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", | |
1392 | csts, result); | |
1393 | } | |
1394 | ||
2d55cd5f | 1395 | static void nvme_watchdog_timer(unsigned long data) |
1fa6aead | 1396 | { |
2d55cd5f CH |
1397 | struct nvme_dev *dev = (struct nvme_dev *)data; |
1398 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
1fa6aead | 1399 | |
c875a709 GP |
1400 | /* Skip controllers under certain specific conditions. */ |
1401 | if (nvme_should_reset(dev, csts)) { | |
c5f6ce97 | 1402 | if (!nvme_reset(dev)) |
d2a61918 | 1403 | nvme_warn_reset(dev, csts); |
2d55cd5f | 1404 | return; |
1fa6aead | 1405 | } |
2d55cd5f CH |
1406 | |
1407 | mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); | |
1fa6aead MW |
1408 | } |
1409 | ||
749941f2 | 1410 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1411 | { |
949928c1 | 1412 | unsigned i, max; |
749941f2 | 1413 | int ret = 0; |
42f61420 | 1414 | |
749941f2 | 1415 | for (i = dev->queue_count; i <= dev->max_qid; i++) { |
d3af3ecd SL |
1416 | /* vector == qid - 1, match nvme_create_queue */ |
1417 | if (!nvme_alloc_queue(dev, i, dev->q_depth, | |
1418 | pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) { | |
749941f2 | 1419 | ret = -ENOMEM; |
42f61420 | 1420 | break; |
749941f2 CH |
1421 | } |
1422 | } | |
42f61420 | 1423 | |
949928c1 KB |
1424 | max = min(dev->max_qid, dev->queue_count - 1); |
1425 | for (i = dev->online_queues; i <= max; i++) { | |
749941f2 | 1426 | ret = nvme_create_queue(dev->queues[i], i); |
d4875622 | 1427 | if (ret) |
42f61420 | 1428 | break; |
27e8166c | 1429 | } |
749941f2 CH |
1430 | |
1431 | /* | |
1432 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1433 | * than the desired aount of queues, and even a controller without | |
1434 | * I/O queues an still be used to issue admin commands. This might | |
1435 | * be useful to upgrade a buggy firmware for example. | |
1436 | */ | |
1437 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1438 | } |
1439 | ||
202021c1 SB |
1440 | static ssize_t nvme_cmb_show(struct device *dev, |
1441 | struct device_attribute *attr, | |
1442 | char *buf) | |
1443 | { | |
1444 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
1445 | ||
c965809c | 1446 | return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", |
202021c1 SB |
1447 | ndev->cmbloc, ndev->cmbsz); |
1448 | } | |
1449 | static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); | |
1450 | ||
8ffaadf7 JD |
1451 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1452 | { | |
1453 | u64 szu, size, offset; | |
8ffaadf7 JD |
1454 | resource_size_t bar_size; |
1455 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1456 | void __iomem *cmb; | |
1457 | dma_addr_t dma_addr; | |
1458 | ||
7a67cbea | 1459 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1460 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1461 | return NULL; | |
202021c1 | 1462 | dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 | 1463 | |
202021c1 SB |
1464 | if (!use_cmb_sqes) |
1465 | return NULL; | |
8ffaadf7 JD |
1466 | |
1467 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1468 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
202021c1 SB |
1469 | offset = szu * NVME_CMB_OFST(dev->cmbloc); |
1470 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc)); | |
8ffaadf7 JD |
1471 | |
1472 | if (offset > bar_size) | |
1473 | return NULL; | |
1474 | ||
1475 | /* | |
1476 | * Controllers may support a CMB size larger than their BAR, | |
1477 | * for example, due to being behind a bridge. Reduce the CMB to | |
1478 | * the reported size of the BAR | |
1479 | */ | |
1480 | if (size > bar_size - offset) | |
1481 | size = bar_size - offset; | |
1482 | ||
202021c1 | 1483 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset; |
8ffaadf7 JD |
1484 | cmb = ioremap_wc(dma_addr, size); |
1485 | if (!cmb) | |
1486 | return NULL; | |
1487 | ||
1488 | dev->cmb_dma_addr = dma_addr; | |
1489 | dev->cmb_size = size; | |
1490 | return cmb; | |
1491 | } | |
1492 | ||
1493 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1494 | { | |
1495 | if (dev->cmb) { | |
1496 | iounmap(dev->cmb); | |
1497 | dev->cmb = NULL; | |
1498 | } | |
1499 | } | |
1500 | ||
9d713c2b KB |
1501 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1502 | { | |
b80d5ccc | 1503 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
1504 | } |
1505 | ||
8d85fce7 | 1506 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1507 | { |
a4aea562 | 1508 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1509 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
dca51e78 | 1510 | int result, nr_io_queues, size; |
b60503ba | 1511 | |
2800b8e7 | 1512 | nr_io_queues = num_online_cpus(); |
9a0be7ab CH |
1513 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1514 | if (result < 0) | |
1b23484b | 1515 | return result; |
9a0be7ab | 1516 | |
f5fa90dc | 1517 | if (nr_io_queues == 0) |
a5229050 | 1518 | return 0; |
b60503ba | 1519 | |
8ffaadf7 JD |
1520 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1521 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1522 | sizeof(struct nvme_command)); | |
1523 | if (result > 0) | |
1524 | dev->q_depth = result; | |
1525 | else | |
1526 | nvme_release_cmb(dev); | |
1527 | } | |
1528 | ||
9d713c2b KB |
1529 | size = db_bar_size(dev, nr_io_queues); |
1530 | if (size > 8192) { | |
f1938f6e | 1531 | iounmap(dev->bar); |
9d713c2b KB |
1532 | do { |
1533 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1534 | if (dev->bar) | |
1535 | break; | |
1536 | if (!--nr_io_queues) | |
1537 | return -ENOMEM; | |
1538 | size = db_bar_size(dev, nr_io_queues); | |
1539 | } while (1); | |
7a67cbea | 1540 | dev->dbs = dev->bar + 4096; |
5a92e700 | 1541 | adminq->q_db = dev->dbs; |
f1938f6e MW |
1542 | } |
1543 | ||
9d713c2b | 1544 | /* Deregister the admin queue's interrupt */ |
dca51e78 | 1545 | free_irq(pci_irq_vector(pdev, 0), adminq); |
9d713c2b | 1546 | |
e32efbfc JA |
1547 | /* |
1548 | * If we enable msix early due to not intx, disable it again before | |
1549 | * setting up the full range we need. | |
1550 | */ | |
dca51e78 CH |
1551 | pci_free_irq_vectors(pdev); |
1552 | nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues, | |
1553 | PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY); | |
1554 | if (nr_io_queues <= 0) | |
1555 | return -EIO; | |
1556 | dev->max_qid = nr_io_queues; | |
fa08a396 | 1557 | |
063a8096 MW |
1558 | /* |
1559 | * Should investigate if there's a performance win from allocating | |
1560 | * more queues than interrupt vectors; it might allow the submission | |
1561 | * path to scale better, even if the receive path is limited by the | |
1562 | * number of interrupts. | |
1563 | */ | |
063a8096 | 1564 | |
dca51e78 | 1565 | result = queue_request_irq(adminq); |
758dd7fd JD |
1566 | if (result) { |
1567 | adminq->cq_vector = -1; | |
d4875622 | 1568 | return result; |
758dd7fd | 1569 | } |
749941f2 | 1570 | return nvme_create_io_queues(dev); |
b60503ba MW |
1571 | } |
1572 | ||
db3cbfff | 1573 | static void nvme_del_queue_end(struct request *req, int error) |
a5768aa8 | 1574 | { |
db3cbfff | 1575 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 1576 | |
db3cbfff KB |
1577 | blk_mq_free_request(req); |
1578 | complete(&nvmeq->dev->ioq_wait); | |
a5768aa8 KB |
1579 | } |
1580 | ||
db3cbfff | 1581 | static void nvme_del_cq_end(struct request *req, int error) |
a5768aa8 | 1582 | { |
db3cbfff | 1583 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 1584 | |
db3cbfff KB |
1585 | if (!error) { |
1586 | unsigned long flags; | |
1587 | ||
2e39e0f6 ML |
1588 | /* |
1589 | * We might be called with the AQ q_lock held | |
1590 | * and the I/O queue q_lock should always | |
1591 | * nest inside the AQ one. | |
1592 | */ | |
1593 | spin_lock_irqsave_nested(&nvmeq->q_lock, flags, | |
1594 | SINGLE_DEPTH_NESTING); | |
db3cbfff KB |
1595 | nvme_process_cq(nvmeq); |
1596 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
a5768aa8 | 1597 | } |
db3cbfff KB |
1598 | |
1599 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
1600 | } |
1601 | ||
db3cbfff | 1602 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 1603 | { |
db3cbfff KB |
1604 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
1605 | struct request *req; | |
1606 | struct nvme_command cmd; | |
bda4e0fb | 1607 | |
db3cbfff KB |
1608 | memset(&cmd, 0, sizeof(cmd)); |
1609 | cmd.delete_queue.opcode = opcode; | |
1610 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 1611 | |
eb71f435 | 1612 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
db3cbfff KB |
1613 | if (IS_ERR(req)) |
1614 | return PTR_ERR(req); | |
bda4e0fb | 1615 | |
db3cbfff KB |
1616 | req->timeout = ADMIN_TIMEOUT; |
1617 | req->end_io_data = nvmeq; | |
1618 | ||
1619 | blk_execute_rq_nowait(q, NULL, req, false, | |
1620 | opcode == nvme_admin_delete_cq ? | |
1621 | nvme_del_cq_end : nvme_del_queue_end); | |
1622 | return 0; | |
bda4e0fb KB |
1623 | } |
1624 | ||
70659060 | 1625 | static void nvme_disable_io_queues(struct nvme_dev *dev, int queues) |
a5768aa8 | 1626 | { |
70659060 | 1627 | int pass; |
db3cbfff KB |
1628 | unsigned long timeout; |
1629 | u8 opcode = nvme_admin_delete_sq; | |
a5768aa8 | 1630 | |
db3cbfff | 1631 | for (pass = 0; pass < 2; pass++) { |
014a0d60 | 1632 | int sent = 0, i = queues; |
db3cbfff KB |
1633 | |
1634 | reinit_completion(&dev->ioq_wait); | |
1635 | retry: | |
1636 | timeout = ADMIN_TIMEOUT; | |
c21377f8 GKB |
1637 | for (; i > 0; i--, sent++) |
1638 | if (nvme_delete_queue(dev->queues[i], opcode)) | |
db3cbfff | 1639 | break; |
c21377f8 | 1640 | |
db3cbfff KB |
1641 | while (sent--) { |
1642 | timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); | |
1643 | if (timeout == 0) | |
1644 | return; | |
1645 | if (i) | |
1646 | goto retry; | |
1647 | } | |
1648 | opcode = nvme_admin_delete_cq; | |
1649 | } | |
a5768aa8 KB |
1650 | } |
1651 | ||
422ef0c7 MW |
1652 | /* |
1653 | * Return: error value if an error occurred setting up the queues or calling | |
1654 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1655 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1656 | * failures should be reported. | |
1657 | */ | |
8d85fce7 | 1658 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1659 | { |
5bae7f73 | 1660 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1661 | dev->tagset.ops = &nvme_mq_ops; |
1662 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1663 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1664 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1665 | dev->tagset.queue_depth = | |
a4aea562 | 1666 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1667 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1668 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1669 | dev->tagset.driver_data = dev; | |
b60503ba | 1670 | |
ffe7704d KB |
1671 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1672 | return 0; | |
5bae7f73 | 1673 | dev->ctrl.tagset = &dev->tagset; |
f9f38e33 HK |
1674 | |
1675 | nvme_dbbuf_set(dev); | |
949928c1 KB |
1676 | } else { |
1677 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
1678 | ||
1679 | /* Free previously allocated queues that are no longer usable */ | |
1680 | nvme_free_queues(dev, dev->online_queues); | |
ffe7704d | 1681 | } |
949928c1 | 1682 | |
e1e5e564 | 1683 | return 0; |
b60503ba MW |
1684 | } |
1685 | ||
b00a726a | 1686 | static int nvme_pci_enable(struct nvme_dev *dev) |
0877cb0d | 1687 | { |
42f61420 | 1688 | u64 cap; |
b00a726a | 1689 | int result = -ENOMEM; |
e75ec752 | 1690 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1691 | |
1692 | if (pci_enable_device_mem(pdev)) | |
1693 | return result; | |
1694 | ||
0877cb0d | 1695 | pci_set_master(pdev); |
0877cb0d | 1696 | |
e75ec752 CH |
1697 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1698 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1699 | goto disable; |
0877cb0d | 1700 | |
7a67cbea | 1701 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 | 1702 | result = -ENODEV; |
b00a726a | 1703 | goto disable; |
0e53d180 | 1704 | } |
e32efbfc JA |
1705 | |
1706 | /* | |
a5229050 KB |
1707 | * Some devices and/or platforms don't advertise or work with INTx |
1708 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll | |
1709 | * adjust this later. | |
e32efbfc | 1710 | */ |
dca51e78 CH |
1711 | result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
1712 | if (result < 0) | |
1713 | return result; | |
e32efbfc | 1714 | |
7a67cbea CH |
1715 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1716 | ||
42f61420 KB |
1717 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1718 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea | 1719 | dev->dbs = dev->bar + 4096; |
1f390c1f SG |
1720 | |
1721 | /* | |
1722 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
1723 | * some MacBook7,1 to avoid controller resets and data loss. | |
1724 | */ | |
1725 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
1726 | dev->q_depth = 2; | |
1727 | dev_warn(dev->dev, "detected Apple NVMe controller, set " | |
1728 | "queue depth=%u to work around controller resets\n", | |
1729 | dev->q_depth); | |
1730 | } | |
1731 | ||
202021c1 SB |
1732 | /* |
1733 | * CMBs can currently only exist on >=1.2 PCIe devices. We only | |
1734 | * populate sysfs if a CMB is implemented. Note that we add the | |
1735 | * CMB attribute to the nvme_ctrl kobj which removes the need to remove | |
1736 | * it on exit. Since nvme_dev_attrs_group has no name we can pass | |
1737 | * NULL as final argument to sysfs_add_file_to_group. | |
1738 | */ | |
1739 | ||
8ef2074d | 1740 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) { |
8ffaadf7 | 1741 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d | 1742 | |
202021c1 SB |
1743 | if (dev->cmbsz) { |
1744 | if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, | |
1745 | &dev_attr_cmb.attr, NULL)) | |
1746 | dev_warn(dev->dev, | |
1747 | "failed to add sysfs attribute for CMB\n"); | |
1748 | } | |
1749 | } | |
1750 | ||
a0a3408e KB |
1751 | pci_enable_pcie_error_reporting(pdev); |
1752 | pci_save_state(pdev); | |
0877cb0d KB |
1753 | return 0; |
1754 | ||
1755 | disable: | |
0877cb0d KB |
1756 | pci_disable_device(pdev); |
1757 | return result; | |
1758 | } | |
1759 | ||
1760 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
b00a726a KB |
1761 | { |
1762 | if (dev->bar) | |
1763 | iounmap(dev->bar); | |
a1f447b3 | 1764 | pci_release_mem_regions(to_pci_dev(dev->dev)); |
b00a726a KB |
1765 | } |
1766 | ||
1767 | static void nvme_pci_disable(struct nvme_dev *dev) | |
0877cb0d | 1768 | { |
e75ec752 CH |
1769 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1770 | ||
dca51e78 | 1771 | pci_free_irq_vectors(pdev); |
0877cb0d | 1772 | |
a0a3408e KB |
1773 | if (pci_is_enabled(pdev)) { |
1774 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 1775 | pci_disable_device(pdev); |
4d115420 | 1776 | } |
4d115420 KB |
1777 | } |
1778 | ||
a5cdb68c | 1779 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 1780 | { |
70659060 | 1781 | int i, queues; |
302ad8cc KB |
1782 | bool dead = true; |
1783 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
22404274 | 1784 | |
2d55cd5f | 1785 | del_timer_sync(&dev->watchdog_timer); |
1fa6aead | 1786 | |
77bf25ea | 1787 | mutex_lock(&dev->shutdown_lock); |
302ad8cc KB |
1788 | if (pci_is_enabled(pdev)) { |
1789 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
1790 | ||
1791 | if (dev->ctrl.state == NVME_CTRL_LIVE) | |
1792 | nvme_start_freeze(&dev->ctrl); | |
1793 | dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || | |
1794 | pdev->error_state != pci_channel_io_normal); | |
c9d3bf88 | 1795 | } |
c21377f8 | 1796 | |
302ad8cc KB |
1797 | /* |
1798 | * Give the controller a chance to complete all entered requests if | |
1799 | * doing a safe shutdown. | |
1800 | */ | |
1801 | if (!dead && shutdown) | |
1802 | nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); | |
1803 | nvme_stop_queues(&dev->ctrl); | |
1804 | ||
70659060 | 1805 | queues = dev->online_queues - 1; |
c21377f8 GKB |
1806 | for (i = dev->queue_count - 1; i > 0; i--) |
1807 | nvme_suspend_queue(dev->queues[i]); | |
1808 | ||
302ad8cc | 1809 | if (dead) { |
82469c59 GKB |
1810 | /* A device might become IO incapable very soon during |
1811 | * probe, before the admin queue is configured. Thus, | |
1812 | * queue_count can be 0 here. | |
1813 | */ | |
1814 | if (dev->queue_count) | |
1815 | nvme_suspend_queue(dev->queues[0]); | |
4d115420 | 1816 | } else { |
70659060 | 1817 | nvme_disable_io_queues(dev, queues); |
a5cdb68c | 1818 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 1819 | } |
b00a726a | 1820 | nvme_pci_disable(dev); |
07836e65 | 1821 | |
e1958e65 ML |
1822 | blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); |
1823 | blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); | |
302ad8cc KB |
1824 | |
1825 | /* | |
1826 | * The driver will not be starting up queues again if shutting down so | |
1827 | * must flush all entered requests to their failed completion to avoid | |
1828 | * deadlocking blk-mq hot-cpu notifier. | |
1829 | */ | |
1830 | if (shutdown) | |
1831 | nvme_start_queues(&dev->ctrl); | |
77bf25ea | 1832 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
1833 | } |
1834 | ||
091b6092 MW |
1835 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1836 | { | |
e75ec752 | 1837 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
1838 | PAGE_SIZE, PAGE_SIZE, 0); |
1839 | if (!dev->prp_page_pool) | |
1840 | return -ENOMEM; | |
1841 | ||
99802a7a | 1842 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 1843 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
1844 | 256, 256, 0); |
1845 | if (!dev->prp_small_pool) { | |
1846 | dma_pool_destroy(dev->prp_page_pool); | |
1847 | return -ENOMEM; | |
1848 | } | |
091b6092 MW |
1849 | return 0; |
1850 | } | |
1851 | ||
1852 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1853 | { | |
1854 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1855 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1856 | } |
1857 | ||
1673f1f0 | 1858 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 1859 | { |
1673f1f0 | 1860 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 1861 | |
f9f38e33 | 1862 | nvme_dbbuf_dma_free(dev); |
e75ec752 | 1863 | put_device(dev->dev); |
4af0e21c KB |
1864 | if (dev->tagset.tags) |
1865 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
1866 | if (dev->ctrl.admin_q) |
1867 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 | 1868 | kfree(dev->queues); |
e286bcfc | 1869 | free_opal_dev(dev->ctrl.opal_dev); |
5e82e952 KB |
1870 | kfree(dev); |
1871 | } | |
1872 | ||
f58944e2 KB |
1873 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) |
1874 | { | |
237045fc | 1875 | dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); |
f58944e2 KB |
1876 | |
1877 | kref_get(&dev->ctrl.kref); | |
69d9a99c | 1878 | nvme_dev_disable(dev, false); |
f58944e2 KB |
1879 | if (!schedule_work(&dev->remove_work)) |
1880 | nvme_put_ctrl(&dev->ctrl); | |
1881 | } | |
1882 | ||
fd634f41 | 1883 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 1884 | { |
fd634f41 | 1885 | struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); |
a98e58e5 | 1886 | bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); |
f58944e2 | 1887 | int result = -ENODEV; |
5e82e952 | 1888 | |
bb8d261e | 1889 | if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING)) |
fd634f41 | 1890 | goto out; |
5e82e952 | 1891 | |
fd634f41 CH |
1892 | /* |
1893 | * If we're called to reset a live controller first shut it down before | |
1894 | * moving on. | |
1895 | */ | |
b00a726a | 1896 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
a5cdb68c | 1897 | nvme_dev_disable(dev, false); |
5e82e952 | 1898 | |
bb8d261e | 1899 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) |
9bf2b972 KB |
1900 | goto out; |
1901 | ||
b00a726a | 1902 | result = nvme_pci_enable(dev); |
f0b50732 | 1903 | if (result) |
3cf519b5 | 1904 | goto out; |
f0b50732 KB |
1905 | |
1906 | result = nvme_configure_admin_queue(dev); | |
1907 | if (result) | |
f58944e2 | 1908 | goto out; |
f0b50732 | 1909 | |
a4aea562 | 1910 | nvme_init_queue(dev->queues[0], 0); |
0fb59cbc KB |
1911 | result = nvme_alloc_admin_tags(dev); |
1912 | if (result) | |
f58944e2 | 1913 | goto out; |
b9afca3e | 1914 | |
ce4541f4 CH |
1915 | result = nvme_init_identify(&dev->ctrl); |
1916 | if (result) | |
f58944e2 | 1917 | goto out; |
ce4541f4 | 1918 | |
e286bcfc SB |
1919 | if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { |
1920 | if (!dev->ctrl.opal_dev) | |
1921 | dev->ctrl.opal_dev = | |
1922 | init_opal_dev(&dev->ctrl, &nvme_sec_submit); | |
1923 | else if (was_suspend) | |
1924 | opal_unlock_from_suspend(dev->ctrl.opal_dev); | |
1925 | } else { | |
1926 | free_opal_dev(dev->ctrl.opal_dev); | |
1927 | dev->ctrl.opal_dev = NULL; | |
4f1244c8 | 1928 | } |
a98e58e5 | 1929 | |
f9f38e33 HK |
1930 | if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { |
1931 | result = nvme_dbbuf_dma_alloc(dev); | |
1932 | if (result) | |
1933 | dev_warn(dev->dev, | |
1934 | "unable to allocate dma for dbbuf\n"); | |
1935 | } | |
1936 | ||
f0b50732 | 1937 | result = nvme_setup_io_queues(dev); |
badc34d4 | 1938 | if (result) |
f58944e2 | 1939 | goto out; |
f0b50732 | 1940 | |
21f033f7 KB |
1941 | /* |
1942 | * A controller that can not execute IO typically requires user | |
1943 | * intervention to correct. For such degraded controllers, the driver | |
1944 | * should not submit commands the user did not request, so skip | |
1945 | * registering for asynchronous event notification on this condition. | |
1946 | */ | |
f866fc42 CH |
1947 | if (dev->online_queues > 1) |
1948 | nvme_queue_async_events(&dev->ctrl); | |
3cf519b5 | 1949 | |
2d55cd5f | 1950 | mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); |
3cf519b5 | 1951 | |
2659e57b CH |
1952 | /* |
1953 | * Keep the controller around but remove all namespaces if we don't have | |
1954 | * any working I/O queue. | |
1955 | */ | |
3cf519b5 | 1956 | if (dev->online_queues < 2) { |
1b3c47c1 | 1957 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
3b24774e | 1958 | nvme_kill_queues(&dev->ctrl); |
5bae7f73 | 1959 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 | 1960 | } else { |
25646264 | 1961 | nvme_start_queues(&dev->ctrl); |
302ad8cc | 1962 | nvme_wait_freeze(&dev->ctrl); |
3cf519b5 | 1963 | nvme_dev_add(dev); |
302ad8cc | 1964 | nvme_unfreeze(&dev->ctrl); |
3cf519b5 CH |
1965 | } |
1966 | ||
bb8d261e CH |
1967 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { |
1968 | dev_warn(dev->ctrl.device, "failed to mark controller live\n"); | |
1969 | goto out; | |
1970 | } | |
92911a55 CH |
1971 | |
1972 | if (dev->online_queues > 1) | |
5955be21 | 1973 | nvme_queue_scan(&dev->ctrl); |
3cf519b5 | 1974 | return; |
f0b50732 | 1975 | |
3cf519b5 | 1976 | out: |
f58944e2 | 1977 | nvme_remove_dead_ctrl(dev, result); |
f0b50732 KB |
1978 | } |
1979 | ||
5c8809e6 | 1980 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 1981 | { |
5c8809e6 | 1982 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 1983 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 | 1984 | |
69d9a99c | 1985 | nvme_kill_queues(&dev->ctrl); |
9a6b9458 | 1986 | if (pci_get_drvdata(pdev)) |
921920ab | 1987 | device_release_driver(&pdev->dev); |
1673f1f0 | 1988 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
1989 | } |
1990 | ||
4cc06521 | 1991 | static int nvme_reset(struct nvme_dev *dev) |
9a6b9458 | 1992 | { |
1c63dc66 | 1993 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 | 1994 | return -ENODEV; |
c5f6ce97 KB |
1995 | if (work_busy(&dev->reset_work)) |
1996 | return -ENODEV; | |
846cc05f CH |
1997 | if (!queue_work(nvme_workq, &dev->reset_work)) |
1998 | return -EBUSY; | |
846cc05f | 1999 | return 0; |
9a6b9458 KB |
2000 | } |
2001 | ||
1c63dc66 | 2002 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 2003 | { |
1c63dc66 | 2004 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 2005 | return 0; |
9ca97374 TH |
2006 | } |
2007 | ||
5fd4ce1b | 2008 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 2009 | { |
5fd4ce1b CH |
2010 | writel(val, to_nvme_dev(ctrl)->bar + off); |
2011 | return 0; | |
2012 | } | |
4cc06521 | 2013 | |
7fd8930f CH |
2014 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2015 | { | |
2016 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
2017 | return 0; | |
4cc06521 KB |
2018 | } |
2019 | ||
f3ca80fc CH |
2020 | static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) |
2021 | { | |
c5f6ce97 KB |
2022 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
2023 | int ret = nvme_reset(dev); | |
2024 | ||
2025 | if (!ret) | |
2026 | flush_work(&dev->reset_work); | |
2027 | return ret; | |
4cc06521 | 2028 | } |
f3ca80fc | 2029 | |
1c63dc66 | 2030 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
1a353d85 | 2031 | .name = "pcie", |
e439bb12 | 2032 | .module = THIS_MODULE, |
1c63dc66 | 2033 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 2034 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 2035 | .reg_read64 = nvme_pci_reg_read64, |
f3ca80fc | 2036 | .reset_ctrl = nvme_pci_reset_ctrl, |
1673f1f0 | 2037 | .free_ctrl = nvme_pci_free_ctrl, |
f866fc42 | 2038 | .submit_async_event = nvme_pci_submit_async_event, |
1c63dc66 | 2039 | }; |
4cc06521 | 2040 | |
b00a726a KB |
2041 | static int nvme_dev_map(struct nvme_dev *dev) |
2042 | { | |
b00a726a KB |
2043 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2044 | ||
a1f447b3 | 2045 | if (pci_request_mem_regions(pdev, "nvme")) |
b00a726a KB |
2046 | return -ENODEV; |
2047 | ||
2048 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); | |
2049 | if (!dev->bar) | |
2050 | goto release; | |
2051 | ||
9fa196e7 | 2052 | return 0; |
b00a726a | 2053 | release: |
9fa196e7 MG |
2054 | pci_release_mem_regions(pdev); |
2055 | return -ENODEV; | |
b00a726a KB |
2056 | } |
2057 | ||
8d85fce7 | 2058 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2059 | { |
a4aea562 | 2060 | int node, result = -ENOMEM; |
b60503ba MW |
2061 | struct nvme_dev *dev; |
2062 | ||
a4aea562 MB |
2063 | node = dev_to_node(&pdev->dev); |
2064 | if (node == NUMA_NO_NODE) | |
2fa84351 | 2065 | set_dev_node(&pdev->dev, first_memory_node); |
a4aea562 MB |
2066 | |
2067 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2068 | if (!dev) |
2069 | return -ENOMEM; | |
a4aea562 MB |
2070 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2071 | GFP_KERNEL, node); | |
b60503ba MW |
2072 | if (!dev->queues) |
2073 | goto free; | |
2074 | ||
e75ec752 | 2075 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2076 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2077 | |
b00a726a KB |
2078 | result = nvme_dev_map(dev); |
2079 | if (result) | |
2080 | goto free; | |
2081 | ||
f3ca80fc | 2082 | INIT_WORK(&dev->reset_work, nvme_reset_work); |
5c8809e6 | 2083 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
2d55cd5f CH |
2084 | setup_timer(&dev->watchdog_timer, nvme_watchdog_timer, |
2085 | (unsigned long)dev); | |
77bf25ea | 2086 | mutex_init(&dev->shutdown_lock); |
db3cbfff | 2087 | init_completion(&dev->ioq_wait); |
b60503ba | 2088 | |
091b6092 MW |
2089 | result = nvme_setup_prp_pools(dev); |
2090 | if (result) | |
a96d4f5c | 2091 | goto put_pci; |
4cc06521 | 2092 | |
f3ca80fc CH |
2093 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
2094 | id->driver_data); | |
4cc06521 | 2095 | if (result) |
2e1d8448 | 2096 | goto release_pools; |
740216fc | 2097 | |
1b3c47c1 SG |
2098 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
2099 | ||
92f7a162 | 2100 | queue_work(nvme_workq, &dev->reset_work); |
b60503ba MW |
2101 | return 0; |
2102 | ||
0877cb0d | 2103 | release_pools: |
091b6092 | 2104 | nvme_release_prp_pools(dev); |
a96d4f5c | 2105 | put_pci: |
e75ec752 | 2106 | put_device(dev->dev); |
b00a726a | 2107 | nvme_dev_unmap(dev); |
b60503ba MW |
2108 | free: |
2109 | kfree(dev->queues); | |
b60503ba MW |
2110 | kfree(dev); |
2111 | return result; | |
2112 | } | |
2113 | ||
f0d54a54 KB |
2114 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
2115 | { | |
a6739479 | 2116 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 2117 | |
a6739479 | 2118 | if (prepare) |
a5cdb68c | 2119 | nvme_dev_disable(dev, false); |
a6739479 | 2120 | else |
c5f6ce97 | 2121 | nvme_reset(dev); |
f0d54a54 KB |
2122 | } |
2123 | ||
09ece142 KB |
2124 | static void nvme_shutdown(struct pci_dev *pdev) |
2125 | { | |
2126 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
a5cdb68c | 2127 | nvme_dev_disable(dev, true); |
09ece142 KB |
2128 | } |
2129 | ||
f58944e2 KB |
2130 | /* |
2131 | * The driver's remove may be called on a device in a partially initialized | |
2132 | * state. This function must not have any dependencies on the device state in | |
2133 | * order to proceed. | |
2134 | */ | |
8d85fce7 | 2135 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2136 | { |
2137 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 2138 | |
bb8d261e CH |
2139 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
2140 | ||
9a6b9458 | 2141 | pci_set_drvdata(pdev, NULL); |
0ff9d4e1 | 2142 | |
6db28eda | 2143 | if (!pci_device_is_present(pdev)) { |
0ff9d4e1 | 2144 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); |
6db28eda KB |
2145 | nvme_dev_disable(dev, false); |
2146 | } | |
0ff9d4e1 | 2147 | |
9bf2b972 | 2148 | flush_work(&dev->reset_work); |
53029b04 | 2149 | nvme_uninit_ctrl(&dev->ctrl); |
a5cdb68c | 2150 | nvme_dev_disable(dev, true); |
a4aea562 | 2151 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2152 | nvme_free_queues(dev, 0); |
8ffaadf7 | 2153 | nvme_release_cmb(dev); |
9a6b9458 | 2154 | nvme_release_prp_pools(dev); |
b00a726a | 2155 | nvme_dev_unmap(dev); |
1673f1f0 | 2156 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2157 | } |
2158 | ||
13880f5b KB |
2159 | static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) |
2160 | { | |
2161 | int ret = 0; | |
2162 | ||
2163 | if (numvfs == 0) { | |
2164 | if (pci_vfs_assigned(pdev)) { | |
2165 | dev_warn(&pdev->dev, | |
2166 | "Cannot disable SR-IOV VFs while assigned\n"); | |
2167 | return -EPERM; | |
2168 | } | |
2169 | pci_disable_sriov(pdev); | |
2170 | return 0; | |
2171 | } | |
2172 | ||
2173 | ret = pci_enable_sriov(pdev, numvfs); | |
2174 | return ret ? ret : numvfs; | |
2175 | } | |
2176 | ||
671a6018 | 2177 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2178 | static int nvme_suspend(struct device *dev) |
2179 | { | |
2180 | struct pci_dev *pdev = to_pci_dev(dev); | |
2181 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2182 | ||
a5cdb68c | 2183 | nvme_dev_disable(ndev, true); |
cd638946 KB |
2184 | return 0; |
2185 | } | |
2186 | ||
2187 | static int nvme_resume(struct device *dev) | |
2188 | { | |
2189 | struct pci_dev *pdev = to_pci_dev(dev); | |
2190 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2191 | |
c5f6ce97 | 2192 | nvme_reset(ndev); |
9a6b9458 | 2193 | return 0; |
cd638946 | 2194 | } |
671a6018 | 2195 | #endif |
cd638946 KB |
2196 | |
2197 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2198 | |
a0a3408e KB |
2199 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2200 | pci_channel_state_t state) | |
2201 | { | |
2202 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2203 | ||
2204 | /* | |
2205 | * A frozen channel requires a reset. When detected, this method will | |
2206 | * shutdown the controller to quiesce. The controller will be restarted | |
2207 | * after the slot reset through driver's slot_reset callback. | |
2208 | */ | |
a0a3408e KB |
2209 | switch (state) { |
2210 | case pci_channel_io_normal: | |
2211 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2212 | case pci_channel_io_frozen: | |
d011fb31 KB |
2213 | dev_warn(dev->ctrl.device, |
2214 | "frozen state error detected, reset controller\n"); | |
a5cdb68c | 2215 | nvme_dev_disable(dev, false); |
a0a3408e KB |
2216 | return PCI_ERS_RESULT_NEED_RESET; |
2217 | case pci_channel_io_perm_failure: | |
d011fb31 KB |
2218 | dev_warn(dev->ctrl.device, |
2219 | "failure state error detected, request disconnect\n"); | |
a0a3408e KB |
2220 | return PCI_ERS_RESULT_DISCONNECT; |
2221 | } | |
2222 | return PCI_ERS_RESULT_NEED_RESET; | |
2223 | } | |
2224 | ||
2225 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2226 | { | |
2227 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2228 | ||
1b3c47c1 | 2229 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e | 2230 | pci_restore_state(pdev); |
c5f6ce97 | 2231 | nvme_reset(dev); |
a0a3408e KB |
2232 | return PCI_ERS_RESULT_RECOVERED; |
2233 | } | |
2234 | ||
2235 | static void nvme_error_resume(struct pci_dev *pdev) | |
2236 | { | |
2237 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2238 | } | |
2239 | ||
1d352035 | 2240 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2241 | .error_detected = nvme_error_detected, |
b60503ba MW |
2242 | .slot_reset = nvme_slot_reset, |
2243 | .resume = nvme_error_resume, | |
f0d54a54 | 2244 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2245 | }; |
2246 | ||
6eb0d698 | 2247 | static const struct pci_device_id nvme_id_table[] = { |
106198ed | 2248 | { PCI_VDEVICE(INTEL, 0x0953), |
08095e70 | 2249 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
e850fd16 | 2250 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
99466e70 KB |
2251 | { PCI_VDEVICE(INTEL, 0x0a53), |
2252 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
e850fd16 | 2253 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
99466e70 KB |
2254 | { PCI_VDEVICE(INTEL, 0x0a54), |
2255 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
e850fd16 | 2256 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
540c801c KB |
2257 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2258 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
54adc010 GP |
2259 | { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ |
2260 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
015282c9 WW |
2261 | { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ |
2262 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
b60503ba | 2263 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2264 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
124298bd | 2265 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, |
b60503ba MW |
2266 | { 0, } |
2267 | }; | |
2268 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2269 | ||
2270 | static struct pci_driver nvme_driver = { | |
2271 | .name = "nvme", | |
2272 | .id_table = nvme_id_table, | |
2273 | .probe = nvme_probe, | |
8d85fce7 | 2274 | .remove = nvme_remove, |
09ece142 | 2275 | .shutdown = nvme_shutdown, |
cd638946 KB |
2276 | .driver = { |
2277 | .pm = &nvme_dev_pm_ops, | |
2278 | }, | |
13880f5b | 2279 | .sriov_configure = nvme_pci_sriov_configure, |
b60503ba MW |
2280 | .err_handler = &nvme_err_handler, |
2281 | }; | |
2282 | ||
2283 | static int __init nvme_init(void) | |
2284 | { | |
0ac13140 | 2285 | int result; |
1fa6aead | 2286 | |
92f7a162 | 2287 | nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0); |
9a6b9458 | 2288 | if (!nvme_workq) |
b9afca3e | 2289 | return -ENOMEM; |
9a6b9458 | 2290 | |
f3db22fe KB |
2291 | result = pci_register_driver(&nvme_driver); |
2292 | if (result) | |
576d55d6 | 2293 | destroy_workqueue(nvme_workq); |
b60503ba MW |
2294 | return result; |
2295 | } | |
2296 | ||
2297 | static void __exit nvme_exit(void) | |
2298 | { | |
2299 | pci_unregister_driver(&nvme_driver); | |
9a6b9458 | 2300 | destroy_workqueue(nvme_workq); |
21bd78bc | 2301 | _nvme_check_size(); |
b60503ba MW |
2302 | } |
2303 | ||
2304 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2305 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2306 | MODULE_VERSION("1.0"); |
b60503ba MW |
2307 | module_init(nvme_init); |
2308 | module_exit(nvme_exit); |