]>
Commit | Line | Data |
---|---|---|
b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
a0a3408e | 15 | #include <linux/aer.h> |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
42f61420 | 19 | #include <linux/cpu.h> |
fd63e9ce | 20 | #include <linux/delay.h> |
b60503ba MW |
21 | #include <linux/errno.h> |
22 | #include <linux/fs.h> | |
23 | #include <linux/genhd.h> | |
4cc09e2d | 24 | #include <linux/hdreg.h> |
5aff9382 | 25 | #include <linux/idr.h> |
b60503ba MW |
26 | #include <linux/init.h> |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/kdev_t.h> | |
1fa6aead | 30 | #include <linux/kthread.h> |
b60503ba MW |
31 | #include <linux/kernel.h> |
32 | #include <linux/mm.h> | |
33 | #include <linux/module.h> | |
34 | #include <linux/moduleparam.h> | |
77bf25ea | 35 | #include <linux/mutex.h> |
b60503ba | 36 | #include <linux/pci.h> |
be7b6275 | 37 | #include <linux/poison.h> |
c3bfe717 | 38 | #include <linux/ptrace.h> |
b60503ba MW |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
e1e5e564 | 41 | #include <linux/t10-pi.h> |
b60503ba | 42 | #include <linux/types.h> |
2f8e2c87 | 43 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 44 | #include <asm/unaligned.h> |
797a796a | 45 | |
f11bb3e2 CH |
46 | #include "nvme.h" |
47 | ||
9d43cf64 | 48 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 49 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
50 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
51 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
adf68f21 CH |
52 | |
53 | /* | |
54 | * We handle AEN commands ourselves and don't even let the | |
55 | * block layer know about them. | |
56 | */ | |
57 | #define NVME_NR_AEN_COMMANDS 1 | |
58 | #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS) | |
9d43cf64 | 59 | |
21d34711 | 60 | unsigned char admin_timeout = 60; |
9d43cf64 KB |
61 | module_param(admin_timeout, byte, 0644); |
62 | MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands"); | |
b60503ba | 63 | |
bd67608a MW |
64 | unsigned char nvme_io_timeout = 30; |
65 | module_param_named(io_timeout, nvme_io_timeout, byte, 0644); | |
b355084a | 66 | MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); |
b60503ba | 67 | |
5fd4ce1b | 68 | unsigned char shutdown_timeout = 5; |
2484f407 DM |
69 | module_param(shutdown_timeout, byte, 0644); |
70 | MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown"); | |
71 | ||
58ffacb5 MW |
72 | static int use_threaded_interrupts; |
73 | module_param(use_threaded_interrupts, int, 0); | |
74 | ||
8ffaadf7 JD |
75 | static bool use_cmb_sqes = true; |
76 | module_param(use_cmb_sqes, bool, 0644); | |
77 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
78 | ||
1fa6aead MW |
79 | static LIST_HEAD(dev_list); |
80 | static struct task_struct *nvme_thread; | |
9a6b9458 | 81 | static struct workqueue_struct *nvme_workq; |
b9afca3e | 82 | static wait_queue_head_t nvme_kthread_wait; |
1fa6aead | 83 | |
1c63dc66 CH |
84 | struct nvme_dev; |
85 | struct nvme_queue; | |
b3fffdef | 86 | |
4cc06521 | 87 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 88 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
5c8809e6 | 89 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev); |
a5cdb68c | 90 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
d4b4ff8e | 91 | |
1c63dc66 CH |
92 | /* |
93 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
94 | */ | |
95 | struct nvme_dev { | |
96 | struct list_head node; | |
97 | struct nvme_queue **queues; | |
98 | struct blk_mq_tag_set tagset; | |
99 | struct blk_mq_tag_set admin_tagset; | |
100 | u32 __iomem *dbs; | |
101 | struct device *dev; | |
102 | struct dma_pool *prp_page_pool; | |
103 | struct dma_pool *prp_small_pool; | |
104 | unsigned queue_count; | |
105 | unsigned online_queues; | |
106 | unsigned max_qid; | |
107 | int q_depth; | |
108 | u32 db_stride; | |
1c63dc66 CH |
109 | struct msix_entry *entry; |
110 | void __iomem *bar; | |
1c63dc66 | 111 | struct work_struct reset_work; |
1c63dc66 | 112 | struct work_struct scan_work; |
5c8809e6 | 113 | struct work_struct remove_work; |
77bf25ea | 114 | struct mutex shutdown_lock; |
1c63dc66 | 115 | bool subsystem; |
1c63dc66 CH |
116 | void __iomem *cmb; |
117 | dma_addr_t cmb_dma_addr; | |
118 | u64 cmb_size; | |
119 | u32 cmbsz; | |
fd634f41 | 120 | unsigned long flags; |
db3cbfff | 121 | |
fd634f41 | 122 | #define NVME_CTRL_RESETTING 0 |
1c63dc66 CH |
123 | |
124 | struct nvme_ctrl ctrl; | |
db3cbfff | 125 | struct completion ioq_wait; |
4d115420 | 126 | }; |
1fa6aead | 127 | |
1c63dc66 CH |
128 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
129 | { | |
130 | return container_of(ctrl, struct nvme_dev, ctrl); | |
131 | } | |
132 | ||
b60503ba MW |
133 | /* |
134 | * An NVM Express queue. Each device has at least two (one for admin | |
135 | * commands and one for I/O commands). | |
136 | */ | |
137 | struct nvme_queue { | |
138 | struct device *q_dmadev; | |
091b6092 | 139 | struct nvme_dev *dev; |
3193f07b | 140 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
141 | spinlock_t q_lock; |
142 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 143 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 144 | volatile struct nvme_completion *cqes; |
42483228 | 145 | struct blk_mq_tags **tags; |
b60503ba MW |
146 | dma_addr_t sq_dma_addr; |
147 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
148 | u32 __iomem *q_db; |
149 | u16 q_depth; | |
6222d172 | 150 | s16 cq_vector; |
b60503ba MW |
151 | u16 sq_head; |
152 | u16 sq_tail; | |
153 | u16 cq_head; | |
c30341dc | 154 | u16 qid; |
e9539f47 MW |
155 | u8 cq_phase; |
156 | u8 cqe_seen; | |
b60503ba MW |
157 | }; |
158 | ||
71bd150c CH |
159 | /* |
160 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
161 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 162 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
163 | * allocated to store the PRP list. |
164 | */ | |
165 | struct nvme_iod { | |
f4800d6d CH |
166 | struct nvme_queue *nvmeq; |
167 | int aborted; | |
71bd150c | 168 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
169 | int nents; /* Used in scatterlist */ |
170 | int length; /* Of data, in bytes */ | |
171 | dma_addr_t first_dma; | |
bf684057 | 172 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
173 | struct scatterlist *sg; |
174 | struct scatterlist inline_sg[0]; | |
b60503ba MW |
175 | }; |
176 | ||
177 | /* | |
178 | * Check we didin't inadvertently grow the command struct | |
179 | */ | |
180 | static inline void _nvme_check_size(void) | |
181 | { | |
182 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
183 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
184 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
185 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
186 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 187 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 188 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
189 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
190 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
191 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
192 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 193 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
194 | } |
195 | ||
ac3dd5bd JA |
196 | /* |
197 | * Max size of iod being embedded in the request payload | |
198 | */ | |
199 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 200 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
201 | |
202 | /* | |
203 | * Will slightly overestimate the number of pages needed. This is OK | |
204 | * as it only leads to a small amount of wasted memory for the lifetime of | |
205 | * the I/O. | |
206 | */ | |
207 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
208 | { | |
5fd4ce1b CH |
209 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
210 | dev->ctrl.page_size); | |
ac3dd5bd JA |
211 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
212 | } | |
213 | ||
f4800d6d CH |
214 | static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, |
215 | unsigned int size, unsigned int nseg) | |
ac3dd5bd | 216 | { |
f4800d6d CH |
217 | return sizeof(__le64 *) * nvme_npages(size, dev) + |
218 | sizeof(struct scatterlist) * nseg; | |
219 | } | |
ac3dd5bd | 220 | |
f4800d6d CH |
221 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) |
222 | { | |
223 | return sizeof(struct nvme_iod) + | |
224 | nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); | |
ac3dd5bd JA |
225 | } |
226 | ||
a4aea562 MB |
227 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
228 | unsigned int hctx_idx) | |
e85248e5 | 229 | { |
a4aea562 MB |
230 | struct nvme_dev *dev = data; |
231 | struct nvme_queue *nvmeq = dev->queues[0]; | |
232 | ||
42483228 KB |
233 | WARN_ON(hctx_idx != 0); |
234 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
235 | WARN_ON(nvmeq->tags); | |
236 | ||
a4aea562 | 237 | hctx->driver_data = nvmeq; |
42483228 | 238 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 239 | return 0; |
e85248e5 MW |
240 | } |
241 | ||
4af0e21c KB |
242 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
243 | { | |
244 | struct nvme_queue *nvmeq = hctx->driver_data; | |
245 | ||
246 | nvmeq->tags = NULL; | |
247 | } | |
248 | ||
a4aea562 MB |
249 | static int nvme_admin_init_request(void *data, struct request *req, |
250 | unsigned int hctx_idx, unsigned int rq_idx, | |
251 | unsigned int numa_node) | |
22404274 | 252 | { |
a4aea562 | 253 | struct nvme_dev *dev = data; |
f4800d6d | 254 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
255 | struct nvme_queue *nvmeq = dev->queues[0]; |
256 | ||
257 | BUG_ON(!nvmeq); | |
f4800d6d | 258 | iod->nvmeq = nvmeq; |
a4aea562 | 259 | return 0; |
22404274 KB |
260 | } |
261 | ||
a4aea562 MB |
262 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
263 | unsigned int hctx_idx) | |
b60503ba | 264 | { |
a4aea562 | 265 | struct nvme_dev *dev = data; |
42483228 | 266 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 267 | |
42483228 KB |
268 | if (!nvmeq->tags) |
269 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 270 | |
42483228 | 271 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
272 | hctx->driver_data = nvmeq; |
273 | return 0; | |
b60503ba MW |
274 | } |
275 | ||
a4aea562 MB |
276 | static int nvme_init_request(void *data, struct request *req, |
277 | unsigned int hctx_idx, unsigned int rq_idx, | |
278 | unsigned int numa_node) | |
b60503ba | 279 | { |
a4aea562 | 280 | struct nvme_dev *dev = data; |
f4800d6d | 281 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
282 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
283 | ||
284 | BUG_ON(!nvmeq); | |
f4800d6d | 285 | iod->nvmeq = nvmeq; |
a4aea562 MB |
286 | return 0; |
287 | } | |
288 | ||
adf68f21 CH |
289 | static void nvme_complete_async_event(struct nvme_dev *dev, |
290 | struct nvme_completion *cqe) | |
a4aea562 | 291 | { |
adf68f21 CH |
292 | u16 status = le16_to_cpu(cqe->status) >> 1; |
293 | u32 result = le32_to_cpu(cqe->result); | |
a4aea562 MB |
294 | |
295 | if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) | |
adf68f21 | 296 | ++dev->ctrl.event_limit; |
a5768aa8 KB |
297 | if (status != NVME_SC_SUCCESS) |
298 | return; | |
299 | ||
300 | switch (result & 0xff07) { | |
301 | case NVME_AER_NOTICE_NS_CHANGED: | |
adf68f21 CH |
302 | dev_info(dev->dev, "rescanning\n"); |
303 | queue_work(nvme_workq, &dev->scan_work); | |
a5768aa8 | 304 | default: |
adf68f21 | 305 | dev_warn(dev->dev, "async event result %08x\n", result); |
a4aea562 | 306 | } |
b60503ba MW |
307 | } |
308 | ||
309 | /** | |
adf68f21 | 310 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
311 | * @nvmeq: The queue to use |
312 | * @cmd: The command to send | |
313 | * | |
314 | * Safe to use from interrupt context | |
315 | */ | |
e3f879bf SB |
316 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
317 | struct nvme_command *cmd) | |
b60503ba | 318 | { |
a4aea562 MB |
319 | u16 tail = nvmeq->sq_tail; |
320 | ||
8ffaadf7 JD |
321 | if (nvmeq->sq_cmds_io) |
322 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
323 | else | |
324 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
325 | ||
b60503ba MW |
326 | if (++tail == nvmeq->q_depth) |
327 | tail = 0; | |
7547881d | 328 | writel(tail, nvmeq->q_db); |
b60503ba | 329 | nvmeq->sq_tail = tail; |
b60503ba MW |
330 | } |
331 | ||
f4800d6d | 332 | static __le64 **iod_list(struct request *req) |
b60503ba | 333 | { |
f4800d6d CH |
334 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
335 | return (__le64 **)(iod->sg + req->nr_phys_segments); | |
b60503ba MW |
336 | } |
337 | ||
f4800d6d | 338 | static int nvme_init_iod(struct request *rq, struct nvme_dev *dev) |
ac3dd5bd | 339 | { |
f4800d6d CH |
340 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
341 | int nseg = rq->nr_phys_segments; | |
342 | unsigned size; | |
ac3dd5bd | 343 | |
f4800d6d CH |
344 | if (rq->cmd_flags & REQ_DISCARD) |
345 | size = sizeof(struct nvme_dsm_range); | |
346 | else | |
347 | size = blk_rq_bytes(rq); | |
ac3dd5bd | 348 | |
f4800d6d CH |
349 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
350 | iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); | |
351 | if (!iod->sg) | |
352 | return BLK_MQ_RQ_QUEUE_BUSY; | |
353 | } else { | |
354 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
355 | } |
356 | ||
f4800d6d CH |
357 | iod->aborted = 0; |
358 | iod->npages = -1; | |
359 | iod->nents = 0; | |
360 | iod->length = size; | |
361 | return 0; | |
ac3dd5bd JA |
362 | } |
363 | ||
f4800d6d | 364 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 365 | { |
f4800d6d | 366 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
5fd4ce1b | 367 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 | 368 | int i; |
f4800d6d | 369 | __le64 **list = iod_list(req); |
eca18b23 MW |
370 | dma_addr_t prp_dma = iod->first_dma; |
371 | ||
372 | if (iod->npages == 0) | |
373 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
374 | for (i = 0; i < iod->npages; i++) { | |
375 | __le64 *prp_list = list[i]; | |
376 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
377 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
378 | prp_dma = next_prp_dma; | |
379 | } | |
ac3dd5bd | 380 | |
f4800d6d CH |
381 | if (iod->sg != iod->inline_sg) |
382 | kfree(iod->sg); | |
b4ff9c8d KB |
383 | } |
384 | ||
52b68d7e | 385 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
386 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
387 | { | |
388 | if (be32_to_cpu(pi->ref_tag) == v) | |
389 | pi->ref_tag = cpu_to_be32(p); | |
390 | } | |
391 | ||
392 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
393 | { | |
394 | if (be32_to_cpu(pi->ref_tag) == p) | |
395 | pi->ref_tag = cpu_to_be32(v); | |
396 | } | |
397 | ||
398 | /** | |
399 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
400 | * | |
401 | * The virtual start sector is the one that was originally submitted by the | |
402 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
403 | * start sector may be different. Remap protection information to match the | |
404 | * physical LBA on writes, and back to the original seed on reads. | |
405 | * | |
406 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
407 | */ | |
408 | static void nvme_dif_remap(struct request *req, | |
409 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
410 | { | |
411 | struct nvme_ns *ns = req->rq_disk->private_data; | |
412 | struct bio_integrity_payload *bip; | |
413 | struct t10_pi_tuple *pi; | |
414 | void *p, *pmap; | |
415 | u32 i, nlb, ts, phys, virt; | |
416 | ||
417 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
418 | return; | |
419 | ||
420 | bip = bio_integrity(req->bio); | |
421 | if (!bip) | |
422 | return; | |
423 | ||
424 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
425 | |
426 | p = pmap; | |
427 | virt = bip_get_seed(bip); | |
428 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
429 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 430 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
431 | |
432 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
433 | pi = (struct t10_pi_tuple *)p; | |
434 | dif_swap(phys, virt, pi); | |
435 | p += ts; | |
436 | } | |
437 | kunmap_atomic(pmap); | |
438 | } | |
52b68d7e KB |
439 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
440 | static void nvme_dif_remap(struct request *req, | |
441 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
442 | { | |
443 | } | |
444 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
445 | { | |
446 | } | |
447 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
448 | { | |
449 | } | |
52b68d7e KB |
450 | #endif |
451 | ||
f4800d6d | 452 | static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req, |
69d2b571 | 453 | int total_len) |
ff22b54f | 454 | { |
f4800d6d | 455 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 456 | struct dma_pool *pool; |
eca18b23 MW |
457 | int length = total_len; |
458 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
459 | int dma_len = sg_dma_len(sg); |
460 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 461 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 462 | int offset = dma_addr & (page_size - 1); |
e025344c | 463 | __le64 *prp_list; |
f4800d6d | 464 | __le64 **list = iod_list(req); |
e025344c | 465 | dma_addr_t prp_dma; |
eca18b23 | 466 | int nprps, i; |
ff22b54f | 467 | |
1d090624 | 468 | length -= (page_size - offset); |
ff22b54f | 469 | if (length <= 0) |
69d2b571 | 470 | return true; |
ff22b54f | 471 | |
1d090624 | 472 | dma_len -= (page_size - offset); |
ff22b54f | 473 | if (dma_len) { |
1d090624 | 474 | dma_addr += (page_size - offset); |
ff22b54f MW |
475 | } else { |
476 | sg = sg_next(sg); | |
477 | dma_addr = sg_dma_address(sg); | |
478 | dma_len = sg_dma_len(sg); | |
479 | } | |
480 | ||
1d090624 | 481 | if (length <= page_size) { |
edd10d33 | 482 | iod->first_dma = dma_addr; |
69d2b571 | 483 | return true; |
e025344c SMM |
484 | } |
485 | ||
1d090624 | 486 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
487 | if (nprps <= (256 / 8)) { |
488 | pool = dev->prp_small_pool; | |
eca18b23 | 489 | iod->npages = 0; |
99802a7a MW |
490 | } else { |
491 | pool = dev->prp_page_pool; | |
eca18b23 | 492 | iod->npages = 1; |
99802a7a MW |
493 | } |
494 | ||
69d2b571 | 495 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 496 | if (!prp_list) { |
edd10d33 | 497 | iod->first_dma = dma_addr; |
eca18b23 | 498 | iod->npages = -1; |
69d2b571 | 499 | return false; |
b77954cb | 500 | } |
eca18b23 MW |
501 | list[0] = prp_list; |
502 | iod->first_dma = prp_dma; | |
e025344c SMM |
503 | i = 0; |
504 | for (;;) { | |
1d090624 | 505 | if (i == page_size >> 3) { |
e025344c | 506 | __le64 *old_prp_list = prp_list; |
69d2b571 | 507 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 508 | if (!prp_list) |
69d2b571 | 509 | return false; |
eca18b23 | 510 | list[iod->npages++] = prp_list; |
7523d834 MW |
511 | prp_list[0] = old_prp_list[i - 1]; |
512 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
513 | i = 1; | |
e025344c SMM |
514 | } |
515 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
516 | dma_len -= page_size; |
517 | dma_addr += page_size; | |
518 | length -= page_size; | |
e025344c SMM |
519 | if (length <= 0) |
520 | break; | |
521 | if (dma_len > 0) | |
522 | continue; | |
523 | BUG_ON(dma_len < 0); | |
524 | sg = sg_next(sg); | |
525 | dma_addr = sg_dma_address(sg); | |
526 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
527 | } |
528 | ||
69d2b571 | 529 | return true; |
ff22b54f MW |
530 | } |
531 | ||
f4800d6d | 532 | static int nvme_map_data(struct nvme_dev *dev, struct request *req, |
ba1ca37e | 533 | struct nvme_command *cmnd) |
d29ec824 | 534 | { |
f4800d6d | 535 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
536 | struct request_queue *q = req->q; |
537 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
538 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
539 | int ret = BLK_MQ_RQ_QUEUE_ERROR; | |
d29ec824 | 540 | |
ba1ca37e CH |
541 | sg_init_table(iod->sg, req->nr_phys_segments); |
542 | iod->nents = blk_rq_map_sg(q, req, iod->sg); | |
543 | if (!iod->nents) | |
544 | goto out; | |
d29ec824 | 545 | |
ba1ca37e CH |
546 | ret = BLK_MQ_RQ_QUEUE_BUSY; |
547 | if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir)) | |
548 | goto out; | |
d29ec824 | 549 | |
f4800d6d | 550 | if (!nvme_setup_prps(dev, req, blk_rq_bytes(req))) |
ba1ca37e | 551 | goto out_unmap; |
0e5e4f0e | 552 | |
ba1ca37e CH |
553 | ret = BLK_MQ_RQ_QUEUE_ERROR; |
554 | if (blk_integrity_rq(req)) { | |
555 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
556 | goto out_unmap; | |
0e5e4f0e | 557 | |
bf684057 CH |
558 | sg_init_table(&iod->meta_sg, 1); |
559 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 560 | goto out_unmap; |
0e5e4f0e | 561 | |
ba1ca37e CH |
562 | if (rq_data_dir(req)) |
563 | nvme_dif_remap(req, nvme_dif_prep); | |
0e5e4f0e | 564 | |
bf684057 | 565 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 566 | goto out_unmap; |
d29ec824 | 567 | } |
00df5cb4 | 568 | |
ba1ca37e CH |
569 | cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
570 | cmnd->rw.prp2 = cpu_to_le64(iod->first_dma); | |
571 | if (blk_integrity_rq(req)) | |
bf684057 | 572 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
ba1ca37e | 573 | return BLK_MQ_RQ_QUEUE_OK; |
00df5cb4 | 574 | |
ba1ca37e CH |
575 | out_unmap: |
576 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
577 | out: | |
578 | return ret; | |
00df5cb4 MW |
579 | } |
580 | ||
f4800d6d | 581 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
b60503ba | 582 | { |
f4800d6d | 583 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
584 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
585 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
586 | ||
587 | if (iod->nents) { | |
588 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
589 | if (blk_integrity_rq(req)) { | |
590 | if (!rq_data_dir(req)) | |
591 | nvme_dif_remap(req, nvme_dif_complete); | |
bf684057 | 592 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
e1e5e564 | 593 | } |
e19b127f | 594 | } |
e1e5e564 | 595 | |
f4800d6d | 596 | nvme_free_iod(dev, req); |
d4f6c3ab | 597 | } |
b60503ba | 598 | |
a4aea562 MB |
599 | /* |
600 | * We reuse the small pool to allocate the 16-byte range here as it is not | |
601 | * worth having a special pool for these or additional cases to handle freeing | |
602 | * the iod. | |
603 | */ | |
ba1ca37e | 604 | static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
f4800d6d | 605 | struct request *req, struct nvme_command *cmnd) |
0e5e4f0e | 606 | { |
f4800d6d | 607 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e | 608 | struct nvme_dsm_range *range; |
b60503ba | 609 | |
ba1ca37e CH |
610 | range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC, |
611 | &iod->first_dma); | |
612 | if (!range) | |
613 | return BLK_MQ_RQ_QUEUE_BUSY; | |
f4800d6d | 614 | iod_list(req)[0] = (__le64 *)range; |
ba1ca37e | 615 | iod->npages = 0; |
0e5e4f0e | 616 | |
0e5e4f0e | 617 | range->cattr = cpu_to_le32(0); |
a4aea562 MB |
618 | range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift); |
619 | range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
0e5e4f0e | 620 | |
ba1ca37e CH |
621 | memset(cmnd, 0, sizeof(*cmnd)); |
622 | cmnd->dsm.opcode = nvme_cmd_dsm; | |
623 | cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); | |
624 | cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); | |
625 | cmnd->dsm.nr = 0; | |
626 | cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); | |
627 | return BLK_MQ_RQ_QUEUE_OK; | |
edd10d33 KB |
628 | } |
629 | ||
d29ec824 CH |
630 | /* |
631 | * NOTE: ns is NULL when called on the admin queue. | |
632 | */ | |
a4aea562 MB |
633 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
634 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 635 | { |
a4aea562 MB |
636 | struct nvme_ns *ns = hctx->queue->queuedata; |
637 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 638 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 639 | struct request *req = bd->rq; |
ba1ca37e CH |
640 | struct nvme_command cmnd; |
641 | int ret = BLK_MQ_RQ_QUEUE_OK; | |
edd10d33 | 642 | |
e1e5e564 KB |
643 | /* |
644 | * If formated with metadata, require the block layer provide a buffer | |
645 | * unless this namespace is formated such that the metadata can be | |
646 | * stripped/generated by the controller with PRACT=1. | |
647 | */ | |
d29ec824 | 648 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 KB |
649 | if (!(ns->pi_type && ns->ms == 8) && |
650 | req->cmd_type != REQ_TYPE_DRV_PRIV) { | |
eee417b0 | 651 | blk_mq_end_request(req, -EFAULT); |
e1e5e564 KB |
652 | return BLK_MQ_RQ_QUEUE_OK; |
653 | } | |
654 | } | |
655 | ||
f4800d6d CH |
656 | ret = nvme_init_iod(req, dev); |
657 | if (ret) | |
658 | return ret; | |
a4aea562 | 659 | |
a4aea562 | 660 | if (req->cmd_flags & REQ_DISCARD) { |
f4800d6d | 661 | ret = nvme_setup_discard(nvmeq, ns, req, &cmnd); |
ba1ca37e CH |
662 | } else { |
663 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) | |
664 | memcpy(&cmnd, req->cmd, sizeof(cmnd)); | |
665 | else if (req->cmd_flags & REQ_FLUSH) | |
666 | nvme_setup_flush(ns, &cmnd); | |
667 | else | |
668 | nvme_setup_rw(ns, req, &cmnd); | |
a4aea562 | 669 | |
ba1ca37e | 670 | if (req->nr_phys_segments) |
f4800d6d | 671 | ret = nvme_map_data(dev, req, &cmnd); |
edd10d33 | 672 | } |
a4aea562 | 673 | |
ba1ca37e CH |
674 | if (ret) |
675 | goto out; | |
a4aea562 | 676 | |
ba1ca37e | 677 | cmnd.common.command_id = req->tag; |
aae239e1 | 678 | blk_mq_start_request(req); |
a4aea562 | 679 | |
ba1ca37e | 680 | spin_lock_irq(&nvmeq->q_lock); |
ae1fba20 KB |
681 | if (unlikely(nvmeq->cq_vector < 0)) { |
682 | ret = BLK_MQ_RQ_QUEUE_BUSY; | |
683 | spin_unlock_irq(&nvmeq->q_lock); | |
684 | goto out; | |
685 | } | |
ba1ca37e | 686 | __nvme_submit_cmd(nvmeq, &cmnd); |
a4aea562 MB |
687 | nvme_process_cq(nvmeq); |
688 | spin_unlock_irq(&nvmeq->q_lock); | |
689 | return BLK_MQ_RQ_QUEUE_OK; | |
ba1ca37e | 690 | out: |
f4800d6d | 691 | nvme_free_iod(dev, req); |
ba1ca37e | 692 | return ret; |
b60503ba | 693 | } |
e1e5e564 | 694 | |
eee417b0 CH |
695 | static void nvme_complete_rq(struct request *req) |
696 | { | |
f4800d6d CH |
697 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
698 | struct nvme_dev *dev = iod->nvmeq->dev; | |
eee417b0 | 699 | int error = 0; |
e1e5e564 | 700 | |
f4800d6d | 701 | nvme_unmap_data(dev, req); |
e1e5e564 | 702 | |
eee417b0 CH |
703 | if (unlikely(req->errors)) { |
704 | if (nvme_req_needs_retry(req, req->errors)) { | |
705 | nvme_requeue_req(req); | |
706 | return; | |
e1e5e564 | 707 | } |
1974b1ae | 708 | |
eee417b0 CH |
709 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) |
710 | error = req->errors; | |
711 | else | |
712 | error = nvme_error_status(req->errors); | |
713 | } | |
a4aea562 | 714 | |
f4800d6d | 715 | if (unlikely(iod->aborted)) { |
eee417b0 CH |
716 | dev_warn(dev->dev, |
717 | "completing aborted command with status: %04x\n", | |
718 | req->errors); | |
719 | } | |
a4aea562 | 720 | |
eee417b0 | 721 | blk_mq_end_request(req, error); |
b60503ba MW |
722 | } |
723 | ||
a0fa9647 | 724 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 725 | { |
82123460 | 726 | u16 head, phase; |
b60503ba | 727 | |
b60503ba | 728 | head = nvmeq->cq_head; |
82123460 | 729 | phase = nvmeq->cq_phase; |
b60503ba MW |
730 | |
731 | for (;;) { | |
b60503ba | 732 | struct nvme_completion cqe = nvmeq->cqes[head]; |
adf68f21 | 733 | u16 status = le16_to_cpu(cqe.status); |
eee417b0 | 734 | struct request *req; |
adf68f21 CH |
735 | |
736 | if ((status & 1) != phase) | |
b60503ba MW |
737 | break; |
738 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
739 | if (++head == nvmeq->q_depth) { | |
740 | head = 0; | |
82123460 | 741 | phase = !phase; |
b60503ba | 742 | } |
adf68f21 | 743 | |
a0fa9647 JA |
744 | if (tag && *tag == cqe.command_id) |
745 | *tag = -1; | |
adf68f21 | 746 | |
aae239e1 CH |
747 | if (unlikely(cqe.command_id >= nvmeq->q_depth)) { |
748 | dev_warn(nvmeq->q_dmadev, | |
749 | "invalid id %d completed on queue %d\n", | |
750 | cqe.command_id, le16_to_cpu(cqe.sq_id)); | |
751 | continue; | |
752 | } | |
753 | ||
adf68f21 CH |
754 | /* |
755 | * AEN requests are special as they don't time out and can | |
756 | * survive any kind of queue freeze and often don't respond to | |
757 | * aborts. We don't even bother to allocate a struct request | |
758 | * for them but rather special case them here. | |
759 | */ | |
760 | if (unlikely(nvmeq->qid == 0 && | |
761 | cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { | |
762 | nvme_complete_async_event(nvmeq->dev, &cqe); | |
763 | continue; | |
764 | } | |
765 | ||
eee417b0 CH |
766 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); |
767 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) { | |
768 | u32 result = le32_to_cpu(cqe.result); | |
769 | req->special = (void *)(uintptr_t)result; | |
770 | } | |
771 | blk_mq_complete_request(req, status >> 1); | |
772 | ||
b60503ba MW |
773 | } |
774 | ||
775 | /* If the controller ignores the cq head doorbell and continuously | |
776 | * writes to the queue, it is theoretically possible to wrap around | |
777 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
778 | * requires that 0.1% of your interrupts are handled, so this isn't | |
779 | * a big problem. | |
780 | */ | |
82123460 | 781 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 782 | return; |
b60503ba | 783 | |
604e8c8d KB |
784 | if (likely(nvmeq->cq_vector >= 0)) |
785 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 786 | nvmeq->cq_head = head; |
82123460 | 787 | nvmeq->cq_phase = phase; |
b60503ba | 788 | |
e9539f47 | 789 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
790 | } |
791 | ||
792 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
793 | { | |
794 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
795 | } |
796 | ||
797 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
798 | { |
799 | irqreturn_t result; | |
800 | struct nvme_queue *nvmeq = data; | |
801 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
802 | nvme_process_cq(nvmeq); |
803 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
804 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
805 | spin_unlock(&nvmeq->q_lock); |
806 | return result; | |
807 | } | |
808 | ||
809 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
810 | { | |
811 | struct nvme_queue *nvmeq = data; | |
812 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
813 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
814 | return IRQ_NONE; | |
815 | return IRQ_WAKE_THREAD; | |
816 | } | |
817 | ||
a0fa9647 JA |
818 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
819 | { | |
820 | struct nvme_queue *nvmeq = hctx->driver_data; | |
821 | ||
822 | if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == | |
823 | nvmeq->cq_phase) { | |
824 | spin_lock_irq(&nvmeq->q_lock); | |
825 | __nvme_process_cq(nvmeq, &tag); | |
826 | spin_unlock_irq(&nvmeq->q_lock); | |
827 | ||
828 | if (tag == -1) | |
829 | return 1; | |
830 | } | |
831 | ||
832 | return 0; | |
833 | } | |
834 | ||
adf68f21 | 835 | static void nvme_submit_async_event(struct nvme_dev *dev) |
b60503ba | 836 | { |
a4aea562 | 837 | struct nvme_command c; |
b60503ba | 838 | |
a4aea562 MB |
839 | memset(&c, 0, sizeof(c)); |
840 | c.common.opcode = nvme_admin_async_event; | |
adf68f21 | 841 | c.common.command_id = NVME_AQ_BLKMQ_DEPTH + --dev->ctrl.event_limit; |
3c0cf138 | 842 | |
adf68f21 | 843 | __nvme_submit_cmd(dev->queues[0], &c); |
f705f837 CH |
844 | } |
845 | ||
b60503ba | 846 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 847 | { |
b60503ba MW |
848 | struct nvme_command c; |
849 | ||
850 | memset(&c, 0, sizeof(c)); | |
851 | c.delete_queue.opcode = opcode; | |
852 | c.delete_queue.qid = cpu_to_le16(id); | |
853 | ||
1c63dc66 | 854 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
855 | } |
856 | ||
b60503ba MW |
857 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
858 | struct nvme_queue *nvmeq) | |
859 | { | |
b60503ba MW |
860 | struct nvme_command c; |
861 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
862 | ||
d29ec824 CH |
863 | /* |
864 | * Note: we (ab)use the fact the the prp fields survive if no data | |
865 | * is attached to the request. | |
866 | */ | |
b60503ba MW |
867 | memset(&c, 0, sizeof(c)); |
868 | c.create_cq.opcode = nvme_admin_create_cq; | |
869 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
870 | c.create_cq.cqid = cpu_to_le16(qid); | |
871 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
872 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
873 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
874 | ||
1c63dc66 | 875 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
876 | } |
877 | ||
878 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
879 | struct nvme_queue *nvmeq) | |
880 | { | |
b60503ba MW |
881 | struct nvme_command c; |
882 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
883 | ||
d29ec824 CH |
884 | /* |
885 | * Note: we (ab)use the fact the the prp fields survive if no data | |
886 | * is attached to the request. | |
887 | */ | |
b60503ba MW |
888 | memset(&c, 0, sizeof(c)); |
889 | c.create_sq.opcode = nvme_admin_create_sq; | |
890 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
891 | c.create_sq.sqid = cpu_to_le16(qid); | |
892 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
893 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
894 | c.create_sq.cqid = cpu_to_le16(qid); | |
895 | ||
1c63dc66 | 896 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
897 | } |
898 | ||
899 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
900 | { | |
901 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
902 | } | |
903 | ||
904 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
905 | { | |
906 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
907 | } | |
908 | ||
e7a2a87d | 909 | static void abort_endio(struct request *req, int error) |
bc5fc7e4 | 910 | { |
f4800d6d CH |
911 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
912 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e7a2a87d CH |
913 | u32 result = (u32)(uintptr_t)req->special; |
914 | u16 status = req->errors; | |
e44ac588 | 915 | |
e7a2a87d CH |
916 | dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result); |
917 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); | |
d29ec824 | 918 | |
e7a2a87d | 919 | blk_mq_free_request(req); |
bc5fc7e4 MW |
920 | } |
921 | ||
31c7c7d2 | 922 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 923 | { |
f4800d6d CH |
924 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
925 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 926 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 927 | struct request *abort_req; |
a4aea562 | 928 | struct nvme_command cmd; |
c30341dc | 929 | |
31c7c7d2 | 930 | /* |
fd634f41 CH |
931 | * Shutdown immediately if controller times out while starting. The |
932 | * reset work will see the pci device disabled when it gets the forced | |
933 | * cancellation error. All outstanding requests are completed on | |
934 | * shutdown, so we return BLK_EH_HANDLED. | |
935 | */ | |
936 | if (test_bit(NVME_CTRL_RESETTING, &dev->flags)) { | |
937 | dev_warn(dev->dev, | |
938 | "I/O %d QID %d timeout, disable controller\n", | |
939 | req->tag, nvmeq->qid); | |
a5cdb68c | 940 | nvme_dev_disable(dev, false); |
fd634f41 CH |
941 | req->errors = NVME_SC_CANCELLED; |
942 | return BLK_EH_HANDLED; | |
c30341dc KB |
943 | } |
944 | ||
fd634f41 CH |
945 | /* |
946 | * Shutdown the controller immediately and schedule a reset if the | |
947 | * command was already aborted once before and still hasn't been | |
948 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 949 | */ |
f4800d6d | 950 | if (!nvmeq->qid || iod->aborted) { |
e1569a16 KB |
951 | dev_warn(dev->dev, |
952 | "I/O %d QID %d timeout, reset controller\n", | |
953 | req->tag, nvmeq->qid); | |
a5cdb68c | 954 | nvme_dev_disable(dev, false); |
e1569a16 | 955 | queue_work(nvme_workq, &dev->reset_work); |
c30341dc | 956 | |
e1569a16 KB |
957 | /* |
958 | * Mark the request as handled, since the inline shutdown | |
959 | * forces all outstanding requests to complete. | |
960 | */ | |
961 | req->errors = NVME_SC_CANCELLED; | |
962 | return BLK_EH_HANDLED; | |
c30341dc | 963 | } |
c30341dc | 964 | |
f4800d6d | 965 | iod->aborted = 1; |
c30341dc | 966 | |
e7a2a87d | 967 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 968 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 969 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 970 | } |
a4aea562 | 971 | |
c30341dc KB |
972 | memset(&cmd, 0, sizeof(cmd)); |
973 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 974 | cmd.abort.cid = req->tag; |
c30341dc | 975 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 976 | |
31c7c7d2 CH |
977 | dev_warn(nvmeq->q_dmadev, "I/O %d QID %d timeout, aborting\n", |
978 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
979 | |
980 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
981 | BLK_MQ_REQ_NOWAIT); | |
982 | if (IS_ERR(abort_req)) { | |
983 | atomic_inc(&dev->ctrl.abort_limit); | |
984 | return BLK_EH_RESET_TIMER; | |
985 | } | |
986 | ||
987 | abort_req->timeout = ADMIN_TIMEOUT; | |
988 | abort_req->end_io_data = NULL; | |
989 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
c30341dc | 990 | |
31c7c7d2 CH |
991 | /* |
992 | * The aborted req will be completed on receiving the abort req. | |
993 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
994 | * as the device then is in a faulty state. | |
995 | */ | |
996 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
997 | } |
998 | ||
42483228 | 999 | static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved) |
a09115b2 | 1000 | { |
a4aea562 | 1001 | struct nvme_queue *nvmeq = data; |
aae239e1 | 1002 | int status; |
cef6a948 KB |
1003 | |
1004 | if (!blk_mq_request_started(req)) | |
1005 | return; | |
a09115b2 | 1006 | |
f8e68a7c | 1007 | dev_dbg_ratelimited(nvmeq->q_dmadev, |
aae239e1 | 1008 | "Cancelling I/O %d QID %d\n", req->tag, nvmeq->qid); |
a4aea562 | 1009 | |
1d49c38c | 1010 | status = NVME_SC_ABORT_REQ; |
cef6a948 | 1011 | if (blk_queue_dying(req->q)) |
aae239e1 CH |
1012 | status |= NVME_SC_DNR; |
1013 | blk_mq_complete_request(req, status); | |
a4aea562 | 1014 | } |
22404274 | 1015 | |
a4aea562 MB |
1016 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1017 | { | |
9e866774 MW |
1018 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1019 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1020 | if (nvmeq->sq_cmds) |
1021 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1022 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1023 | kfree(nvmeq); | |
1024 | } | |
1025 | ||
a1a5ef99 | 1026 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1027 | { |
1028 | int i; | |
1029 | ||
a1a5ef99 | 1030 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1031 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1032 | dev->queue_count--; |
a4aea562 | 1033 | dev->queues[i] = NULL; |
f435c282 | 1034 | nvme_free_queue(nvmeq); |
121c7ad4 | 1035 | } |
22404274 KB |
1036 | } |
1037 | ||
4d115420 KB |
1038 | /** |
1039 | * nvme_suspend_queue - put queue into suspended state | |
1040 | * @nvmeq - queue to suspend | |
4d115420 KB |
1041 | */ |
1042 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1043 | { |
2b25d981 | 1044 | int vector; |
b60503ba | 1045 | |
a09115b2 | 1046 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1047 | if (nvmeq->cq_vector == -1) { |
1048 | spin_unlock_irq(&nvmeq->q_lock); | |
1049 | return 1; | |
1050 | } | |
1051 | vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; | |
42f61420 | 1052 | nvmeq->dev->online_queues--; |
2b25d981 | 1053 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1054 | spin_unlock_irq(&nvmeq->q_lock); |
1055 | ||
1c63dc66 | 1056 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
25646264 | 1057 | blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q); |
6df3dbc8 | 1058 | |
aba2080f MW |
1059 | irq_set_affinity_hint(vector, NULL); |
1060 | free_irq(vector, nvmeq); | |
b60503ba | 1061 | |
4d115420 KB |
1062 | return 0; |
1063 | } | |
b60503ba | 1064 | |
4d115420 KB |
1065 | static void nvme_clear_queue(struct nvme_queue *nvmeq) |
1066 | { | |
22404274 | 1067 | spin_lock_irq(&nvmeq->q_lock); |
42483228 KB |
1068 | if (nvmeq->tags && *nvmeq->tags) |
1069 | blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq); | |
22404274 | 1070 | spin_unlock_irq(&nvmeq->q_lock); |
b60503ba MW |
1071 | } |
1072 | ||
a5cdb68c | 1073 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 1074 | { |
a5cdb68c | 1075 | struct nvme_queue *nvmeq = dev->queues[0]; |
4d115420 KB |
1076 | |
1077 | if (!nvmeq) | |
1078 | return; | |
1079 | if (nvme_suspend_queue(nvmeq)) | |
1080 | return; | |
1081 | ||
a5cdb68c KB |
1082 | if (shutdown) |
1083 | nvme_shutdown_ctrl(&dev->ctrl); | |
1084 | else | |
1085 | nvme_disable_ctrl(&dev->ctrl, lo_hi_readq( | |
1086 | dev->bar + NVME_REG_CAP)); | |
07836e65 KB |
1087 | |
1088 | spin_lock_irq(&nvmeq->q_lock); | |
1089 | nvme_process_cq(nvmeq); | |
1090 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1091 | } |
1092 | ||
8ffaadf7 JD |
1093 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1094 | int entry_size) | |
1095 | { | |
1096 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1097 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1098 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1099 | |
1100 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1101 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1102 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1103 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1104 | |
1105 | /* | |
1106 | * Ensure the reduced q_depth is above some threshold where it | |
1107 | * would be better to map queues in system memory with the | |
1108 | * original depth | |
1109 | */ | |
1110 | if (q_depth < 64) | |
1111 | return -ENOMEM; | |
1112 | } | |
1113 | ||
1114 | return q_depth; | |
1115 | } | |
1116 | ||
1117 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1118 | int qid, int depth) | |
1119 | { | |
1120 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1121 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1122 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1123 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1124 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1125 | } else { | |
1126 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1127 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1128 | if (!nvmeq->sq_cmds) | |
1129 | return -ENOMEM; | |
1130 | } | |
1131 | ||
1132 | return 0; | |
1133 | } | |
1134 | ||
b60503ba | 1135 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
2b25d981 | 1136 | int depth) |
b60503ba | 1137 | { |
a4aea562 | 1138 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1139 | if (!nvmeq) |
1140 | return NULL; | |
1141 | ||
e75ec752 | 1142 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1143 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1144 | if (!nvmeq->cqes) |
1145 | goto free_nvmeq; | |
b60503ba | 1146 | |
8ffaadf7 | 1147 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1148 | goto free_cqdma; |
1149 | ||
e75ec752 | 1150 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1151 | nvmeq->dev = dev; |
3193f07b | 1152 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1c63dc66 | 1153 | dev->ctrl.instance, qid); |
b60503ba MW |
1154 | spin_lock_init(&nvmeq->q_lock); |
1155 | nvmeq->cq_head = 0; | |
82123460 | 1156 | nvmeq->cq_phase = 1; |
b80d5ccc | 1157 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1158 | nvmeq->q_depth = depth; |
c30341dc | 1159 | nvmeq->qid = qid; |
758dd7fd | 1160 | nvmeq->cq_vector = -1; |
a4aea562 | 1161 | dev->queues[qid] = nvmeq; |
b60503ba | 1162 | |
36a7e993 JD |
1163 | /* make sure queue descriptor is set before queue count, for kthread */ |
1164 | mb(); | |
1165 | dev->queue_count++; | |
1166 | ||
b60503ba MW |
1167 | return nvmeq; |
1168 | ||
1169 | free_cqdma: | |
e75ec752 | 1170 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1171 | nvmeq->cq_dma_addr); |
1172 | free_nvmeq: | |
1173 | kfree(nvmeq); | |
1174 | return NULL; | |
1175 | } | |
1176 | ||
3001082c MW |
1177 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1178 | const char *name) | |
1179 | { | |
58ffacb5 MW |
1180 | if (use_threaded_interrupts) |
1181 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
481e5bad | 1182 | nvme_irq_check, nvme_irq, IRQF_SHARED, |
58ffacb5 | 1183 | name, nvmeq); |
3001082c | 1184 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
481e5bad | 1185 | IRQF_SHARED, name, nvmeq); |
3001082c MW |
1186 | } |
1187 | ||
22404274 | 1188 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1189 | { |
22404274 | 1190 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1191 | |
7be50e93 | 1192 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1193 | nvmeq->sq_tail = 0; |
1194 | nvmeq->cq_head = 0; | |
1195 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1196 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1197 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1198 | dev->online_queues++; |
7be50e93 | 1199 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1200 | } |
1201 | ||
1202 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1203 | { | |
1204 | struct nvme_dev *dev = nvmeq->dev; | |
1205 | int result; | |
3f85d50b | 1206 | |
2b25d981 | 1207 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1208 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1209 | if (result < 0) | |
22404274 | 1210 | return result; |
b60503ba MW |
1211 | |
1212 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1213 | if (result < 0) | |
1214 | goto release_cq; | |
1215 | ||
3193f07b | 1216 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
b60503ba MW |
1217 | if (result < 0) |
1218 | goto release_sq; | |
1219 | ||
22404274 | 1220 | nvme_init_queue(nvmeq, qid); |
22404274 | 1221 | return result; |
b60503ba MW |
1222 | |
1223 | release_sq: | |
1224 | adapter_delete_sq(dev, qid); | |
1225 | release_cq: | |
1226 | adapter_delete_cq(dev, qid); | |
22404274 | 1227 | return result; |
b60503ba MW |
1228 | } |
1229 | ||
a4aea562 | 1230 | static struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1231 | .queue_rq = nvme_queue_rq, |
eee417b0 | 1232 | .complete = nvme_complete_rq, |
a4aea562 MB |
1233 | .map_queue = blk_mq_map_queue, |
1234 | .init_hctx = nvme_admin_init_hctx, | |
4af0e21c | 1235 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1236 | .init_request = nvme_admin_init_request, |
1237 | .timeout = nvme_timeout, | |
1238 | }; | |
1239 | ||
1240 | static struct blk_mq_ops nvme_mq_ops = { | |
1241 | .queue_rq = nvme_queue_rq, | |
eee417b0 | 1242 | .complete = nvme_complete_rq, |
a4aea562 MB |
1243 | .map_queue = blk_mq_map_queue, |
1244 | .init_hctx = nvme_init_hctx, | |
1245 | .init_request = nvme_init_request, | |
1246 | .timeout = nvme_timeout, | |
a0fa9647 | 1247 | .poll = nvme_poll, |
a4aea562 MB |
1248 | }; |
1249 | ||
ea191d2f KB |
1250 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1251 | { | |
1c63dc66 CH |
1252 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
1253 | blk_cleanup_queue(dev->ctrl.admin_q); | |
ea191d2f KB |
1254 | blk_mq_free_tag_set(&dev->admin_tagset); |
1255 | } | |
1256 | } | |
1257 | ||
a4aea562 MB |
1258 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1259 | { | |
1c63dc66 | 1260 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1261 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1262 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c KB |
1263 | |
1264 | /* | |
1265 | * Subtract one to leave an empty queue entry for 'Full Queue' | |
1266 | * condition. See NVM-Express 1.2 specification, section 4.1.2. | |
1267 | */ | |
1268 | dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; | |
a4aea562 | 1269 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1270 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1271 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1272 | dev->admin_tagset.driver_data = dev; |
1273 | ||
1274 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1275 | return -ENOMEM; | |
1276 | ||
1c63dc66 CH |
1277 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1278 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1279 | blk_mq_free_tag_set(&dev->admin_tagset); |
1280 | return -ENOMEM; | |
1281 | } | |
1c63dc66 | 1282 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1283 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1284 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1285 | return -ENODEV; |
1286 | } | |
0fb59cbc | 1287 | } else |
25646264 | 1288 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); |
a4aea562 MB |
1289 | |
1290 | return 0; | |
1291 | } | |
1292 | ||
8d85fce7 | 1293 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1294 | { |
ba47e386 | 1295 | int result; |
b60503ba | 1296 | u32 aqa; |
7a67cbea | 1297 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1298 | struct nvme_queue *nvmeq; |
1299 | ||
7a67cbea | 1300 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ? |
dfbac8c7 KB |
1301 | NVME_CAP_NSSRC(cap) : 0; |
1302 | ||
7a67cbea CH |
1303 | if (dev->subsystem && |
1304 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1305 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1306 | |
5fd4ce1b | 1307 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1308 | if (result < 0) |
1309 | return result; | |
b60503ba | 1310 | |
a4aea562 | 1311 | nvmeq = dev->queues[0]; |
cd638946 | 1312 | if (!nvmeq) { |
2b25d981 | 1313 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1314 | if (!nvmeq) |
1315 | return -ENOMEM; | |
cd638946 | 1316 | } |
b60503ba MW |
1317 | |
1318 | aqa = nvmeq->q_depth - 1; | |
1319 | aqa |= aqa << 16; | |
1320 | ||
7a67cbea CH |
1321 | writel(aqa, dev->bar + NVME_REG_AQA); |
1322 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1323 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1324 | |
5fd4ce1b | 1325 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1326 | if (result) |
a4aea562 MB |
1327 | goto free_nvmeq; |
1328 | ||
2b25d981 | 1329 | nvmeq->cq_vector = 0; |
3193f07b | 1330 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
758dd7fd JD |
1331 | if (result) { |
1332 | nvmeq->cq_vector = -1; | |
0fb59cbc | 1333 | goto free_nvmeq; |
758dd7fd | 1334 | } |
025c557a | 1335 | |
b60503ba | 1336 | return result; |
a4aea562 | 1337 | |
a4aea562 MB |
1338 | free_nvmeq: |
1339 | nvme_free_queues(dev, 0); | |
1340 | return result; | |
b60503ba MW |
1341 | } |
1342 | ||
1fa6aead MW |
1343 | static int nvme_kthread(void *data) |
1344 | { | |
d4b4ff8e | 1345 | struct nvme_dev *dev, *next; |
1fa6aead MW |
1346 | |
1347 | while (!kthread_should_stop()) { | |
564a232c | 1348 | set_current_state(TASK_INTERRUPTIBLE); |
1fa6aead | 1349 | spin_lock(&dev_list_lock); |
d4b4ff8e | 1350 | list_for_each_entry_safe(dev, next, &dev_list, node) { |
1fa6aead | 1351 | int i; |
7a67cbea | 1352 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
dfbac8c7 | 1353 | |
846cc05f CH |
1354 | /* |
1355 | * Skip controllers currently under reset. | |
1356 | */ | |
1357 | if (work_pending(&dev->reset_work) || work_busy(&dev->reset_work)) | |
1358 | continue; | |
dfbac8c7 KB |
1359 | |
1360 | if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) || | |
1361 | csts & NVME_CSTS_CFS) { | |
846cc05f | 1362 | if (queue_work(nvme_workq, &dev->reset_work)) { |
90667892 CH |
1363 | dev_warn(dev->dev, |
1364 | "Failed status: %x, reset controller\n", | |
7a67cbea | 1365 | readl(dev->bar + NVME_REG_CSTS)); |
90667892 | 1366 | } |
d4b4ff8e KB |
1367 | continue; |
1368 | } | |
1fa6aead | 1369 | for (i = 0; i < dev->queue_count; i++) { |
a4aea562 | 1370 | struct nvme_queue *nvmeq = dev->queues[i]; |
740216fc MW |
1371 | if (!nvmeq) |
1372 | continue; | |
1fa6aead | 1373 | spin_lock_irq(&nvmeq->q_lock); |
bc57a0f7 | 1374 | nvme_process_cq(nvmeq); |
6fccf938 | 1375 | |
adf68f21 CH |
1376 | while (i == 0 && dev->ctrl.event_limit > 0) |
1377 | nvme_submit_async_event(dev); | |
1fa6aead MW |
1378 | spin_unlock_irq(&nvmeq->q_lock); |
1379 | } | |
1380 | } | |
1381 | spin_unlock(&dev_list_lock); | |
acb7aa0d | 1382 | schedule_timeout(round_jiffies_relative(HZ)); |
1fa6aead MW |
1383 | } |
1384 | return 0; | |
1385 | } | |
1386 | ||
749941f2 | 1387 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1388 | { |
a4aea562 | 1389 | unsigned i; |
749941f2 | 1390 | int ret = 0; |
42f61420 | 1391 | |
749941f2 CH |
1392 | for (i = dev->queue_count; i <= dev->max_qid; i++) { |
1393 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) { | |
1394 | ret = -ENOMEM; | |
42f61420 | 1395 | break; |
749941f2 CH |
1396 | } |
1397 | } | |
42f61420 | 1398 | |
749941f2 CH |
1399 | for (i = dev->online_queues; i <= dev->queue_count - 1; i++) { |
1400 | ret = nvme_create_queue(dev->queues[i], i); | |
1401 | if (ret) { | |
2659e57b | 1402 | nvme_free_queues(dev, i); |
42f61420 | 1403 | break; |
2659e57b | 1404 | } |
27e8166c | 1405 | } |
749941f2 CH |
1406 | |
1407 | /* | |
1408 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1409 | * than the desired aount of queues, and even a controller without | |
1410 | * I/O queues an still be used to issue admin commands. This might | |
1411 | * be useful to upgrade a buggy firmware for example. | |
1412 | */ | |
1413 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1414 | } |
1415 | ||
8ffaadf7 JD |
1416 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1417 | { | |
1418 | u64 szu, size, offset; | |
1419 | u32 cmbloc; | |
1420 | resource_size_t bar_size; | |
1421 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1422 | void __iomem *cmb; | |
1423 | dma_addr_t dma_addr; | |
1424 | ||
1425 | if (!use_cmb_sqes) | |
1426 | return NULL; | |
1427 | ||
7a67cbea | 1428 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1429 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1430 | return NULL; | |
1431 | ||
7a67cbea | 1432 | cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 JD |
1433 | |
1434 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1435 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
1436 | offset = szu * NVME_CMB_OFST(cmbloc); | |
1437 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); | |
1438 | ||
1439 | if (offset > bar_size) | |
1440 | return NULL; | |
1441 | ||
1442 | /* | |
1443 | * Controllers may support a CMB size larger than their BAR, | |
1444 | * for example, due to being behind a bridge. Reduce the CMB to | |
1445 | * the reported size of the BAR | |
1446 | */ | |
1447 | if (size > bar_size - offset) | |
1448 | size = bar_size - offset; | |
1449 | ||
1450 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; | |
1451 | cmb = ioremap_wc(dma_addr, size); | |
1452 | if (!cmb) | |
1453 | return NULL; | |
1454 | ||
1455 | dev->cmb_dma_addr = dma_addr; | |
1456 | dev->cmb_size = size; | |
1457 | return cmb; | |
1458 | } | |
1459 | ||
1460 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1461 | { | |
1462 | if (dev->cmb) { | |
1463 | iounmap(dev->cmb); | |
1464 | dev->cmb = NULL; | |
1465 | } | |
1466 | } | |
1467 | ||
9d713c2b KB |
1468 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1469 | { | |
b80d5ccc | 1470 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
1471 | } |
1472 | ||
8d85fce7 | 1473 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1474 | { |
a4aea562 | 1475 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1476 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
42f61420 | 1477 | int result, i, vecs, nr_io_queues, size; |
b60503ba | 1478 | |
42f61420 | 1479 | nr_io_queues = num_possible_cpus(); |
9a0be7ab CH |
1480 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1481 | if (result < 0) | |
1b23484b | 1482 | return result; |
9a0be7ab CH |
1483 | |
1484 | /* | |
1485 | * Degraded controllers might return an error when setting the queue | |
1486 | * count. We still want to be able to bring them online and offer | |
1487 | * access to the admin queue, as that might be only way to fix them up. | |
1488 | */ | |
1489 | if (result > 0) { | |
1490 | dev_err(dev->dev, "Could not set queue count (%d)\n", result); | |
1491 | nr_io_queues = 0; | |
1492 | result = 0; | |
1493 | } | |
b60503ba | 1494 | |
8ffaadf7 JD |
1495 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1496 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1497 | sizeof(struct nvme_command)); | |
1498 | if (result > 0) | |
1499 | dev->q_depth = result; | |
1500 | else | |
1501 | nvme_release_cmb(dev); | |
1502 | } | |
1503 | ||
9d713c2b KB |
1504 | size = db_bar_size(dev, nr_io_queues); |
1505 | if (size > 8192) { | |
f1938f6e | 1506 | iounmap(dev->bar); |
9d713c2b KB |
1507 | do { |
1508 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1509 | if (dev->bar) | |
1510 | break; | |
1511 | if (!--nr_io_queues) | |
1512 | return -ENOMEM; | |
1513 | size = db_bar_size(dev, nr_io_queues); | |
1514 | } while (1); | |
7a67cbea | 1515 | dev->dbs = dev->bar + 4096; |
5a92e700 | 1516 | adminq->q_db = dev->dbs; |
f1938f6e MW |
1517 | } |
1518 | ||
9d713c2b | 1519 | /* Deregister the admin queue's interrupt */ |
3193f07b | 1520 | free_irq(dev->entry[0].vector, adminq); |
9d713c2b | 1521 | |
e32efbfc JA |
1522 | /* |
1523 | * If we enable msix early due to not intx, disable it again before | |
1524 | * setting up the full range we need. | |
1525 | */ | |
1526 | if (!pdev->irq) | |
1527 | pci_disable_msix(pdev); | |
1528 | ||
be577fab | 1529 | for (i = 0; i < nr_io_queues; i++) |
1b23484b | 1530 | dev->entry[i].entry = i; |
be577fab AG |
1531 | vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); |
1532 | if (vecs < 0) { | |
1533 | vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); | |
1534 | if (vecs < 0) { | |
1535 | vecs = 1; | |
1536 | } else { | |
1537 | for (i = 0; i < vecs; i++) | |
1538 | dev->entry[i].vector = i + pdev->irq; | |
fa08a396 RRG |
1539 | } |
1540 | } | |
1541 | ||
063a8096 MW |
1542 | /* |
1543 | * Should investigate if there's a performance win from allocating | |
1544 | * more queues than interrupt vectors; it might allow the submission | |
1545 | * path to scale better, even if the receive path is limited by the | |
1546 | * number of interrupts. | |
1547 | */ | |
1548 | nr_io_queues = vecs; | |
42f61420 | 1549 | dev->max_qid = nr_io_queues; |
063a8096 | 1550 | |
3193f07b | 1551 | result = queue_request_irq(dev, adminq, adminq->irqname); |
758dd7fd JD |
1552 | if (result) { |
1553 | adminq->cq_vector = -1; | |
22404274 | 1554 | goto free_queues; |
758dd7fd | 1555 | } |
1b23484b | 1556 | |
cd638946 | 1557 | /* Free previously allocated queues that are no longer usable */ |
42f61420 | 1558 | nvme_free_queues(dev, nr_io_queues + 1); |
749941f2 | 1559 | return nvme_create_io_queues(dev); |
b60503ba | 1560 | |
22404274 | 1561 | free_queues: |
a1a5ef99 | 1562 | nvme_free_queues(dev, 1); |
22404274 | 1563 | return result; |
b60503ba MW |
1564 | } |
1565 | ||
bda4e0fb | 1566 | static void nvme_set_irq_hints(struct nvme_dev *dev) |
a5768aa8 | 1567 | { |
bda4e0fb KB |
1568 | struct nvme_queue *nvmeq; |
1569 | int i; | |
a5768aa8 | 1570 | |
bda4e0fb KB |
1571 | for (i = 0; i < dev->online_queues; i++) { |
1572 | nvmeq = dev->queues[i]; | |
a5768aa8 | 1573 | |
bda4e0fb KB |
1574 | if (!nvmeq->tags || !(*nvmeq->tags)) |
1575 | continue; | |
a5768aa8 | 1576 | |
bda4e0fb KB |
1577 | irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, |
1578 | blk_mq_tags_cpumask(*nvmeq->tags)); | |
a5768aa8 | 1579 | } |
a5768aa8 KB |
1580 | } |
1581 | ||
a5768aa8 | 1582 | static void nvme_dev_scan(struct work_struct *work) |
a5768aa8 | 1583 | { |
a5768aa8 | 1584 | struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work); |
a5768aa8 KB |
1585 | |
1586 | if (!dev->tagset.tags) | |
1587 | return; | |
5bae7f73 | 1588 | nvme_scan_namespaces(&dev->ctrl); |
bda4e0fb | 1589 | nvme_set_irq_hints(dev); |
a5768aa8 KB |
1590 | } |
1591 | ||
db3cbfff | 1592 | static void nvme_del_queue_end(struct request *req, int error) |
a5768aa8 | 1593 | { |
db3cbfff | 1594 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 1595 | |
db3cbfff KB |
1596 | blk_mq_free_request(req); |
1597 | complete(&nvmeq->dev->ioq_wait); | |
a5768aa8 KB |
1598 | } |
1599 | ||
db3cbfff | 1600 | static void nvme_del_cq_end(struct request *req, int error) |
a5768aa8 | 1601 | { |
db3cbfff | 1602 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 1603 | |
db3cbfff KB |
1604 | if (!error) { |
1605 | unsigned long flags; | |
1606 | ||
1607 | spin_lock_irqsave(&nvmeq->q_lock, flags); | |
1608 | nvme_process_cq(nvmeq); | |
1609 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
a5768aa8 | 1610 | } |
db3cbfff KB |
1611 | |
1612 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
1613 | } |
1614 | ||
db3cbfff | 1615 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 1616 | { |
db3cbfff KB |
1617 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
1618 | struct request *req; | |
1619 | struct nvme_command cmd; | |
bda4e0fb | 1620 | |
db3cbfff KB |
1621 | memset(&cmd, 0, sizeof(cmd)); |
1622 | cmd.delete_queue.opcode = opcode; | |
1623 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 1624 | |
db3cbfff KB |
1625 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT); |
1626 | if (IS_ERR(req)) | |
1627 | return PTR_ERR(req); | |
bda4e0fb | 1628 | |
db3cbfff KB |
1629 | req->timeout = ADMIN_TIMEOUT; |
1630 | req->end_io_data = nvmeq; | |
1631 | ||
1632 | blk_execute_rq_nowait(q, NULL, req, false, | |
1633 | opcode == nvme_admin_delete_cq ? | |
1634 | nvme_del_cq_end : nvme_del_queue_end); | |
1635 | return 0; | |
bda4e0fb KB |
1636 | } |
1637 | ||
db3cbfff | 1638 | static void nvme_disable_io_queues(struct nvme_dev *dev) |
a5768aa8 | 1639 | { |
db3cbfff KB |
1640 | int pass; |
1641 | unsigned long timeout; | |
1642 | u8 opcode = nvme_admin_delete_sq; | |
a5768aa8 | 1643 | |
db3cbfff KB |
1644 | for (pass = 0; pass < 2; pass++) { |
1645 | int sent = 0, i = dev->queue_count - 1; | |
1646 | ||
1647 | reinit_completion(&dev->ioq_wait); | |
1648 | retry: | |
1649 | timeout = ADMIN_TIMEOUT; | |
1650 | for (; i > 0; i--) { | |
1651 | struct nvme_queue *nvmeq = dev->queues[i]; | |
1652 | ||
1653 | if (!pass) | |
1654 | nvme_suspend_queue(nvmeq); | |
1655 | if (nvme_delete_queue(nvmeq, opcode)) | |
1656 | break; | |
1657 | ++sent; | |
1658 | } | |
1659 | while (sent--) { | |
1660 | timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); | |
1661 | if (timeout == 0) | |
1662 | return; | |
1663 | if (i) | |
1664 | goto retry; | |
1665 | } | |
1666 | opcode = nvme_admin_delete_cq; | |
1667 | } | |
a5768aa8 KB |
1668 | } |
1669 | ||
422ef0c7 MW |
1670 | /* |
1671 | * Return: error value if an error occurred setting up the queues or calling | |
1672 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1673 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1674 | * failures should be reported. | |
1675 | */ | |
8d85fce7 | 1676 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1677 | { |
5bae7f73 | 1678 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1679 | dev->tagset.ops = &nvme_mq_ops; |
1680 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1681 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1682 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1683 | dev->tagset.queue_depth = | |
a4aea562 | 1684 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1685 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1686 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1687 | dev->tagset.driver_data = dev; | |
b60503ba | 1688 | |
ffe7704d KB |
1689 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1690 | return 0; | |
5bae7f73 | 1691 | dev->ctrl.tagset = &dev->tagset; |
ffe7704d | 1692 | } |
92f7a162 | 1693 | queue_work(nvme_workq, &dev->scan_work); |
e1e5e564 | 1694 | return 0; |
b60503ba MW |
1695 | } |
1696 | ||
0877cb0d KB |
1697 | static int nvme_dev_map(struct nvme_dev *dev) |
1698 | { | |
42f61420 | 1699 | u64 cap; |
0877cb0d | 1700 | int bars, result = -ENOMEM; |
e75ec752 | 1701 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1702 | |
1703 | if (pci_enable_device_mem(pdev)) | |
1704 | return result; | |
1705 | ||
1706 | dev->entry[0].vector = pdev->irq; | |
1707 | pci_set_master(pdev); | |
1708 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
be7837e8 JA |
1709 | if (!bars) |
1710 | goto disable_pci; | |
1711 | ||
0877cb0d KB |
1712 | if (pci_request_selected_regions(pdev, bars, "nvme")) |
1713 | goto disable_pci; | |
1714 | ||
e75ec752 CH |
1715 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1716 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1717 | goto disable; |
0877cb0d | 1718 | |
0877cb0d KB |
1719 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
1720 | if (!dev->bar) | |
1721 | goto disable; | |
e32efbfc | 1722 | |
7a67cbea | 1723 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 KB |
1724 | result = -ENODEV; |
1725 | goto unmap; | |
1726 | } | |
e32efbfc JA |
1727 | |
1728 | /* | |
1729 | * Some devices don't advertse INTx interrupts, pre-enable a single | |
1730 | * MSIX vec for setup. We'll adjust this later. | |
1731 | */ | |
1732 | if (!pdev->irq) { | |
1733 | result = pci_enable_msix(pdev, dev->entry, 1); | |
1734 | if (result < 0) | |
1735 | goto unmap; | |
1736 | } | |
1737 | ||
7a67cbea CH |
1738 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1739 | ||
42f61420 KB |
1740 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1741 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea | 1742 | dev->dbs = dev->bar + 4096; |
1f390c1f SG |
1743 | |
1744 | /* | |
1745 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
1746 | * some MacBook7,1 to avoid controller resets and data loss. | |
1747 | */ | |
1748 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
1749 | dev->q_depth = 2; | |
1750 | dev_warn(dev->dev, "detected Apple NVMe controller, set " | |
1751 | "queue depth=%u to work around controller resets\n", | |
1752 | dev->q_depth); | |
1753 | } | |
1754 | ||
7a67cbea | 1755 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2)) |
8ffaadf7 | 1756 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d | 1757 | |
a0a3408e KB |
1758 | pci_enable_pcie_error_reporting(pdev); |
1759 | pci_save_state(pdev); | |
0877cb0d KB |
1760 | return 0; |
1761 | ||
0e53d180 KB |
1762 | unmap: |
1763 | iounmap(dev->bar); | |
1764 | dev->bar = NULL; | |
0877cb0d KB |
1765 | disable: |
1766 | pci_release_regions(pdev); | |
1767 | disable_pci: | |
1768 | pci_disable_device(pdev); | |
1769 | return result; | |
1770 | } | |
1771 | ||
1772 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
1773 | { | |
e75ec752 CH |
1774 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1775 | ||
1776 | if (pdev->msi_enabled) | |
1777 | pci_disable_msi(pdev); | |
1778 | else if (pdev->msix_enabled) | |
1779 | pci_disable_msix(pdev); | |
0877cb0d KB |
1780 | |
1781 | if (dev->bar) { | |
1782 | iounmap(dev->bar); | |
1783 | dev->bar = NULL; | |
e75ec752 | 1784 | pci_release_regions(pdev); |
0877cb0d KB |
1785 | } |
1786 | ||
a0a3408e KB |
1787 | if (pci_is_enabled(pdev)) { |
1788 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 1789 | pci_disable_device(pdev); |
4d115420 | 1790 | } |
4d115420 KB |
1791 | } |
1792 | ||
7385014c | 1793 | static int nvme_dev_list_add(struct nvme_dev *dev) |
4d115420 | 1794 | { |
7385014c | 1795 | bool start_thread = false; |
4d115420 | 1796 | |
7385014c CH |
1797 | spin_lock(&dev_list_lock); |
1798 | if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) { | |
1799 | start_thread = true; | |
1800 | nvme_thread = NULL; | |
4d115420 | 1801 | } |
7385014c CH |
1802 | list_add(&dev->node, &dev_list); |
1803 | spin_unlock(&dev_list_lock); | |
4d115420 | 1804 | |
7385014c CH |
1805 | if (start_thread) { |
1806 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
1807 | wake_up_all(&nvme_kthread_wait); | |
1808 | } else | |
1809 | wait_event_killable(nvme_kthread_wait, nvme_thread); | |
4d115420 | 1810 | |
7385014c CH |
1811 | if (IS_ERR_OR_NULL(nvme_thread)) |
1812 | return nvme_thread ? PTR_ERR(nvme_thread) : -EINTR; | |
1813 | ||
1814 | return 0; | |
4d115420 KB |
1815 | } |
1816 | ||
b9afca3e DM |
1817 | /* |
1818 | * Remove the node from the device list and check | |
1819 | * for whether or not we need to stop the nvme_thread. | |
1820 | */ | |
1821 | static void nvme_dev_list_remove(struct nvme_dev *dev) | |
1822 | { | |
1823 | struct task_struct *tmp = NULL; | |
1824 | ||
1825 | spin_lock(&dev_list_lock); | |
1826 | list_del_init(&dev->node); | |
1827 | if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) { | |
1828 | tmp = nvme_thread; | |
1829 | nvme_thread = NULL; | |
1830 | } | |
1831 | spin_unlock(&dev_list_lock); | |
1832 | ||
1833 | if (tmp) | |
1834 | kthread_stop(tmp); | |
1835 | } | |
1836 | ||
a5cdb68c | 1837 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 1838 | { |
22404274 | 1839 | int i; |
7c1b2450 | 1840 | u32 csts = -1; |
22404274 | 1841 | |
b9afca3e | 1842 | nvme_dev_list_remove(dev); |
1fa6aead | 1843 | |
77bf25ea | 1844 | mutex_lock(&dev->shutdown_lock); |
c9d3bf88 | 1845 | if (dev->bar) { |
25646264 | 1846 | nvme_stop_queues(&dev->ctrl); |
7a67cbea | 1847 | csts = readl(dev->bar + NVME_REG_CSTS); |
c9d3bf88 | 1848 | } |
7c1b2450 | 1849 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
4d115420 | 1850 | for (i = dev->queue_count - 1; i >= 0; i--) { |
a4aea562 | 1851 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 | 1852 | nvme_suspend_queue(nvmeq); |
4d115420 KB |
1853 | } |
1854 | } else { | |
1855 | nvme_disable_io_queues(dev); | |
a5cdb68c | 1856 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 1857 | } |
f0b50732 | 1858 | nvme_dev_unmap(dev); |
07836e65 KB |
1859 | |
1860 | for (i = dev->queue_count - 1; i >= 0; i--) | |
1861 | nvme_clear_queue(dev->queues[i]); | |
77bf25ea | 1862 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
1863 | } |
1864 | ||
091b6092 MW |
1865 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1866 | { | |
e75ec752 | 1867 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
1868 | PAGE_SIZE, PAGE_SIZE, 0); |
1869 | if (!dev->prp_page_pool) | |
1870 | return -ENOMEM; | |
1871 | ||
99802a7a | 1872 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 1873 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
1874 | 256, 256, 0); |
1875 | if (!dev->prp_small_pool) { | |
1876 | dma_pool_destroy(dev->prp_page_pool); | |
1877 | return -ENOMEM; | |
1878 | } | |
091b6092 MW |
1879 | return 0; |
1880 | } | |
1881 | ||
1882 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1883 | { | |
1884 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1885 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1886 | } |
1887 | ||
1673f1f0 | 1888 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 1889 | { |
1673f1f0 | 1890 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 1891 | |
e75ec752 | 1892 | put_device(dev->dev); |
4af0e21c KB |
1893 | if (dev->tagset.tags) |
1894 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
1895 | if (dev->ctrl.admin_q) |
1896 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 KB |
1897 | kfree(dev->queues); |
1898 | kfree(dev->entry); | |
1899 | kfree(dev); | |
1900 | } | |
1901 | ||
fd634f41 | 1902 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 1903 | { |
fd634f41 | 1904 | struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); |
3cf519b5 | 1905 | int result; |
5e82e952 | 1906 | |
fd634f41 CH |
1907 | if (WARN_ON(test_bit(NVME_CTRL_RESETTING, &dev->flags))) |
1908 | goto out; | |
5e82e952 | 1909 | |
fd634f41 CH |
1910 | /* |
1911 | * If we're called to reset a live controller first shut it down before | |
1912 | * moving on. | |
1913 | */ | |
1914 | if (dev->bar) | |
a5cdb68c | 1915 | nvme_dev_disable(dev, false); |
5e82e952 | 1916 | |
fd634f41 | 1917 | set_bit(NVME_CTRL_RESETTING, &dev->flags); |
f0b50732 KB |
1918 | |
1919 | result = nvme_dev_map(dev); | |
1920 | if (result) | |
3cf519b5 | 1921 | goto out; |
f0b50732 KB |
1922 | |
1923 | result = nvme_configure_admin_queue(dev); | |
1924 | if (result) | |
1925 | goto unmap; | |
1926 | ||
a4aea562 | 1927 | nvme_init_queue(dev->queues[0], 0); |
0fb59cbc KB |
1928 | result = nvme_alloc_admin_tags(dev); |
1929 | if (result) | |
1930 | goto disable; | |
b9afca3e | 1931 | |
ce4541f4 CH |
1932 | result = nvme_init_identify(&dev->ctrl); |
1933 | if (result) | |
1934 | goto free_tags; | |
1935 | ||
f0b50732 | 1936 | result = nvme_setup_io_queues(dev); |
badc34d4 | 1937 | if (result) |
0fb59cbc | 1938 | goto free_tags; |
f0b50732 | 1939 | |
adf68f21 | 1940 | dev->ctrl.event_limit = NVME_NR_AEN_COMMANDS; |
3cf519b5 | 1941 | |
7385014c CH |
1942 | result = nvme_dev_list_add(dev); |
1943 | if (result) | |
1944 | goto remove; | |
3cf519b5 | 1945 | |
2659e57b CH |
1946 | /* |
1947 | * Keep the controller around but remove all namespaces if we don't have | |
1948 | * any working I/O queue. | |
1949 | */ | |
3cf519b5 CH |
1950 | if (dev->online_queues < 2) { |
1951 | dev_warn(dev->dev, "IO queues not created\n"); | |
5bae7f73 | 1952 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 | 1953 | } else { |
25646264 | 1954 | nvme_start_queues(&dev->ctrl); |
3cf519b5 CH |
1955 | nvme_dev_add(dev); |
1956 | } | |
1957 | ||
fd634f41 | 1958 | clear_bit(NVME_CTRL_RESETTING, &dev->flags); |
3cf519b5 | 1959 | return; |
f0b50732 | 1960 | |
7385014c CH |
1961 | remove: |
1962 | nvme_dev_list_remove(dev); | |
0fb59cbc KB |
1963 | free_tags: |
1964 | nvme_dev_remove_admin(dev); | |
1c63dc66 CH |
1965 | blk_put_queue(dev->ctrl.admin_q); |
1966 | dev->ctrl.admin_q = NULL; | |
4af0e21c | 1967 | dev->queues[0]->tags = NULL; |
f0b50732 | 1968 | disable: |
a5cdb68c | 1969 | nvme_disable_admin_queue(dev, false); |
f0b50732 KB |
1970 | unmap: |
1971 | nvme_dev_unmap(dev); | |
3cf519b5 | 1972 | out: |
5c8809e6 | 1973 | nvme_remove_dead_ctrl(dev); |
f0b50732 KB |
1974 | } |
1975 | ||
5c8809e6 | 1976 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 1977 | { |
5c8809e6 | 1978 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 1979 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 KB |
1980 | |
1981 | if (pci_get_drvdata(pdev)) | |
c81f4975 | 1982 | pci_stop_and_remove_bus_device_locked(pdev); |
1673f1f0 | 1983 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
1984 | } |
1985 | ||
5c8809e6 | 1986 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev) |
de3eff2b | 1987 | { |
5c8809e6 | 1988 | dev_warn(dev->dev, "Removing after probe failure\n"); |
1673f1f0 | 1989 | kref_get(&dev->ctrl.kref); |
5c8809e6 | 1990 | if (!schedule_work(&dev->remove_work)) |
1673f1f0 | 1991 | nvme_put_ctrl(&dev->ctrl); |
de3eff2b KB |
1992 | } |
1993 | ||
4cc06521 | 1994 | static int nvme_reset(struct nvme_dev *dev) |
9a6b9458 | 1995 | { |
1c63dc66 | 1996 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 | 1997 | return -ENODEV; |
ffe7704d | 1998 | |
846cc05f CH |
1999 | if (!queue_work(nvme_workq, &dev->reset_work)) |
2000 | return -EBUSY; | |
ffe7704d | 2001 | |
846cc05f | 2002 | flush_work(&dev->reset_work); |
846cc05f | 2003 | return 0; |
9a6b9458 KB |
2004 | } |
2005 | ||
1c63dc66 | 2006 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 2007 | { |
1c63dc66 | 2008 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 2009 | return 0; |
9ca97374 TH |
2010 | } |
2011 | ||
5fd4ce1b | 2012 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 2013 | { |
5fd4ce1b CH |
2014 | writel(val, to_nvme_dev(ctrl)->bar + off); |
2015 | return 0; | |
2016 | } | |
4cc06521 | 2017 | |
7fd8930f CH |
2018 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2019 | { | |
2020 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
2021 | return 0; | |
4cc06521 KB |
2022 | } |
2023 | ||
5bae7f73 | 2024 | static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl) |
4cc06521 | 2025 | { |
5bae7f73 | 2026 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
4cc06521 | 2027 | |
5bae7f73 CH |
2028 | return !dev->bar || dev->online_queues < 2; |
2029 | } | |
4cc06521 | 2030 | |
f3ca80fc CH |
2031 | static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) |
2032 | { | |
2033 | return nvme_reset(to_nvme_dev(ctrl)); | |
4cc06521 | 2034 | } |
f3ca80fc | 2035 | |
1c63dc66 CH |
2036 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
2037 | .reg_read32 = nvme_pci_reg_read32, | |
5fd4ce1b | 2038 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 2039 | .reg_read64 = nvme_pci_reg_read64, |
5bae7f73 | 2040 | .io_incapable = nvme_pci_io_incapable, |
f3ca80fc | 2041 | .reset_ctrl = nvme_pci_reset_ctrl, |
1673f1f0 | 2042 | .free_ctrl = nvme_pci_free_ctrl, |
1c63dc66 | 2043 | }; |
4cc06521 | 2044 | |
8d85fce7 | 2045 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2046 | { |
a4aea562 | 2047 | int node, result = -ENOMEM; |
b60503ba MW |
2048 | struct nvme_dev *dev; |
2049 | ||
a4aea562 MB |
2050 | node = dev_to_node(&pdev->dev); |
2051 | if (node == NUMA_NO_NODE) | |
2052 | set_dev_node(&pdev->dev, 0); | |
2053 | ||
2054 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2055 | if (!dev) |
2056 | return -ENOMEM; | |
a4aea562 MB |
2057 | dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), |
2058 | GFP_KERNEL, node); | |
b60503ba MW |
2059 | if (!dev->entry) |
2060 | goto free; | |
a4aea562 MB |
2061 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2062 | GFP_KERNEL, node); | |
b60503ba MW |
2063 | if (!dev->queues) |
2064 | goto free; | |
2065 | ||
e75ec752 | 2066 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2067 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2068 | |
f3ca80fc CH |
2069 | INIT_LIST_HEAD(&dev->node); |
2070 | INIT_WORK(&dev->scan_work, nvme_dev_scan); | |
f3ca80fc | 2071 | INIT_WORK(&dev->reset_work, nvme_reset_work); |
5c8809e6 | 2072 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
77bf25ea | 2073 | mutex_init(&dev->shutdown_lock); |
db3cbfff | 2074 | init_completion(&dev->ioq_wait); |
b60503ba | 2075 | |
091b6092 MW |
2076 | result = nvme_setup_prp_pools(dev); |
2077 | if (result) | |
a96d4f5c | 2078 | goto put_pci; |
4cc06521 | 2079 | |
f3ca80fc CH |
2080 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
2081 | id->driver_data); | |
4cc06521 | 2082 | if (result) |
2e1d8448 | 2083 | goto release_pools; |
740216fc | 2084 | |
92f7a162 | 2085 | queue_work(nvme_workq, &dev->reset_work); |
b60503ba MW |
2086 | return 0; |
2087 | ||
0877cb0d | 2088 | release_pools: |
091b6092 | 2089 | nvme_release_prp_pools(dev); |
a96d4f5c | 2090 | put_pci: |
e75ec752 | 2091 | put_device(dev->dev); |
b60503ba MW |
2092 | free: |
2093 | kfree(dev->queues); | |
2094 | kfree(dev->entry); | |
2095 | kfree(dev); | |
2096 | return result; | |
2097 | } | |
2098 | ||
f0d54a54 KB |
2099 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
2100 | { | |
a6739479 | 2101 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 2102 | |
a6739479 | 2103 | if (prepare) |
a5cdb68c | 2104 | nvme_dev_disable(dev, false); |
a6739479 | 2105 | else |
92f7a162 | 2106 | queue_work(nvme_workq, &dev->reset_work); |
f0d54a54 KB |
2107 | } |
2108 | ||
09ece142 KB |
2109 | static void nvme_shutdown(struct pci_dev *pdev) |
2110 | { | |
2111 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
a5cdb68c | 2112 | nvme_dev_disable(dev, true); |
09ece142 KB |
2113 | } |
2114 | ||
8d85fce7 | 2115 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2116 | { |
2117 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 2118 | |
9a6b9458 | 2119 | pci_set_drvdata(pdev, NULL); |
a5768aa8 | 2120 | flush_work(&dev->scan_work); |
5bae7f73 | 2121 | nvme_remove_namespaces(&dev->ctrl); |
53029b04 | 2122 | nvme_uninit_ctrl(&dev->ctrl); |
a5cdb68c | 2123 | nvme_dev_disable(dev, true); |
ff23a2a1 | 2124 | flush_work(&dev->reset_work); |
a4aea562 | 2125 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2126 | nvme_free_queues(dev, 0); |
8ffaadf7 | 2127 | nvme_release_cmb(dev); |
9a6b9458 | 2128 | nvme_release_prp_pools(dev); |
1673f1f0 | 2129 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2130 | } |
2131 | ||
671a6018 | 2132 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2133 | static int nvme_suspend(struct device *dev) |
2134 | { | |
2135 | struct pci_dev *pdev = to_pci_dev(dev); | |
2136 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2137 | ||
a5cdb68c | 2138 | nvme_dev_disable(ndev, true); |
cd638946 KB |
2139 | return 0; |
2140 | } | |
2141 | ||
2142 | static int nvme_resume(struct device *dev) | |
2143 | { | |
2144 | struct pci_dev *pdev = to_pci_dev(dev); | |
2145 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2146 | |
92f7a162 | 2147 | queue_work(nvme_workq, &ndev->reset_work); |
9a6b9458 | 2148 | return 0; |
cd638946 | 2149 | } |
671a6018 | 2150 | #endif |
cd638946 KB |
2151 | |
2152 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2153 | |
a0a3408e KB |
2154 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2155 | pci_channel_state_t state) | |
2156 | { | |
2157 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2158 | ||
2159 | /* | |
2160 | * A frozen channel requires a reset. When detected, this method will | |
2161 | * shutdown the controller to quiesce. The controller will be restarted | |
2162 | * after the slot reset through driver's slot_reset callback. | |
2163 | */ | |
2164 | dev_warn(&pdev->dev, "error detected: state:%d\n", state); | |
2165 | switch (state) { | |
2166 | case pci_channel_io_normal: | |
2167 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2168 | case pci_channel_io_frozen: | |
a5cdb68c | 2169 | nvme_dev_disable(dev, false); |
a0a3408e KB |
2170 | return PCI_ERS_RESULT_NEED_RESET; |
2171 | case pci_channel_io_perm_failure: | |
2172 | return PCI_ERS_RESULT_DISCONNECT; | |
2173 | } | |
2174 | return PCI_ERS_RESULT_NEED_RESET; | |
2175 | } | |
2176 | ||
2177 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2178 | { | |
2179 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2180 | ||
2181 | dev_info(&pdev->dev, "restart after slot reset\n"); | |
2182 | pci_restore_state(pdev); | |
2183 | queue_work(nvme_workq, &dev->reset_work); | |
2184 | return PCI_ERS_RESULT_RECOVERED; | |
2185 | } | |
2186 | ||
2187 | static void nvme_error_resume(struct pci_dev *pdev) | |
2188 | { | |
2189 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2190 | } | |
2191 | ||
1d352035 | 2192 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2193 | .error_detected = nvme_error_detected, |
b60503ba MW |
2194 | .slot_reset = nvme_slot_reset, |
2195 | .resume = nvme_error_resume, | |
f0d54a54 | 2196 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2197 | }; |
2198 | ||
2199 | /* Move to pci_ids.h later */ | |
2200 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
2201 | ||
6eb0d698 | 2202 | static const struct pci_device_id nvme_id_table[] = { |
106198ed CH |
2203 | { PCI_VDEVICE(INTEL, 0x0953), |
2204 | .driver_data = NVME_QUIRK_STRIPE_SIZE, }, | |
540c801c KB |
2205 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2206 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
b60503ba | 2207 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2208 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
b60503ba MW |
2209 | { 0, } |
2210 | }; | |
2211 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2212 | ||
2213 | static struct pci_driver nvme_driver = { | |
2214 | .name = "nvme", | |
2215 | .id_table = nvme_id_table, | |
2216 | .probe = nvme_probe, | |
8d85fce7 | 2217 | .remove = nvme_remove, |
09ece142 | 2218 | .shutdown = nvme_shutdown, |
cd638946 KB |
2219 | .driver = { |
2220 | .pm = &nvme_dev_pm_ops, | |
2221 | }, | |
b60503ba MW |
2222 | .err_handler = &nvme_err_handler, |
2223 | }; | |
2224 | ||
2225 | static int __init nvme_init(void) | |
2226 | { | |
0ac13140 | 2227 | int result; |
1fa6aead | 2228 | |
b9afca3e | 2229 | init_waitqueue_head(&nvme_kthread_wait); |
b60503ba | 2230 | |
92f7a162 | 2231 | nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0); |
9a6b9458 | 2232 | if (!nvme_workq) |
b9afca3e | 2233 | return -ENOMEM; |
9a6b9458 | 2234 | |
5bae7f73 | 2235 | result = nvme_core_init(); |
5c42ea16 | 2236 | if (result < 0) |
9a6b9458 | 2237 | goto kill_workq; |
b3fffdef | 2238 | |
f3db22fe KB |
2239 | result = pci_register_driver(&nvme_driver); |
2240 | if (result) | |
f3ca80fc | 2241 | goto core_exit; |
1fa6aead | 2242 | return 0; |
b60503ba | 2243 | |
f3ca80fc | 2244 | core_exit: |
5bae7f73 | 2245 | nvme_core_exit(); |
9a6b9458 KB |
2246 | kill_workq: |
2247 | destroy_workqueue(nvme_workq); | |
b60503ba MW |
2248 | return result; |
2249 | } | |
2250 | ||
2251 | static void __exit nvme_exit(void) | |
2252 | { | |
2253 | pci_unregister_driver(&nvme_driver); | |
5bae7f73 | 2254 | nvme_core_exit(); |
9a6b9458 | 2255 | destroy_workqueue(nvme_workq); |
b9afca3e | 2256 | BUG_ON(nvme_thread && !IS_ERR(nvme_thread)); |
21bd78bc | 2257 | _nvme_check_size(); |
b60503ba MW |
2258 | } |
2259 | ||
2260 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2261 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2262 | MODULE_VERSION("1.0"); |
b60503ba MW |
2263 | module_init(nvme_init); |
2264 | module_exit(nvme_exit); |