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Commit | Line | Data |
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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
a0a3408e | 15 | #include <linux/aer.h> |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
dca51e78 | 19 | #include <linux/blk-mq-pci.h> |
ff5350a8 | 20 | #include <linux/dmi.h> |
b60503ba MW |
21 | #include <linux/init.h> |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/io.h> | |
b60503ba MW |
24 | #include <linux/mm.h> |
25 | #include <linux/module.h> | |
77bf25ea | 26 | #include <linux/mutex.h> |
b60503ba | 27 | #include <linux/pci.h> |
be7b6275 | 28 | #include <linux/poison.h> |
e1e5e564 | 29 | #include <linux/t10-pi.h> |
2d55cd5f | 30 | #include <linux/timer.h> |
b60503ba | 31 | #include <linux/types.h> |
2f8e2c87 | 32 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 33 | #include <asm/unaligned.h> |
a98e58e5 | 34 | #include <linux/sed-opal.h> |
797a796a | 35 | |
f11bb3e2 CH |
36 | #include "nvme.h" |
37 | ||
b60503ba MW |
38 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
39 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
c965809c | 40 | |
adf68f21 CH |
41 | /* |
42 | * We handle AEN commands ourselves and don't even let the | |
43 | * block layer know about them. | |
44 | */ | |
f866fc42 | 45 | #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS) |
9d43cf64 | 46 | |
58ffacb5 MW |
47 | static int use_threaded_interrupts; |
48 | module_param(use_threaded_interrupts, int, 0); | |
49 | ||
8ffaadf7 JD |
50 | static bool use_cmb_sqes = true; |
51 | module_param(use_cmb_sqes, bool, 0644); | |
52 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
53 | ||
87ad72a5 CH |
54 | static unsigned int max_host_mem_size_mb = 128; |
55 | module_param(max_host_mem_size_mb, uint, 0444); | |
56 | MODULE_PARM_DESC(max_host_mem_size_mb, | |
57 | "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); | |
1fa6aead | 58 | |
b27c1e68 | 59 | static int io_queue_depth_set(const char *val, const struct kernel_param *kp); |
60 | static const struct kernel_param_ops io_queue_depth_ops = { | |
61 | .set = io_queue_depth_set, | |
62 | .get = param_get_int, | |
63 | }; | |
64 | ||
65 | static int io_queue_depth = 1024; | |
66 | module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); | |
67 | MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); | |
68 | ||
1c63dc66 CH |
69 | struct nvme_dev; |
70 | struct nvme_queue; | |
b3fffdef | 71 | |
a0fa9647 | 72 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
a5cdb68c | 73 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
d4b4ff8e | 74 | |
1c63dc66 CH |
75 | /* |
76 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
77 | */ | |
78 | struct nvme_dev { | |
1c63dc66 CH |
79 | struct nvme_queue **queues; |
80 | struct blk_mq_tag_set tagset; | |
81 | struct blk_mq_tag_set admin_tagset; | |
82 | u32 __iomem *dbs; | |
83 | struct device *dev; | |
84 | struct dma_pool *prp_page_pool; | |
85 | struct dma_pool *prp_small_pool; | |
1c63dc66 CH |
86 | unsigned online_queues; |
87 | unsigned max_qid; | |
88 | int q_depth; | |
89 | u32 db_stride; | |
1c63dc66 | 90 | void __iomem *bar; |
97f6ef64 | 91 | unsigned long bar_mapped_size; |
5c8809e6 | 92 | struct work_struct remove_work; |
77bf25ea | 93 | struct mutex shutdown_lock; |
1c63dc66 | 94 | bool subsystem; |
1c63dc66 CH |
95 | void __iomem *cmb; |
96 | dma_addr_t cmb_dma_addr; | |
97 | u64 cmb_size; | |
98 | u32 cmbsz; | |
202021c1 | 99 | u32 cmbloc; |
1c63dc66 | 100 | struct nvme_ctrl ctrl; |
db3cbfff | 101 | struct completion ioq_wait; |
87ad72a5 CH |
102 | |
103 | /* shadow doorbell buffer support: */ | |
f9f38e33 HK |
104 | u32 *dbbuf_dbs; |
105 | dma_addr_t dbbuf_dbs_dma_addr; | |
106 | u32 *dbbuf_eis; | |
107 | dma_addr_t dbbuf_eis_dma_addr; | |
87ad72a5 CH |
108 | |
109 | /* host memory buffer support: */ | |
110 | u64 host_mem_size; | |
111 | u32 nr_host_mem_descs; | |
112 | struct nvme_host_mem_buf_desc *host_mem_descs; | |
113 | void **host_mem_desc_bufs; | |
4d115420 | 114 | }; |
1fa6aead | 115 | |
b27c1e68 | 116 | static int io_queue_depth_set(const char *val, const struct kernel_param *kp) |
117 | { | |
118 | int n = 0, ret; | |
119 | ||
120 | ret = kstrtoint(val, 10, &n); | |
121 | if (ret != 0 || n < 2) | |
122 | return -EINVAL; | |
123 | ||
124 | return param_set_int(val, kp); | |
125 | } | |
126 | ||
f9f38e33 HK |
127 | static inline unsigned int sq_idx(unsigned int qid, u32 stride) |
128 | { | |
129 | return qid * 2 * stride; | |
130 | } | |
131 | ||
132 | static inline unsigned int cq_idx(unsigned int qid, u32 stride) | |
133 | { | |
134 | return (qid * 2 + 1) * stride; | |
135 | } | |
136 | ||
1c63dc66 CH |
137 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
138 | { | |
139 | return container_of(ctrl, struct nvme_dev, ctrl); | |
140 | } | |
141 | ||
b60503ba MW |
142 | /* |
143 | * An NVM Express queue. Each device has at least two (one for admin | |
144 | * commands and one for I/O commands). | |
145 | */ | |
146 | struct nvme_queue { | |
147 | struct device *q_dmadev; | |
091b6092 | 148 | struct nvme_dev *dev; |
b60503ba MW |
149 | spinlock_t q_lock; |
150 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 151 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 152 | volatile struct nvme_completion *cqes; |
42483228 | 153 | struct blk_mq_tags **tags; |
b60503ba MW |
154 | dma_addr_t sq_dma_addr; |
155 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
156 | u32 __iomem *q_db; |
157 | u16 q_depth; | |
6222d172 | 158 | s16 cq_vector; |
b60503ba MW |
159 | u16 sq_tail; |
160 | u16 cq_head; | |
c30341dc | 161 | u16 qid; |
e9539f47 MW |
162 | u8 cq_phase; |
163 | u8 cqe_seen; | |
f9f38e33 HK |
164 | u32 *dbbuf_sq_db; |
165 | u32 *dbbuf_cq_db; | |
166 | u32 *dbbuf_sq_ei; | |
167 | u32 *dbbuf_cq_ei; | |
b60503ba MW |
168 | }; |
169 | ||
71bd150c CH |
170 | /* |
171 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
172 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 173 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
174 | * allocated to store the PRP list. |
175 | */ | |
176 | struct nvme_iod { | |
d49187e9 | 177 | struct nvme_request req; |
f4800d6d CH |
178 | struct nvme_queue *nvmeq; |
179 | int aborted; | |
71bd150c | 180 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
181 | int nents; /* Used in scatterlist */ |
182 | int length; /* Of data, in bytes */ | |
183 | dma_addr_t first_dma; | |
bf684057 | 184 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
185 | struct scatterlist *sg; |
186 | struct scatterlist inline_sg[0]; | |
b60503ba MW |
187 | }; |
188 | ||
189 | /* | |
190 | * Check we didin't inadvertently grow the command struct | |
191 | */ | |
192 | static inline void _nvme_check_size(void) | |
193 | { | |
194 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
195 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
196 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
197 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
198 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 199 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 200 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba | 201 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
0add5e8e JT |
202 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); |
203 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); | |
b60503ba | 204 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); |
6ecec745 | 205 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
f9f38e33 HK |
206 | BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); |
207 | } | |
208 | ||
209 | static inline unsigned int nvme_dbbuf_size(u32 stride) | |
210 | { | |
211 | return ((num_possible_cpus() + 1) * 8 * stride); | |
212 | } | |
213 | ||
214 | static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) | |
215 | { | |
216 | unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); | |
217 | ||
218 | if (dev->dbbuf_dbs) | |
219 | return 0; | |
220 | ||
221 | dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, | |
222 | &dev->dbbuf_dbs_dma_addr, | |
223 | GFP_KERNEL); | |
224 | if (!dev->dbbuf_dbs) | |
225 | return -ENOMEM; | |
226 | dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, | |
227 | &dev->dbbuf_eis_dma_addr, | |
228 | GFP_KERNEL); | |
229 | if (!dev->dbbuf_eis) { | |
230 | dma_free_coherent(dev->dev, mem_size, | |
231 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
232 | dev->dbbuf_dbs = NULL; | |
233 | return -ENOMEM; | |
234 | } | |
235 | ||
236 | return 0; | |
237 | } | |
238 | ||
239 | static void nvme_dbbuf_dma_free(struct nvme_dev *dev) | |
240 | { | |
241 | unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); | |
242 | ||
243 | if (dev->dbbuf_dbs) { | |
244 | dma_free_coherent(dev->dev, mem_size, | |
245 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
246 | dev->dbbuf_dbs = NULL; | |
247 | } | |
248 | if (dev->dbbuf_eis) { | |
249 | dma_free_coherent(dev->dev, mem_size, | |
250 | dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); | |
251 | dev->dbbuf_eis = NULL; | |
252 | } | |
253 | } | |
254 | ||
255 | static void nvme_dbbuf_init(struct nvme_dev *dev, | |
256 | struct nvme_queue *nvmeq, int qid) | |
257 | { | |
258 | if (!dev->dbbuf_dbs || !qid) | |
259 | return; | |
260 | ||
261 | nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; | |
262 | nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; | |
263 | nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; | |
264 | nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; | |
265 | } | |
266 | ||
267 | static void nvme_dbbuf_set(struct nvme_dev *dev) | |
268 | { | |
269 | struct nvme_command c; | |
270 | ||
271 | if (!dev->dbbuf_dbs) | |
272 | return; | |
273 | ||
274 | memset(&c, 0, sizeof(c)); | |
275 | c.dbbuf.opcode = nvme_admin_dbbuf; | |
276 | c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); | |
277 | c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); | |
278 | ||
279 | if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { | |
9bdcfb10 | 280 | dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); |
f9f38e33 HK |
281 | /* Free memory and continue on */ |
282 | nvme_dbbuf_dma_free(dev); | |
283 | } | |
284 | } | |
285 | ||
286 | static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) | |
287 | { | |
288 | return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); | |
289 | } | |
290 | ||
291 | /* Update dbbuf and return true if an MMIO is required */ | |
292 | static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, | |
293 | volatile u32 *dbbuf_ei) | |
294 | { | |
295 | if (dbbuf_db) { | |
296 | u16 old_value; | |
297 | ||
298 | /* | |
299 | * Ensure that the queue is written before updating | |
300 | * the doorbell in memory | |
301 | */ | |
302 | wmb(); | |
303 | ||
304 | old_value = *dbbuf_db; | |
305 | *dbbuf_db = value; | |
306 | ||
307 | if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) | |
308 | return false; | |
309 | } | |
310 | ||
311 | return true; | |
b60503ba MW |
312 | } |
313 | ||
ac3dd5bd JA |
314 | /* |
315 | * Max size of iod being embedded in the request payload | |
316 | */ | |
317 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 318 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
319 | |
320 | /* | |
321 | * Will slightly overestimate the number of pages needed. This is OK | |
322 | * as it only leads to a small amount of wasted memory for the lifetime of | |
323 | * the I/O. | |
324 | */ | |
325 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
326 | { | |
5fd4ce1b CH |
327 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
328 | dev->ctrl.page_size); | |
ac3dd5bd JA |
329 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
330 | } | |
331 | ||
f4800d6d CH |
332 | static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, |
333 | unsigned int size, unsigned int nseg) | |
ac3dd5bd | 334 | { |
f4800d6d CH |
335 | return sizeof(__le64 *) * nvme_npages(size, dev) + |
336 | sizeof(struct scatterlist) * nseg; | |
337 | } | |
ac3dd5bd | 338 | |
f4800d6d CH |
339 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) |
340 | { | |
341 | return sizeof(struct nvme_iod) + | |
342 | nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); | |
ac3dd5bd JA |
343 | } |
344 | ||
a4aea562 MB |
345 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
346 | unsigned int hctx_idx) | |
e85248e5 | 347 | { |
a4aea562 MB |
348 | struct nvme_dev *dev = data; |
349 | struct nvme_queue *nvmeq = dev->queues[0]; | |
350 | ||
42483228 KB |
351 | WARN_ON(hctx_idx != 0); |
352 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
353 | WARN_ON(nvmeq->tags); | |
354 | ||
a4aea562 | 355 | hctx->driver_data = nvmeq; |
42483228 | 356 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 357 | return 0; |
e85248e5 MW |
358 | } |
359 | ||
4af0e21c KB |
360 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
361 | { | |
362 | struct nvme_queue *nvmeq = hctx->driver_data; | |
363 | ||
364 | nvmeq->tags = NULL; | |
365 | } | |
366 | ||
a4aea562 MB |
367 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
368 | unsigned int hctx_idx) | |
b60503ba | 369 | { |
a4aea562 | 370 | struct nvme_dev *dev = data; |
42483228 | 371 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 372 | |
42483228 KB |
373 | if (!nvmeq->tags) |
374 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 375 | |
42483228 | 376 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
377 | hctx->driver_data = nvmeq; |
378 | return 0; | |
b60503ba MW |
379 | } |
380 | ||
d6296d39 CH |
381 | static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, |
382 | unsigned int hctx_idx, unsigned int numa_node) | |
b60503ba | 383 | { |
d6296d39 | 384 | struct nvme_dev *dev = set->driver_data; |
f4800d6d | 385 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
0350815a CH |
386 | int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; |
387 | struct nvme_queue *nvmeq = dev->queues[queue_idx]; | |
a4aea562 MB |
388 | |
389 | BUG_ON(!nvmeq); | |
f4800d6d | 390 | iod->nvmeq = nvmeq; |
a4aea562 MB |
391 | return 0; |
392 | } | |
393 | ||
dca51e78 CH |
394 | static int nvme_pci_map_queues(struct blk_mq_tag_set *set) |
395 | { | |
396 | struct nvme_dev *dev = set->driver_data; | |
397 | ||
398 | return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev)); | |
399 | } | |
400 | ||
b60503ba | 401 | /** |
adf68f21 | 402 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
403 | * @nvmeq: The queue to use |
404 | * @cmd: The command to send | |
405 | * | |
406 | * Safe to use from interrupt context | |
407 | */ | |
e3f879bf SB |
408 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
409 | struct nvme_command *cmd) | |
b60503ba | 410 | { |
a4aea562 MB |
411 | u16 tail = nvmeq->sq_tail; |
412 | ||
8ffaadf7 JD |
413 | if (nvmeq->sq_cmds_io) |
414 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
415 | else | |
416 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
417 | ||
b60503ba MW |
418 | if (++tail == nvmeq->q_depth) |
419 | tail = 0; | |
f9f38e33 HK |
420 | if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db, |
421 | nvmeq->dbbuf_sq_ei)) | |
422 | writel(tail, nvmeq->q_db); | |
b60503ba | 423 | nvmeq->sq_tail = tail; |
b60503ba MW |
424 | } |
425 | ||
f4800d6d | 426 | static __le64 **iod_list(struct request *req) |
b60503ba | 427 | { |
f4800d6d | 428 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
f9d03f96 | 429 | return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req)); |
b60503ba MW |
430 | } |
431 | ||
fc17b653 | 432 | static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) |
ac3dd5bd | 433 | { |
f4800d6d | 434 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
f9d03f96 | 435 | int nseg = blk_rq_nr_phys_segments(rq); |
b131c61d | 436 | unsigned int size = blk_rq_payload_bytes(rq); |
ac3dd5bd | 437 | |
f4800d6d CH |
438 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
439 | iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); | |
440 | if (!iod->sg) | |
fc17b653 | 441 | return BLK_STS_RESOURCE; |
f4800d6d CH |
442 | } else { |
443 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
444 | } |
445 | ||
f4800d6d CH |
446 | iod->aborted = 0; |
447 | iod->npages = -1; | |
448 | iod->nents = 0; | |
449 | iod->length = size; | |
f80ec966 | 450 | |
fc17b653 | 451 | return BLK_STS_OK; |
ac3dd5bd JA |
452 | } |
453 | ||
f4800d6d | 454 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 455 | { |
f4800d6d | 456 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
5fd4ce1b | 457 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 | 458 | int i; |
f4800d6d | 459 | __le64 **list = iod_list(req); |
eca18b23 MW |
460 | dma_addr_t prp_dma = iod->first_dma; |
461 | ||
462 | if (iod->npages == 0) | |
463 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
464 | for (i = 0; i < iod->npages; i++) { | |
465 | __le64 *prp_list = list[i]; | |
466 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
467 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
468 | prp_dma = next_prp_dma; | |
469 | } | |
ac3dd5bd | 470 | |
f4800d6d CH |
471 | if (iod->sg != iod->inline_sg) |
472 | kfree(iod->sg); | |
b4ff9c8d KB |
473 | } |
474 | ||
52b68d7e | 475 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
476 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
477 | { | |
478 | if (be32_to_cpu(pi->ref_tag) == v) | |
479 | pi->ref_tag = cpu_to_be32(p); | |
480 | } | |
481 | ||
482 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
483 | { | |
484 | if (be32_to_cpu(pi->ref_tag) == p) | |
485 | pi->ref_tag = cpu_to_be32(v); | |
486 | } | |
487 | ||
488 | /** | |
489 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
490 | * | |
491 | * The virtual start sector is the one that was originally submitted by the | |
492 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
493 | * start sector may be different. Remap protection information to match the | |
494 | * physical LBA on writes, and back to the original seed on reads. | |
495 | * | |
496 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
497 | */ | |
498 | static void nvme_dif_remap(struct request *req, | |
499 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
500 | { | |
501 | struct nvme_ns *ns = req->rq_disk->private_data; | |
502 | struct bio_integrity_payload *bip; | |
503 | struct t10_pi_tuple *pi; | |
504 | void *p, *pmap; | |
505 | u32 i, nlb, ts, phys, virt; | |
506 | ||
507 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
508 | return; | |
509 | ||
510 | bip = bio_integrity(req->bio); | |
511 | if (!bip) | |
512 | return; | |
513 | ||
514 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
515 | |
516 | p = pmap; | |
517 | virt = bip_get_seed(bip); | |
518 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
519 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 520 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
521 | |
522 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
523 | pi = (struct t10_pi_tuple *)p; | |
524 | dif_swap(phys, virt, pi); | |
525 | p += ts; | |
526 | } | |
527 | kunmap_atomic(pmap); | |
528 | } | |
52b68d7e KB |
529 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
530 | static void nvme_dif_remap(struct request *req, | |
531 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
532 | { | |
533 | } | |
534 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
535 | { | |
536 | } | |
537 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
538 | { | |
539 | } | |
52b68d7e KB |
540 | #endif |
541 | ||
86eea289 | 542 | static blk_status_t nvme_setup_prps(struct nvme_dev *dev, struct request *req) |
ff22b54f | 543 | { |
f4800d6d | 544 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 545 | struct dma_pool *pool; |
b131c61d | 546 | int length = blk_rq_payload_bytes(req); |
eca18b23 | 547 | struct scatterlist *sg = iod->sg; |
ff22b54f MW |
548 | int dma_len = sg_dma_len(sg); |
549 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 550 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 551 | int offset = dma_addr & (page_size - 1); |
e025344c | 552 | __le64 *prp_list; |
f4800d6d | 553 | __le64 **list = iod_list(req); |
e025344c | 554 | dma_addr_t prp_dma; |
eca18b23 | 555 | int nprps, i; |
ff22b54f | 556 | |
1d090624 | 557 | length -= (page_size - offset); |
ff22b54f | 558 | if (length <= 0) |
86eea289 | 559 | return BLK_STS_OK; |
ff22b54f | 560 | |
1d090624 | 561 | dma_len -= (page_size - offset); |
ff22b54f | 562 | if (dma_len) { |
1d090624 | 563 | dma_addr += (page_size - offset); |
ff22b54f MW |
564 | } else { |
565 | sg = sg_next(sg); | |
566 | dma_addr = sg_dma_address(sg); | |
567 | dma_len = sg_dma_len(sg); | |
568 | } | |
569 | ||
1d090624 | 570 | if (length <= page_size) { |
edd10d33 | 571 | iod->first_dma = dma_addr; |
86eea289 | 572 | return BLK_STS_OK; |
e025344c SMM |
573 | } |
574 | ||
1d090624 | 575 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
576 | if (nprps <= (256 / 8)) { |
577 | pool = dev->prp_small_pool; | |
eca18b23 | 578 | iod->npages = 0; |
99802a7a MW |
579 | } else { |
580 | pool = dev->prp_page_pool; | |
eca18b23 | 581 | iod->npages = 1; |
99802a7a MW |
582 | } |
583 | ||
69d2b571 | 584 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 585 | if (!prp_list) { |
edd10d33 | 586 | iod->first_dma = dma_addr; |
eca18b23 | 587 | iod->npages = -1; |
86eea289 | 588 | return BLK_STS_RESOURCE; |
b77954cb | 589 | } |
eca18b23 MW |
590 | list[0] = prp_list; |
591 | iod->first_dma = prp_dma; | |
e025344c SMM |
592 | i = 0; |
593 | for (;;) { | |
1d090624 | 594 | if (i == page_size >> 3) { |
e025344c | 595 | __le64 *old_prp_list = prp_list; |
69d2b571 | 596 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 597 | if (!prp_list) |
86eea289 | 598 | return BLK_STS_RESOURCE; |
eca18b23 | 599 | list[iod->npages++] = prp_list; |
7523d834 MW |
600 | prp_list[0] = old_prp_list[i - 1]; |
601 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
602 | i = 1; | |
e025344c SMM |
603 | } |
604 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
605 | dma_len -= page_size; |
606 | dma_addr += page_size; | |
607 | length -= page_size; | |
e025344c SMM |
608 | if (length <= 0) |
609 | break; | |
610 | if (dma_len > 0) | |
611 | continue; | |
86eea289 KB |
612 | if (unlikely(dma_len < 0)) |
613 | goto bad_sgl; | |
e025344c SMM |
614 | sg = sg_next(sg); |
615 | dma_addr = sg_dma_address(sg); | |
616 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
617 | } |
618 | ||
86eea289 KB |
619 | return BLK_STS_OK; |
620 | ||
621 | bad_sgl: | |
622 | if (WARN_ONCE(1, "Invalid SGL for payload:%d nents:%d\n", | |
623 | blk_rq_payload_bytes(req), iod->nents)) { | |
624 | for_each_sg(iod->sg, sg, iod->nents, i) { | |
625 | dma_addr_t phys = sg_phys(sg); | |
626 | pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " | |
627 | "dma_address:%pad dma_length:%d\n", i, &phys, | |
628 | sg->offset, sg->length, | |
629 | &sg_dma_address(sg), | |
630 | sg_dma_len(sg)); | |
631 | } | |
632 | } | |
633 | return BLK_STS_IOERR; | |
634 | ||
ff22b54f MW |
635 | } |
636 | ||
fc17b653 | 637 | static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, |
b131c61d | 638 | struct nvme_command *cmnd) |
d29ec824 | 639 | { |
f4800d6d | 640 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
641 | struct request_queue *q = req->q; |
642 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
643 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
fc17b653 | 644 | blk_status_t ret = BLK_STS_IOERR; |
d29ec824 | 645 | |
f9d03f96 | 646 | sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); |
ba1ca37e CH |
647 | iod->nents = blk_rq_map_sg(q, req, iod->sg); |
648 | if (!iod->nents) | |
649 | goto out; | |
d29ec824 | 650 | |
fc17b653 | 651 | ret = BLK_STS_RESOURCE; |
2b6b535d MFO |
652 | if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, |
653 | DMA_ATTR_NO_WARN)) | |
ba1ca37e | 654 | goto out; |
d29ec824 | 655 | |
86eea289 KB |
656 | ret = nvme_setup_prps(dev, req); |
657 | if (ret != BLK_STS_OK) | |
ba1ca37e | 658 | goto out_unmap; |
0e5e4f0e | 659 | |
fc17b653 | 660 | ret = BLK_STS_IOERR; |
ba1ca37e CH |
661 | if (blk_integrity_rq(req)) { |
662 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
663 | goto out_unmap; | |
0e5e4f0e | 664 | |
bf684057 CH |
665 | sg_init_table(&iod->meta_sg, 1); |
666 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 667 | goto out_unmap; |
0e5e4f0e | 668 | |
ba1ca37e CH |
669 | if (rq_data_dir(req)) |
670 | nvme_dif_remap(req, nvme_dif_prep); | |
0e5e4f0e | 671 | |
bf684057 | 672 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 673 | goto out_unmap; |
d29ec824 | 674 | } |
00df5cb4 | 675 | |
eb793e2c CH |
676 | cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
677 | cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma); | |
ba1ca37e | 678 | if (blk_integrity_rq(req)) |
bf684057 | 679 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
fc17b653 | 680 | return BLK_STS_OK; |
00df5cb4 | 681 | |
ba1ca37e CH |
682 | out_unmap: |
683 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
684 | out: | |
685 | return ret; | |
00df5cb4 MW |
686 | } |
687 | ||
f4800d6d | 688 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
b60503ba | 689 | { |
f4800d6d | 690 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
691 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
692 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
693 | ||
694 | if (iod->nents) { | |
695 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
696 | if (blk_integrity_rq(req)) { | |
697 | if (!rq_data_dir(req)) | |
698 | nvme_dif_remap(req, nvme_dif_complete); | |
bf684057 | 699 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
e1e5e564 | 700 | } |
e19b127f | 701 | } |
e1e5e564 | 702 | |
f9d03f96 | 703 | nvme_cleanup_cmd(req); |
f4800d6d | 704 | nvme_free_iod(dev, req); |
d4f6c3ab | 705 | } |
b60503ba | 706 | |
d29ec824 CH |
707 | /* |
708 | * NOTE: ns is NULL when called on the admin queue. | |
709 | */ | |
fc17b653 | 710 | static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
a4aea562 | 711 | const struct blk_mq_queue_data *bd) |
edd10d33 | 712 | { |
a4aea562 MB |
713 | struct nvme_ns *ns = hctx->queue->queuedata; |
714 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 715 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 716 | struct request *req = bd->rq; |
ba1ca37e | 717 | struct nvme_command cmnd; |
ebe6d874 | 718 | blk_status_t ret; |
e1e5e564 | 719 | |
f9d03f96 | 720 | ret = nvme_setup_cmd(ns, req, &cmnd); |
fc17b653 | 721 | if (ret) |
f4800d6d | 722 | return ret; |
a4aea562 | 723 | |
b131c61d | 724 | ret = nvme_init_iod(req, dev); |
fc17b653 | 725 | if (ret) |
f9d03f96 | 726 | goto out_free_cmd; |
a4aea562 | 727 | |
fc17b653 | 728 | if (blk_rq_nr_phys_segments(req)) { |
b131c61d | 729 | ret = nvme_map_data(dev, req, &cmnd); |
fc17b653 CH |
730 | if (ret) |
731 | goto out_cleanup_iod; | |
732 | } | |
a4aea562 | 733 | |
aae239e1 | 734 | blk_mq_start_request(req); |
a4aea562 | 735 | |
ba1ca37e | 736 | spin_lock_irq(&nvmeq->q_lock); |
ae1fba20 | 737 | if (unlikely(nvmeq->cq_vector < 0)) { |
fc17b653 | 738 | ret = BLK_STS_IOERR; |
ae1fba20 | 739 | spin_unlock_irq(&nvmeq->q_lock); |
f9d03f96 | 740 | goto out_cleanup_iod; |
ae1fba20 | 741 | } |
ba1ca37e | 742 | __nvme_submit_cmd(nvmeq, &cmnd); |
a4aea562 MB |
743 | nvme_process_cq(nvmeq); |
744 | spin_unlock_irq(&nvmeq->q_lock); | |
fc17b653 | 745 | return BLK_STS_OK; |
f9d03f96 | 746 | out_cleanup_iod: |
f4800d6d | 747 | nvme_free_iod(dev, req); |
f9d03f96 CH |
748 | out_free_cmd: |
749 | nvme_cleanup_cmd(req); | |
ba1ca37e | 750 | return ret; |
b60503ba | 751 | } |
e1e5e564 | 752 | |
77f02a7a | 753 | static void nvme_pci_complete_rq(struct request *req) |
eee417b0 | 754 | { |
f4800d6d | 755 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 | 756 | |
77f02a7a CH |
757 | nvme_unmap_data(iod->nvmeq->dev, req); |
758 | nvme_complete_rq(req); | |
b60503ba MW |
759 | } |
760 | ||
d783e0bd MR |
761 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
762 | static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, | |
763 | u16 phase) | |
764 | { | |
765 | return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; | |
766 | } | |
767 | ||
eb281c82 | 768 | static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) |
b60503ba | 769 | { |
eb281c82 | 770 | u16 head = nvmeq->cq_head; |
adf68f21 | 771 | |
eb281c82 SG |
772 | if (likely(nvmeq->cq_vector >= 0)) { |
773 | if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, | |
774 | nvmeq->dbbuf_cq_ei)) | |
775 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
776 | } | |
777 | } | |
aae239e1 | 778 | |
83a12fb7 SG |
779 | static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, |
780 | struct nvme_completion *cqe) | |
781 | { | |
782 | struct request *req; | |
adf68f21 | 783 | |
83a12fb7 SG |
784 | if (unlikely(cqe->command_id >= nvmeq->q_depth)) { |
785 | dev_warn(nvmeq->dev->ctrl.device, | |
786 | "invalid id %d completed on queue %d\n", | |
787 | cqe->command_id, le16_to_cpu(cqe->sq_id)); | |
788 | return; | |
b60503ba MW |
789 | } |
790 | ||
83a12fb7 SG |
791 | /* |
792 | * AEN requests are special as they don't time out and can | |
793 | * survive any kind of queue freeze and often don't respond to | |
794 | * aborts. We don't even bother to allocate a struct request | |
795 | * for them but rather special case them here. | |
796 | */ | |
797 | if (unlikely(nvmeq->qid == 0 && | |
798 | cqe->command_id >= NVME_AQ_BLKMQ_DEPTH)) { | |
799 | nvme_complete_async_event(&nvmeq->dev->ctrl, | |
800 | cqe->status, &cqe->result); | |
a0fa9647 | 801 | return; |
83a12fb7 | 802 | } |
b60503ba | 803 | |
83a12fb7 SG |
804 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); |
805 | nvme_end_request(req, cqe->status, cqe->result); | |
806 | } | |
b60503ba | 807 | |
920d13a8 SG |
808 | static inline bool nvme_read_cqe(struct nvme_queue *nvmeq, |
809 | struct nvme_completion *cqe) | |
b60503ba | 810 | { |
920d13a8 SG |
811 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { |
812 | *cqe = nvmeq->cqes[nvmeq->cq_head]; | |
adf68f21 | 813 | |
920d13a8 SG |
814 | if (++nvmeq->cq_head == nvmeq->q_depth) { |
815 | nvmeq->cq_head = 0; | |
816 | nvmeq->cq_phase = !nvmeq->cq_phase; | |
b60503ba | 817 | } |
920d13a8 | 818 | return true; |
b60503ba | 819 | } |
920d13a8 | 820 | return false; |
a0fa9647 JA |
821 | } |
822 | ||
823 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
824 | { | |
920d13a8 SG |
825 | struct nvme_completion cqe; |
826 | int consumed = 0; | |
b60503ba | 827 | |
920d13a8 SG |
828 | while (nvme_read_cqe(nvmeq, &cqe)) { |
829 | nvme_handle_cqe(nvmeq, &cqe); | |
830 | consumed++; | |
920d13a8 | 831 | } |
eb281c82 | 832 | |
920d13a8 SG |
833 | if (consumed) { |
834 | nvme_ring_cq_doorbell(nvmeq); | |
835 | nvmeq->cqe_seen = 1; | |
836 | } | |
b60503ba MW |
837 | } |
838 | ||
839 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
840 | { |
841 | irqreturn_t result; | |
842 | struct nvme_queue *nvmeq = data; | |
843 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
844 | nvme_process_cq(nvmeq); |
845 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
846 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
847 | spin_unlock(&nvmeq->q_lock); |
848 | return result; | |
849 | } | |
850 | ||
851 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
852 | { | |
853 | struct nvme_queue *nvmeq = data; | |
d783e0bd MR |
854 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) |
855 | return IRQ_WAKE_THREAD; | |
856 | return IRQ_NONE; | |
58ffacb5 MW |
857 | } |
858 | ||
7776db1c | 859 | static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) |
a0fa9647 | 860 | { |
442e19b7 SG |
861 | struct nvme_completion cqe; |
862 | int found = 0, consumed = 0; | |
a0fa9647 | 863 | |
442e19b7 SG |
864 | if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) |
865 | return 0; | |
a0fa9647 | 866 | |
442e19b7 SG |
867 | spin_lock_irq(&nvmeq->q_lock); |
868 | while (nvme_read_cqe(nvmeq, &cqe)) { | |
869 | nvme_handle_cqe(nvmeq, &cqe); | |
870 | consumed++; | |
871 | ||
872 | if (tag == cqe.command_id) { | |
873 | found = 1; | |
874 | break; | |
875 | } | |
876 | } | |
877 | ||
878 | if (consumed) | |
879 | nvme_ring_cq_doorbell(nvmeq); | |
880 | spin_unlock_irq(&nvmeq->q_lock); | |
881 | ||
882 | return found; | |
a0fa9647 JA |
883 | } |
884 | ||
7776db1c KB |
885 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
886 | { | |
887 | struct nvme_queue *nvmeq = hctx->driver_data; | |
888 | ||
889 | return __nvme_poll(nvmeq, tag); | |
890 | } | |
891 | ||
f866fc42 | 892 | static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx) |
b60503ba | 893 | { |
f866fc42 | 894 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9396dec9 | 895 | struct nvme_queue *nvmeq = dev->queues[0]; |
a4aea562 | 896 | struct nvme_command c; |
b60503ba | 897 | |
a4aea562 MB |
898 | memset(&c, 0, sizeof(c)); |
899 | c.common.opcode = nvme_admin_async_event; | |
f866fc42 | 900 | c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx; |
3c0cf138 | 901 | |
9396dec9 | 902 | spin_lock_irq(&nvmeq->q_lock); |
f866fc42 | 903 | __nvme_submit_cmd(nvmeq, &c); |
9396dec9 | 904 | spin_unlock_irq(&nvmeq->q_lock); |
f705f837 CH |
905 | } |
906 | ||
b60503ba | 907 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 908 | { |
b60503ba MW |
909 | struct nvme_command c; |
910 | ||
911 | memset(&c, 0, sizeof(c)); | |
912 | c.delete_queue.opcode = opcode; | |
913 | c.delete_queue.qid = cpu_to_le16(id); | |
914 | ||
1c63dc66 | 915 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
916 | } |
917 | ||
b60503ba MW |
918 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
919 | struct nvme_queue *nvmeq) | |
920 | { | |
b60503ba MW |
921 | struct nvme_command c; |
922 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
923 | ||
d29ec824 CH |
924 | /* |
925 | * Note: we (ab)use the fact the the prp fields survive if no data | |
926 | * is attached to the request. | |
927 | */ | |
b60503ba MW |
928 | memset(&c, 0, sizeof(c)); |
929 | c.create_cq.opcode = nvme_admin_create_cq; | |
930 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
931 | c.create_cq.cqid = cpu_to_le16(qid); | |
932 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
933 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
934 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
935 | ||
1c63dc66 | 936 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
937 | } |
938 | ||
939 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
940 | struct nvme_queue *nvmeq) | |
941 | { | |
b60503ba | 942 | struct nvme_command c; |
81c1cd98 | 943 | int flags = NVME_QUEUE_PHYS_CONTIG; |
b60503ba | 944 | |
d29ec824 CH |
945 | /* |
946 | * Note: we (ab)use the fact the the prp fields survive if no data | |
947 | * is attached to the request. | |
948 | */ | |
b60503ba MW |
949 | memset(&c, 0, sizeof(c)); |
950 | c.create_sq.opcode = nvme_admin_create_sq; | |
951 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
952 | c.create_sq.sqid = cpu_to_le16(qid); | |
953 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
954 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
955 | c.create_sq.cqid = cpu_to_le16(qid); | |
956 | ||
1c63dc66 | 957 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
958 | } |
959 | ||
960 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
961 | { | |
962 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
963 | } | |
964 | ||
965 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
966 | { | |
967 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
968 | } | |
969 | ||
2a842aca | 970 | static void abort_endio(struct request *req, blk_status_t error) |
bc5fc7e4 | 971 | { |
f4800d6d CH |
972 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
973 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e44ac588 | 974 | |
27fa9bc5 CH |
975 | dev_warn(nvmeq->dev->ctrl.device, |
976 | "Abort status: 0x%x", nvme_req(req)->status); | |
e7a2a87d | 977 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
e7a2a87d | 978 | blk_mq_free_request(req); |
bc5fc7e4 MW |
979 | } |
980 | ||
b2a0eb1a KB |
981 | static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) |
982 | { | |
983 | ||
984 | /* If true, indicates loss of adapter communication, possibly by a | |
985 | * NVMe Subsystem reset. | |
986 | */ | |
987 | bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); | |
988 | ||
989 | /* If there is a reset ongoing, we shouldn't reset again. */ | |
990 | if (dev->ctrl.state == NVME_CTRL_RESETTING) | |
991 | return false; | |
992 | ||
993 | /* We shouldn't reset unless the controller is on fatal error state | |
994 | * _or_ if we lost the communication with it. | |
995 | */ | |
996 | if (!(csts & NVME_CSTS_CFS) && !nssro) | |
997 | return false; | |
998 | ||
999 | /* If PCI error recovery process is happening, we cannot reset or | |
1000 | * the recovery mechanism will surely fail. | |
1001 | */ | |
1002 | if (pci_channel_offline(to_pci_dev(dev->dev))) | |
1003 | return false; | |
1004 | ||
1005 | return true; | |
1006 | } | |
1007 | ||
1008 | static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) | |
1009 | { | |
1010 | /* Read a config register to help see what died. */ | |
1011 | u16 pci_status; | |
1012 | int result; | |
1013 | ||
1014 | result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, | |
1015 | &pci_status); | |
1016 | if (result == PCIBIOS_SUCCESSFUL) | |
1017 | dev_warn(dev->ctrl.device, | |
1018 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", | |
1019 | csts, pci_status); | |
1020 | else | |
1021 | dev_warn(dev->ctrl.device, | |
1022 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", | |
1023 | csts, result); | |
1024 | } | |
1025 | ||
31c7c7d2 | 1026 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 1027 | { |
f4800d6d CH |
1028 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
1029 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 1030 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 1031 | struct request *abort_req; |
a4aea562 | 1032 | struct nvme_command cmd; |
b2a0eb1a KB |
1033 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
1034 | ||
1035 | /* | |
1036 | * Reset immediately if the controller is failed | |
1037 | */ | |
1038 | if (nvme_should_reset(dev, csts)) { | |
1039 | nvme_warn_reset(dev, csts); | |
1040 | nvme_dev_disable(dev, false); | |
d86c4d8e | 1041 | nvme_reset_ctrl(&dev->ctrl); |
b2a0eb1a KB |
1042 | return BLK_EH_HANDLED; |
1043 | } | |
c30341dc | 1044 | |
7776db1c KB |
1045 | /* |
1046 | * Did we miss an interrupt? | |
1047 | */ | |
1048 | if (__nvme_poll(nvmeq, req->tag)) { | |
1049 | dev_warn(dev->ctrl.device, | |
1050 | "I/O %d QID %d timeout, completion polled\n", | |
1051 | req->tag, nvmeq->qid); | |
1052 | return BLK_EH_HANDLED; | |
1053 | } | |
1054 | ||
31c7c7d2 | 1055 | /* |
fd634f41 CH |
1056 | * Shutdown immediately if controller times out while starting. The |
1057 | * reset work will see the pci device disabled when it gets the forced | |
1058 | * cancellation error. All outstanding requests are completed on | |
1059 | * shutdown, so we return BLK_EH_HANDLED. | |
1060 | */ | |
bb8d261e | 1061 | if (dev->ctrl.state == NVME_CTRL_RESETTING) { |
1b3c47c1 | 1062 | dev_warn(dev->ctrl.device, |
fd634f41 CH |
1063 | "I/O %d QID %d timeout, disable controller\n", |
1064 | req->tag, nvmeq->qid); | |
a5cdb68c | 1065 | nvme_dev_disable(dev, false); |
27fa9bc5 | 1066 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
fd634f41 | 1067 | return BLK_EH_HANDLED; |
c30341dc KB |
1068 | } |
1069 | ||
fd634f41 CH |
1070 | /* |
1071 | * Shutdown the controller immediately and schedule a reset if the | |
1072 | * command was already aborted once before and still hasn't been | |
1073 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 1074 | */ |
f4800d6d | 1075 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 1076 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
1077 | "I/O %d QID %d timeout, reset controller\n", |
1078 | req->tag, nvmeq->qid); | |
a5cdb68c | 1079 | nvme_dev_disable(dev, false); |
d86c4d8e | 1080 | nvme_reset_ctrl(&dev->ctrl); |
c30341dc | 1081 | |
e1569a16 KB |
1082 | /* |
1083 | * Mark the request as handled, since the inline shutdown | |
1084 | * forces all outstanding requests to complete. | |
1085 | */ | |
27fa9bc5 | 1086 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
e1569a16 | 1087 | return BLK_EH_HANDLED; |
c30341dc | 1088 | } |
c30341dc | 1089 | |
e7a2a87d | 1090 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 1091 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 1092 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 1093 | } |
7bf7d778 | 1094 | iod->aborted = 1; |
a4aea562 | 1095 | |
c30341dc KB |
1096 | memset(&cmd, 0, sizeof(cmd)); |
1097 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 1098 | cmd.abort.cid = req->tag; |
c30341dc | 1099 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 1100 | |
1b3c47c1 SG |
1101 | dev_warn(nvmeq->dev->ctrl.device, |
1102 | "I/O %d QID %d timeout, aborting\n", | |
1103 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
1104 | |
1105 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
eb71f435 | 1106 | BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
e7a2a87d CH |
1107 | if (IS_ERR(abort_req)) { |
1108 | atomic_inc(&dev->ctrl.abort_limit); | |
1109 | return BLK_EH_RESET_TIMER; | |
1110 | } | |
1111 | ||
1112 | abort_req->timeout = ADMIN_TIMEOUT; | |
1113 | abort_req->end_io_data = NULL; | |
1114 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
c30341dc | 1115 | |
31c7c7d2 CH |
1116 | /* |
1117 | * The aborted req will be completed on receiving the abort req. | |
1118 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1119 | * as the device then is in a faulty state. | |
1120 | */ | |
1121 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
1122 | } |
1123 | ||
a4aea562 MB |
1124 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1125 | { | |
9e866774 MW |
1126 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1127 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1128 | if (nvmeq->sq_cmds) |
1129 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1130 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1131 | kfree(nvmeq); | |
1132 | } | |
1133 | ||
a1a5ef99 | 1134 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1135 | { |
1136 | int i; | |
1137 | ||
d858e5f0 | 1138 | for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1139 | struct nvme_queue *nvmeq = dev->queues[i]; |
d858e5f0 | 1140 | dev->ctrl.queue_count--; |
a4aea562 | 1141 | dev->queues[i] = NULL; |
f435c282 | 1142 | nvme_free_queue(nvmeq); |
121c7ad4 | 1143 | } |
22404274 KB |
1144 | } |
1145 | ||
4d115420 KB |
1146 | /** |
1147 | * nvme_suspend_queue - put queue into suspended state | |
1148 | * @nvmeq - queue to suspend | |
4d115420 KB |
1149 | */ |
1150 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1151 | { |
2b25d981 | 1152 | int vector; |
b60503ba | 1153 | |
a09115b2 | 1154 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1155 | if (nvmeq->cq_vector == -1) { |
1156 | spin_unlock_irq(&nvmeq->q_lock); | |
1157 | return 1; | |
1158 | } | |
0ff199cb | 1159 | vector = nvmeq->cq_vector; |
42f61420 | 1160 | nvmeq->dev->online_queues--; |
2b25d981 | 1161 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1162 | spin_unlock_irq(&nvmeq->q_lock); |
1163 | ||
1c63dc66 | 1164 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
c81545f9 | 1165 | blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); |
6df3dbc8 | 1166 | |
0ff199cb | 1167 | pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); |
b60503ba | 1168 | |
4d115420 KB |
1169 | return 0; |
1170 | } | |
b60503ba | 1171 | |
a5cdb68c | 1172 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 1173 | { |
a5cdb68c | 1174 | struct nvme_queue *nvmeq = dev->queues[0]; |
4d115420 KB |
1175 | |
1176 | if (!nvmeq) | |
1177 | return; | |
1178 | if (nvme_suspend_queue(nvmeq)) | |
1179 | return; | |
1180 | ||
a5cdb68c KB |
1181 | if (shutdown) |
1182 | nvme_shutdown_ctrl(&dev->ctrl); | |
1183 | else | |
20d0dfe6 | 1184 | nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); |
07836e65 KB |
1185 | |
1186 | spin_lock_irq(&nvmeq->q_lock); | |
1187 | nvme_process_cq(nvmeq); | |
1188 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1189 | } |
1190 | ||
8ffaadf7 JD |
1191 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1192 | int entry_size) | |
1193 | { | |
1194 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1195 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1196 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1197 | |
1198 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1199 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1200 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1201 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1202 | |
1203 | /* | |
1204 | * Ensure the reduced q_depth is above some threshold where it | |
1205 | * would be better to map queues in system memory with the | |
1206 | * original depth | |
1207 | */ | |
1208 | if (q_depth < 64) | |
1209 | return -ENOMEM; | |
1210 | } | |
1211 | ||
1212 | return q_depth; | |
1213 | } | |
1214 | ||
1215 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1216 | int qid, int depth) | |
1217 | { | |
1218 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1219 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1220 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1221 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1222 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1223 | } else { | |
1224 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1225 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1226 | if (!nvmeq->sq_cmds) | |
1227 | return -ENOMEM; | |
1228 | } | |
1229 | ||
1230 | return 0; | |
1231 | } | |
1232 | ||
b60503ba | 1233 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
d3af3ecd | 1234 | int depth, int node) |
b60503ba | 1235 | { |
d3af3ecd SL |
1236 | struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL, |
1237 | node); | |
b60503ba MW |
1238 | if (!nvmeq) |
1239 | return NULL; | |
1240 | ||
e75ec752 | 1241 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1242 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1243 | if (!nvmeq->cqes) |
1244 | goto free_nvmeq; | |
b60503ba | 1245 | |
8ffaadf7 | 1246 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1247 | goto free_cqdma; |
1248 | ||
e75ec752 | 1249 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1250 | nvmeq->dev = dev; |
b60503ba MW |
1251 | spin_lock_init(&nvmeq->q_lock); |
1252 | nvmeq->cq_head = 0; | |
82123460 | 1253 | nvmeq->cq_phase = 1; |
b80d5ccc | 1254 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1255 | nvmeq->q_depth = depth; |
c30341dc | 1256 | nvmeq->qid = qid; |
758dd7fd | 1257 | nvmeq->cq_vector = -1; |
a4aea562 | 1258 | dev->queues[qid] = nvmeq; |
d858e5f0 | 1259 | dev->ctrl.queue_count++; |
36a7e993 | 1260 | |
b60503ba MW |
1261 | return nvmeq; |
1262 | ||
1263 | free_cqdma: | |
e75ec752 | 1264 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1265 | nvmeq->cq_dma_addr); |
1266 | free_nvmeq: | |
1267 | kfree(nvmeq); | |
1268 | return NULL; | |
1269 | } | |
1270 | ||
dca51e78 | 1271 | static int queue_request_irq(struct nvme_queue *nvmeq) |
3001082c | 1272 | { |
0ff199cb CH |
1273 | struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); |
1274 | int nr = nvmeq->dev->ctrl.instance; | |
1275 | ||
1276 | if (use_threaded_interrupts) { | |
1277 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, | |
1278 | nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1279 | } else { | |
1280 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, | |
1281 | NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1282 | } | |
3001082c MW |
1283 | } |
1284 | ||
22404274 | 1285 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1286 | { |
22404274 | 1287 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1288 | |
7be50e93 | 1289 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1290 | nvmeq->sq_tail = 0; |
1291 | nvmeq->cq_head = 0; | |
1292 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1293 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1294 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
f9f38e33 | 1295 | nvme_dbbuf_init(dev, nvmeq, qid); |
42f61420 | 1296 | dev->online_queues++; |
7be50e93 | 1297 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1298 | } |
1299 | ||
1300 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1301 | { | |
1302 | struct nvme_dev *dev = nvmeq->dev; | |
1303 | int result; | |
3f85d50b | 1304 | |
2b25d981 | 1305 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1306 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1307 | if (result < 0) | |
22404274 | 1308 | return result; |
b60503ba MW |
1309 | |
1310 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1311 | if (result < 0) | |
1312 | goto release_cq; | |
1313 | ||
dca51e78 | 1314 | result = queue_request_irq(nvmeq); |
b60503ba MW |
1315 | if (result < 0) |
1316 | goto release_sq; | |
1317 | ||
22404274 | 1318 | nvme_init_queue(nvmeq, qid); |
22404274 | 1319 | return result; |
b60503ba MW |
1320 | |
1321 | release_sq: | |
1322 | adapter_delete_sq(dev, qid); | |
1323 | release_cq: | |
1324 | adapter_delete_cq(dev, qid); | |
22404274 | 1325 | return result; |
b60503ba MW |
1326 | } |
1327 | ||
f363b089 | 1328 | static const struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1329 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1330 | .complete = nvme_pci_complete_rq, |
a4aea562 | 1331 | .init_hctx = nvme_admin_init_hctx, |
4af0e21c | 1332 | .exit_hctx = nvme_admin_exit_hctx, |
0350815a | 1333 | .init_request = nvme_init_request, |
a4aea562 MB |
1334 | .timeout = nvme_timeout, |
1335 | }; | |
1336 | ||
f363b089 | 1337 | static const struct blk_mq_ops nvme_mq_ops = { |
a4aea562 | 1338 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1339 | .complete = nvme_pci_complete_rq, |
a4aea562 MB |
1340 | .init_hctx = nvme_init_hctx, |
1341 | .init_request = nvme_init_request, | |
dca51e78 | 1342 | .map_queues = nvme_pci_map_queues, |
a4aea562 | 1343 | .timeout = nvme_timeout, |
a0fa9647 | 1344 | .poll = nvme_poll, |
a4aea562 MB |
1345 | }; |
1346 | ||
ea191d2f KB |
1347 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1348 | { | |
1c63dc66 | 1349 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
69d9a99c KB |
1350 | /* |
1351 | * If the controller was reset during removal, it's possible | |
1352 | * user requests may be waiting on a stopped queue. Start the | |
1353 | * queue to flush these to completion. | |
1354 | */ | |
c81545f9 | 1355 | blk_mq_unquiesce_queue(dev->ctrl.admin_q); |
1c63dc66 | 1356 | blk_cleanup_queue(dev->ctrl.admin_q); |
ea191d2f KB |
1357 | blk_mq_free_tag_set(&dev->admin_tagset); |
1358 | } | |
1359 | } | |
1360 | ||
a4aea562 MB |
1361 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1362 | { | |
1c63dc66 | 1363 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1364 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1365 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c KB |
1366 | |
1367 | /* | |
1368 | * Subtract one to leave an empty queue entry for 'Full Queue' | |
1369 | * condition. See NVM-Express 1.2 specification, section 4.1.2. | |
1370 | */ | |
1371 | dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; | |
a4aea562 | 1372 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1373 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1374 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
d3484991 | 1375 | dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; |
a4aea562 MB |
1376 | dev->admin_tagset.driver_data = dev; |
1377 | ||
1378 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1379 | return -ENOMEM; | |
1380 | ||
1c63dc66 CH |
1381 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1382 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1383 | blk_mq_free_tag_set(&dev->admin_tagset); |
1384 | return -ENOMEM; | |
1385 | } | |
1c63dc66 | 1386 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1387 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1388 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1389 | return -ENODEV; |
1390 | } | |
0fb59cbc | 1391 | } else |
c81545f9 | 1392 | blk_mq_unquiesce_queue(dev->ctrl.admin_q); |
a4aea562 MB |
1393 | |
1394 | return 0; | |
1395 | } | |
1396 | ||
97f6ef64 XY |
1397 | static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1398 | { | |
1399 | return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); | |
1400 | } | |
1401 | ||
1402 | static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) | |
1403 | { | |
1404 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1405 | ||
1406 | if (size <= dev->bar_mapped_size) | |
1407 | return 0; | |
1408 | if (size > pci_resource_len(pdev, 0)) | |
1409 | return -ENOMEM; | |
1410 | if (dev->bar) | |
1411 | iounmap(dev->bar); | |
1412 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1413 | if (!dev->bar) { | |
1414 | dev->bar_mapped_size = 0; | |
1415 | return -ENOMEM; | |
1416 | } | |
1417 | dev->bar_mapped_size = size; | |
1418 | dev->dbs = dev->bar + NVME_REG_DBS; | |
1419 | ||
1420 | return 0; | |
1421 | } | |
1422 | ||
01ad0990 | 1423 | static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1424 | { |
ba47e386 | 1425 | int result; |
b60503ba MW |
1426 | u32 aqa; |
1427 | struct nvme_queue *nvmeq; | |
1428 | ||
97f6ef64 XY |
1429 | result = nvme_remap_bar(dev, db_bar_size(dev, 0)); |
1430 | if (result < 0) | |
1431 | return result; | |
1432 | ||
8ef2074d | 1433 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? |
20d0dfe6 | 1434 | NVME_CAP_NSSRC(dev->ctrl.cap) : 0; |
dfbac8c7 | 1435 | |
7a67cbea CH |
1436 | if (dev->subsystem && |
1437 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1438 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1439 | |
20d0dfe6 | 1440 | result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); |
ba47e386 MW |
1441 | if (result < 0) |
1442 | return result; | |
b60503ba | 1443 | |
a4aea562 | 1444 | nvmeq = dev->queues[0]; |
cd638946 | 1445 | if (!nvmeq) { |
d3af3ecd SL |
1446 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, |
1447 | dev_to_node(dev->dev)); | |
cd638946 KB |
1448 | if (!nvmeq) |
1449 | return -ENOMEM; | |
cd638946 | 1450 | } |
b60503ba MW |
1451 | |
1452 | aqa = nvmeq->q_depth - 1; | |
1453 | aqa |= aqa << 16; | |
1454 | ||
7a67cbea CH |
1455 | writel(aqa, dev->bar + NVME_REG_AQA); |
1456 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1457 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1458 | |
20d0dfe6 | 1459 | result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); |
025c557a | 1460 | if (result) |
d4875622 | 1461 | return result; |
a4aea562 | 1462 | |
2b25d981 | 1463 | nvmeq->cq_vector = 0; |
dca51e78 | 1464 | result = queue_request_irq(nvmeq); |
758dd7fd JD |
1465 | if (result) { |
1466 | nvmeq->cq_vector = -1; | |
d4875622 | 1467 | return result; |
758dd7fd | 1468 | } |
025c557a | 1469 | |
b60503ba MW |
1470 | return result; |
1471 | } | |
1472 | ||
749941f2 | 1473 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1474 | { |
949928c1 | 1475 | unsigned i, max; |
749941f2 | 1476 | int ret = 0; |
42f61420 | 1477 | |
d858e5f0 | 1478 | for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { |
d3af3ecd SL |
1479 | /* vector == qid - 1, match nvme_create_queue */ |
1480 | if (!nvme_alloc_queue(dev, i, dev->q_depth, | |
1481 | pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) { | |
749941f2 | 1482 | ret = -ENOMEM; |
42f61420 | 1483 | break; |
749941f2 CH |
1484 | } |
1485 | } | |
42f61420 | 1486 | |
d858e5f0 | 1487 | max = min(dev->max_qid, dev->ctrl.queue_count - 1); |
949928c1 | 1488 | for (i = dev->online_queues; i <= max; i++) { |
749941f2 | 1489 | ret = nvme_create_queue(dev->queues[i], i); |
d4875622 | 1490 | if (ret) |
42f61420 | 1491 | break; |
27e8166c | 1492 | } |
749941f2 CH |
1493 | |
1494 | /* | |
1495 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1496 | * than the desired aount of queues, and even a controller without | |
1497 | * I/O queues an still be used to issue admin commands. This might | |
1498 | * be useful to upgrade a buggy firmware for example. | |
1499 | */ | |
1500 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1501 | } |
1502 | ||
202021c1 SB |
1503 | static ssize_t nvme_cmb_show(struct device *dev, |
1504 | struct device_attribute *attr, | |
1505 | char *buf) | |
1506 | { | |
1507 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
1508 | ||
c965809c | 1509 | return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", |
202021c1 SB |
1510 | ndev->cmbloc, ndev->cmbsz); |
1511 | } | |
1512 | static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); | |
1513 | ||
8ffaadf7 JD |
1514 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1515 | { | |
1516 | u64 szu, size, offset; | |
8ffaadf7 JD |
1517 | resource_size_t bar_size; |
1518 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1519 | void __iomem *cmb; | |
1520 | dma_addr_t dma_addr; | |
1521 | ||
7a67cbea | 1522 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1523 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1524 | return NULL; | |
202021c1 | 1525 | dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 | 1526 | |
202021c1 SB |
1527 | if (!use_cmb_sqes) |
1528 | return NULL; | |
8ffaadf7 JD |
1529 | |
1530 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1531 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
202021c1 SB |
1532 | offset = szu * NVME_CMB_OFST(dev->cmbloc); |
1533 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc)); | |
8ffaadf7 JD |
1534 | |
1535 | if (offset > bar_size) | |
1536 | return NULL; | |
1537 | ||
1538 | /* | |
1539 | * Controllers may support a CMB size larger than their BAR, | |
1540 | * for example, due to being behind a bridge. Reduce the CMB to | |
1541 | * the reported size of the BAR | |
1542 | */ | |
1543 | if (size > bar_size - offset) | |
1544 | size = bar_size - offset; | |
1545 | ||
202021c1 | 1546 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset; |
8ffaadf7 JD |
1547 | cmb = ioremap_wc(dma_addr, size); |
1548 | if (!cmb) | |
1549 | return NULL; | |
1550 | ||
1551 | dev->cmb_dma_addr = dma_addr; | |
1552 | dev->cmb_size = size; | |
1553 | return cmb; | |
1554 | } | |
1555 | ||
1556 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1557 | { | |
1558 | if (dev->cmb) { | |
1559 | iounmap(dev->cmb); | |
1560 | dev->cmb = NULL; | |
f63572df JD |
1561 | if (dev->cmbsz) { |
1562 | sysfs_remove_file_from_group(&dev->ctrl.device->kobj, | |
1563 | &dev_attr_cmb.attr, NULL); | |
1564 | dev->cmbsz = 0; | |
1565 | } | |
8ffaadf7 JD |
1566 | } |
1567 | } | |
1568 | ||
87ad72a5 CH |
1569 | static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) |
1570 | { | |
1571 | size_t len = dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs); | |
1572 | struct nvme_command c; | |
1573 | u64 dma_addr; | |
1574 | int ret; | |
1575 | ||
1576 | dma_addr = dma_map_single(dev->dev, dev->host_mem_descs, len, | |
1577 | DMA_TO_DEVICE); | |
1578 | if (dma_mapping_error(dev->dev, dma_addr)) | |
1579 | return -ENOMEM; | |
1580 | ||
1581 | memset(&c, 0, sizeof(c)); | |
1582 | c.features.opcode = nvme_admin_set_features; | |
1583 | c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); | |
1584 | c.features.dword11 = cpu_to_le32(bits); | |
1585 | c.features.dword12 = cpu_to_le32(dev->host_mem_size >> | |
1586 | ilog2(dev->ctrl.page_size)); | |
1587 | c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); | |
1588 | c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); | |
1589 | c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); | |
1590 | ||
1591 | ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); | |
1592 | if (ret) { | |
1593 | dev_warn(dev->ctrl.device, | |
1594 | "failed to set host mem (err %d, flags %#x).\n", | |
1595 | ret, bits); | |
1596 | } | |
1597 | dma_unmap_single(dev->dev, dma_addr, len, DMA_TO_DEVICE); | |
1598 | return ret; | |
1599 | } | |
1600 | ||
1601 | static void nvme_free_host_mem(struct nvme_dev *dev) | |
1602 | { | |
1603 | int i; | |
1604 | ||
1605 | for (i = 0; i < dev->nr_host_mem_descs; i++) { | |
1606 | struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; | |
1607 | size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; | |
1608 | ||
1609 | dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], | |
1610 | le64_to_cpu(desc->addr)); | |
1611 | } | |
1612 | ||
1613 | kfree(dev->host_mem_desc_bufs); | |
1614 | dev->host_mem_desc_bufs = NULL; | |
1615 | kfree(dev->host_mem_descs); | |
1616 | dev->host_mem_descs = NULL; | |
1617 | } | |
1618 | ||
1619 | static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) | |
9d713c2b | 1620 | { |
87ad72a5 | 1621 | struct nvme_host_mem_buf_desc *descs; |
2ee0e4ed DC |
1622 | u32 chunk_size, max_entries; |
1623 | int i = 0; | |
87ad72a5 | 1624 | void **bufs; |
2ee0e4ed | 1625 | u64 size = 0, tmp; |
87ad72a5 CH |
1626 | |
1627 | /* start big and work our way down */ | |
1628 | chunk_size = min(preferred, (u64)PAGE_SIZE << MAX_ORDER); | |
1629 | retry: | |
1630 | tmp = (preferred + chunk_size - 1); | |
1631 | do_div(tmp, chunk_size); | |
1632 | max_entries = tmp; | |
1633 | descs = kcalloc(max_entries, sizeof(*descs), GFP_KERNEL); | |
1634 | if (!descs) | |
1635 | goto out; | |
1636 | ||
1637 | bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); | |
1638 | if (!bufs) | |
1639 | goto out_free_descs; | |
1640 | ||
1641 | for (size = 0; size < preferred; size += chunk_size) { | |
1642 | u32 len = min_t(u64, chunk_size, preferred - size); | |
1643 | dma_addr_t dma_addr; | |
1644 | ||
1645 | bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, | |
1646 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); | |
1647 | if (!bufs[i]) | |
1648 | break; | |
1649 | ||
1650 | descs[i].addr = cpu_to_le64(dma_addr); | |
1651 | descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); | |
1652 | i++; | |
1653 | } | |
1654 | ||
1655 | if (!size || (min && size < min)) { | |
1656 | dev_warn(dev->ctrl.device, | |
1657 | "failed to allocate host memory buffer.\n"); | |
1658 | goto out_free_bufs; | |
1659 | } | |
1660 | ||
1661 | dev_info(dev->ctrl.device, | |
1662 | "allocated %lld MiB host memory buffer.\n", | |
1663 | size >> ilog2(SZ_1M)); | |
1664 | dev->nr_host_mem_descs = i; | |
1665 | dev->host_mem_size = size; | |
1666 | dev->host_mem_descs = descs; | |
1667 | dev->host_mem_desc_bufs = bufs; | |
1668 | return 0; | |
1669 | ||
1670 | out_free_bufs: | |
1671 | while (--i >= 0) { | |
1672 | size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; | |
1673 | ||
1674 | dma_free_coherent(dev->dev, size, bufs[i], | |
1675 | le64_to_cpu(descs[i].addr)); | |
1676 | } | |
1677 | ||
1678 | kfree(bufs); | |
1679 | out_free_descs: | |
1680 | kfree(descs); | |
1681 | out: | |
1682 | /* try a smaller chunk size if we failed early */ | |
1683 | if (chunk_size >= PAGE_SIZE * 2 && (i == 0 || size < min)) { | |
1684 | chunk_size /= 2; | |
1685 | goto retry; | |
1686 | } | |
1687 | dev->host_mem_descs = NULL; | |
1688 | return -ENOMEM; | |
1689 | } | |
1690 | ||
1691 | static void nvme_setup_host_mem(struct nvme_dev *dev) | |
1692 | { | |
1693 | u64 max = (u64)max_host_mem_size_mb * SZ_1M; | |
1694 | u64 preferred = (u64)dev->ctrl.hmpre * 4096; | |
1695 | u64 min = (u64)dev->ctrl.hmmin * 4096; | |
1696 | u32 enable_bits = NVME_HOST_MEM_ENABLE; | |
1697 | ||
1698 | preferred = min(preferred, max); | |
1699 | if (min > max) { | |
1700 | dev_warn(dev->ctrl.device, | |
1701 | "min host memory (%lld MiB) above limit (%d MiB).\n", | |
1702 | min >> ilog2(SZ_1M), max_host_mem_size_mb); | |
1703 | nvme_free_host_mem(dev); | |
1704 | return; | |
1705 | } | |
1706 | ||
1707 | /* | |
1708 | * If we already have a buffer allocated check if we can reuse it. | |
1709 | */ | |
1710 | if (dev->host_mem_descs) { | |
1711 | if (dev->host_mem_size >= min) | |
1712 | enable_bits |= NVME_HOST_MEM_RETURN; | |
1713 | else | |
1714 | nvme_free_host_mem(dev); | |
1715 | } | |
1716 | ||
1717 | if (!dev->host_mem_descs) { | |
1718 | if (nvme_alloc_host_mem(dev, min, preferred)) | |
1719 | return; | |
1720 | } | |
1721 | ||
1722 | if (nvme_set_host_mem(dev, enable_bits)) | |
1723 | nvme_free_host_mem(dev); | |
9d713c2b KB |
1724 | } |
1725 | ||
8d85fce7 | 1726 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1727 | { |
a4aea562 | 1728 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1729 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
97f6ef64 XY |
1730 | int result, nr_io_queues; |
1731 | unsigned long size; | |
b60503ba | 1732 | |
425a17cb | 1733 | nr_io_queues = num_present_cpus(); |
9a0be7ab CH |
1734 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1735 | if (result < 0) | |
1b23484b | 1736 | return result; |
9a0be7ab | 1737 | |
f5fa90dc | 1738 | if (nr_io_queues == 0) |
a5229050 | 1739 | return 0; |
b60503ba | 1740 | |
8ffaadf7 JD |
1741 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1742 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1743 | sizeof(struct nvme_command)); | |
1744 | if (result > 0) | |
1745 | dev->q_depth = result; | |
1746 | else | |
1747 | nvme_release_cmb(dev); | |
1748 | } | |
1749 | ||
97f6ef64 XY |
1750 | do { |
1751 | size = db_bar_size(dev, nr_io_queues); | |
1752 | result = nvme_remap_bar(dev, size); | |
1753 | if (!result) | |
1754 | break; | |
1755 | if (!--nr_io_queues) | |
1756 | return -ENOMEM; | |
1757 | } while (1); | |
1758 | adminq->q_db = dev->dbs; | |
f1938f6e | 1759 | |
9d713c2b | 1760 | /* Deregister the admin queue's interrupt */ |
0ff199cb | 1761 | pci_free_irq(pdev, 0, adminq); |
9d713c2b | 1762 | |
e32efbfc JA |
1763 | /* |
1764 | * If we enable msix early due to not intx, disable it again before | |
1765 | * setting up the full range we need. | |
1766 | */ | |
dca51e78 CH |
1767 | pci_free_irq_vectors(pdev); |
1768 | nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues, | |
1769 | PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY); | |
1770 | if (nr_io_queues <= 0) | |
1771 | return -EIO; | |
1772 | dev->max_qid = nr_io_queues; | |
fa08a396 | 1773 | |
063a8096 MW |
1774 | /* |
1775 | * Should investigate if there's a performance win from allocating | |
1776 | * more queues than interrupt vectors; it might allow the submission | |
1777 | * path to scale better, even if the receive path is limited by the | |
1778 | * number of interrupts. | |
1779 | */ | |
063a8096 | 1780 | |
dca51e78 | 1781 | result = queue_request_irq(adminq); |
758dd7fd JD |
1782 | if (result) { |
1783 | adminq->cq_vector = -1; | |
d4875622 | 1784 | return result; |
758dd7fd | 1785 | } |
749941f2 | 1786 | return nvme_create_io_queues(dev); |
b60503ba MW |
1787 | } |
1788 | ||
2a842aca | 1789 | static void nvme_del_queue_end(struct request *req, blk_status_t error) |
a5768aa8 | 1790 | { |
db3cbfff | 1791 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 1792 | |
db3cbfff KB |
1793 | blk_mq_free_request(req); |
1794 | complete(&nvmeq->dev->ioq_wait); | |
a5768aa8 KB |
1795 | } |
1796 | ||
2a842aca | 1797 | static void nvme_del_cq_end(struct request *req, blk_status_t error) |
a5768aa8 | 1798 | { |
db3cbfff | 1799 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 1800 | |
db3cbfff KB |
1801 | if (!error) { |
1802 | unsigned long flags; | |
1803 | ||
2e39e0f6 ML |
1804 | /* |
1805 | * We might be called with the AQ q_lock held | |
1806 | * and the I/O queue q_lock should always | |
1807 | * nest inside the AQ one. | |
1808 | */ | |
1809 | spin_lock_irqsave_nested(&nvmeq->q_lock, flags, | |
1810 | SINGLE_DEPTH_NESTING); | |
db3cbfff KB |
1811 | nvme_process_cq(nvmeq); |
1812 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
a5768aa8 | 1813 | } |
db3cbfff KB |
1814 | |
1815 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
1816 | } |
1817 | ||
db3cbfff | 1818 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 1819 | { |
db3cbfff KB |
1820 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
1821 | struct request *req; | |
1822 | struct nvme_command cmd; | |
bda4e0fb | 1823 | |
db3cbfff KB |
1824 | memset(&cmd, 0, sizeof(cmd)); |
1825 | cmd.delete_queue.opcode = opcode; | |
1826 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 1827 | |
eb71f435 | 1828 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
db3cbfff KB |
1829 | if (IS_ERR(req)) |
1830 | return PTR_ERR(req); | |
bda4e0fb | 1831 | |
db3cbfff KB |
1832 | req->timeout = ADMIN_TIMEOUT; |
1833 | req->end_io_data = nvmeq; | |
1834 | ||
1835 | blk_execute_rq_nowait(q, NULL, req, false, | |
1836 | opcode == nvme_admin_delete_cq ? | |
1837 | nvme_del_cq_end : nvme_del_queue_end); | |
1838 | return 0; | |
bda4e0fb KB |
1839 | } |
1840 | ||
70659060 | 1841 | static void nvme_disable_io_queues(struct nvme_dev *dev, int queues) |
a5768aa8 | 1842 | { |
70659060 | 1843 | int pass; |
db3cbfff KB |
1844 | unsigned long timeout; |
1845 | u8 opcode = nvme_admin_delete_sq; | |
a5768aa8 | 1846 | |
db3cbfff | 1847 | for (pass = 0; pass < 2; pass++) { |
014a0d60 | 1848 | int sent = 0, i = queues; |
db3cbfff KB |
1849 | |
1850 | reinit_completion(&dev->ioq_wait); | |
1851 | retry: | |
1852 | timeout = ADMIN_TIMEOUT; | |
c21377f8 GKB |
1853 | for (; i > 0; i--, sent++) |
1854 | if (nvme_delete_queue(dev->queues[i], opcode)) | |
db3cbfff | 1855 | break; |
c21377f8 | 1856 | |
db3cbfff KB |
1857 | while (sent--) { |
1858 | timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); | |
1859 | if (timeout == 0) | |
1860 | return; | |
1861 | if (i) | |
1862 | goto retry; | |
1863 | } | |
1864 | opcode = nvme_admin_delete_cq; | |
1865 | } | |
a5768aa8 KB |
1866 | } |
1867 | ||
422ef0c7 MW |
1868 | /* |
1869 | * Return: error value if an error occurred setting up the queues or calling | |
1870 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1871 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1872 | * failures should be reported. | |
1873 | */ | |
8d85fce7 | 1874 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1875 | { |
5bae7f73 | 1876 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1877 | dev->tagset.ops = &nvme_mq_ops; |
1878 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1879 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1880 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1881 | dev->tagset.queue_depth = | |
a4aea562 | 1882 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1883 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1884 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1885 | dev->tagset.driver_data = dev; | |
b60503ba | 1886 | |
ffe7704d KB |
1887 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1888 | return 0; | |
5bae7f73 | 1889 | dev->ctrl.tagset = &dev->tagset; |
f9f38e33 HK |
1890 | |
1891 | nvme_dbbuf_set(dev); | |
949928c1 KB |
1892 | } else { |
1893 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
1894 | ||
1895 | /* Free previously allocated queues that are no longer usable */ | |
1896 | nvme_free_queues(dev, dev->online_queues); | |
ffe7704d | 1897 | } |
949928c1 | 1898 | |
e1e5e564 | 1899 | return 0; |
b60503ba MW |
1900 | } |
1901 | ||
b00a726a | 1902 | static int nvme_pci_enable(struct nvme_dev *dev) |
0877cb0d | 1903 | { |
b00a726a | 1904 | int result = -ENOMEM; |
e75ec752 | 1905 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1906 | |
1907 | if (pci_enable_device_mem(pdev)) | |
1908 | return result; | |
1909 | ||
0877cb0d | 1910 | pci_set_master(pdev); |
0877cb0d | 1911 | |
e75ec752 CH |
1912 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1913 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1914 | goto disable; |
0877cb0d | 1915 | |
7a67cbea | 1916 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 | 1917 | result = -ENODEV; |
b00a726a | 1918 | goto disable; |
0e53d180 | 1919 | } |
e32efbfc JA |
1920 | |
1921 | /* | |
a5229050 KB |
1922 | * Some devices and/or platforms don't advertise or work with INTx |
1923 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll | |
1924 | * adjust this later. | |
e32efbfc | 1925 | */ |
dca51e78 CH |
1926 | result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
1927 | if (result < 0) | |
1928 | return result; | |
e32efbfc | 1929 | |
20d0dfe6 | 1930 | dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
7a67cbea | 1931 | |
20d0dfe6 | 1932 | dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, |
b27c1e68 | 1933 | io_queue_depth); |
20d0dfe6 | 1934 | dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); |
7a67cbea | 1935 | dev->dbs = dev->bar + 4096; |
1f390c1f SG |
1936 | |
1937 | /* | |
1938 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
1939 | * some MacBook7,1 to avoid controller resets and data loss. | |
1940 | */ | |
1941 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
1942 | dev->q_depth = 2; | |
9bdcfb10 CH |
1943 | dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " |
1944 | "set queue depth=%u to work around controller resets\n", | |
1f390c1f | 1945 | dev->q_depth); |
d554b5e1 MP |
1946 | } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && |
1947 | (pdev->device == 0xa821 || pdev->device == 0xa822) && | |
20d0dfe6 | 1948 | NVME_CAP_MQES(dev->ctrl.cap) == 0) { |
d554b5e1 MP |
1949 | dev->q_depth = 64; |
1950 | dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " | |
1951 | "set queue depth=%u\n", dev->q_depth); | |
1f390c1f SG |
1952 | } |
1953 | ||
202021c1 SB |
1954 | /* |
1955 | * CMBs can currently only exist on >=1.2 PCIe devices. We only | |
1956 | * populate sysfs if a CMB is implemented. Note that we add the | |
1957 | * CMB attribute to the nvme_ctrl kobj which removes the need to remove | |
1958 | * it on exit. Since nvme_dev_attrs_group has no name we can pass | |
1959 | * NULL as final argument to sysfs_add_file_to_group. | |
1960 | */ | |
1961 | ||
8ef2074d | 1962 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) { |
8ffaadf7 | 1963 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d | 1964 | |
202021c1 SB |
1965 | if (dev->cmbsz) { |
1966 | if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, | |
1967 | &dev_attr_cmb.attr, NULL)) | |
9bdcfb10 | 1968 | dev_warn(dev->ctrl.device, |
202021c1 SB |
1969 | "failed to add sysfs attribute for CMB\n"); |
1970 | } | |
1971 | } | |
1972 | ||
a0a3408e KB |
1973 | pci_enable_pcie_error_reporting(pdev); |
1974 | pci_save_state(pdev); | |
0877cb0d KB |
1975 | return 0; |
1976 | ||
1977 | disable: | |
0877cb0d KB |
1978 | pci_disable_device(pdev); |
1979 | return result; | |
1980 | } | |
1981 | ||
1982 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
b00a726a KB |
1983 | { |
1984 | if (dev->bar) | |
1985 | iounmap(dev->bar); | |
a1f447b3 | 1986 | pci_release_mem_regions(to_pci_dev(dev->dev)); |
b00a726a KB |
1987 | } |
1988 | ||
1989 | static void nvme_pci_disable(struct nvme_dev *dev) | |
0877cb0d | 1990 | { |
e75ec752 CH |
1991 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1992 | ||
f63572df | 1993 | nvme_release_cmb(dev); |
dca51e78 | 1994 | pci_free_irq_vectors(pdev); |
0877cb0d | 1995 | |
a0a3408e KB |
1996 | if (pci_is_enabled(pdev)) { |
1997 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 1998 | pci_disable_device(pdev); |
4d115420 | 1999 | } |
4d115420 KB |
2000 | } |
2001 | ||
a5cdb68c | 2002 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 2003 | { |
70659060 | 2004 | int i, queues; |
302ad8cc KB |
2005 | bool dead = true; |
2006 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
22404274 | 2007 | |
77bf25ea | 2008 | mutex_lock(&dev->shutdown_lock); |
302ad8cc KB |
2009 | if (pci_is_enabled(pdev)) { |
2010 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
2011 | ||
ebef7368 KB |
2012 | if (dev->ctrl.state == NVME_CTRL_LIVE || |
2013 | dev->ctrl.state == NVME_CTRL_RESETTING) | |
302ad8cc KB |
2014 | nvme_start_freeze(&dev->ctrl); |
2015 | dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || | |
2016 | pdev->error_state != pci_channel_io_normal); | |
c9d3bf88 | 2017 | } |
c21377f8 | 2018 | |
302ad8cc KB |
2019 | /* |
2020 | * Give the controller a chance to complete all entered requests if | |
2021 | * doing a safe shutdown. | |
2022 | */ | |
87ad72a5 CH |
2023 | if (!dead) { |
2024 | if (shutdown) | |
2025 | nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); | |
2026 | ||
2027 | /* | |
2028 | * If the controller is still alive tell it to stop using the | |
2029 | * host memory buffer. In theory the shutdown / reset should | |
2030 | * make sure that it doesn't access the host memoery anymore, | |
2031 | * but I'd rather be safe than sorry.. | |
2032 | */ | |
2033 | if (dev->host_mem_descs) | |
2034 | nvme_set_host_mem(dev, 0); | |
2035 | ||
2036 | } | |
302ad8cc KB |
2037 | nvme_stop_queues(&dev->ctrl); |
2038 | ||
70659060 | 2039 | queues = dev->online_queues - 1; |
d858e5f0 | 2040 | for (i = dev->ctrl.queue_count - 1; i > 0; i--) |
c21377f8 GKB |
2041 | nvme_suspend_queue(dev->queues[i]); |
2042 | ||
302ad8cc | 2043 | if (dead) { |
82469c59 GKB |
2044 | /* A device might become IO incapable very soon during |
2045 | * probe, before the admin queue is configured. Thus, | |
2046 | * queue_count can be 0 here. | |
2047 | */ | |
d858e5f0 | 2048 | if (dev->ctrl.queue_count) |
82469c59 | 2049 | nvme_suspend_queue(dev->queues[0]); |
4d115420 | 2050 | } else { |
70659060 | 2051 | nvme_disable_io_queues(dev, queues); |
a5cdb68c | 2052 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 2053 | } |
b00a726a | 2054 | nvme_pci_disable(dev); |
07836e65 | 2055 | |
e1958e65 ML |
2056 | blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); |
2057 | blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); | |
302ad8cc KB |
2058 | |
2059 | /* | |
2060 | * The driver will not be starting up queues again if shutting down so | |
2061 | * must flush all entered requests to their failed completion to avoid | |
2062 | * deadlocking blk-mq hot-cpu notifier. | |
2063 | */ | |
2064 | if (shutdown) | |
2065 | nvme_start_queues(&dev->ctrl); | |
77bf25ea | 2066 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
2067 | } |
2068 | ||
091b6092 MW |
2069 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2070 | { | |
e75ec752 | 2071 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
2072 | PAGE_SIZE, PAGE_SIZE, 0); |
2073 | if (!dev->prp_page_pool) | |
2074 | return -ENOMEM; | |
2075 | ||
99802a7a | 2076 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 2077 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
2078 | 256, 256, 0); |
2079 | if (!dev->prp_small_pool) { | |
2080 | dma_pool_destroy(dev->prp_page_pool); | |
2081 | return -ENOMEM; | |
2082 | } | |
091b6092 MW |
2083 | return 0; |
2084 | } | |
2085 | ||
2086 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2087 | { | |
2088 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2089 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2090 | } |
2091 | ||
1673f1f0 | 2092 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 2093 | { |
1673f1f0 | 2094 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 2095 | |
f9f38e33 | 2096 | nvme_dbbuf_dma_free(dev); |
e75ec752 | 2097 | put_device(dev->dev); |
4af0e21c KB |
2098 | if (dev->tagset.tags) |
2099 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
2100 | if (dev->ctrl.admin_q) |
2101 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 | 2102 | kfree(dev->queues); |
e286bcfc | 2103 | free_opal_dev(dev->ctrl.opal_dev); |
5e82e952 KB |
2104 | kfree(dev); |
2105 | } | |
2106 | ||
f58944e2 KB |
2107 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) |
2108 | { | |
237045fc | 2109 | dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); |
f58944e2 KB |
2110 | |
2111 | kref_get(&dev->ctrl.kref); | |
69d9a99c | 2112 | nvme_dev_disable(dev, false); |
f58944e2 KB |
2113 | if (!schedule_work(&dev->remove_work)) |
2114 | nvme_put_ctrl(&dev->ctrl); | |
2115 | } | |
2116 | ||
fd634f41 | 2117 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 2118 | { |
d86c4d8e CH |
2119 | struct nvme_dev *dev = |
2120 | container_of(work, struct nvme_dev, ctrl.reset_work); | |
a98e58e5 | 2121 | bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); |
f58944e2 | 2122 | int result = -ENODEV; |
5e82e952 | 2123 | |
82b057ca | 2124 | if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) |
fd634f41 | 2125 | goto out; |
5e82e952 | 2126 | |
fd634f41 CH |
2127 | /* |
2128 | * If we're called to reset a live controller first shut it down before | |
2129 | * moving on. | |
2130 | */ | |
b00a726a | 2131 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
a5cdb68c | 2132 | nvme_dev_disable(dev, false); |
5e82e952 | 2133 | |
b00a726a | 2134 | result = nvme_pci_enable(dev); |
f0b50732 | 2135 | if (result) |
3cf519b5 | 2136 | goto out; |
f0b50732 | 2137 | |
01ad0990 | 2138 | result = nvme_pci_configure_admin_queue(dev); |
f0b50732 | 2139 | if (result) |
f58944e2 | 2140 | goto out; |
f0b50732 | 2141 | |
a4aea562 | 2142 | nvme_init_queue(dev->queues[0], 0); |
0fb59cbc KB |
2143 | result = nvme_alloc_admin_tags(dev); |
2144 | if (result) | |
f58944e2 | 2145 | goto out; |
b9afca3e | 2146 | |
ce4541f4 CH |
2147 | result = nvme_init_identify(&dev->ctrl); |
2148 | if (result) | |
f58944e2 | 2149 | goto out; |
ce4541f4 | 2150 | |
e286bcfc SB |
2151 | if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { |
2152 | if (!dev->ctrl.opal_dev) | |
2153 | dev->ctrl.opal_dev = | |
2154 | init_opal_dev(&dev->ctrl, &nvme_sec_submit); | |
2155 | else if (was_suspend) | |
2156 | opal_unlock_from_suspend(dev->ctrl.opal_dev); | |
2157 | } else { | |
2158 | free_opal_dev(dev->ctrl.opal_dev); | |
2159 | dev->ctrl.opal_dev = NULL; | |
4f1244c8 | 2160 | } |
a98e58e5 | 2161 | |
f9f38e33 HK |
2162 | if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { |
2163 | result = nvme_dbbuf_dma_alloc(dev); | |
2164 | if (result) | |
2165 | dev_warn(dev->dev, | |
2166 | "unable to allocate dma for dbbuf\n"); | |
2167 | } | |
2168 | ||
87ad72a5 CH |
2169 | if (dev->ctrl.hmpre) |
2170 | nvme_setup_host_mem(dev); | |
2171 | ||
f0b50732 | 2172 | result = nvme_setup_io_queues(dev); |
badc34d4 | 2173 | if (result) |
f58944e2 | 2174 | goto out; |
f0b50732 | 2175 | |
2659e57b CH |
2176 | /* |
2177 | * Keep the controller around but remove all namespaces if we don't have | |
2178 | * any working I/O queue. | |
2179 | */ | |
3cf519b5 | 2180 | if (dev->online_queues < 2) { |
1b3c47c1 | 2181 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
3b24774e | 2182 | nvme_kill_queues(&dev->ctrl); |
5bae7f73 | 2183 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 | 2184 | } else { |
25646264 | 2185 | nvme_start_queues(&dev->ctrl); |
302ad8cc | 2186 | nvme_wait_freeze(&dev->ctrl); |
3cf519b5 | 2187 | nvme_dev_add(dev); |
302ad8cc | 2188 | nvme_unfreeze(&dev->ctrl); |
3cf519b5 CH |
2189 | } |
2190 | ||
bb8d261e CH |
2191 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { |
2192 | dev_warn(dev->ctrl.device, "failed to mark controller live\n"); | |
2193 | goto out; | |
2194 | } | |
92911a55 | 2195 | |
d09f2b45 | 2196 | nvme_start_ctrl(&dev->ctrl); |
3cf519b5 | 2197 | return; |
f0b50732 | 2198 | |
3cf519b5 | 2199 | out: |
f58944e2 | 2200 | nvme_remove_dead_ctrl(dev, result); |
f0b50732 KB |
2201 | } |
2202 | ||
5c8809e6 | 2203 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 2204 | { |
5c8809e6 | 2205 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 2206 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 | 2207 | |
69d9a99c | 2208 | nvme_kill_queues(&dev->ctrl); |
9a6b9458 | 2209 | if (pci_get_drvdata(pdev)) |
921920ab | 2210 | device_release_driver(&pdev->dev); |
1673f1f0 | 2211 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
2212 | } |
2213 | ||
1c63dc66 | 2214 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 2215 | { |
1c63dc66 | 2216 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 2217 | return 0; |
9ca97374 TH |
2218 | } |
2219 | ||
5fd4ce1b | 2220 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 2221 | { |
5fd4ce1b CH |
2222 | writel(val, to_nvme_dev(ctrl)->bar + off); |
2223 | return 0; | |
2224 | } | |
4cc06521 | 2225 | |
7fd8930f CH |
2226 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2227 | { | |
2228 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
2229 | return 0; | |
4cc06521 KB |
2230 | } |
2231 | ||
1c63dc66 | 2232 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
1a353d85 | 2233 | .name = "pcie", |
e439bb12 | 2234 | .module = THIS_MODULE, |
c81bfba9 | 2235 | .flags = NVME_F_METADATA_SUPPORTED, |
1c63dc66 | 2236 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 2237 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 2238 | .reg_read64 = nvme_pci_reg_read64, |
1673f1f0 | 2239 | .free_ctrl = nvme_pci_free_ctrl, |
f866fc42 | 2240 | .submit_async_event = nvme_pci_submit_async_event, |
1c63dc66 | 2241 | }; |
4cc06521 | 2242 | |
b00a726a KB |
2243 | static int nvme_dev_map(struct nvme_dev *dev) |
2244 | { | |
b00a726a KB |
2245 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2246 | ||
a1f447b3 | 2247 | if (pci_request_mem_regions(pdev, "nvme")) |
b00a726a KB |
2248 | return -ENODEV; |
2249 | ||
97f6ef64 | 2250 | if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) |
b00a726a KB |
2251 | goto release; |
2252 | ||
9fa196e7 | 2253 | return 0; |
b00a726a | 2254 | release: |
9fa196e7 MG |
2255 | pci_release_mem_regions(pdev); |
2256 | return -ENODEV; | |
b00a726a KB |
2257 | } |
2258 | ||
ff5350a8 AL |
2259 | static unsigned long check_dell_samsung_bug(struct pci_dev *pdev) |
2260 | { | |
2261 | if (pdev->vendor == 0x144d && pdev->device == 0xa802) { | |
2262 | /* | |
2263 | * Several Samsung devices seem to drop off the PCIe bus | |
2264 | * randomly when APST is on and uses the deepest sleep state. | |
2265 | * This has been observed on a Samsung "SM951 NVMe SAMSUNG | |
2266 | * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD | |
2267 | * 950 PRO 256GB", but it seems to be restricted to two Dell | |
2268 | * laptops. | |
2269 | */ | |
2270 | if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && | |
2271 | (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || | |
2272 | dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) | |
2273 | return NVME_QUIRK_NO_DEEPEST_PS; | |
2274 | } | |
2275 | ||
2276 | return 0; | |
2277 | } | |
2278 | ||
8d85fce7 | 2279 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2280 | { |
a4aea562 | 2281 | int node, result = -ENOMEM; |
b60503ba | 2282 | struct nvme_dev *dev; |
ff5350a8 | 2283 | unsigned long quirks = id->driver_data; |
b60503ba | 2284 | |
a4aea562 MB |
2285 | node = dev_to_node(&pdev->dev); |
2286 | if (node == NUMA_NO_NODE) | |
2fa84351 | 2287 | set_dev_node(&pdev->dev, first_memory_node); |
a4aea562 MB |
2288 | |
2289 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2290 | if (!dev) |
2291 | return -ENOMEM; | |
a4aea562 MB |
2292 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2293 | GFP_KERNEL, node); | |
b60503ba MW |
2294 | if (!dev->queues) |
2295 | goto free; | |
2296 | ||
e75ec752 | 2297 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2298 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2299 | |
b00a726a KB |
2300 | result = nvme_dev_map(dev); |
2301 | if (result) | |
b00c9b7a | 2302 | goto put_pci; |
b00a726a | 2303 | |
d86c4d8e | 2304 | INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); |
5c8809e6 | 2305 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
77bf25ea | 2306 | mutex_init(&dev->shutdown_lock); |
db3cbfff | 2307 | init_completion(&dev->ioq_wait); |
b60503ba | 2308 | |
091b6092 MW |
2309 | result = nvme_setup_prp_pools(dev); |
2310 | if (result) | |
b00c9b7a | 2311 | goto unmap; |
4cc06521 | 2312 | |
ff5350a8 AL |
2313 | quirks |= check_dell_samsung_bug(pdev); |
2314 | ||
f3ca80fc | 2315 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
ff5350a8 | 2316 | quirks); |
4cc06521 | 2317 | if (result) |
2e1d8448 | 2318 | goto release_pools; |
740216fc | 2319 | |
82b057ca | 2320 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING); |
1b3c47c1 SG |
2321 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
2322 | ||
d86c4d8e | 2323 | queue_work(nvme_wq, &dev->ctrl.reset_work); |
b60503ba MW |
2324 | return 0; |
2325 | ||
0877cb0d | 2326 | release_pools: |
091b6092 | 2327 | nvme_release_prp_pools(dev); |
b00c9b7a CJ |
2328 | unmap: |
2329 | nvme_dev_unmap(dev); | |
a96d4f5c | 2330 | put_pci: |
e75ec752 | 2331 | put_device(dev->dev); |
b60503ba MW |
2332 | free: |
2333 | kfree(dev->queues); | |
b60503ba MW |
2334 | kfree(dev); |
2335 | return result; | |
2336 | } | |
2337 | ||
775755ed | 2338 | static void nvme_reset_prepare(struct pci_dev *pdev) |
f0d54a54 | 2339 | { |
a6739479 | 2340 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f263fbb8 | 2341 | nvme_dev_disable(dev, false); |
775755ed | 2342 | } |
f0d54a54 | 2343 | |
775755ed CH |
2344 | static void nvme_reset_done(struct pci_dev *pdev) |
2345 | { | |
f263fbb8 LT |
2346 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
2347 | nvme_reset_ctrl(&dev->ctrl); | |
f0d54a54 KB |
2348 | } |
2349 | ||
09ece142 KB |
2350 | static void nvme_shutdown(struct pci_dev *pdev) |
2351 | { | |
2352 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
a5cdb68c | 2353 | nvme_dev_disable(dev, true); |
09ece142 KB |
2354 | } |
2355 | ||
f58944e2 KB |
2356 | /* |
2357 | * The driver's remove may be called on a device in a partially initialized | |
2358 | * state. This function must not have any dependencies on the device state in | |
2359 | * order to proceed. | |
2360 | */ | |
8d85fce7 | 2361 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2362 | { |
2363 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 2364 | |
bb8d261e CH |
2365 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
2366 | ||
d86c4d8e | 2367 | cancel_work_sync(&dev->ctrl.reset_work); |
9a6b9458 | 2368 | pci_set_drvdata(pdev, NULL); |
0ff9d4e1 | 2369 | |
6db28eda | 2370 | if (!pci_device_is_present(pdev)) { |
0ff9d4e1 | 2371 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); |
6db28eda KB |
2372 | nvme_dev_disable(dev, false); |
2373 | } | |
0ff9d4e1 | 2374 | |
d86c4d8e | 2375 | flush_work(&dev->ctrl.reset_work); |
d09f2b45 SG |
2376 | nvme_stop_ctrl(&dev->ctrl); |
2377 | nvme_remove_namespaces(&dev->ctrl); | |
a5cdb68c | 2378 | nvme_dev_disable(dev, true); |
87ad72a5 | 2379 | nvme_free_host_mem(dev); |
a4aea562 | 2380 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2381 | nvme_free_queues(dev, 0); |
d09f2b45 | 2382 | nvme_uninit_ctrl(&dev->ctrl); |
9a6b9458 | 2383 | nvme_release_prp_pools(dev); |
b00a726a | 2384 | nvme_dev_unmap(dev); |
1673f1f0 | 2385 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2386 | } |
2387 | ||
13880f5b KB |
2388 | static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) |
2389 | { | |
2390 | int ret = 0; | |
2391 | ||
2392 | if (numvfs == 0) { | |
2393 | if (pci_vfs_assigned(pdev)) { | |
2394 | dev_warn(&pdev->dev, | |
2395 | "Cannot disable SR-IOV VFs while assigned\n"); | |
2396 | return -EPERM; | |
2397 | } | |
2398 | pci_disable_sriov(pdev); | |
2399 | return 0; | |
2400 | } | |
2401 | ||
2402 | ret = pci_enable_sriov(pdev, numvfs); | |
2403 | return ret ? ret : numvfs; | |
2404 | } | |
2405 | ||
671a6018 | 2406 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2407 | static int nvme_suspend(struct device *dev) |
2408 | { | |
2409 | struct pci_dev *pdev = to_pci_dev(dev); | |
2410 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2411 | ||
a5cdb68c | 2412 | nvme_dev_disable(ndev, true); |
cd638946 KB |
2413 | return 0; |
2414 | } | |
2415 | ||
2416 | static int nvme_resume(struct device *dev) | |
2417 | { | |
2418 | struct pci_dev *pdev = to_pci_dev(dev); | |
2419 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2420 | |
d86c4d8e | 2421 | nvme_reset_ctrl(&ndev->ctrl); |
9a6b9458 | 2422 | return 0; |
cd638946 | 2423 | } |
671a6018 | 2424 | #endif |
cd638946 KB |
2425 | |
2426 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2427 | |
a0a3408e KB |
2428 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2429 | pci_channel_state_t state) | |
2430 | { | |
2431 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2432 | ||
2433 | /* | |
2434 | * A frozen channel requires a reset. When detected, this method will | |
2435 | * shutdown the controller to quiesce. The controller will be restarted | |
2436 | * after the slot reset through driver's slot_reset callback. | |
2437 | */ | |
a0a3408e KB |
2438 | switch (state) { |
2439 | case pci_channel_io_normal: | |
2440 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2441 | case pci_channel_io_frozen: | |
d011fb31 KB |
2442 | dev_warn(dev->ctrl.device, |
2443 | "frozen state error detected, reset controller\n"); | |
a5cdb68c | 2444 | nvme_dev_disable(dev, false); |
a0a3408e KB |
2445 | return PCI_ERS_RESULT_NEED_RESET; |
2446 | case pci_channel_io_perm_failure: | |
d011fb31 KB |
2447 | dev_warn(dev->ctrl.device, |
2448 | "failure state error detected, request disconnect\n"); | |
a0a3408e KB |
2449 | return PCI_ERS_RESULT_DISCONNECT; |
2450 | } | |
2451 | return PCI_ERS_RESULT_NEED_RESET; | |
2452 | } | |
2453 | ||
2454 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2455 | { | |
2456 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2457 | ||
1b3c47c1 | 2458 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e | 2459 | pci_restore_state(pdev); |
d86c4d8e | 2460 | nvme_reset_ctrl(&dev->ctrl); |
a0a3408e KB |
2461 | return PCI_ERS_RESULT_RECOVERED; |
2462 | } | |
2463 | ||
2464 | static void nvme_error_resume(struct pci_dev *pdev) | |
2465 | { | |
2466 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2467 | } | |
2468 | ||
1d352035 | 2469 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2470 | .error_detected = nvme_error_detected, |
b60503ba MW |
2471 | .slot_reset = nvme_slot_reset, |
2472 | .resume = nvme_error_resume, | |
775755ed CH |
2473 | .reset_prepare = nvme_reset_prepare, |
2474 | .reset_done = nvme_reset_done, | |
b60503ba MW |
2475 | }; |
2476 | ||
6eb0d698 | 2477 | static const struct pci_device_id nvme_id_table[] = { |
106198ed | 2478 | { PCI_VDEVICE(INTEL, 0x0953), |
08095e70 | 2479 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
e850fd16 | 2480 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
99466e70 KB |
2481 | { PCI_VDEVICE(INTEL, 0x0a53), |
2482 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
e850fd16 | 2483 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
99466e70 KB |
2484 | { PCI_VDEVICE(INTEL, 0x0a54), |
2485 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
e850fd16 | 2486 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
f99cb7af DWF |
2487 | { PCI_VDEVICE(INTEL, 0x0a55), |
2488 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
2489 | NVME_QUIRK_DEALLOCATE_ZEROES, }, | |
50af47d0 AL |
2490 | { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ |
2491 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS }, | |
540c801c KB |
2492 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2493 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
54adc010 GP |
2494 | { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ |
2495 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
015282c9 WW |
2496 | { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ |
2497 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
d554b5e1 MP |
2498 | { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ |
2499 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
2500 | { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ | |
2501 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
b60503ba | 2502 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2503 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
124298bd | 2504 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, |
b60503ba MW |
2505 | { 0, } |
2506 | }; | |
2507 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2508 | ||
2509 | static struct pci_driver nvme_driver = { | |
2510 | .name = "nvme", | |
2511 | .id_table = nvme_id_table, | |
2512 | .probe = nvme_probe, | |
8d85fce7 | 2513 | .remove = nvme_remove, |
09ece142 | 2514 | .shutdown = nvme_shutdown, |
cd638946 KB |
2515 | .driver = { |
2516 | .pm = &nvme_dev_pm_ops, | |
2517 | }, | |
13880f5b | 2518 | .sriov_configure = nvme_pci_sriov_configure, |
b60503ba MW |
2519 | .err_handler = &nvme_err_handler, |
2520 | }; | |
2521 | ||
2522 | static int __init nvme_init(void) | |
2523 | { | |
9a6327d2 | 2524 | return pci_register_driver(&nvme_driver); |
b60503ba MW |
2525 | } |
2526 | ||
2527 | static void __exit nvme_exit(void) | |
2528 | { | |
2529 | pci_unregister_driver(&nvme_driver); | |
21bd78bc | 2530 | _nvme_check_size(); |
b60503ba MW |
2531 | } |
2532 | ||
2533 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2534 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2535 | MODULE_VERSION("1.0"); |
b60503ba MW |
2536 | module_init(nvme_init); |
2537 | module_exit(nvme_exit); |