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5f37396d | 1 | // SPDX-License-Identifier: GPL-2.0 |
b60503ba MW |
2 | /* |
3 | * NVM Express device driver | |
6eb0d698 | 4 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
5 | */ |
6 | ||
a0a3408e | 7 | #include <linux/aer.h> |
18119775 | 8 | #include <linux/async.h> |
b60503ba | 9 | #include <linux/blkdev.h> |
a4aea562 | 10 | #include <linux/blk-mq.h> |
dca51e78 | 11 | #include <linux/blk-mq-pci.h> |
ff5350a8 | 12 | #include <linux/dmi.h> |
b60503ba MW |
13 | #include <linux/init.h> |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/io.h> | |
b60503ba MW |
16 | #include <linux/mm.h> |
17 | #include <linux/module.h> | |
77bf25ea | 18 | #include <linux/mutex.h> |
d0877473 | 19 | #include <linux/once.h> |
b60503ba | 20 | #include <linux/pci.h> |
e1e5e564 | 21 | #include <linux/t10-pi.h> |
b60503ba | 22 | #include <linux/types.h> |
2f8e2c87 | 23 | #include <linux/io-64-nonatomic-lo-hi.h> |
a98e58e5 | 24 | #include <linux/sed-opal.h> |
0f238ff5 | 25 | #include <linux/pci-p2pdma.h> |
797a796a | 26 | |
604c01d5 | 27 | #include "trace.h" |
f11bb3e2 CH |
28 | #include "nvme.h" |
29 | ||
b60503ba MW |
30 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
31 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
c965809c | 32 | |
a7a7cbe3 | 33 | #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) |
9d43cf64 | 34 | |
943e942e JA |
35 | /* |
36 | * These can be higher, but we need to ensure that any command doesn't | |
37 | * require an sg allocation that needs more than a page of data. | |
38 | */ | |
39 | #define NVME_MAX_KB_SZ 4096 | |
40 | #define NVME_MAX_SEGS 127 | |
41 | ||
58ffacb5 MW |
42 | static int use_threaded_interrupts; |
43 | module_param(use_threaded_interrupts, int, 0); | |
44 | ||
8ffaadf7 | 45 | static bool use_cmb_sqes = true; |
69f4eb9f | 46 | module_param(use_cmb_sqes, bool, 0444); |
8ffaadf7 JD |
47 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); |
48 | ||
87ad72a5 CH |
49 | static unsigned int max_host_mem_size_mb = 128; |
50 | module_param(max_host_mem_size_mb, uint, 0444); | |
51 | MODULE_PARM_DESC(max_host_mem_size_mb, | |
52 | "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); | |
1fa6aead | 53 | |
a7a7cbe3 CK |
54 | static unsigned int sgl_threshold = SZ_32K; |
55 | module_param(sgl_threshold, uint, 0644); | |
56 | MODULE_PARM_DESC(sgl_threshold, | |
57 | "Use SGLs when average request segment size is larger or equal to " | |
58 | "this size. Use 0 to disable SGLs."); | |
59 | ||
b27c1e68 | 60 | static int io_queue_depth_set(const char *val, const struct kernel_param *kp); |
61 | static const struct kernel_param_ops io_queue_depth_ops = { | |
62 | .set = io_queue_depth_set, | |
63 | .get = param_get_int, | |
64 | }; | |
65 | ||
66 | static int io_queue_depth = 1024; | |
67 | module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); | |
68 | MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); | |
69 | ||
3b6592f7 JA |
70 | static int queue_count_set(const char *val, const struct kernel_param *kp); |
71 | static const struct kernel_param_ops queue_count_ops = { | |
72 | .set = queue_count_set, | |
73 | .get = param_get_int, | |
74 | }; | |
75 | ||
76 | static int write_queues; | |
77 | module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644); | |
78 | MODULE_PARM_DESC(write_queues, | |
79 | "Number of queues to use for writes. If not set, reads and writes " | |
80 | "will share a queue set."); | |
81 | ||
a4668d9b | 82 | static int poll_queues = 0; |
4b04cc6a JA |
83 | module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644); |
84 | MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); | |
85 | ||
1c63dc66 CH |
86 | struct nvme_dev; |
87 | struct nvme_queue; | |
b3fffdef | 88 | |
a5cdb68c | 89 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
8fae268b | 90 | static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); |
d4b4ff8e | 91 | |
1c63dc66 CH |
92 | /* |
93 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
94 | */ | |
95 | struct nvme_dev { | |
147b27e4 | 96 | struct nvme_queue *queues; |
1c63dc66 CH |
97 | struct blk_mq_tag_set tagset; |
98 | struct blk_mq_tag_set admin_tagset; | |
99 | u32 __iomem *dbs; | |
100 | struct device *dev; | |
101 | struct dma_pool *prp_page_pool; | |
102 | struct dma_pool *prp_small_pool; | |
1c63dc66 CH |
103 | unsigned online_queues; |
104 | unsigned max_qid; | |
e20ba6e1 | 105 | unsigned io_queues[HCTX_MAX_TYPES]; |
22b55601 | 106 | unsigned int num_vecs; |
1c63dc66 CH |
107 | int q_depth; |
108 | u32 db_stride; | |
1c63dc66 | 109 | void __iomem *bar; |
97f6ef64 | 110 | unsigned long bar_mapped_size; |
5c8809e6 | 111 | struct work_struct remove_work; |
77bf25ea | 112 | struct mutex shutdown_lock; |
1c63dc66 | 113 | bool subsystem; |
1c63dc66 | 114 | u64 cmb_size; |
0f238ff5 | 115 | bool cmb_use_sqes; |
1c63dc66 | 116 | u32 cmbsz; |
202021c1 | 117 | u32 cmbloc; |
1c63dc66 | 118 | struct nvme_ctrl ctrl; |
87ad72a5 | 119 | |
943e942e JA |
120 | mempool_t *iod_mempool; |
121 | ||
87ad72a5 | 122 | /* shadow doorbell buffer support: */ |
f9f38e33 HK |
123 | u32 *dbbuf_dbs; |
124 | dma_addr_t dbbuf_dbs_dma_addr; | |
125 | u32 *dbbuf_eis; | |
126 | dma_addr_t dbbuf_eis_dma_addr; | |
87ad72a5 CH |
127 | |
128 | /* host memory buffer support: */ | |
129 | u64 host_mem_size; | |
130 | u32 nr_host_mem_descs; | |
4033f35d | 131 | dma_addr_t host_mem_descs_dma; |
87ad72a5 CH |
132 | struct nvme_host_mem_buf_desc *host_mem_descs; |
133 | void **host_mem_desc_bufs; | |
4d115420 | 134 | }; |
1fa6aead | 135 | |
b27c1e68 | 136 | static int io_queue_depth_set(const char *val, const struct kernel_param *kp) |
137 | { | |
138 | int n = 0, ret; | |
139 | ||
140 | ret = kstrtoint(val, 10, &n); | |
141 | if (ret != 0 || n < 2) | |
142 | return -EINVAL; | |
143 | ||
144 | return param_set_int(val, kp); | |
145 | } | |
146 | ||
3b6592f7 JA |
147 | static int queue_count_set(const char *val, const struct kernel_param *kp) |
148 | { | |
66564867 | 149 | int n, ret; |
3b6592f7 JA |
150 | |
151 | ret = kstrtoint(val, 10, &n); | |
e895fedf BVA |
152 | if (ret) |
153 | return ret; | |
3b6592f7 JA |
154 | if (n > num_possible_cpus()) |
155 | n = num_possible_cpus(); | |
156 | ||
157 | return param_set_int(val, kp); | |
158 | } | |
159 | ||
f9f38e33 HK |
160 | static inline unsigned int sq_idx(unsigned int qid, u32 stride) |
161 | { | |
162 | return qid * 2 * stride; | |
163 | } | |
164 | ||
165 | static inline unsigned int cq_idx(unsigned int qid, u32 stride) | |
166 | { | |
167 | return (qid * 2 + 1) * stride; | |
168 | } | |
169 | ||
1c63dc66 CH |
170 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
171 | { | |
172 | return container_of(ctrl, struct nvme_dev, ctrl); | |
173 | } | |
174 | ||
b60503ba MW |
175 | /* |
176 | * An NVM Express queue. Each device has at least two (one for admin | |
177 | * commands and one for I/O commands). | |
178 | */ | |
179 | struct nvme_queue { | |
091b6092 | 180 | struct nvme_dev *dev; |
1ab0cd69 | 181 | spinlock_t sq_lock; |
b60503ba | 182 | struct nvme_command *sq_cmds; |
3a7afd8e CH |
183 | /* only used for poll queues: */ |
184 | spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; | |
b60503ba | 185 | volatile struct nvme_completion *cqes; |
42483228 | 186 | struct blk_mq_tags **tags; |
b60503ba MW |
187 | dma_addr_t sq_dma_addr; |
188 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
189 | u32 __iomem *q_db; |
190 | u16 q_depth; | |
7c349dde | 191 | u16 cq_vector; |
b60503ba | 192 | u16 sq_tail; |
04f3eafd | 193 | u16 last_sq_tail; |
b60503ba | 194 | u16 cq_head; |
68fa9dbe | 195 | u16 last_cq_head; |
c30341dc | 196 | u16 qid; |
e9539f47 | 197 | u8 cq_phase; |
4e224106 CH |
198 | unsigned long flags; |
199 | #define NVMEQ_ENABLED 0 | |
63223078 | 200 | #define NVMEQ_SQ_CMB 1 |
d1ed6aa1 | 201 | #define NVMEQ_DELETE_ERROR 2 |
7c349dde | 202 | #define NVMEQ_POLLED 3 |
f9f38e33 HK |
203 | u32 *dbbuf_sq_db; |
204 | u32 *dbbuf_cq_db; | |
205 | u32 *dbbuf_sq_ei; | |
206 | u32 *dbbuf_cq_ei; | |
d1ed6aa1 | 207 | struct completion delete_done; |
b60503ba MW |
208 | }; |
209 | ||
71bd150c | 210 | /* |
9b048119 CH |
211 | * The nvme_iod describes the data in an I/O. |
212 | * | |
213 | * The sg pointer contains the list of PRP/SGL chunk allocations in addition | |
214 | * to the actual struct scatterlist. | |
71bd150c CH |
215 | */ |
216 | struct nvme_iod { | |
d49187e9 | 217 | struct nvme_request req; |
f4800d6d | 218 | struct nvme_queue *nvmeq; |
a7a7cbe3 | 219 | bool use_sgl; |
f4800d6d | 220 | int aborted; |
71bd150c | 221 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c | 222 | int nents; /* Used in scatterlist */ |
71bd150c | 223 | dma_addr_t first_dma; |
dff824b2 | 224 | unsigned int dma_len; /* length of single DMA segment mapping */ |
783b94bd | 225 | dma_addr_t meta_dma; |
f4800d6d | 226 | struct scatterlist *sg; |
b60503ba MW |
227 | }; |
228 | ||
3b6592f7 JA |
229 | static unsigned int max_io_queues(void) |
230 | { | |
4b04cc6a | 231 | return num_possible_cpus() + write_queues + poll_queues; |
3b6592f7 JA |
232 | } |
233 | ||
234 | static unsigned int max_queue_count(void) | |
235 | { | |
236 | /* IO queues + admin queue */ | |
237 | return 1 + max_io_queues(); | |
238 | } | |
239 | ||
f9f38e33 HK |
240 | static inline unsigned int nvme_dbbuf_size(u32 stride) |
241 | { | |
3b6592f7 | 242 | return (max_queue_count() * 8 * stride); |
f9f38e33 HK |
243 | } |
244 | ||
245 | static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) | |
246 | { | |
247 | unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); | |
248 | ||
249 | if (dev->dbbuf_dbs) | |
250 | return 0; | |
251 | ||
252 | dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, | |
253 | &dev->dbbuf_dbs_dma_addr, | |
254 | GFP_KERNEL); | |
255 | if (!dev->dbbuf_dbs) | |
256 | return -ENOMEM; | |
257 | dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, | |
258 | &dev->dbbuf_eis_dma_addr, | |
259 | GFP_KERNEL); | |
260 | if (!dev->dbbuf_eis) { | |
261 | dma_free_coherent(dev->dev, mem_size, | |
262 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
263 | dev->dbbuf_dbs = NULL; | |
264 | return -ENOMEM; | |
265 | } | |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
270 | static void nvme_dbbuf_dma_free(struct nvme_dev *dev) | |
271 | { | |
272 | unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); | |
273 | ||
274 | if (dev->dbbuf_dbs) { | |
275 | dma_free_coherent(dev->dev, mem_size, | |
276 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
277 | dev->dbbuf_dbs = NULL; | |
278 | } | |
279 | if (dev->dbbuf_eis) { | |
280 | dma_free_coherent(dev->dev, mem_size, | |
281 | dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); | |
282 | dev->dbbuf_eis = NULL; | |
283 | } | |
284 | } | |
285 | ||
286 | static void nvme_dbbuf_init(struct nvme_dev *dev, | |
287 | struct nvme_queue *nvmeq, int qid) | |
288 | { | |
289 | if (!dev->dbbuf_dbs || !qid) | |
290 | return; | |
291 | ||
292 | nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; | |
293 | nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; | |
294 | nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; | |
295 | nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; | |
296 | } | |
297 | ||
298 | static void nvme_dbbuf_set(struct nvme_dev *dev) | |
299 | { | |
300 | struct nvme_command c; | |
301 | ||
302 | if (!dev->dbbuf_dbs) | |
303 | return; | |
304 | ||
305 | memset(&c, 0, sizeof(c)); | |
306 | c.dbbuf.opcode = nvme_admin_dbbuf; | |
307 | c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); | |
308 | c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); | |
309 | ||
310 | if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { | |
9bdcfb10 | 311 | dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); |
f9f38e33 HK |
312 | /* Free memory and continue on */ |
313 | nvme_dbbuf_dma_free(dev); | |
314 | } | |
315 | } | |
316 | ||
317 | static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) | |
318 | { | |
319 | return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); | |
320 | } | |
321 | ||
322 | /* Update dbbuf and return true if an MMIO is required */ | |
323 | static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, | |
324 | volatile u32 *dbbuf_ei) | |
325 | { | |
326 | if (dbbuf_db) { | |
327 | u16 old_value; | |
328 | ||
329 | /* | |
330 | * Ensure that the queue is written before updating | |
331 | * the doorbell in memory | |
332 | */ | |
333 | wmb(); | |
334 | ||
335 | old_value = *dbbuf_db; | |
336 | *dbbuf_db = value; | |
337 | ||
f1ed3df2 MW |
338 | /* |
339 | * Ensure that the doorbell is updated before reading the event | |
340 | * index from memory. The controller needs to provide similar | |
341 | * ordering to ensure the envent index is updated before reading | |
342 | * the doorbell. | |
343 | */ | |
344 | mb(); | |
345 | ||
f9f38e33 HK |
346 | if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) |
347 | return false; | |
348 | } | |
349 | ||
350 | return true; | |
b60503ba MW |
351 | } |
352 | ||
ac3dd5bd JA |
353 | /* |
354 | * Will slightly overestimate the number of pages needed. This is OK | |
355 | * as it only leads to a small amount of wasted memory for the lifetime of | |
356 | * the I/O. | |
357 | */ | |
358 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
359 | { | |
5fd4ce1b CH |
360 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
361 | dev->ctrl.page_size); | |
ac3dd5bd JA |
362 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
363 | } | |
364 | ||
a7a7cbe3 CK |
365 | /* |
366 | * Calculates the number of pages needed for the SGL segments. For example a 4k | |
367 | * page can accommodate 256 SGL descriptors. | |
368 | */ | |
369 | static int nvme_pci_npages_sgl(unsigned int num_seg) | |
ac3dd5bd | 370 | { |
a7a7cbe3 | 371 | return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); |
f4800d6d | 372 | } |
ac3dd5bd | 373 | |
a7a7cbe3 CK |
374 | static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, |
375 | unsigned int size, unsigned int nseg, bool use_sgl) | |
f4800d6d | 376 | { |
a7a7cbe3 CK |
377 | size_t alloc_size; |
378 | ||
379 | if (use_sgl) | |
380 | alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); | |
381 | else | |
382 | alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); | |
383 | ||
384 | return alloc_size + sizeof(struct scatterlist) * nseg; | |
f4800d6d | 385 | } |
ac3dd5bd | 386 | |
a4aea562 MB |
387 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
388 | unsigned int hctx_idx) | |
e85248e5 | 389 | { |
a4aea562 | 390 | struct nvme_dev *dev = data; |
147b27e4 | 391 | struct nvme_queue *nvmeq = &dev->queues[0]; |
a4aea562 | 392 | |
42483228 KB |
393 | WARN_ON(hctx_idx != 0); |
394 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
395 | WARN_ON(nvmeq->tags); | |
396 | ||
a4aea562 | 397 | hctx->driver_data = nvmeq; |
42483228 | 398 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 399 | return 0; |
e85248e5 MW |
400 | } |
401 | ||
4af0e21c KB |
402 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
403 | { | |
404 | struct nvme_queue *nvmeq = hctx->driver_data; | |
405 | ||
406 | nvmeq->tags = NULL; | |
407 | } | |
408 | ||
a4aea562 MB |
409 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
410 | unsigned int hctx_idx) | |
b60503ba | 411 | { |
a4aea562 | 412 | struct nvme_dev *dev = data; |
147b27e4 | 413 | struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; |
a4aea562 | 414 | |
42483228 KB |
415 | if (!nvmeq->tags) |
416 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 417 | |
42483228 | 418 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
419 | hctx->driver_data = nvmeq; |
420 | return 0; | |
b60503ba MW |
421 | } |
422 | ||
d6296d39 CH |
423 | static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, |
424 | unsigned int hctx_idx, unsigned int numa_node) | |
b60503ba | 425 | { |
d6296d39 | 426 | struct nvme_dev *dev = set->driver_data; |
f4800d6d | 427 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
0350815a | 428 | int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; |
147b27e4 | 429 | struct nvme_queue *nvmeq = &dev->queues[queue_idx]; |
a4aea562 MB |
430 | |
431 | BUG_ON(!nvmeq); | |
f4800d6d | 432 | iod->nvmeq = nvmeq; |
59e29ce6 SG |
433 | |
434 | nvme_req(req)->ctrl = &dev->ctrl; | |
a4aea562 MB |
435 | return 0; |
436 | } | |
437 | ||
3b6592f7 JA |
438 | static int queue_irq_offset(struct nvme_dev *dev) |
439 | { | |
440 | /* if we have more than 1 vec, admin queue offsets us by 1 */ | |
441 | if (dev->num_vecs > 1) | |
442 | return 1; | |
443 | ||
444 | return 0; | |
445 | } | |
446 | ||
dca51e78 CH |
447 | static int nvme_pci_map_queues(struct blk_mq_tag_set *set) |
448 | { | |
449 | struct nvme_dev *dev = set->driver_data; | |
3b6592f7 JA |
450 | int i, qoff, offset; |
451 | ||
452 | offset = queue_irq_offset(dev); | |
453 | for (i = 0, qoff = 0; i < set->nr_maps; i++) { | |
454 | struct blk_mq_queue_map *map = &set->map[i]; | |
455 | ||
456 | map->nr_queues = dev->io_queues[i]; | |
457 | if (!map->nr_queues) { | |
e20ba6e1 | 458 | BUG_ON(i == HCTX_TYPE_DEFAULT); |
7e849dd9 | 459 | continue; |
3b6592f7 JA |
460 | } |
461 | ||
4b04cc6a JA |
462 | /* |
463 | * The poll queue(s) doesn't have an IRQ (and hence IRQ | |
464 | * affinity), so use the regular blk-mq cpu mapping | |
465 | */ | |
3b6592f7 | 466 | map->queue_offset = qoff; |
cb9e0e50 | 467 | if (i != HCTX_TYPE_POLL && offset) |
4b04cc6a JA |
468 | blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); |
469 | else | |
470 | blk_mq_map_queues(map); | |
3b6592f7 JA |
471 | qoff += map->nr_queues; |
472 | offset += map->nr_queues; | |
473 | } | |
474 | ||
475 | return 0; | |
dca51e78 CH |
476 | } |
477 | ||
04f3eafd JA |
478 | /* |
479 | * Write sq tail if we are asked to, or if the next command would wrap. | |
480 | */ | |
481 | static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) | |
482 | { | |
483 | if (!write_sq) { | |
484 | u16 next_tail = nvmeq->sq_tail + 1; | |
485 | ||
486 | if (next_tail == nvmeq->q_depth) | |
487 | next_tail = 0; | |
488 | if (next_tail != nvmeq->last_sq_tail) | |
489 | return; | |
490 | } | |
491 | ||
492 | if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, | |
493 | nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) | |
494 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
495 | nvmeq->last_sq_tail = nvmeq->sq_tail; | |
496 | } | |
497 | ||
b60503ba | 498 | /** |
90ea5ca4 | 499 | * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
500 | * @nvmeq: The queue to use |
501 | * @cmd: The command to send | |
04f3eafd | 502 | * @write_sq: whether to write to the SQ doorbell |
b60503ba | 503 | */ |
04f3eafd JA |
504 | static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, |
505 | bool write_sq) | |
b60503ba | 506 | { |
90ea5ca4 | 507 | spin_lock(&nvmeq->sq_lock); |
0f238ff5 | 508 | memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); |
90ea5ca4 CH |
509 | if (++nvmeq->sq_tail == nvmeq->q_depth) |
510 | nvmeq->sq_tail = 0; | |
04f3eafd JA |
511 | nvme_write_sq_db(nvmeq, write_sq); |
512 | spin_unlock(&nvmeq->sq_lock); | |
513 | } | |
514 | ||
515 | static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) | |
516 | { | |
517 | struct nvme_queue *nvmeq = hctx->driver_data; | |
518 | ||
519 | spin_lock(&nvmeq->sq_lock); | |
520 | if (nvmeq->sq_tail != nvmeq->last_sq_tail) | |
521 | nvme_write_sq_db(nvmeq, true); | |
90ea5ca4 | 522 | spin_unlock(&nvmeq->sq_lock); |
b60503ba MW |
523 | } |
524 | ||
a7a7cbe3 | 525 | static void **nvme_pci_iod_list(struct request *req) |
b60503ba | 526 | { |
f4800d6d | 527 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a7a7cbe3 | 528 | return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); |
b60503ba MW |
529 | } |
530 | ||
955b1b5a MI |
531 | static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) |
532 | { | |
533 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
20469a37 | 534 | int nseg = blk_rq_nr_phys_segments(req); |
955b1b5a MI |
535 | unsigned int avg_seg_size; |
536 | ||
20469a37 KB |
537 | if (nseg == 0) |
538 | return false; | |
539 | ||
540 | avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); | |
955b1b5a MI |
541 | |
542 | if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) | |
543 | return false; | |
544 | if (!iod->nvmeq->qid) | |
545 | return false; | |
546 | if (!sgl_threshold || avg_seg_size < sgl_threshold) | |
547 | return false; | |
548 | return true; | |
549 | } | |
550 | ||
7fe07d14 | 551 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
b60503ba | 552 | { |
f4800d6d | 553 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
7fe07d14 CH |
554 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
555 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
a7a7cbe3 CK |
556 | const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; |
557 | dma_addr_t dma_addr = iod->first_dma, next_dma_addr; | |
eca18b23 | 558 | int i; |
eca18b23 | 559 | |
dff824b2 CH |
560 | if (iod->dma_len) { |
561 | dma_unmap_page(dev->dev, dma_addr, iod->dma_len, dma_dir); | |
562 | return; | |
7fe07d14 CH |
563 | } |
564 | ||
dff824b2 CH |
565 | WARN_ON_ONCE(!iod->nents); |
566 | ||
567 | /* P2PDMA requests do not need to be unmapped */ | |
568 | if (!is_pci_p2pdma_page(sg_page(iod->sg))) | |
569 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); | |
570 | ||
571 | ||
eca18b23 | 572 | if (iod->npages == 0) |
a7a7cbe3 CK |
573 | dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], |
574 | dma_addr); | |
575 | ||
eca18b23 | 576 | for (i = 0; i < iod->npages; i++) { |
a7a7cbe3 CK |
577 | void *addr = nvme_pci_iod_list(req)[i]; |
578 | ||
579 | if (iod->use_sgl) { | |
580 | struct nvme_sgl_desc *sg_list = addr; | |
581 | ||
582 | next_dma_addr = | |
583 | le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); | |
584 | } else { | |
585 | __le64 *prp_list = addr; | |
586 | ||
587 | next_dma_addr = le64_to_cpu(prp_list[last_prp]); | |
588 | } | |
589 | ||
590 | dma_pool_free(dev->prp_page_pool, addr, dma_addr); | |
591 | dma_addr = next_dma_addr; | |
eca18b23 | 592 | } |
ac3dd5bd | 593 | |
d43f1ccf | 594 | mempool_free(iod->sg, dev->iod_mempool); |
b4ff9c8d KB |
595 | } |
596 | ||
d0877473 KB |
597 | static void nvme_print_sgl(struct scatterlist *sgl, int nents) |
598 | { | |
599 | int i; | |
600 | struct scatterlist *sg; | |
601 | ||
602 | for_each_sg(sgl, sg, nents, i) { | |
603 | dma_addr_t phys = sg_phys(sg); | |
604 | pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " | |
605 | "dma_address:%pad dma_length:%d\n", | |
606 | i, &phys, sg->offset, sg->length, &sg_dma_address(sg), | |
607 | sg_dma_len(sg)); | |
608 | } | |
609 | } | |
610 | ||
a7a7cbe3 CK |
611 | static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, |
612 | struct request *req, struct nvme_rw_command *cmnd) | |
ff22b54f | 613 | { |
f4800d6d | 614 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 615 | struct dma_pool *pool; |
b131c61d | 616 | int length = blk_rq_payload_bytes(req); |
eca18b23 | 617 | struct scatterlist *sg = iod->sg; |
ff22b54f MW |
618 | int dma_len = sg_dma_len(sg); |
619 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 620 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 621 | int offset = dma_addr & (page_size - 1); |
e025344c | 622 | __le64 *prp_list; |
a7a7cbe3 | 623 | void **list = nvme_pci_iod_list(req); |
e025344c | 624 | dma_addr_t prp_dma; |
eca18b23 | 625 | int nprps, i; |
ff22b54f | 626 | |
1d090624 | 627 | length -= (page_size - offset); |
5228b328 JS |
628 | if (length <= 0) { |
629 | iod->first_dma = 0; | |
a7a7cbe3 | 630 | goto done; |
5228b328 | 631 | } |
ff22b54f | 632 | |
1d090624 | 633 | dma_len -= (page_size - offset); |
ff22b54f | 634 | if (dma_len) { |
1d090624 | 635 | dma_addr += (page_size - offset); |
ff22b54f MW |
636 | } else { |
637 | sg = sg_next(sg); | |
638 | dma_addr = sg_dma_address(sg); | |
639 | dma_len = sg_dma_len(sg); | |
640 | } | |
641 | ||
1d090624 | 642 | if (length <= page_size) { |
edd10d33 | 643 | iod->first_dma = dma_addr; |
a7a7cbe3 | 644 | goto done; |
e025344c SMM |
645 | } |
646 | ||
1d090624 | 647 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
648 | if (nprps <= (256 / 8)) { |
649 | pool = dev->prp_small_pool; | |
eca18b23 | 650 | iod->npages = 0; |
99802a7a MW |
651 | } else { |
652 | pool = dev->prp_page_pool; | |
eca18b23 | 653 | iod->npages = 1; |
99802a7a MW |
654 | } |
655 | ||
69d2b571 | 656 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 657 | if (!prp_list) { |
edd10d33 | 658 | iod->first_dma = dma_addr; |
eca18b23 | 659 | iod->npages = -1; |
86eea289 | 660 | return BLK_STS_RESOURCE; |
b77954cb | 661 | } |
eca18b23 MW |
662 | list[0] = prp_list; |
663 | iod->first_dma = prp_dma; | |
e025344c SMM |
664 | i = 0; |
665 | for (;;) { | |
1d090624 | 666 | if (i == page_size >> 3) { |
e025344c | 667 | __le64 *old_prp_list = prp_list; |
69d2b571 | 668 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 669 | if (!prp_list) |
86eea289 | 670 | return BLK_STS_RESOURCE; |
eca18b23 | 671 | list[iod->npages++] = prp_list; |
7523d834 MW |
672 | prp_list[0] = old_prp_list[i - 1]; |
673 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
674 | i = 1; | |
e025344c SMM |
675 | } |
676 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
677 | dma_len -= page_size; |
678 | dma_addr += page_size; | |
679 | length -= page_size; | |
e025344c SMM |
680 | if (length <= 0) |
681 | break; | |
682 | if (dma_len > 0) | |
683 | continue; | |
86eea289 KB |
684 | if (unlikely(dma_len < 0)) |
685 | goto bad_sgl; | |
e025344c SMM |
686 | sg = sg_next(sg); |
687 | dma_addr = sg_dma_address(sg); | |
688 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
689 | } |
690 | ||
a7a7cbe3 CK |
691 | done: |
692 | cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); | |
693 | cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); | |
694 | ||
86eea289 KB |
695 | return BLK_STS_OK; |
696 | ||
697 | bad_sgl: | |
d0877473 KB |
698 | WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), |
699 | "Invalid SGL for payload:%d nents:%d\n", | |
700 | blk_rq_payload_bytes(req), iod->nents); | |
86eea289 | 701 | return BLK_STS_IOERR; |
ff22b54f MW |
702 | } |
703 | ||
a7a7cbe3 CK |
704 | static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, |
705 | struct scatterlist *sg) | |
706 | { | |
707 | sge->addr = cpu_to_le64(sg_dma_address(sg)); | |
708 | sge->length = cpu_to_le32(sg_dma_len(sg)); | |
709 | sge->type = NVME_SGL_FMT_DATA_DESC << 4; | |
710 | } | |
711 | ||
712 | static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, | |
713 | dma_addr_t dma_addr, int entries) | |
714 | { | |
715 | sge->addr = cpu_to_le64(dma_addr); | |
716 | if (entries < SGES_PER_PAGE) { | |
717 | sge->length = cpu_to_le32(entries * sizeof(*sge)); | |
718 | sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; | |
719 | } else { | |
720 | sge->length = cpu_to_le32(PAGE_SIZE); | |
721 | sge->type = NVME_SGL_FMT_SEG_DESC << 4; | |
722 | } | |
723 | } | |
724 | ||
725 | static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, | |
b0f2853b | 726 | struct request *req, struct nvme_rw_command *cmd, int entries) |
a7a7cbe3 CK |
727 | { |
728 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
a7a7cbe3 CK |
729 | struct dma_pool *pool; |
730 | struct nvme_sgl_desc *sg_list; | |
731 | struct scatterlist *sg = iod->sg; | |
a7a7cbe3 | 732 | dma_addr_t sgl_dma; |
b0f2853b | 733 | int i = 0; |
a7a7cbe3 | 734 | |
a7a7cbe3 CK |
735 | /* setting the transfer type as SGL */ |
736 | cmd->flags = NVME_CMD_SGL_METABUF; | |
737 | ||
b0f2853b | 738 | if (entries == 1) { |
a7a7cbe3 CK |
739 | nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); |
740 | return BLK_STS_OK; | |
741 | } | |
742 | ||
743 | if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { | |
744 | pool = dev->prp_small_pool; | |
745 | iod->npages = 0; | |
746 | } else { | |
747 | pool = dev->prp_page_pool; | |
748 | iod->npages = 1; | |
749 | } | |
750 | ||
751 | sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); | |
752 | if (!sg_list) { | |
753 | iod->npages = -1; | |
754 | return BLK_STS_RESOURCE; | |
755 | } | |
756 | ||
757 | nvme_pci_iod_list(req)[0] = sg_list; | |
758 | iod->first_dma = sgl_dma; | |
759 | ||
760 | nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); | |
761 | ||
762 | do { | |
763 | if (i == SGES_PER_PAGE) { | |
764 | struct nvme_sgl_desc *old_sg_desc = sg_list; | |
765 | struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; | |
766 | ||
767 | sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); | |
768 | if (!sg_list) | |
769 | return BLK_STS_RESOURCE; | |
770 | ||
771 | i = 0; | |
772 | nvme_pci_iod_list(req)[iod->npages++] = sg_list; | |
773 | sg_list[i++] = *link; | |
774 | nvme_pci_sgl_set_seg(link, sgl_dma, entries); | |
775 | } | |
776 | ||
777 | nvme_pci_sgl_set_data(&sg_list[i++], sg); | |
a7a7cbe3 | 778 | sg = sg_next(sg); |
b0f2853b | 779 | } while (--entries > 0); |
a7a7cbe3 | 780 | |
a7a7cbe3 CK |
781 | return BLK_STS_OK; |
782 | } | |
783 | ||
dff824b2 CH |
784 | static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, |
785 | struct request *req, struct nvme_rw_command *cmnd, | |
786 | struct bio_vec *bv) | |
787 | { | |
788 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
789 | unsigned int first_prp_len = dev->ctrl.page_size - bv->bv_offset; | |
790 | ||
791 | iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); | |
792 | if (dma_mapping_error(dev->dev, iod->first_dma)) | |
793 | return BLK_STS_RESOURCE; | |
794 | iod->dma_len = bv->bv_len; | |
795 | ||
796 | cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); | |
797 | if (bv->bv_len > first_prp_len) | |
798 | cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); | |
799 | return 0; | |
800 | } | |
801 | ||
29791057 CH |
802 | static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, |
803 | struct request *req, struct nvme_rw_command *cmnd, | |
804 | struct bio_vec *bv) | |
805 | { | |
806 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
807 | ||
808 | iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); | |
809 | if (dma_mapping_error(dev->dev, iod->first_dma)) | |
810 | return BLK_STS_RESOURCE; | |
811 | iod->dma_len = bv->bv_len; | |
812 | ||
049bf372 | 813 | cmnd->flags = NVME_CMD_SGL_METABUF; |
29791057 CH |
814 | cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); |
815 | cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); | |
816 | cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; | |
817 | return 0; | |
818 | } | |
819 | ||
fc17b653 | 820 | static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, |
b131c61d | 821 | struct nvme_command *cmnd) |
d29ec824 | 822 | { |
f4800d6d | 823 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
70479b71 | 824 | blk_status_t ret = BLK_STS_RESOURCE; |
b0f2853b | 825 | int nr_mapped; |
d29ec824 | 826 | |
dff824b2 CH |
827 | if (blk_rq_nr_phys_segments(req) == 1) { |
828 | struct bio_vec bv = req_bvec(req); | |
829 | ||
830 | if (!is_pci_p2pdma_page(bv.bv_page)) { | |
831 | if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2) | |
832 | return nvme_setup_prp_simple(dev, req, | |
833 | &cmnd->rw, &bv); | |
29791057 CH |
834 | |
835 | if (iod->nvmeq->qid && | |
836 | dev->ctrl.sgls & ((1 << 0) | (1 << 1))) | |
837 | return nvme_setup_sgl_simple(dev, req, | |
838 | &cmnd->rw, &bv); | |
dff824b2 CH |
839 | } |
840 | } | |
841 | ||
842 | iod->dma_len = 0; | |
d43f1ccf CH |
843 | iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); |
844 | if (!iod->sg) | |
845 | return BLK_STS_RESOURCE; | |
f9d03f96 | 846 | sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); |
70479b71 | 847 | iod->nents = blk_rq_map_sg(req->q, req, iod->sg); |
ba1ca37e CH |
848 | if (!iod->nents) |
849 | goto out; | |
d29ec824 | 850 | |
e0596ab2 LG |
851 | if (is_pci_p2pdma_page(sg_page(iod->sg))) |
852 | nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents, | |
70479b71 | 853 | rq_dma_dir(req)); |
e0596ab2 LG |
854 | else |
855 | nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, | |
70479b71 | 856 | rq_dma_dir(req), DMA_ATTR_NO_WARN); |
b0f2853b | 857 | if (!nr_mapped) |
ba1ca37e | 858 | goto out; |
d29ec824 | 859 | |
70479b71 | 860 | iod->use_sgl = nvme_pci_use_sgls(dev, req); |
955b1b5a | 861 | if (iod->use_sgl) |
b0f2853b | 862 | ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); |
a7a7cbe3 CK |
863 | else |
864 | ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); | |
4aedb705 | 865 | out: |
86eea289 | 866 | if (ret != BLK_STS_OK) |
4aedb705 CH |
867 | nvme_unmap_data(dev, req); |
868 | return ret; | |
869 | } | |
3045c0d0 | 870 | |
4aedb705 CH |
871 | static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, |
872 | struct nvme_command *cmnd) | |
873 | { | |
874 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
00df5cb4 | 875 | |
4aedb705 CH |
876 | iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), |
877 | rq_dma_dir(req), 0); | |
878 | if (dma_mapping_error(dev->dev, iod->meta_dma)) | |
879 | return BLK_STS_IOERR; | |
880 | cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); | |
881 | return 0; | |
00df5cb4 MW |
882 | } |
883 | ||
d29ec824 CH |
884 | /* |
885 | * NOTE: ns is NULL when called on the admin queue. | |
886 | */ | |
fc17b653 | 887 | static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
a4aea562 | 888 | const struct blk_mq_queue_data *bd) |
edd10d33 | 889 | { |
a4aea562 MB |
890 | struct nvme_ns *ns = hctx->queue->queuedata; |
891 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 892 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 893 | struct request *req = bd->rq; |
9b048119 | 894 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e | 895 | struct nvme_command cmnd; |
ebe6d874 | 896 | blk_status_t ret; |
e1e5e564 | 897 | |
9b048119 CH |
898 | iod->aborted = 0; |
899 | iod->npages = -1; | |
900 | iod->nents = 0; | |
901 | ||
d1f06f4a JA |
902 | /* |
903 | * We should not need to do this, but we're still using this to | |
904 | * ensure we can drain requests on a dying queue. | |
905 | */ | |
4e224106 | 906 | if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) |
d1f06f4a JA |
907 | return BLK_STS_IOERR; |
908 | ||
f9d03f96 | 909 | ret = nvme_setup_cmd(ns, req, &cmnd); |
fc17b653 | 910 | if (ret) |
f4800d6d | 911 | return ret; |
a4aea562 | 912 | |
fc17b653 | 913 | if (blk_rq_nr_phys_segments(req)) { |
b131c61d | 914 | ret = nvme_map_data(dev, req, &cmnd); |
fc17b653 | 915 | if (ret) |
9b048119 | 916 | goto out_free_cmd; |
fc17b653 | 917 | } |
a4aea562 | 918 | |
4aedb705 CH |
919 | if (blk_integrity_rq(req)) { |
920 | ret = nvme_map_metadata(dev, req, &cmnd); | |
921 | if (ret) | |
922 | goto out_unmap_data; | |
923 | } | |
924 | ||
aae239e1 | 925 | blk_mq_start_request(req); |
04f3eafd | 926 | nvme_submit_cmd(nvmeq, &cmnd, bd->last); |
fc17b653 | 927 | return BLK_STS_OK; |
4aedb705 CH |
928 | out_unmap_data: |
929 | nvme_unmap_data(dev, req); | |
f9d03f96 CH |
930 | out_free_cmd: |
931 | nvme_cleanup_cmd(req); | |
ba1ca37e | 932 | return ret; |
b60503ba | 933 | } |
e1e5e564 | 934 | |
77f02a7a | 935 | static void nvme_pci_complete_rq(struct request *req) |
eee417b0 | 936 | { |
f4800d6d | 937 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
4aedb705 | 938 | struct nvme_dev *dev = iod->nvmeq->dev; |
a4aea562 | 939 | |
915f04c9 | 940 | nvme_cleanup_cmd(req); |
4aedb705 CH |
941 | if (blk_integrity_rq(req)) |
942 | dma_unmap_page(dev->dev, iod->meta_dma, | |
943 | rq_integrity_vec(req)->bv_len, rq_data_dir(req)); | |
b15c592d | 944 | if (blk_rq_nr_phys_segments(req)) |
4aedb705 | 945 | nvme_unmap_data(dev, req); |
77f02a7a | 946 | nvme_complete_rq(req); |
b60503ba MW |
947 | } |
948 | ||
d783e0bd | 949 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
750dde44 | 950 | static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) |
d783e0bd | 951 | { |
750dde44 CH |
952 | return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == |
953 | nvmeq->cq_phase; | |
d783e0bd MR |
954 | } |
955 | ||
eb281c82 | 956 | static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) |
b60503ba | 957 | { |
eb281c82 | 958 | u16 head = nvmeq->cq_head; |
adf68f21 | 959 | |
397c699f KB |
960 | if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, |
961 | nvmeq->dbbuf_cq_ei)) | |
962 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
eb281c82 | 963 | } |
aae239e1 | 964 | |
5cb525c8 | 965 | static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) |
83a12fb7 | 966 | { |
5cb525c8 | 967 | volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; |
83a12fb7 | 968 | struct request *req; |
adf68f21 | 969 | |
83a12fb7 SG |
970 | if (unlikely(cqe->command_id >= nvmeq->q_depth)) { |
971 | dev_warn(nvmeq->dev->ctrl.device, | |
972 | "invalid id %d completed on queue %d\n", | |
973 | cqe->command_id, le16_to_cpu(cqe->sq_id)); | |
974 | return; | |
b60503ba MW |
975 | } |
976 | ||
83a12fb7 SG |
977 | /* |
978 | * AEN requests are special as they don't time out and can | |
979 | * survive any kind of queue freeze and often don't respond to | |
980 | * aborts. We don't even bother to allocate a struct request | |
981 | * for them but rather special case them here. | |
982 | */ | |
983 | if (unlikely(nvmeq->qid == 0 && | |
38dabe21 | 984 | cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { |
83a12fb7 SG |
985 | nvme_complete_async_event(&nvmeq->dev->ctrl, |
986 | cqe->status, &cqe->result); | |
a0fa9647 | 987 | return; |
83a12fb7 | 988 | } |
b60503ba | 989 | |
83a12fb7 | 990 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); |
604c01d5 | 991 | trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); |
83a12fb7 SG |
992 | nvme_end_request(req, cqe->status, cqe->result); |
993 | } | |
b60503ba | 994 | |
5cb525c8 | 995 | static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) |
b60503ba | 996 | { |
5cb525c8 JA |
997 | while (start != end) { |
998 | nvme_handle_cqe(nvmeq, start); | |
999 | if (++start == nvmeq->q_depth) | |
1000 | start = 0; | |
1001 | } | |
1002 | } | |
adf68f21 | 1003 | |
5cb525c8 JA |
1004 | static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) |
1005 | { | |
dcca1662 | 1006 | if (nvmeq->cq_head == nvmeq->q_depth - 1) { |
5cb525c8 JA |
1007 | nvmeq->cq_head = 0; |
1008 | nvmeq->cq_phase = !nvmeq->cq_phase; | |
dcca1662 HY |
1009 | } else { |
1010 | nvmeq->cq_head++; | |
b60503ba | 1011 | } |
a0fa9647 JA |
1012 | } |
1013 | ||
1052b8ac JA |
1014 | static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, |
1015 | u16 *end, unsigned int tag) | |
a0fa9647 | 1016 | { |
1052b8ac | 1017 | int found = 0; |
b60503ba | 1018 | |
5cb525c8 | 1019 | *start = nvmeq->cq_head; |
1052b8ac JA |
1020 | while (nvme_cqe_pending(nvmeq)) { |
1021 | if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) | |
1022 | found++; | |
5cb525c8 | 1023 | nvme_update_cq_head(nvmeq); |
920d13a8 | 1024 | } |
5cb525c8 | 1025 | *end = nvmeq->cq_head; |
eb281c82 | 1026 | |
5cb525c8 | 1027 | if (*start != *end) |
920d13a8 | 1028 | nvme_ring_cq_doorbell(nvmeq); |
5cb525c8 | 1029 | return found; |
b60503ba MW |
1030 | } |
1031 | ||
1032 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 | 1033 | { |
58ffacb5 | 1034 | struct nvme_queue *nvmeq = data; |
68fa9dbe | 1035 | irqreturn_t ret = IRQ_NONE; |
5cb525c8 JA |
1036 | u16 start, end; |
1037 | ||
3a7afd8e CH |
1038 | /* |
1039 | * The rmb/wmb pair ensures we see all updates from a previous run of | |
1040 | * the irq handler, even if that was on another CPU. | |
1041 | */ | |
1042 | rmb(); | |
68fa9dbe JA |
1043 | if (nvmeq->cq_head != nvmeq->last_cq_head) |
1044 | ret = IRQ_HANDLED; | |
5cb525c8 | 1045 | nvme_process_cq(nvmeq, &start, &end, -1); |
68fa9dbe | 1046 | nvmeq->last_cq_head = nvmeq->cq_head; |
3a7afd8e | 1047 | wmb(); |
5cb525c8 | 1048 | |
68fa9dbe JA |
1049 | if (start != end) { |
1050 | nvme_complete_cqes(nvmeq, start, end); | |
1051 | return IRQ_HANDLED; | |
1052 | } | |
1053 | ||
1054 | return ret; | |
58ffacb5 MW |
1055 | } |
1056 | ||
1057 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
1058 | { | |
1059 | struct nvme_queue *nvmeq = data; | |
750dde44 | 1060 | if (nvme_cqe_pending(nvmeq)) |
d783e0bd MR |
1061 | return IRQ_WAKE_THREAD; |
1062 | return IRQ_NONE; | |
58ffacb5 MW |
1063 | } |
1064 | ||
0b2a8a9f CH |
1065 | /* |
1066 | * Poll for completions any queue, including those not dedicated to polling. | |
1067 | * Can be called from any context. | |
1068 | */ | |
1069 | static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag) | |
a0fa9647 | 1070 | { |
3a7afd8e | 1071 | struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); |
5cb525c8 | 1072 | u16 start, end; |
1052b8ac | 1073 | int found; |
a0fa9647 | 1074 | |
3a7afd8e CH |
1075 | /* |
1076 | * For a poll queue we need to protect against the polling thread | |
1077 | * using the CQ lock. For normal interrupt driven threads we have | |
1078 | * to disable the interrupt to avoid racing with it. | |
1079 | */ | |
7c349dde | 1080 | if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) { |
3a7afd8e | 1081 | spin_lock(&nvmeq->cq_poll_lock); |
91a509f8 | 1082 | found = nvme_process_cq(nvmeq, &start, &end, tag); |
3a7afd8e | 1083 | spin_unlock(&nvmeq->cq_poll_lock); |
91a509f8 CH |
1084 | } else { |
1085 | disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); | |
1086 | found = nvme_process_cq(nvmeq, &start, &end, tag); | |
3a7afd8e | 1087 | enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); |
91a509f8 | 1088 | } |
442e19b7 | 1089 | |
5cb525c8 | 1090 | nvme_complete_cqes(nvmeq, start, end); |
442e19b7 | 1091 | return found; |
a0fa9647 JA |
1092 | } |
1093 | ||
9743139c | 1094 | static int nvme_poll(struct blk_mq_hw_ctx *hctx) |
dabcefab JA |
1095 | { |
1096 | struct nvme_queue *nvmeq = hctx->driver_data; | |
1097 | u16 start, end; | |
1098 | bool found; | |
1099 | ||
1100 | if (!nvme_cqe_pending(nvmeq)) | |
1101 | return 0; | |
1102 | ||
3a7afd8e | 1103 | spin_lock(&nvmeq->cq_poll_lock); |
9743139c | 1104 | found = nvme_process_cq(nvmeq, &start, &end, -1); |
3a7afd8e | 1105 | spin_unlock(&nvmeq->cq_poll_lock); |
dabcefab JA |
1106 | |
1107 | nvme_complete_cqes(nvmeq, start, end); | |
1108 | return found; | |
1109 | } | |
1110 | ||
ad22c355 | 1111 | static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) |
b60503ba | 1112 | { |
f866fc42 | 1113 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
147b27e4 | 1114 | struct nvme_queue *nvmeq = &dev->queues[0]; |
a4aea562 | 1115 | struct nvme_command c; |
b60503ba | 1116 | |
a4aea562 MB |
1117 | memset(&c, 0, sizeof(c)); |
1118 | c.common.opcode = nvme_admin_async_event; | |
ad22c355 | 1119 | c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; |
04f3eafd | 1120 | nvme_submit_cmd(nvmeq, &c, true); |
f705f837 CH |
1121 | } |
1122 | ||
b60503ba | 1123 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 1124 | { |
b60503ba MW |
1125 | struct nvme_command c; |
1126 | ||
1127 | memset(&c, 0, sizeof(c)); | |
1128 | c.delete_queue.opcode = opcode; | |
1129 | c.delete_queue.qid = cpu_to_le16(id); | |
1130 | ||
1c63dc66 | 1131 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1132 | } |
1133 | ||
b60503ba | 1134 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
a8e3e0bb | 1135 | struct nvme_queue *nvmeq, s16 vector) |
b60503ba | 1136 | { |
b60503ba | 1137 | struct nvme_command c; |
4b04cc6a JA |
1138 | int flags = NVME_QUEUE_PHYS_CONTIG; |
1139 | ||
7c349dde | 1140 | if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) |
4b04cc6a | 1141 | flags |= NVME_CQ_IRQ_ENABLED; |
b60503ba | 1142 | |
d29ec824 | 1143 | /* |
16772ae6 | 1144 | * Note: we (ab)use the fact that the prp fields survive if no data |
d29ec824 CH |
1145 | * is attached to the request. |
1146 | */ | |
b60503ba MW |
1147 | memset(&c, 0, sizeof(c)); |
1148 | c.create_cq.opcode = nvme_admin_create_cq; | |
1149 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
1150 | c.create_cq.cqid = cpu_to_le16(qid); | |
1151 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1152 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
7c349dde | 1153 | c.create_cq.irq_vector = cpu_to_le16(vector); |
b60503ba | 1154 | |
1c63dc66 | 1155 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1156 | } |
1157 | ||
1158 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
1159 | struct nvme_queue *nvmeq) | |
1160 | { | |
9abd68ef | 1161 | struct nvme_ctrl *ctrl = &dev->ctrl; |
b60503ba | 1162 | struct nvme_command c; |
81c1cd98 | 1163 | int flags = NVME_QUEUE_PHYS_CONTIG; |
b60503ba | 1164 | |
9abd68ef JA |
1165 | /* |
1166 | * Some drives have a bug that auto-enables WRRU if MEDIUM isn't | |
1167 | * set. Since URGENT priority is zeroes, it makes all queues | |
1168 | * URGENT. | |
1169 | */ | |
1170 | if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) | |
1171 | flags |= NVME_SQ_PRIO_MEDIUM; | |
1172 | ||
d29ec824 | 1173 | /* |
16772ae6 | 1174 | * Note: we (ab)use the fact that the prp fields survive if no data |
d29ec824 CH |
1175 | * is attached to the request. |
1176 | */ | |
b60503ba MW |
1177 | memset(&c, 0, sizeof(c)); |
1178 | c.create_sq.opcode = nvme_admin_create_sq; | |
1179 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
1180 | c.create_sq.sqid = cpu_to_le16(qid); | |
1181 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1182 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
1183 | c.create_sq.cqid = cpu_to_le16(qid); | |
1184 | ||
1c63dc66 | 1185 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1186 | } |
1187 | ||
1188 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
1189 | { | |
1190 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
1191 | } | |
1192 | ||
1193 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
1194 | { | |
1195 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
1196 | } | |
1197 | ||
2a842aca | 1198 | static void abort_endio(struct request *req, blk_status_t error) |
bc5fc7e4 | 1199 | { |
f4800d6d CH |
1200 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
1201 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e44ac588 | 1202 | |
27fa9bc5 CH |
1203 | dev_warn(nvmeq->dev->ctrl.device, |
1204 | "Abort status: 0x%x", nvme_req(req)->status); | |
e7a2a87d | 1205 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
e7a2a87d | 1206 | blk_mq_free_request(req); |
bc5fc7e4 MW |
1207 | } |
1208 | ||
b2a0eb1a KB |
1209 | static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) |
1210 | { | |
1211 | ||
1212 | /* If true, indicates loss of adapter communication, possibly by a | |
1213 | * NVMe Subsystem reset. | |
1214 | */ | |
1215 | bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); | |
1216 | ||
ad70062c JW |
1217 | /* If there is a reset/reinit ongoing, we shouldn't reset again. */ |
1218 | switch (dev->ctrl.state) { | |
1219 | case NVME_CTRL_RESETTING: | |
ad6a0a52 | 1220 | case NVME_CTRL_CONNECTING: |
b2a0eb1a | 1221 | return false; |
ad70062c JW |
1222 | default: |
1223 | break; | |
1224 | } | |
b2a0eb1a KB |
1225 | |
1226 | /* We shouldn't reset unless the controller is on fatal error state | |
1227 | * _or_ if we lost the communication with it. | |
1228 | */ | |
1229 | if (!(csts & NVME_CSTS_CFS) && !nssro) | |
1230 | return false; | |
1231 | ||
b2a0eb1a KB |
1232 | return true; |
1233 | } | |
1234 | ||
1235 | static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) | |
1236 | { | |
1237 | /* Read a config register to help see what died. */ | |
1238 | u16 pci_status; | |
1239 | int result; | |
1240 | ||
1241 | result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, | |
1242 | &pci_status); | |
1243 | if (result == PCIBIOS_SUCCESSFUL) | |
1244 | dev_warn(dev->ctrl.device, | |
1245 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", | |
1246 | csts, pci_status); | |
1247 | else | |
1248 | dev_warn(dev->ctrl.device, | |
1249 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", | |
1250 | csts, result); | |
1251 | } | |
1252 | ||
31c7c7d2 | 1253 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 1254 | { |
f4800d6d CH |
1255 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
1256 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 1257 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 1258 | struct request *abort_req; |
a4aea562 | 1259 | struct nvme_command cmd; |
b2a0eb1a KB |
1260 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
1261 | ||
651438bb WX |
1262 | /* If PCI error recovery process is happening, we cannot reset or |
1263 | * the recovery mechanism will surely fail. | |
1264 | */ | |
1265 | mb(); | |
1266 | if (pci_channel_offline(to_pci_dev(dev->dev))) | |
1267 | return BLK_EH_RESET_TIMER; | |
1268 | ||
b2a0eb1a KB |
1269 | /* |
1270 | * Reset immediately if the controller is failed | |
1271 | */ | |
1272 | if (nvme_should_reset(dev, csts)) { | |
1273 | nvme_warn_reset(dev, csts); | |
1274 | nvme_dev_disable(dev, false); | |
d86c4d8e | 1275 | nvme_reset_ctrl(&dev->ctrl); |
db8c48e4 | 1276 | return BLK_EH_DONE; |
b2a0eb1a | 1277 | } |
c30341dc | 1278 | |
7776db1c KB |
1279 | /* |
1280 | * Did we miss an interrupt? | |
1281 | */ | |
0b2a8a9f | 1282 | if (nvme_poll_irqdisable(nvmeq, req->tag)) { |
7776db1c KB |
1283 | dev_warn(dev->ctrl.device, |
1284 | "I/O %d QID %d timeout, completion polled\n", | |
1285 | req->tag, nvmeq->qid); | |
db8c48e4 | 1286 | return BLK_EH_DONE; |
7776db1c KB |
1287 | } |
1288 | ||
31c7c7d2 | 1289 | /* |
fd634f41 CH |
1290 | * Shutdown immediately if controller times out while starting. The |
1291 | * reset work will see the pci device disabled when it gets the forced | |
1292 | * cancellation error. All outstanding requests are completed on | |
db8c48e4 | 1293 | * shutdown, so we return BLK_EH_DONE. |
fd634f41 | 1294 | */ |
4244140d KB |
1295 | switch (dev->ctrl.state) { |
1296 | case NVME_CTRL_CONNECTING: | |
2036f726 KB |
1297 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
1298 | /* fall through */ | |
1299 | case NVME_CTRL_DELETING: | |
b9cac43c | 1300 | dev_warn_ratelimited(dev->ctrl.device, |
fd634f41 CH |
1301 | "I/O %d QID %d timeout, disable controller\n", |
1302 | req->tag, nvmeq->qid); | |
2036f726 | 1303 | nvme_dev_disable(dev, true); |
27fa9bc5 | 1304 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
db8c48e4 | 1305 | return BLK_EH_DONE; |
39a9dd81 KB |
1306 | case NVME_CTRL_RESETTING: |
1307 | return BLK_EH_RESET_TIMER; | |
4244140d KB |
1308 | default: |
1309 | break; | |
c30341dc KB |
1310 | } |
1311 | ||
fd634f41 CH |
1312 | /* |
1313 | * Shutdown the controller immediately and schedule a reset if the | |
1314 | * command was already aborted once before and still hasn't been | |
1315 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 1316 | */ |
f4800d6d | 1317 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 1318 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
1319 | "I/O %d QID %d timeout, reset controller\n", |
1320 | req->tag, nvmeq->qid); | |
a5cdb68c | 1321 | nvme_dev_disable(dev, false); |
d86c4d8e | 1322 | nvme_reset_ctrl(&dev->ctrl); |
c30341dc | 1323 | |
27fa9bc5 | 1324 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
db8c48e4 | 1325 | return BLK_EH_DONE; |
c30341dc | 1326 | } |
c30341dc | 1327 | |
e7a2a87d | 1328 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 1329 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 1330 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 1331 | } |
7bf7d778 | 1332 | iod->aborted = 1; |
a4aea562 | 1333 | |
c30341dc KB |
1334 | memset(&cmd, 0, sizeof(cmd)); |
1335 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 1336 | cmd.abort.cid = req->tag; |
c30341dc | 1337 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 1338 | |
1b3c47c1 SG |
1339 | dev_warn(nvmeq->dev->ctrl.device, |
1340 | "I/O %d QID %d timeout, aborting\n", | |
1341 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
1342 | |
1343 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
eb71f435 | 1344 | BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
e7a2a87d CH |
1345 | if (IS_ERR(abort_req)) { |
1346 | atomic_inc(&dev->ctrl.abort_limit); | |
1347 | return BLK_EH_RESET_TIMER; | |
1348 | } | |
1349 | ||
1350 | abort_req->timeout = ADMIN_TIMEOUT; | |
1351 | abort_req->end_io_data = NULL; | |
1352 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
c30341dc | 1353 | |
31c7c7d2 CH |
1354 | /* |
1355 | * The aborted req will be completed on receiving the abort req. | |
1356 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1357 | * as the device then is in a faulty state. | |
1358 | */ | |
1359 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
1360 | } |
1361 | ||
a4aea562 MB |
1362 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1363 | { | |
88a041f4 | 1364 | dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq->q_depth), |
9e866774 | 1365 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); |
63223078 CH |
1366 | if (!nvmeq->sq_cmds) |
1367 | return; | |
0f238ff5 | 1368 | |
63223078 | 1369 | if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { |
88a041f4 | 1370 | pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), |
63223078 CH |
1371 | nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth)); |
1372 | } else { | |
88a041f4 | 1373 | dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq->q_depth), |
63223078 | 1374 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
0f238ff5 | 1375 | } |
9e866774 MW |
1376 | } |
1377 | ||
a1a5ef99 | 1378 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1379 | { |
1380 | int i; | |
1381 | ||
d858e5f0 | 1382 | for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { |
d858e5f0 | 1383 | dev->ctrl.queue_count--; |
147b27e4 | 1384 | nvme_free_queue(&dev->queues[i]); |
121c7ad4 | 1385 | } |
22404274 KB |
1386 | } |
1387 | ||
4d115420 KB |
1388 | /** |
1389 | * nvme_suspend_queue - put queue into suspended state | |
40581d1a | 1390 | * @nvmeq: queue to suspend |
4d115420 KB |
1391 | */ |
1392 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1393 | { |
4e224106 | 1394 | if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) |
2b25d981 | 1395 | return 1; |
a09115b2 | 1396 | |
4e224106 | 1397 | /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ |
d1f06f4a | 1398 | mb(); |
a09115b2 | 1399 | |
4e224106 | 1400 | nvmeq->dev->online_queues--; |
1c63dc66 | 1401 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
c81545f9 | 1402 | blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); |
7c349dde KB |
1403 | if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) |
1404 | pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); | |
4d115420 KB |
1405 | return 0; |
1406 | } | |
b60503ba | 1407 | |
8fae268b KB |
1408 | static void nvme_suspend_io_queues(struct nvme_dev *dev) |
1409 | { | |
1410 | int i; | |
1411 | ||
1412 | for (i = dev->ctrl.queue_count - 1; i > 0; i--) | |
1413 | nvme_suspend_queue(&dev->queues[i]); | |
1414 | } | |
1415 | ||
a5cdb68c | 1416 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 1417 | { |
147b27e4 | 1418 | struct nvme_queue *nvmeq = &dev->queues[0]; |
4d115420 | 1419 | |
a5cdb68c KB |
1420 | if (shutdown) |
1421 | nvme_shutdown_ctrl(&dev->ctrl); | |
1422 | else | |
20d0dfe6 | 1423 | nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); |
07836e65 | 1424 | |
0b2a8a9f | 1425 | nvme_poll_irqdisable(nvmeq, -1); |
b60503ba MW |
1426 | } |
1427 | ||
8ffaadf7 JD |
1428 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1429 | int entry_size) | |
1430 | { | |
1431 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1432 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1433 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1434 | |
1435 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1436 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1437 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1438 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1439 | |
1440 | /* | |
1441 | * Ensure the reduced q_depth is above some threshold where it | |
1442 | * would be better to map queues in system memory with the | |
1443 | * original depth | |
1444 | */ | |
1445 | if (q_depth < 64) | |
1446 | return -ENOMEM; | |
1447 | } | |
1448 | ||
1449 | return q_depth; | |
1450 | } | |
1451 | ||
1452 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1453 | int qid, int depth) | |
1454 | { | |
0f238ff5 LG |
1455 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1456 | ||
1457 | if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { | |
1458 | nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth)); | |
1459 | nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, | |
1460 | nvmeq->sq_cmds); | |
63223078 CH |
1461 | if (nvmeq->sq_dma_addr) { |
1462 | set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); | |
1463 | return 0; | |
1464 | } | |
0f238ff5 | 1465 | } |
8ffaadf7 | 1466 | |
63223078 CH |
1467 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), |
1468 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
815c6704 KB |
1469 | if (!nvmeq->sq_cmds) |
1470 | return -ENOMEM; | |
8ffaadf7 JD |
1471 | return 0; |
1472 | } | |
1473 | ||
a6ff7262 | 1474 | static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) |
b60503ba | 1475 | { |
147b27e4 | 1476 | struct nvme_queue *nvmeq = &dev->queues[qid]; |
b60503ba | 1477 | |
62314e40 KB |
1478 | if (dev->ctrl.queue_count > qid) |
1479 | return 0; | |
b60503ba | 1480 | |
750afb08 LC |
1481 | nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth), |
1482 | &nvmeq->cq_dma_addr, GFP_KERNEL); | |
b60503ba MW |
1483 | if (!nvmeq->cqes) |
1484 | goto free_nvmeq; | |
b60503ba | 1485 | |
8ffaadf7 | 1486 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1487 | goto free_cqdma; |
1488 | ||
091b6092 | 1489 | nvmeq->dev = dev; |
1ab0cd69 | 1490 | spin_lock_init(&nvmeq->sq_lock); |
3a7afd8e | 1491 | spin_lock_init(&nvmeq->cq_poll_lock); |
b60503ba | 1492 | nvmeq->cq_head = 0; |
82123460 | 1493 | nvmeq->cq_phase = 1; |
b80d5ccc | 1494 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1495 | nvmeq->q_depth = depth; |
c30341dc | 1496 | nvmeq->qid = qid; |
d858e5f0 | 1497 | dev->ctrl.queue_count++; |
36a7e993 | 1498 | |
147b27e4 | 1499 | return 0; |
b60503ba MW |
1500 | |
1501 | free_cqdma: | |
e75ec752 | 1502 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1503 | nvmeq->cq_dma_addr); |
1504 | free_nvmeq: | |
147b27e4 | 1505 | return -ENOMEM; |
b60503ba MW |
1506 | } |
1507 | ||
dca51e78 | 1508 | static int queue_request_irq(struct nvme_queue *nvmeq) |
3001082c | 1509 | { |
0ff199cb CH |
1510 | struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); |
1511 | int nr = nvmeq->dev->ctrl.instance; | |
1512 | ||
1513 | if (use_threaded_interrupts) { | |
1514 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, | |
1515 | nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1516 | } else { | |
1517 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, | |
1518 | NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1519 | } | |
3001082c MW |
1520 | } |
1521 | ||
22404274 | 1522 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1523 | { |
22404274 | 1524 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1525 | |
22404274 | 1526 | nvmeq->sq_tail = 0; |
04f3eafd | 1527 | nvmeq->last_sq_tail = 0; |
22404274 KB |
1528 | nvmeq->cq_head = 0; |
1529 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1530 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1531 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
f9f38e33 | 1532 | nvme_dbbuf_init(dev, nvmeq, qid); |
42f61420 | 1533 | dev->online_queues++; |
3a7afd8e | 1534 | wmb(); /* ensure the first interrupt sees the initialization */ |
22404274 KB |
1535 | } |
1536 | ||
4b04cc6a | 1537 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) |
22404274 KB |
1538 | { |
1539 | struct nvme_dev *dev = nvmeq->dev; | |
1540 | int result; | |
7c349dde | 1541 | u16 vector = 0; |
3f85d50b | 1542 | |
d1ed6aa1 CH |
1543 | clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); |
1544 | ||
22b55601 KB |
1545 | /* |
1546 | * A queue's vector matches the queue identifier unless the controller | |
1547 | * has only one vector available. | |
1548 | */ | |
4b04cc6a JA |
1549 | if (!polled) |
1550 | vector = dev->num_vecs == 1 ? 0 : qid; | |
1551 | else | |
7c349dde | 1552 | set_bit(NVMEQ_POLLED, &nvmeq->flags); |
4b04cc6a | 1553 | |
a8e3e0bb | 1554 | result = adapter_alloc_cq(dev, qid, nvmeq, vector); |
ded45505 KB |
1555 | if (result) |
1556 | return result; | |
b60503ba MW |
1557 | |
1558 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1559 | if (result < 0) | |
ded45505 KB |
1560 | return result; |
1561 | else if (result) | |
b60503ba MW |
1562 | goto release_cq; |
1563 | ||
a8e3e0bb | 1564 | nvmeq->cq_vector = vector; |
161b8be2 | 1565 | nvme_init_queue(nvmeq, qid); |
4b04cc6a | 1566 | |
7c349dde KB |
1567 | if (!polled) { |
1568 | nvmeq->cq_vector = vector; | |
4b04cc6a JA |
1569 | result = queue_request_irq(nvmeq); |
1570 | if (result < 0) | |
1571 | goto release_sq; | |
1572 | } | |
b60503ba | 1573 | |
4e224106 | 1574 | set_bit(NVMEQ_ENABLED, &nvmeq->flags); |
22404274 | 1575 | return result; |
b60503ba | 1576 | |
a8e3e0bb | 1577 | release_sq: |
f25a2dfc | 1578 | dev->online_queues--; |
b60503ba | 1579 | adapter_delete_sq(dev, qid); |
a8e3e0bb | 1580 | release_cq: |
b60503ba | 1581 | adapter_delete_cq(dev, qid); |
22404274 | 1582 | return result; |
b60503ba MW |
1583 | } |
1584 | ||
f363b089 | 1585 | static const struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1586 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1587 | .complete = nvme_pci_complete_rq, |
a4aea562 | 1588 | .init_hctx = nvme_admin_init_hctx, |
4af0e21c | 1589 | .exit_hctx = nvme_admin_exit_hctx, |
0350815a | 1590 | .init_request = nvme_init_request, |
a4aea562 MB |
1591 | .timeout = nvme_timeout, |
1592 | }; | |
1593 | ||
f363b089 | 1594 | static const struct blk_mq_ops nvme_mq_ops = { |
376f7ef8 CH |
1595 | .queue_rq = nvme_queue_rq, |
1596 | .complete = nvme_pci_complete_rq, | |
1597 | .commit_rqs = nvme_commit_rqs, | |
1598 | .init_hctx = nvme_init_hctx, | |
1599 | .init_request = nvme_init_request, | |
1600 | .map_queues = nvme_pci_map_queues, | |
1601 | .timeout = nvme_timeout, | |
1602 | .poll = nvme_poll, | |
dabcefab JA |
1603 | }; |
1604 | ||
ea191d2f KB |
1605 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1606 | { | |
1c63dc66 | 1607 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
69d9a99c KB |
1608 | /* |
1609 | * If the controller was reset during removal, it's possible | |
1610 | * user requests may be waiting on a stopped queue. Start the | |
1611 | * queue to flush these to completion. | |
1612 | */ | |
c81545f9 | 1613 | blk_mq_unquiesce_queue(dev->ctrl.admin_q); |
1c63dc66 | 1614 | blk_cleanup_queue(dev->ctrl.admin_q); |
ea191d2f KB |
1615 | blk_mq_free_tag_set(&dev->admin_tagset); |
1616 | } | |
1617 | } | |
1618 | ||
a4aea562 MB |
1619 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1620 | { | |
1c63dc66 | 1621 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1622 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1623 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c | 1624 | |
38dabe21 | 1625 | dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; |
a4aea562 | 1626 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1627 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
d43f1ccf | 1628 | dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); |
d3484991 | 1629 | dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; |
a4aea562 MB |
1630 | dev->admin_tagset.driver_data = dev; |
1631 | ||
1632 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1633 | return -ENOMEM; | |
34b6c231 | 1634 | dev->ctrl.admin_tagset = &dev->admin_tagset; |
a4aea562 | 1635 | |
1c63dc66 CH |
1636 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1637 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1638 | blk_mq_free_tag_set(&dev->admin_tagset); |
1639 | return -ENOMEM; | |
1640 | } | |
1c63dc66 | 1641 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1642 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1643 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1644 | return -ENODEV; |
1645 | } | |
0fb59cbc | 1646 | } else |
c81545f9 | 1647 | blk_mq_unquiesce_queue(dev->ctrl.admin_q); |
a4aea562 MB |
1648 | |
1649 | return 0; | |
1650 | } | |
1651 | ||
97f6ef64 XY |
1652 | static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1653 | { | |
1654 | return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); | |
1655 | } | |
1656 | ||
1657 | static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) | |
1658 | { | |
1659 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1660 | ||
1661 | if (size <= dev->bar_mapped_size) | |
1662 | return 0; | |
1663 | if (size > pci_resource_len(pdev, 0)) | |
1664 | return -ENOMEM; | |
1665 | if (dev->bar) | |
1666 | iounmap(dev->bar); | |
1667 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1668 | if (!dev->bar) { | |
1669 | dev->bar_mapped_size = 0; | |
1670 | return -ENOMEM; | |
1671 | } | |
1672 | dev->bar_mapped_size = size; | |
1673 | dev->dbs = dev->bar + NVME_REG_DBS; | |
1674 | ||
1675 | return 0; | |
1676 | } | |
1677 | ||
01ad0990 | 1678 | static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1679 | { |
ba47e386 | 1680 | int result; |
b60503ba MW |
1681 | u32 aqa; |
1682 | struct nvme_queue *nvmeq; | |
1683 | ||
97f6ef64 XY |
1684 | result = nvme_remap_bar(dev, db_bar_size(dev, 0)); |
1685 | if (result < 0) | |
1686 | return result; | |
1687 | ||
8ef2074d | 1688 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? |
20d0dfe6 | 1689 | NVME_CAP_NSSRC(dev->ctrl.cap) : 0; |
dfbac8c7 | 1690 | |
7a67cbea CH |
1691 | if (dev->subsystem && |
1692 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1693 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1694 | |
20d0dfe6 | 1695 | result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); |
ba47e386 MW |
1696 | if (result < 0) |
1697 | return result; | |
b60503ba | 1698 | |
a6ff7262 | 1699 | result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
147b27e4 SG |
1700 | if (result) |
1701 | return result; | |
b60503ba | 1702 | |
147b27e4 | 1703 | nvmeq = &dev->queues[0]; |
b60503ba MW |
1704 | aqa = nvmeq->q_depth - 1; |
1705 | aqa |= aqa << 16; | |
1706 | ||
7a67cbea CH |
1707 | writel(aqa, dev->bar + NVME_REG_AQA); |
1708 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1709 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1710 | |
20d0dfe6 | 1711 | result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); |
025c557a | 1712 | if (result) |
d4875622 | 1713 | return result; |
a4aea562 | 1714 | |
2b25d981 | 1715 | nvmeq->cq_vector = 0; |
161b8be2 | 1716 | nvme_init_queue(nvmeq, 0); |
dca51e78 | 1717 | result = queue_request_irq(nvmeq); |
758dd7fd | 1718 | if (result) { |
7c349dde | 1719 | dev->online_queues--; |
d4875622 | 1720 | return result; |
758dd7fd | 1721 | } |
025c557a | 1722 | |
4e224106 | 1723 | set_bit(NVMEQ_ENABLED, &nvmeq->flags); |
b60503ba MW |
1724 | return result; |
1725 | } | |
1726 | ||
749941f2 | 1727 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1728 | { |
4b04cc6a | 1729 | unsigned i, max, rw_queues; |
749941f2 | 1730 | int ret = 0; |
42f61420 | 1731 | |
d858e5f0 | 1732 | for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { |
a6ff7262 | 1733 | if (nvme_alloc_queue(dev, i, dev->q_depth)) { |
749941f2 | 1734 | ret = -ENOMEM; |
42f61420 | 1735 | break; |
749941f2 CH |
1736 | } |
1737 | } | |
42f61420 | 1738 | |
d858e5f0 | 1739 | max = min(dev->max_qid, dev->ctrl.queue_count - 1); |
e20ba6e1 CH |
1740 | if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { |
1741 | rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + | |
1742 | dev->io_queues[HCTX_TYPE_READ]; | |
4b04cc6a JA |
1743 | } else { |
1744 | rw_queues = max; | |
1745 | } | |
1746 | ||
949928c1 | 1747 | for (i = dev->online_queues; i <= max; i++) { |
4b04cc6a JA |
1748 | bool polled = i > rw_queues; |
1749 | ||
1750 | ret = nvme_create_queue(&dev->queues[i], i, polled); | |
d4875622 | 1751 | if (ret) |
42f61420 | 1752 | break; |
27e8166c | 1753 | } |
749941f2 CH |
1754 | |
1755 | /* | |
1756 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
8adb8c14 MI |
1757 | * than the desired amount of queues, and even a controller without |
1758 | * I/O queues can still be used to issue admin commands. This might | |
749941f2 CH |
1759 | * be useful to upgrade a buggy firmware for example. |
1760 | */ | |
1761 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1762 | } |
1763 | ||
202021c1 SB |
1764 | static ssize_t nvme_cmb_show(struct device *dev, |
1765 | struct device_attribute *attr, | |
1766 | char *buf) | |
1767 | { | |
1768 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
1769 | ||
c965809c | 1770 | return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", |
202021c1 SB |
1771 | ndev->cmbloc, ndev->cmbsz); |
1772 | } | |
1773 | static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); | |
1774 | ||
88de4598 | 1775 | static u64 nvme_cmb_size_unit(struct nvme_dev *dev) |
8ffaadf7 | 1776 | { |
88de4598 CH |
1777 | u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; |
1778 | ||
1779 | return 1ULL << (12 + 4 * szu); | |
1780 | } | |
1781 | ||
1782 | static u32 nvme_cmb_size(struct nvme_dev *dev) | |
1783 | { | |
1784 | return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; | |
1785 | } | |
1786 | ||
f65efd6d | 1787 | static void nvme_map_cmb(struct nvme_dev *dev) |
8ffaadf7 | 1788 | { |
88de4598 | 1789 | u64 size, offset; |
8ffaadf7 JD |
1790 | resource_size_t bar_size; |
1791 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
8969f1f8 | 1792 | int bar; |
8ffaadf7 | 1793 | |
9fe5c59f KB |
1794 | if (dev->cmb_size) |
1795 | return; | |
1796 | ||
7a67cbea | 1797 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
f65efd6d CH |
1798 | if (!dev->cmbsz) |
1799 | return; | |
202021c1 | 1800 | dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 | 1801 | |
88de4598 CH |
1802 | size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); |
1803 | offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); | |
8969f1f8 CH |
1804 | bar = NVME_CMB_BIR(dev->cmbloc); |
1805 | bar_size = pci_resource_len(pdev, bar); | |
8ffaadf7 JD |
1806 | |
1807 | if (offset > bar_size) | |
f65efd6d | 1808 | return; |
8ffaadf7 JD |
1809 | |
1810 | /* | |
1811 | * Controllers may support a CMB size larger than their BAR, | |
1812 | * for example, due to being behind a bridge. Reduce the CMB to | |
1813 | * the reported size of the BAR | |
1814 | */ | |
1815 | if (size > bar_size - offset) | |
1816 | size = bar_size - offset; | |
1817 | ||
0f238ff5 LG |
1818 | if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { |
1819 | dev_warn(dev->ctrl.device, | |
1820 | "failed to register the CMB\n"); | |
f65efd6d | 1821 | return; |
0f238ff5 LG |
1822 | } |
1823 | ||
8ffaadf7 | 1824 | dev->cmb_size = size; |
0f238ff5 LG |
1825 | dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); |
1826 | ||
1827 | if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == | |
1828 | (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) | |
1829 | pci_p2pmem_publish(pdev, true); | |
f65efd6d CH |
1830 | |
1831 | if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, | |
1832 | &dev_attr_cmb.attr, NULL)) | |
1833 | dev_warn(dev->ctrl.device, | |
1834 | "failed to add sysfs attribute for CMB\n"); | |
8ffaadf7 JD |
1835 | } |
1836 | ||
1837 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1838 | { | |
0f238ff5 | 1839 | if (dev->cmb_size) { |
1c78f773 MG |
1840 | sysfs_remove_file_from_group(&dev->ctrl.device->kobj, |
1841 | &dev_attr_cmb.attr, NULL); | |
0f238ff5 | 1842 | dev->cmb_size = 0; |
8ffaadf7 JD |
1843 | } |
1844 | } | |
1845 | ||
87ad72a5 CH |
1846 | static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) |
1847 | { | |
4033f35d | 1848 | u64 dma_addr = dev->host_mem_descs_dma; |
87ad72a5 | 1849 | struct nvme_command c; |
87ad72a5 CH |
1850 | int ret; |
1851 | ||
87ad72a5 CH |
1852 | memset(&c, 0, sizeof(c)); |
1853 | c.features.opcode = nvme_admin_set_features; | |
1854 | c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); | |
1855 | c.features.dword11 = cpu_to_le32(bits); | |
1856 | c.features.dword12 = cpu_to_le32(dev->host_mem_size >> | |
1857 | ilog2(dev->ctrl.page_size)); | |
1858 | c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); | |
1859 | c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); | |
1860 | c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); | |
1861 | ||
1862 | ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); | |
1863 | if (ret) { | |
1864 | dev_warn(dev->ctrl.device, | |
1865 | "failed to set host mem (err %d, flags %#x).\n", | |
1866 | ret, bits); | |
1867 | } | |
87ad72a5 CH |
1868 | return ret; |
1869 | } | |
1870 | ||
1871 | static void nvme_free_host_mem(struct nvme_dev *dev) | |
1872 | { | |
1873 | int i; | |
1874 | ||
1875 | for (i = 0; i < dev->nr_host_mem_descs; i++) { | |
1876 | struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; | |
1877 | size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; | |
1878 | ||
cc667f6d LD |
1879 | dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], |
1880 | le64_to_cpu(desc->addr), | |
1881 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); | |
87ad72a5 CH |
1882 | } |
1883 | ||
1884 | kfree(dev->host_mem_desc_bufs); | |
1885 | dev->host_mem_desc_bufs = NULL; | |
4033f35d CH |
1886 | dma_free_coherent(dev->dev, |
1887 | dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), | |
1888 | dev->host_mem_descs, dev->host_mem_descs_dma); | |
87ad72a5 | 1889 | dev->host_mem_descs = NULL; |
7e5dd57e | 1890 | dev->nr_host_mem_descs = 0; |
87ad72a5 CH |
1891 | } |
1892 | ||
92dc6895 CH |
1893 | static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, |
1894 | u32 chunk_size) | |
9d713c2b | 1895 | { |
87ad72a5 | 1896 | struct nvme_host_mem_buf_desc *descs; |
92dc6895 | 1897 | u32 max_entries, len; |
4033f35d | 1898 | dma_addr_t descs_dma; |
2ee0e4ed | 1899 | int i = 0; |
87ad72a5 | 1900 | void **bufs; |
6fbcde66 | 1901 | u64 size, tmp; |
87ad72a5 | 1902 | |
87ad72a5 CH |
1903 | tmp = (preferred + chunk_size - 1); |
1904 | do_div(tmp, chunk_size); | |
1905 | max_entries = tmp; | |
044a9df1 CH |
1906 | |
1907 | if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) | |
1908 | max_entries = dev->ctrl.hmmaxd; | |
1909 | ||
750afb08 LC |
1910 | descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), |
1911 | &descs_dma, GFP_KERNEL); | |
87ad72a5 CH |
1912 | if (!descs) |
1913 | goto out; | |
1914 | ||
1915 | bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); | |
1916 | if (!bufs) | |
1917 | goto out_free_descs; | |
1918 | ||
244a8fe4 | 1919 | for (size = 0; size < preferred && i < max_entries; size += len) { |
87ad72a5 CH |
1920 | dma_addr_t dma_addr; |
1921 | ||
50cdb7c6 | 1922 | len = min_t(u64, chunk_size, preferred - size); |
87ad72a5 CH |
1923 | bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, |
1924 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); | |
1925 | if (!bufs[i]) | |
1926 | break; | |
1927 | ||
1928 | descs[i].addr = cpu_to_le64(dma_addr); | |
1929 | descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); | |
1930 | i++; | |
1931 | } | |
1932 | ||
92dc6895 | 1933 | if (!size) |
87ad72a5 | 1934 | goto out_free_bufs; |
87ad72a5 | 1935 | |
87ad72a5 CH |
1936 | dev->nr_host_mem_descs = i; |
1937 | dev->host_mem_size = size; | |
1938 | dev->host_mem_descs = descs; | |
4033f35d | 1939 | dev->host_mem_descs_dma = descs_dma; |
87ad72a5 CH |
1940 | dev->host_mem_desc_bufs = bufs; |
1941 | return 0; | |
1942 | ||
1943 | out_free_bufs: | |
1944 | while (--i >= 0) { | |
1945 | size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; | |
1946 | ||
cc667f6d LD |
1947 | dma_free_attrs(dev->dev, size, bufs[i], |
1948 | le64_to_cpu(descs[i].addr), | |
1949 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); | |
87ad72a5 CH |
1950 | } |
1951 | ||
1952 | kfree(bufs); | |
1953 | out_free_descs: | |
4033f35d CH |
1954 | dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, |
1955 | descs_dma); | |
87ad72a5 | 1956 | out: |
87ad72a5 CH |
1957 | dev->host_mem_descs = NULL; |
1958 | return -ENOMEM; | |
1959 | } | |
1960 | ||
92dc6895 CH |
1961 | static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) |
1962 | { | |
1963 | u32 chunk_size; | |
1964 | ||
1965 | /* start big and work our way down */ | |
30f92d62 | 1966 | for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); |
044a9df1 | 1967 | chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); |
92dc6895 CH |
1968 | chunk_size /= 2) { |
1969 | if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { | |
1970 | if (!min || dev->host_mem_size >= min) | |
1971 | return 0; | |
1972 | nvme_free_host_mem(dev); | |
1973 | } | |
1974 | } | |
1975 | ||
1976 | return -ENOMEM; | |
1977 | } | |
1978 | ||
9620cfba | 1979 | static int nvme_setup_host_mem(struct nvme_dev *dev) |
87ad72a5 CH |
1980 | { |
1981 | u64 max = (u64)max_host_mem_size_mb * SZ_1M; | |
1982 | u64 preferred = (u64)dev->ctrl.hmpre * 4096; | |
1983 | u64 min = (u64)dev->ctrl.hmmin * 4096; | |
1984 | u32 enable_bits = NVME_HOST_MEM_ENABLE; | |
6fbcde66 | 1985 | int ret; |
87ad72a5 CH |
1986 | |
1987 | preferred = min(preferred, max); | |
1988 | if (min > max) { | |
1989 | dev_warn(dev->ctrl.device, | |
1990 | "min host memory (%lld MiB) above limit (%d MiB).\n", | |
1991 | min >> ilog2(SZ_1M), max_host_mem_size_mb); | |
1992 | nvme_free_host_mem(dev); | |
9620cfba | 1993 | return 0; |
87ad72a5 CH |
1994 | } |
1995 | ||
1996 | /* | |
1997 | * If we already have a buffer allocated check if we can reuse it. | |
1998 | */ | |
1999 | if (dev->host_mem_descs) { | |
2000 | if (dev->host_mem_size >= min) | |
2001 | enable_bits |= NVME_HOST_MEM_RETURN; | |
2002 | else | |
2003 | nvme_free_host_mem(dev); | |
2004 | } | |
2005 | ||
2006 | if (!dev->host_mem_descs) { | |
92dc6895 CH |
2007 | if (nvme_alloc_host_mem(dev, min, preferred)) { |
2008 | dev_warn(dev->ctrl.device, | |
2009 | "failed to allocate host memory buffer.\n"); | |
9620cfba | 2010 | return 0; /* controller must work without HMB */ |
92dc6895 CH |
2011 | } |
2012 | ||
2013 | dev_info(dev->ctrl.device, | |
2014 | "allocated %lld MiB host memory buffer.\n", | |
2015 | dev->host_mem_size >> ilog2(SZ_1M)); | |
87ad72a5 CH |
2016 | } |
2017 | ||
9620cfba CH |
2018 | ret = nvme_set_host_mem(dev, enable_bits); |
2019 | if (ret) | |
87ad72a5 | 2020 | nvme_free_host_mem(dev); |
9620cfba | 2021 | return ret; |
9d713c2b KB |
2022 | } |
2023 | ||
612b7286 ML |
2024 | /* |
2025 | * nirqs is the number of interrupts available for write and read | |
2026 | * queues. The core already reserved an interrupt for the admin queue. | |
2027 | */ | |
2028 | static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) | |
3b6592f7 | 2029 | { |
612b7286 ML |
2030 | struct nvme_dev *dev = affd->priv; |
2031 | unsigned int nr_read_queues; | |
3b6592f7 JA |
2032 | |
2033 | /* | |
612b7286 ML |
2034 | * If there is no interupt available for queues, ensure that |
2035 | * the default queue is set to 1. The affinity set size is | |
2036 | * also set to one, but the irq core ignores it for this case. | |
2037 | * | |
2038 | * If only one interrupt is available or 'write_queue' == 0, combine | |
2039 | * write and read queues. | |
2040 | * | |
2041 | * If 'write_queues' > 0, ensure it leaves room for at least one read | |
2042 | * queue. | |
3b6592f7 | 2043 | */ |
612b7286 ML |
2044 | if (!nrirqs) { |
2045 | nrirqs = 1; | |
2046 | nr_read_queues = 0; | |
2047 | } else if (nrirqs == 1 || !write_queues) { | |
2048 | nr_read_queues = 0; | |
2049 | } else if (write_queues >= nrirqs) { | |
2050 | nr_read_queues = 1; | |
3b6592f7 | 2051 | } else { |
612b7286 | 2052 | nr_read_queues = nrirqs - write_queues; |
3b6592f7 | 2053 | } |
612b7286 ML |
2054 | |
2055 | dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; | |
2056 | affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; | |
2057 | dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; | |
2058 | affd->set_size[HCTX_TYPE_READ] = nr_read_queues; | |
2059 | affd->nr_sets = nr_read_queues ? 2 : 1; | |
3b6592f7 JA |
2060 | } |
2061 | ||
6451fe73 | 2062 | static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) |
3b6592f7 JA |
2063 | { |
2064 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
3b6592f7 | 2065 | struct irq_affinity affd = { |
9cfef55b | 2066 | .pre_vectors = 1, |
612b7286 ML |
2067 | .calc_sets = nvme_calc_irq_sets, |
2068 | .priv = dev, | |
3b6592f7 | 2069 | }; |
6451fe73 JA |
2070 | unsigned int irq_queues, this_p_queues; |
2071 | ||
2072 | /* | |
2073 | * Poll queues don't need interrupts, but we need at least one IO | |
2074 | * queue left over for non-polled IO. | |
2075 | */ | |
2076 | this_p_queues = poll_queues; | |
2077 | if (this_p_queues >= nr_io_queues) { | |
2078 | this_p_queues = nr_io_queues - 1; | |
2079 | irq_queues = 1; | |
2080 | } else { | |
c45b1fa2 | 2081 | irq_queues = nr_io_queues - this_p_queues + 1; |
6451fe73 JA |
2082 | } |
2083 | dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; | |
3b6592f7 | 2084 | |
612b7286 ML |
2085 | /* Initialize for the single interrupt case */ |
2086 | dev->io_queues[HCTX_TYPE_DEFAULT] = 1; | |
2087 | dev->io_queues[HCTX_TYPE_READ] = 0; | |
3b6592f7 | 2088 | |
612b7286 ML |
2089 | return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, |
2090 | PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); | |
3b6592f7 JA |
2091 | } |
2092 | ||
8fae268b KB |
2093 | static void nvme_disable_io_queues(struct nvme_dev *dev) |
2094 | { | |
2095 | if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) | |
2096 | __nvme_disable_io_queues(dev, nvme_admin_delete_cq); | |
2097 | } | |
2098 | ||
8d85fce7 | 2099 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 2100 | { |
147b27e4 | 2101 | struct nvme_queue *adminq = &dev->queues[0]; |
e75ec752 | 2102 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
97f6ef64 XY |
2103 | int result, nr_io_queues; |
2104 | unsigned long size; | |
b60503ba | 2105 | |
3b6592f7 | 2106 | nr_io_queues = max_io_queues(); |
9a0be7ab CH |
2107 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
2108 | if (result < 0) | |
1b23484b | 2109 | return result; |
9a0be7ab | 2110 | |
f5fa90dc | 2111 | if (nr_io_queues == 0) |
a5229050 | 2112 | return 0; |
4e224106 CH |
2113 | |
2114 | clear_bit(NVMEQ_ENABLED, &adminq->flags); | |
b60503ba | 2115 | |
0f238ff5 | 2116 | if (dev->cmb_use_sqes) { |
8ffaadf7 JD |
2117 | result = nvme_cmb_qdepth(dev, nr_io_queues, |
2118 | sizeof(struct nvme_command)); | |
2119 | if (result > 0) | |
2120 | dev->q_depth = result; | |
2121 | else | |
0f238ff5 | 2122 | dev->cmb_use_sqes = false; |
8ffaadf7 JD |
2123 | } |
2124 | ||
97f6ef64 XY |
2125 | do { |
2126 | size = db_bar_size(dev, nr_io_queues); | |
2127 | result = nvme_remap_bar(dev, size); | |
2128 | if (!result) | |
2129 | break; | |
2130 | if (!--nr_io_queues) | |
2131 | return -ENOMEM; | |
2132 | } while (1); | |
2133 | adminq->q_db = dev->dbs; | |
f1938f6e | 2134 | |
8fae268b | 2135 | retry: |
9d713c2b | 2136 | /* Deregister the admin queue's interrupt */ |
0ff199cb | 2137 | pci_free_irq(pdev, 0, adminq); |
9d713c2b | 2138 | |
e32efbfc JA |
2139 | /* |
2140 | * If we enable msix early due to not intx, disable it again before | |
2141 | * setting up the full range we need. | |
2142 | */ | |
dca51e78 | 2143 | pci_free_irq_vectors(pdev); |
3b6592f7 JA |
2144 | |
2145 | result = nvme_setup_irqs(dev, nr_io_queues); | |
22b55601 | 2146 | if (result <= 0) |
dca51e78 | 2147 | return -EIO; |
3b6592f7 | 2148 | |
22b55601 | 2149 | dev->num_vecs = result; |
4b04cc6a | 2150 | result = max(result - 1, 1); |
e20ba6e1 | 2151 | dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; |
fa08a396 | 2152 | |
063a8096 MW |
2153 | /* |
2154 | * Should investigate if there's a performance win from allocating | |
2155 | * more queues than interrupt vectors; it might allow the submission | |
2156 | * path to scale better, even if the receive path is limited by the | |
2157 | * number of interrupts. | |
2158 | */ | |
dca51e78 | 2159 | result = queue_request_irq(adminq); |
7c349dde | 2160 | if (result) |
d4875622 | 2161 | return result; |
4e224106 | 2162 | set_bit(NVMEQ_ENABLED, &adminq->flags); |
8fae268b KB |
2163 | |
2164 | result = nvme_create_io_queues(dev); | |
2165 | if (result || dev->online_queues < 2) | |
2166 | return result; | |
2167 | ||
2168 | if (dev->online_queues - 1 < dev->max_qid) { | |
2169 | nr_io_queues = dev->online_queues - 1; | |
2170 | nvme_disable_io_queues(dev); | |
2171 | nvme_suspend_io_queues(dev); | |
2172 | goto retry; | |
2173 | } | |
2174 | dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", | |
2175 | dev->io_queues[HCTX_TYPE_DEFAULT], | |
2176 | dev->io_queues[HCTX_TYPE_READ], | |
2177 | dev->io_queues[HCTX_TYPE_POLL]); | |
2178 | return 0; | |
b60503ba MW |
2179 | } |
2180 | ||
2a842aca | 2181 | static void nvme_del_queue_end(struct request *req, blk_status_t error) |
a5768aa8 | 2182 | { |
db3cbfff | 2183 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 2184 | |
db3cbfff | 2185 | blk_mq_free_request(req); |
d1ed6aa1 | 2186 | complete(&nvmeq->delete_done); |
a5768aa8 KB |
2187 | } |
2188 | ||
2a842aca | 2189 | static void nvme_del_cq_end(struct request *req, blk_status_t error) |
a5768aa8 | 2190 | { |
db3cbfff | 2191 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 2192 | |
d1ed6aa1 CH |
2193 | if (error) |
2194 | set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); | |
db3cbfff KB |
2195 | |
2196 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
2197 | } |
2198 | ||
db3cbfff | 2199 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 2200 | { |
db3cbfff KB |
2201 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
2202 | struct request *req; | |
2203 | struct nvme_command cmd; | |
bda4e0fb | 2204 | |
db3cbfff KB |
2205 | memset(&cmd, 0, sizeof(cmd)); |
2206 | cmd.delete_queue.opcode = opcode; | |
2207 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 2208 | |
eb71f435 | 2209 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
db3cbfff KB |
2210 | if (IS_ERR(req)) |
2211 | return PTR_ERR(req); | |
bda4e0fb | 2212 | |
db3cbfff KB |
2213 | req->timeout = ADMIN_TIMEOUT; |
2214 | req->end_io_data = nvmeq; | |
2215 | ||
d1ed6aa1 | 2216 | init_completion(&nvmeq->delete_done); |
db3cbfff KB |
2217 | blk_execute_rq_nowait(q, NULL, req, false, |
2218 | opcode == nvme_admin_delete_cq ? | |
2219 | nvme_del_cq_end : nvme_del_queue_end); | |
2220 | return 0; | |
bda4e0fb KB |
2221 | } |
2222 | ||
8fae268b | 2223 | static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) |
a5768aa8 | 2224 | { |
5271edd4 | 2225 | int nr_queues = dev->online_queues - 1, sent = 0; |
db3cbfff | 2226 | unsigned long timeout; |
a5768aa8 | 2227 | |
db3cbfff | 2228 | retry: |
5271edd4 CH |
2229 | timeout = ADMIN_TIMEOUT; |
2230 | while (nr_queues > 0) { | |
2231 | if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) | |
2232 | break; | |
2233 | nr_queues--; | |
2234 | sent++; | |
db3cbfff | 2235 | } |
d1ed6aa1 CH |
2236 | while (sent) { |
2237 | struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; | |
2238 | ||
2239 | timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, | |
5271edd4 CH |
2240 | timeout); |
2241 | if (timeout == 0) | |
2242 | return false; | |
d1ed6aa1 CH |
2243 | |
2244 | /* handle any remaining CQEs */ | |
2245 | if (opcode == nvme_admin_delete_cq && | |
2246 | !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags)) | |
2247 | nvme_poll_irqdisable(nvmeq, -1); | |
2248 | ||
2249 | sent--; | |
5271edd4 CH |
2250 | if (nr_queues) |
2251 | goto retry; | |
2252 | } | |
2253 | return true; | |
a5768aa8 KB |
2254 | } |
2255 | ||
422ef0c7 | 2256 | /* |
2b1b7e78 | 2257 | * return error value only when tagset allocation failed |
422ef0c7 | 2258 | */ |
8d85fce7 | 2259 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 2260 | { |
2b1b7e78 JW |
2261 | int ret; |
2262 | ||
5bae7f73 | 2263 | if (!dev->ctrl.tagset) { |
376f7ef8 | 2264 | dev->tagset.ops = &nvme_mq_ops; |
ffe7704d | 2265 | dev->tagset.nr_hw_queues = dev->online_queues - 1; |
ed92ad37 CH |
2266 | dev->tagset.nr_maps = 2; /* default + read */ |
2267 | if (dev->io_queues[HCTX_TYPE_POLL]) | |
2268 | dev->tagset.nr_maps++; | |
ffe7704d KB |
2269 | dev->tagset.timeout = NVME_IO_TIMEOUT; |
2270 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
2271 | dev->tagset.queue_depth = | |
a4aea562 | 2272 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
d43f1ccf | 2273 | dev->tagset.cmd_size = sizeof(struct nvme_iod); |
ffe7704d KB |
2274 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; |
2275 | dev->tagset.driver_data = dev; | |
b60503ba | 2276 | |
2b1b7e78 JW |
2277 | ret = blk_mq_alloc_tag_set(&dev->tagset); |
2278 | if (ret) { | |
2279 | dev_warn(dev->ctrl.device, | |
2280 | "IO queues tagset allocation failed %d\n", ret); | |
2281 | return ret; | |
2282 | } | |
5bae7f73 | 2283 | dev->ctrl.tagset = &dev->tagset; |
949928c1 KB |
2284 | } else { |
2285 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
2286 | ||
2287 | /* Free previously allocated queues that are no longer usable */ | |
2288 | nvme_free_queues(dev, dev->online_queues); | |
ffe7704d | 2289 | } |
949928c1 | 2290 | |
e8fd41bb | 2291 | nvme_dbbuf_set(dev); |
e1e5e564 | 2292 | return 0; |
b60503ba MW |
2293 | } |
2294 | ||
b00a726a | 2295 | static int nvme_pci_enable(struct nvme_dev *dev) |
0877cb0d | 2296 | { |
b00a726a | 2297 | int result = -ENOMEM; |
e75ec752 | 2298 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
2299 | |
2300 | if (pci_enable_device_mem(pdev)) | |
2301 | return result; | |
2302 | ||
0877cb0d | 2303 | pci_set_master(pdev); |
0877cb0d | 2304 | |
e75ec752 CH |
2305 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
2306 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 2307 | goto disable; |
0877cb0d | 2308 | |
7a67cbea | 2309 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 | 2310 | result = -ENODEV; |
b00a726a | 2311 | goto disable; |
0e53d180 | 2312 | } |
e32efbfc JA |
2313 | |
2314 | /* | |
a5229050 KB |
2315 | * Some devices and/or platforms don't advertise or work with INTx |
2316 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll | |
2317 | * adjust this later. | |
e32efbfc | 2318 | */ |
dca51e78 CH |
2319 | result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
2320 | if (result < 0) | |
2321 | return result; | |
e32efbfc | 2322 | |
20d0dfe6 | 2323 | dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
7a67cbea | 2324 | |
20d0dfe6 | 2325 | dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, |
b27c1e68 | 2326 | io_queue_depth); |
20d0dfe6 | 2327 | dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); |
7a67cbea | 2328 | dev->dbs = dev->bar + 4096; |
1f390c1f SG |
2329 | |
2330 | /* | |
2331 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
2332 | * some MacBook7,1 to avoid controller resets and data loss. | |
2333 | */ | |
2334 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
2335 | dev->q_depth = 2; | |
9bdcfb10 CH |
2336 | dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " |
2337 | "set queue depth=%u to work around controller resets\n", | |
1f390c1f | 2338 | dev->q_depth); |
d554b5e1 MP |
2339 | } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && |
2340 | (pdev->device == 0xa821 || pdev->device == 0xa822) && | |
20d0dfe6 | 2341 | NVME_CAP_MQES(dev->ctrl.cap) == 0) { |
d554b5e1 MP |
2342 | dev->q_depth = 64; |
2343 | dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " | |
2344 | "set queue depth=%u\n", dev->q_depth); | |
1f390c1f SG |
2345 | } |
2346 | ||
f65efd6d | 2347 | nvme_map_cmb(dev); |
202021c1 | 2348 | |
a0a3408e KB |
2349 | pci_enable_pcie_error_reporting(pdev); |
2350 | pci_save_state(pdev); | |
0877cb0d KB |
2351 | return 0; |
2352 | ||
2353 | disable: | |
0877cb0d KB |
2354 | pci_disable_device(pdev); |
2355 | return result; | |
2356 | } | |
2357 | ||
2358 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
b00a726a KB |
2359 | { |
2360 | if (dev->bar) | |
2361 | iounmap(dev->bar); | |
a1f447b3 | 2362 | pci_release_mem_regions(to_pci_dev(dev->dev)); |
b00a726a KB |
2363 | } |
2364 | ||
2365 | static void nvme_pci_disable(struct nvme_dev *dev) | |
0877cb0d | 2366 | { |
e75ec752 CH |
2367 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2368 | ||
dca51e78 | 2369 | pci_free_irq_vectors(pdev); |
0877cb0d | 2370 | |
a0a3408e KB |
2371 | if (pci_is_enabled(pdev)) { |
2372 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 2373 | pci_disable_device(pdev); |
4d115420 | 2374 | } |
4d115420 KB |
2375 | } |
2376 | ||
a5cdb68c | 2377 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 2378 | { |
e43269e6 | 2379 | bool dead = true, freeze = false; |
302ad8cc | 2380 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
22404274 | 2381 | |
77bf25ea | 2382 | mutex_lock(&dev->shutdown_lock); |
302ad8cc KB |
2383 | if (pci_is_enabled(pdev)) { |
2384 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
2385 | ||
ebef7368 | 2386 | if (dev->ctrl.state == NVME_CTRL_LIVE || |
e43269e6 KB |
2387 | dev->ctrl.state == NVME_CTRL_RESETTING) { |
2388 | freeze = true; | |
302ad8cc | 2389 | nvme_start_freeze(&dev->ctrl); |
e43269e6 | 2390 | } |
302ad8cc KB |
2391 | dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || |
2392 | pdev->error_state != pci_channel_io_normal); | |
c9d3bf88 | 2393 | } |
c21377f8 | 2394 | |
302ad8cc KB |
2395 | /* |
2396 | * Give the controller a chance to complete all entered requests if | |
2397 | * doing a safe shutdown. | |
2398 | */ | |
e43269e6 KB |
2399 | if (!dead && shutdown && freeze) |
2400 | nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); | |
9a915a5b JW |
2401 | |
2402 | nvme_stop_queues(&dev->ctrl); | |
87ad72a5 | 2403 | |
64ee0ac0 | 2404 | if (!dead && dev->ctrl.queue_count > 0) { |
8fae268b | 2405 | nvme_disable_io_queues(dev); |
a5cdb68c | 2406 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 2407 | } |
8fae268b KB |
2408 | nvme_suspend_io_queues(dev); |
2409 | nvme_suspend_queue(&dev->queues[0]); | |
b00a726a | 2410 | nvme_pci_disable(dev); |
07836e65 | 2411 | |
e1958e65 ML |
2412 | blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); |
2413 | blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); | |
302ad8cc KB |
2414 | |
2415 | /* | |
2416 | * The driver will not be starting up queues again if shutting down so | |
2417 | * must flush all entered requests to their failed completion to avoid | |
2418 | * deadlocking blk-mq hot-cpu notifier. | |
2419 | */ | |
c8e9e9b7 | 2420 | if (shutdown) { |
302ad8cc | 2421 | nvme_start_queues(&dev->ctrl); |
c8e9e9b7 KB |
2422 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) |
2423 | blk_mq_unquiesce_queue(dev->ctrl.admin_q); | |
2424 | } | |
77bf25ea | 2425 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
2426 | } |
2427 | ||
091b6092 MW |
2428 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2429 | { | |
e75ec752 | 2430 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
2431 | PAGE_SIZE, PAGE_SIZE, 0); |
2432 | if (!dev->prp_page_pool) | |
2433 | return -ENOMEM; | |
2434 | ||
99802a7a | 2435 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 2436 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
2437 | 256, 256, 0); |
2438 | if (!dev->prp_small_pool) { | |
2439 | dma_pool_destroy(dev->prp_page_pool); | |
2440 | return -ENOMEM; | |
2441 | } | |
091b6092 MW |
2442 | return 0; |
2443 | } | |
2444 | ||
2445 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2446 | { | |
2447 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2448 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2449 | } |
2450 | ||
1673f1f0 | 2451 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 2452 | { |
1673f1f0 | 2453 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 2454 | |
f9f38e33 | 2455 | nvme_dbbuf_dma_free(dev); |
e75ec752 | 2456 | put_device(dev->dev); |
4af0e21c KB |
2457 | if (dev->tagset.tags) |
2458 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
2459 | if (dev->ctrl.admin_q) |
2460 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 | 2461 | kfree(dev->queues); |
e286bcfc | 2462 | free_opal_dev(dev->ctrl.opal_dev); |
943e942e | 2463 | mempool_destroy(dev->iod_mempool); |
5e82e952 KB |
2464 | kfree(dev); |
2465 | } | |
2466 | ||
f58944e2 KB |
2467 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) |
2468 | { | |
237045fc | 2469 | dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); |
f58944e2 | 2470 | |
d22524a4 | 2471 | nvme_get_ctrl(&dev->ctrl); |
69d9a99c | 2472 | nvme_dev_disable(dev, false); |
9f9cafc1 | 2473 | nvme_kill_queues(&dev->ctrl); |
03e0f3a6 | 2474 | if (!queue_work(nvme_wq, &dev->remove_work)) |
f58944e2 KB |
2475 | nvme_put_ctrl(&dev->ctrl); |
2476 | } | |
2477 | ||
fd634f41 | 2478 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 2479 | { |
d86c4d8e CH |
2480 | struct nvme_dev *dev = |
2481 | container_of(work, struct nvme_dev, ctrl.reset_work); | |
a98e58e5 | 2482 | bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); |
f58944e2 | 2483 | int result = -ENODEV; |
2b1b7e78 | 2484 | enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; |
5e82e952 | 2485 | |
82b057ca | 2486 | if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) |
fd634f41 | 2487 | goto out; |
5e82e952 | 2488 | |
fd634f41 CH |
2489 | /* |
2490 | * If we're called to reset a live controller first shut it down before | |
2491 | * moving on. | |
2492 | */ | |
b00a726a | 2493 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
a5cdb68c | 2494 | nvme_dev_disable(dev, false); |
d6135c3a | 2495 | nvme_sync_queues(&dev->ctrl); |
5e82e952 | 2496 | |
5c959d73 | 2497 | mutex_lock(&dev->shutdown_lock); |
b00a726a | 2498 | result = nvme_pci_enable(dev); |
f0b50732 | 2499 | if (result) |
4726bcf3 | 2500 | goto out_unlock; |
f0b50732 | 2501 | |
01ad0990 | 2502 | result = nvme_pci_configure_admin_queue(dev); |
f0b50732 | 2503 | if (result) |
4726bcf3 | 2504 | goto out_unlock; |
f0b50732 | 2505 | |
0fb59cbc KB |
2506 | result = nvme_alloc_admin_tags(dev); |
2507 | if (result) | |
4726bcf3 | 2508 | goto out_unlock; |
b9afca3e | 2509 | |
943e942e JA |
2510 | /* |
2511 | * Limit the max command size to prevent iod->sg allocations going | |
2512 | * over a single page. | |
2513 | */ | |
2514 | dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1; | |
2515 | dev->ctrl.max_segments = NVME_MAX_SEGS; | |
a48bc520 CH |
2516 | |
2517 | /* | |
2518 | * Don't limit the IOMMU merged segment size. | |
2519 | */ | |
2520 | dma_set_max_seg_size(dev->dev, 0xffffffff); | |
2521 | ||
5c959d73 KB |
2522 | mutex_unlock(&dev->shutdown_lock); |
2523 | ||
2524 | /* | |
2525 | * Introduce CONNECTING state from nvme-fc/rdma transports to mark the | |
2526 | * initializing procedure here. | |
2527 | */ | |
2528 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { | |
2529 | dev_warn(dev->ctrl.device, | |
2530 | "failed to mark controller CONNECTING\n"); | |
2531 | goto out; | |
2532 | } | |
943e942e | 2533 | |
ce4541f4 CH |
2534 | result = nvme_init_identify(&dev->ctrl); |
2535 | if (result) | |
f58944e2 | 2536 | goto out; |
ce4541f4 | 2537 | |
e286bcfc SB |
2538 | if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { |
2539 | if (!dev->ctrl.opal_dev) | |
2540 | dev->ctrl.opal_dev = | |
2541 | init_opal_dev(&dev->ctrl, &nvme_sec_submit); | |
2542 | else if (was_suspend) | |
2543 | opal_unlock_from_suspend(dev->ctrl.opal_dev); | |
2544 | } else { | |
2545 | free_opal_dev(dev->ctrl.opal_dev); | |
2546 | dev->ctrl.opal_dev = NULL; | |
4f1244c8 | 2547 | } |
a98e58e5 | 2548 | |
f9f38e33 HK |
2549 | if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { |
2550 | result = nvme_dbbuf_dma_alloc(dev); | |
2551 | if (result) | |
2552 | dev_warn(dev->dev, | |
2553 | "unable to allocate dma for dbbuf\n"); | |
2554 | } | |
2555 | ||
9620cfba CH |
2556 | if (dev->ctrl.hmpre) { |
2557 | result = nvme_setup_host_mem(dev); | |
2558 | if (result < 0) | |
2559 | goto out; | |
2560 | } | |
87ad72a5 | 2561 | |
f0b50732 | 2562 | result = nvme_setup_io_queues(dev); |
badc34d4 | 2563 | if (result) |
f58944e2 | 2564 | goto out; |
f0b50732 | 2565 | |
2659e57b CH |
2566 | /* |
2567 | * Keep the controller around but remove all namespaces if we don't have | |
2568 | * any working I/O queue. | |
2569 | */ | |
3cf519b5 | 2570 | if (dev->online_queues < 2) { |
1b3c47c1 | 2571 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
3b24774e | 2572 | nvme_kill_queues(&dev->ctrl); |
5bae7f73 | 2573 | nvme_remove_namespaces(&dev->ctrl); |
2b1b7e78 | 2574 | new_state = NVME_CTRL_ADMIN_ONLY; |
3cf519b5 | 2575 | } else { |
25646264 | 2576 | nvme_start_queues(&dev->ctrl); |
302ad8cc | 2577 | nvme_wait_freeze(&dev->ctrl); |
2b1b7e78 JW |
2578 | /* hit this only when allocate tagset fails */ |
2579 | if (nvme_dev_add(dev)) | |
2580 | new_state = NVME_CTRL_ADMIN_ONLY; | |
302ad8cc | 2581 | nvme_unfreeze(&dev->ctrl); |
3cf519b5 CH |
2582 | } |
2583 | ||
2b1b7e78 JW |
2584 | /* |
2585 | * If only admin queue live, keep it to do further investigation or | |
2586 | * recovery. | |
2587 | */ | |
2588 | if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { | |
2589 | dev_warn(dev->ctrl.device, | |
2590 | "failed to mark controller state %d\n", new_state); | |
bb8d261e CH |
2591 | goto out; |
2592 | } | |
92911a55 | 2593 | |
d09f2b45 | 2594 | nvme_start_ctrl(&dev->ctrl); |
3cf519b5 | 2595 | return; |
f0b50732 | 2596 | |
4726bcf3 KB |
2597 | out_unlock: |
2598 | mutex_unlock(&dev->shutdown_lock); | |
3cf519b5 | 2599 | out: |
f58944e2 | 2600 | nvme_remove_dead_ctrl(dev, result); |
f0b50732 KB |
2601 | } |
2602 | ||
5c8809e6 | 2603 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 2604 | { |
5c8809e6 | 2605 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 2606 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 KB |
2607 | |
2608 | if (pci_get_drvdata(pdev)) | |
921920ab | 2609 | device_release_driver(&pdev->dev); |
1673f1f0 | 2610 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
2611 | } |
2612 | ||
1c63dc66 | 2613 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 2614 | { |
1c63dc66 | 2615 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 2616 | return 0; |
9ca97374 TH |
2617 | } |
2618 | ||
5fd4ce1b | 2619 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 2620 | { |
5fd4ce1b CH |
2621 | writel(val, to_nvme_dev(ctrl)->bar + off); |
2622 | return 0; | |
2623 | } | |
4cc06521 | 2624 | |
7fd8930f CH |
2625 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2626 | { | |
2627 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
2628 | return 0; | |
4cc06521 KB |
2629 | } |
2630 | ||
97c12223 KB |
2631 | static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) |
2632 | { | |
2633 | struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); | |
2634 | ||
2635 | return snprintf(buf, size, "%s", dev_name(&pdev->dev)); | |
2636 | } | |
2637 | ||
1c63dc66 | 2638 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
1a353d85 | 2639 | .name = "pcie", |
e439bb12 | 2640 | .module = THIS_MODULE, |
e0596ab2 LG |
2641 | .flags = NVME_F_METADATA_SUPPORTED | |
2642 | NVME_F_PCI_P2PDMA, | |
1c63dc66 | 2643 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 2644 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 2645 | .reg_read64 = nvme_pci_reg_read64, |
1673f1f0 | 2646 | .free_ctrl = nvme_pci_free_ctrl, |
f866fc42 | 2647 | .submit_async_event = nvme_pci_submit_async_event, |
97c12223 | 2648 | .get_address = nvme_pci_get_address, |
1c63dc66 | 2649 | }; |
4cc06521 | 2650 | |
b00a726a KB |
2651 | static int nvme_dev_map(struct nvme_dev *dev) |
2652 | { | |
b00a726a KB |
2653 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2654 | ||
a1f447b3 | 2655 | if (pci_request_mem_regions(pdev, "nvme")) |
b00a726a KB |
2656 | return -ENODEV; |
2657 | ||
97f6ef64 | 2658 | if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) |
b00a726a KB |
2659 | goto release; |
2660 | ||
9fa196e7 | 2661 | return 0; |
b00a726a | 2662 | release: |
9fa196e7 MG |
2663 | pci_release_mem_regions(pdev); |
2664 | return -ENODEV; | |
b00a726a KB |
2665 | } |
2666 | ||
8427bbc2 | 2667 | static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) |
ff5350a8 AL |
2668 | { |
2669 | if (pdev->vendor == 0x144d && pdev->device == 0xa802) { | |
2670 | /* | |
2671 | * Several Samsung devices seem to drop off the PCIe bus | |
2672 | * randomly when APST is on and uses the deepest sleep state. | |
2673 | * This has been observed on a Samsung "SM951 NVMe SAMSUNG | |
2674 | * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD | |
2675 | * 950 PRO 256GB", but it seems to be restricted to two Dell | |
2676 | * laptops. | |
2677 | */ | |
2678 | if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && | |
2679 | (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || | |
2680 | dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) | |
2681 | return NVME_QUIRK_NO_DEEPEST_PS; | |
8427bbc2 KHF |
2682 | } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { |
2683 | /* | |
2684 | * Samsung SSD 960 EVO drops off the PCIe bus after system | |
467c77d4 JJ |
2685 | * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as |
2686 | * within few minutes after bootup on a Coffee Lake board - | |
2687 | * ASUS PRIME Z370-A | |
8427bbc2 KHF |
2688 | */ |
2689 | if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && | |
467c77d4 JJ |
2690 | (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || |
2691 | dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) | |
8427bbc2 | 2692 | return NVME_QUIRK_NO_APST; |
ff5350a8 AL |
2693 | } |
2694 | ||
2695 | return 0; | |
2696 | } | |
2697 | ||
18119775 KB |
2698 | static void nvme_async_probe(void *data, async_cookie_t cookie) |
2699 | { | |
2700 | struct nvme_dev *dev = data; | |
80f513b5 | 2701 | |
18119775 KB |
2702 | nvme_reset_ctrl_sync(&dev->ctrl); |
2703 | flush_work(&dev->ctrl.scan_work); | |
80f513b5 | 2704 | nvme_put_ctrl(&dev->ctrl); |
18119775 KB |
2705 | } |
2706 | ||
8d85fce7 | 2707 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2708 | { |
a4aea562 | 2709 | int node, result = -ENOMEM; |
b60503ba | 2710 | struct nvme_dev *dev; |
ff5350a8 | 2711 | unsigned long quirks = id->driver_data; |
943e942e | 2712 | size_t alloc_size; |
b60503ba | 2713 | |
a4aea562 MB |
2714 | node = dev_to_node(&pdev->dev); |
2715 | if (node == NUMA_NO_NODE) | |
2fa84351 | 2716 | set_dev_node(&pdev->dev, first_memory_node); |
a4aea562 MB |
2717 | |
2718 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2719 | if (!dev) |
2720 | return -ENOMEM; | |
147b27e4 | 2721 | |
3b6592f7 JA |
2722 | dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), |
2723 | GFP_KERNEL, node); | |
b60503ba MW |
2724 | if (!dev->queues) |
2725 | goto free; | |
2726 | ||
e75ec752 | 2727 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2728 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2729 | |
b00a726a KB |
2730 | result = nvme_dev_map(dev); |
2731 | if (result) | |
b00c9b7a | 2732 | goto put_pci; |
b00a726a | 2733 | |
d86c4d8e | 2734 | INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); |
5c8809e6 | 2735 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
77bf25ea | 2736 | mutex_init(&dev->shutdown_lock); |
b60503ba | 2737 | |
091b6092 MW |
2738 | result = nvme_setup_prp_pools(dev); |
2739 | if (result) | |
b00c9b7a | 2740 | goto unmap; |
4cc06521 | 2741 | |
8427bbc2 | 2742 | quirks |= check_vendor_combination_bug(pdev); |
ff5350a8 | 2743 | |
943e942e JA |
2744 | /* |
2745 | * Double check that our mempool alloc size will cover the biggest | |
2746 | * command we support. | |
2747 | */ | |
2748 | alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, | |
2749 | NVME_MAX_SEGS, true); | |
2750 | WARN_ON_ONCE(alloc_size > PAGE_SIZE); | |
2751 | ||
2752 | dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, | |
2753 | mempool_kfree, | |
2754 | (void *) alloc_size, | |
2755 | GFP_KERNEL, node); | |
2756 | if (!dev->iod_mempool) { | |
2757 | result = -ENOMEM; | |
2758 | goto release_pools; | |
2759 | } | |
2760 | ||
b6e44b4c KB |
2761 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
2762 | quirks); | |
2763 | if (result) | |
2764 | goto release_mempool; | |
2765 | ||
1b3c47c1 SG |
2766 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
2767 | ||
80f513b5 | 2768 | nvme_get_ctrl(&dev->ctrl); |
18119775 | 2769 | async_schedule(nvme_async_probe, dev); |
4caff8fc | 2770 | |
b60503ba MW |
2771 | return 0; |
2772 | ||
b6e44b4c KB |
2773 | release_mempool: |
2774 | mempool_destroy(dev->iod_mempool); | |
0877cb0d | 2775 | release_pools: |
091b6092 | 2776 | nvme_release_prp_pools(dev); |
b00c9b7a CJ |
2777 | unmap: |
2778 | nvme_dev_unmap(dev); | |
a96d4f5c | 2779 | put_pci: |
e75ec752 | 2780 | put_device(dev->dev); |
b60503ba MW |
2781 | free: |
2782 | kfree(dev->queues); | |
b60503ba MW |
2783 | kfree(dev); |
2784 | return result; | |
2785 | } | |
2786 | ||
775755ed | 2787 | static void nvme_reset_prepare(struct pci_dev *pdev) |
f0d54a54 | 2788 | { |
a6739479 | 2789 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f263fbb8 | 2790 | nvme_dev_disable(dev, false); |
775755ed | 2791 | } |
f0d54a54 | 2792 | |
775755ed CH |
2793 | static void nvme_reset_done(struct pci_dev *pdev) |
2794 | { | |
f263fbb8 | 2795 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
79c48ccf | 2796 | nvme_reset_ctrl_sync(&dev->ctrl); |
f0d54a54 KB |
2797 | } |
2798 | ||
09ece142 KB |
2799 | static void nvme_shutdown(struct pci_dev *pdev) |
2800 | { | |
2801 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
a5cdb68c | 2802 | nvme_dev_disable(dev, true); |
09ece142 KB |
2803 | } |
2804 | ||
f58944e2 KB |
2805 | /* |
2806 | * The driver's remove may be called on a device in a partially initialized | |
2807 | * state. This function must not have any dependencies on the device state in | |
2808 | * order to proceed. | |
2809 | */ | |
8d85fce7 | 2810 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2811 | { |
2812 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 2813 | |
bb8d261e | 2814 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
9a6b9458 | 2815 | pci_set_drvdata(pdev, NULL); |
0ff9d4e1 | 2816 | |
6db28eda | 2817 | if (!pci_device_is_present(pdev)) { |
0ff9d4e1 | 2818 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); |
1d39e692 | 2819 | nvme_dev_disable(dev, true); |
cb4bfda6 | 2820 | nvme_dev_remove_admin(dev); |
6db28eda | 2821 | } |
0ff9d4e1 | 2822 | |
d86c4d8e | 2823 | flush_work(&dev->ctrl.reset_work); |
d09f2b45 SG |
2824 | nvme_stop_ctrl(&dev->ctrl); |
2825 | nvme_remove_namespaces(&dev->ctrl); | |
a5cdb68c | 2826 | nvme_dev_disable(dev, true); |
9fe5c59f | 2827 | nvme_release_cmb(dev); |
87ad72a5 | 2828 | nvme_free_host_mem(dev); |
a4aea562 | 2829 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2830 | nvme_free_queues(dev, 0); |
d09f2b45 | 2831 | nvme_uninit_ctrl(&dev->ctrl); |
9a6b9458 | 2832 | nvme_release_prp_pools(dev); |
b00a726a | 2833 | nvme_dev_unmap(dev); |
1673f1f0 | 2834 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2835 | } |
2836 | ||
671a6018 | 2837 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2838 | static int nvme_suspend(struct device *dev) |
2839 | { | |
2840 | struct pci_dev *pdev = to_pci_dev(dev); | |
2841 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2842 | ||
a5cdb68c | 2843 | nvme_dev_disable(ndev, true); |
cd638946 KB |
2844 | return 0; |
2845 | } | |
2846 | ||
2847 | static int nvme_resume(struct device *dev) | |
2848 | { | |
2849 | struct pci_dev *pdev = to_pci_dev(dev); | |
2850 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2851 | |
d86c4d8e | 2852 | nvme_reset_ctrl(&ndev->ctrl); |
9a6b9458 | 2853 | return 0; |
cd638946 | 2854 | } |
671a6018 | 2855 | #endif |
cd638946 KB |
2856 | |
2857 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2858 | |
a0a3408e KB |
2859 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2860 | pci_channel_state_t state) | |
2861 | { | |
2862 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2863 | ||
2864 | /* | |
2865 | * A frozen channel requires a reset. When detected, this method will | |
2866 | * shutdown the controller to quiesce. The controller will be restarted | |
2867 | * after the slot reset through driver's slot_reset callback. | |
2868 | */ | |
a0a3408e KB |
2869 | switch (state) { |
2870 | case pci_channel_io_normal: | |
2871 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2872 | case pci_channel_io_frozen: | |
d011fb31 KB |
2873 | dev_warn(dev->ctrl.device, |
2874 | "frozen state error detected, reset controller\n"); | |
a5cdb68c | 2875 | nvme_dev_disable(dev, false); |
a0a3408e KB |
2876 | return PCI_ERS_RESULT_NEED_RESET; |
2877 | case pci_channel_io_perm_failure: | |
d011fb31 KB |
2878 | dev_warn(dev->ctrl.device, |
2879 | "failure state error detected, request disconnect\n"); | |
a0a3408e KB |
2880 | return PCI_ERS_RESULT_DISCONNECT; |
2881 | } | |
2882 | return PCI_ERS_RESULT_NEED_RESET; | |
2883 | } | |
2884 | ||
2885 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2886 | { | |
2887 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2888 | ||
1b3c47c1 | 2889 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e | 2890 | pci_restore_state(pdev); |
d86c4d8e | 2891 | nvme_reset_ctrl(&dev->ctrl); |
a0a3408e KB |
2892 | return PCI_ERS_RESULT_RECOVERED; |
2893 | } | |
2894 | ||
2895 | static void nvme_error_resume(struct pci_dev *pdev) | |
2896 | { | |
72cd4cc2 KB |
2897 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
2898 | ||
2899 | flush_work(&dev->ctrl.reset_work); | |
a0a3408e KB |
2900 | } |
2901 | ||
1d352035 | 2902 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2903 | .error_detected = nvme_error_detected, |
b60503ba MW |
2904 | .slot_reset = nvme_slot_reset, |
2905 | .resume = nvme_error_resume, | |
775755ed CH |
2906 | .reset_prepare = nvme_reset_prepare, |
2907 | .reset_done = nvme_reset_done, | |
b60503ba MW |
2908 | }; |
2909 | ||
6eb0d698 | 2910 | static const struct pci_device_id nvme_id_table[] = { |
106198ed | 2911 | { PCI_VDEVICE(INTEL, 0x0953), |
08095e70 | 2912 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
e850fd16 | 2913 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
99466e70 KB |
2914 | { PCI_VDEVICE(INTEL, 0x0a53), |
2915 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
e850fd16 | 2916 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
99466e70 KB |
2917 | { PCI_VDEVICE(INTEL, 0x0a54), |
2918 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
e850fd16 | 2919 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
f99cb7af DWF |
2920 | { PCI_VDEVICE(INTEL, 0x0a55), |
2921 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
2922 | NVME_QUIRK_DEALLOCATE_ZEROES, }, | |
50af47d0 | 2923 | { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ |
9abd68ef JA |
2924 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS | |
2925 | NVME_QUIRK_MEDIUM_PRIO_SQ }, | |
6299358d JD |
2926 | { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ |
2927 | .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, | |
540c801c | 2928 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
7b210e4e CH |
2929 | .driver_data = NVME_QUIRK_IDENTIFY_CNS | |
2930 | NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
0302ae60 MP |
2931 | { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ |
2932 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
54adc010 GP |
2933 | { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ |
2934 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
8c97eecc JL |
2935 | { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ |
2936 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
015282c9 WW |
2937 | { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ |
2938 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
d554b5e1 MP |
2939 | { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ |
2940 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
2941 | { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ | |
2942 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
608cc4b1 CH |
2943 | { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ |
2944 | .driver_data = NVME_QUIRK_LIGHTNVM, }, | |
2945 | { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ | |
2946 | .driver_data = NVME_QUIRK_LIGHTNVM, }, | |
ea48e877 WX |
2947 | { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ |
2948 | .driver_data = NVME_QUIRK_LIGHTNVM, }, | |
b60503ba | 2949 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2950 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
124298bd | 2951 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, |
b60503ba MW |
2952 | { 0, } |
2953 | }; | |
2954 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2955 | ||
2956 | static struct pci_driver nvme_driver = { | |
2957 | .name = "nvme", | |
2958 | .id_table = nvme_id_table, | |
2959 | .probe = nvme_probe, | |
8d85fce7 | 2960 | .remove = nvme_remove, |
09ece142 | 2961 | .shutdown = nvme_shutdown, |
cd638946 KB |
2962 | .driver = { |
2963 | .pm = &nvme_dev_pm_ops, | |
2964 | }, | |
74d986ab | 2965 | .sriov_configure = pci_sriov_configure_simple, |
b60503ba MW |
2966 | .err_handler = &nvme_err_handler, |
2967 | }; | |
2968 | ||
2969 | static int __init nvme_init(void) | |
2970 | { | |
81101540 CH |
2971 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); |
2972 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
2973 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
612b7286 | 2974 | BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); |
9a6327d2 | 2975 | return pci_register_driver(&nvme_driver); |
b60503ba MW |
2976 | } |
2977 | ||
2978 | static void __exit nvme_exit(void) | |
2979 | { | |
2980 | pci_unregister_driver(&nvme_driver); | |
03e0f3a6 | 2981 | flush_workqueue(nvme_wq); |
b60503ba MW |
2982 | } |
2983 | ||
2984 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2985 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2986 | MODULE_VERSION("1.0"); |
b60503ba MW |
2987 | module_init(nvme_init); |
2988 | module_exit(nvme_exit); |