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nvme: use driver pdu command for passthrough
[mirror_ubuntu-jammy-kernel.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
ff5350a8 13#include <linux/dmi.h>
b60503ba
MW		 14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
b60503ba
MW		 17#include <linux/mm.h>
18#include <linux/module.h>
77bf25ea 19#include <linux/mutex.h>
d0877473 20#include <linux/once.h>
b60503ba 21#include <linux/pci.h>
d916b1be 22#include <linux/suspend.h>
e1e5e564 23#include <linux/t10-pi.h>
b60503ba 24#include <linux/types.h>
2f8e2c87 25#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 26#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 27#include <linux/sed-opal.h>
0f238ff5 28#include <linux/pci-p2pdma.h>
797a796a 29
604c01d5 30#include "trace.h"
f11bb3e2
CH		 31#include "nvme.h"
32
c1e0cc7e 33#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 34#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 35
a7a7cbe3 36#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 37
943e942e
JA		 38/*
39 * These can be higher, but we need to ensure that any command doesn't
40 * require an sg allocation that needs more than a page of data.
41 */
42#define NVME_MAX_KB_SZ 4096
43#define NVME_MAX_SEGS 127
44
58ffacb5
MW		 45static int use_threaded_interrupts;
46module_param(use_threaded_interrupts, int, 0);
47
8ffaadf7 48static bool use_cmb_sqes = true;
69f4eb9f 49module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 50MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
51
87ad72a5
CH		 52static unsigned int max_host_mem_size_mb = 128;
53module_param(max_host_mem_size_mb, uint, 0444);
54MODULE_PARM_DESC(max_host_mem_size_mb,
55 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 56
a7a7cbe3
CK		 57static unsigned int sgl_threshold = SZ_32K;
58module_param(sgl_threshold, uint, 0644);
59MODULE_PARM_DESC(sgl_threshold,
60 "Use SGLs when average request segment size is larger or equal to "
61 "this size. Use 0 to disable SGLs.");
62
b27c1e68 63static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
64static const struct kernel_param_ops io_queue_depth_ops = {
65 .set = io_queue_depth_set,
61f3b896 66 .get = param_get_uint,
b27c1e68 67};
68
61f3b896 69static unsigned int io_queue_depth = 1024;
b27c1e68 70module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
71MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
72
9c9e76d5
WZ		 73static int io_queue_count_set(const char *val, const struct kernel_param *kp)
74{
75 unsigned int n;
76 int ret;
77
78 ret = kstrtouint(val, 10, &n);
79 if (ret != 0 || n > num_possible_cpus())
80 return -EINVAL;
81 return param_set_uint(val, kp);
82}
83
84static const struct kernel_param_ops io_queue_count_ops = {
85 .set = io_queue_count_set,
86 .get = param_get_uint,
87};
88
3f68baf7 89static unsigned int write_queues;
9c9e76d5 90module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 91MODULE_PARM_DESC(write_queues,
92 "Number of queues to use for writes. If not set, reads and writes "
93 "will share a queue set.");
94
3f68baf7 95static unsigned int poll_queues;
9c9e76d5 96module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 97MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
98
df4f9bc4
DB		 99static bool noacpi;
100module_param(noacpi, bool, 0444);
101MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
102
1c63dc66
CH		 103struct nvme_dev;
104struct nvme_queue;
b3fffdef 105
a5cdb68c 106static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 107static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 108
1c63dc66
CH		 109/*
110 * Represents an NVM Express device. Each nvme_dev is a PCI function.
111 */
112struct nvme_dev {
147b27e4 113 struct nvme_queue *queues;
1c63dc66
CH		 114 struct blk_mq_tag_set tagset;
115 struct blk_mq_tag_set admin_tagset;
116 u32 __iomem *dbs;
117 struct device *dev;
118 struct dma_pool *prp_page_pool;
119 struct dma_pool *prp_small_pool;
1c63dc66
CH		 120 unsigned online_queues;
121 unsigned max_qid;
e20ba6e1 122 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 123 unsigned int num_vecs;
7442ddce 124 u32 q_depth;
c1e0cc7e 125 int io_sqes;
1c63dc66 126 u32 db_stride;
1c63dc66 127 void __iomem *bar;
97f6ef64 128 unsigned long bar_mapped_size;
5c8809e6 129 struct work_struct remove_work;
77bf25ea 130 struct mutex shutdown_lock;
1c63dc66 131 bool subsystem;
1c63dc66 132 u64 cmb_size;
0f238ff5 133 bool cmb_use_sqes;
1c63dc66 134 u32 cmbsz;
202021c1 135 u32 cmbloc;
1c63dc66 136 struct nvme_ctrl ctrl;
d916b1be 137 u32 last_ps;
87ad72a5 138
943e942e
JA		 139 mempool_t *iod_mempool;
140
87ad72a5 141 /* shadow doorbell buffer support: */
f9f38e33
HK		 142 u32 *dbbuf_dbs;
143 dma_addr_t dbbuf_dbs_dma_addr;
144 u32 *dbbuf_eis;
145 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 146
147 /* host memory buffer support: */
148 u64 host_mem_size;
149 u32 nr_host_mem_descs;
4033f35d 150 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 151 struct nvme_host_mem_buf_desc *host_mem_descs;
152 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 153 unsigned int nr_allocated_queues;
154 unsigned int nr_write_queues;
155 unsigned int nr_poll_queues;
4d115420 156};
1fa6aead 157
b27c1e68 158static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
159{
61f3b896 160 int ret;
7442ddce 161 u32 n;
b27c1e68 162
7442ddce 163 ret = kstrtou32(val, 10, &n);
b27c1e68 164 if (ret != 0 || n < 2)
165 return -EINVAL;
166
7442ddce 167 return param_set_uint(val, kp);
b27c1e68 168}
169
f9f38e33
HK		 170static inline unsigned int sq_idx(unsigned int qid, u32 stride)
171{
172 return qid * 2 * stride;
173}
174
175static inline unsigned int cq_idx(unsigned int qid, u32 stride)
176{
177 return (qid * 2 + 1) * stride;
178}
179
1c63dc66
CH		 180static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
181{
182 return container_of(ctrl, struct nvme_dev, ctrl);
183}
184
b60503ba
MW		 185/*
186 * An NVM Express queue. Each device has at least two (one for admin
187 * commands and one for I/O commands).
188 */
189struct nvme_queue {
091b6092 190 struct nvme_dev *dev;
1ab0cd69 191 spinlock_t sq_lock;
c1e0cc7e 192 void *sq_cmds;
3a7afd8e
CH		 193 /* only used for poll queues: */
194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 195 struct nvme_completion *cqes;
b60503ba
MW		 196 dma_addr_t sq_dma_addr;
197 dma_addr_t cq_dma_addr;
b60503ba 198 u32 __iomem *q_db;
7442ddce 199 u32 q_depth;
7c349dde 200 u16 cq_vector;
b60503ba 201 u16 sq_tail;
38210800 202 u16 last_sq_tail;
b60503ba 203 u16 cq_head;
c30341dc 204 u16 qid;
e9539f47 205 u8 cq_phase;
c1e0cc7e 206 u8 sqes;
4e224106
CH		 207 unsigned long flags;
208#define NVMEQ_ENABLED 0
63223078 209#define NVMEQ_SQ_CMB 1
d1ed6aa1 210#define NVMEQ_DELETE_ERROR 2
7c349dde 211#define NVMEQ_POLLED 3
f9f38e33
HK		 212 u32 *dbbuf_sq_db;
213 u32 *dbbuf_cq_db;
214 u32 *dbbuf_sq_ei;
215 u32 *dbbuf_cq_ei;
d1ed6aa1 216 struct completion delete_done;
b60503ba
MW		 217};
218
71bd150c 219/*
9b048119
CH		 220 * The nvme_iod describes the data in an I/O.
221 *
222 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
223 * to the actual struct scatterlist.
71bd150c
CH		 224 */
225struct nvme_iod {
d49187e9 226 struct nvme_request req;
af7fae85 227 struct nvme_command cmd;
f4800d6d 228 struct nvme_queue *nvmeq;
a7a7cbe3 229 bool use_sgl;
f4800d6d 230 int aborted;
71bd150c 231 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 232 int nents; /* Used in scatterlist */
71bd150c 233 dma_addr_t first_dma;
dff824b2 234 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 235 dma_addr_t meta_dma;
f4800d6d 236 struct scatterlist *sg;
b60503ba
MW		 237};
238
2a5bcfdd 239static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 240{
2a5bcfdd 241 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 242}
243
244static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
245{
2a5bcfdd 246 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 247
248 if (dev->dbbuf_dbs)
249 return 0;
250
251 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
252 &dev->dbbuf_dbs_dma_addr,
253 GFP_KERNEL);
254 if (!dev->dbbuf_dbs)
255 return -ENOMEM;
256 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
257 &dev->dbbuf_eis_dma_addr,
258 GFP_KERNEL);
259 if (!dev->dbbuf_eis) {
260 dma_free_coherent(dev->dev, mem_size,
261 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
262 dev->dbbuf_dbs = NULL;
263 return -ENOMEM;
264 }
265
266 return 0;
267}
268
269static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
270{
2a5bcfdd 271 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 272
273 if (dev->dbbuf_dbs) {
274 dma_free_coherent(dev->dev, mem_size,
275 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
276 dev->dbbuf_dbs = NULL;
277 }
278 if (dev->dbbuf_eis) {
279 dma_free_coherent(dev->dev, mem_size,
280 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
281 dev->dbbuf_eis = NULL;
282 }
283}
284
285static void nvme_dbbuf_init(struct nvme_dev *dev,
286 struct nvme_queue *nvmeq, int qid)
287{
288 if (!dev->dbbuf_dbs || !qid)
289 return;
290
291 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
292 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
293 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
294 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
295}
296
0f0d2c87
MI		 297static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
298{
299 if (!nvmeq->qid)
300 return;
301
302 nvmeq->dbbuf_sq_db = NULL;
303 nvmeq->dbbuf_cq_db = NULL;
304 nvmeq->dbbuf_sq_ei = NULL;
305 nvmeq->dbbuf_cq_ei = NULL;
306}
307
f9f38e33
HK		 308static void nvme_dbbuf_set(struct nvme_dev *dev)
309{
310 struct nvme_command c;
0f0d2c87 311 unsigned int i;
f9f38e33
HK		 312
313 if (!dev->dbbuf_dbs)
314 return;
315
316 memset(&c, 0, sizeof(c));
317 c.dbbuf.opcode = nvme_admin_dbbuf;
318 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
319 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
320
321 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 322 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 323 /* Free memory and continue on */
324 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 325
326 for (i = 1; i <= dev->online_queues; i++)
327 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 328 }
329}
330
331static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
332{
333 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
334}
335
336/* Update dbbuf and return true if an MMIO is required */
337static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
338 volatile u32 *dbbuf_ei)
339{
340 if (dbbuf_db) {
341 u16 old_value;
342
343 /*
344 * Ensure that the queue is written before updating
345 * the doorbell in memory
346 */
347 wmb();
348
349 old_value = *dbbuf_db;
350 *dbbuf_db = value;
351
f1ed3df2
MW		 352 /*
353 * Ensure that the doorbell is updated before reading the event
354 * index from memory. The controller needs to provide similar
355 * ordering to ensure the envent index is updated before reading
356 * the doorbell.
357 */
358 mb();
359
f9f38e33
HK		 360 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
361 return false;
362 }
363
364 return true;
b60503ba
MW		 365}
366
ac3dd5bd
JA		 367/*
368 * Will slightly overestimate the number of pages needed. This is OK
369 * as it only leads to a small amount of wasted memory for the lifetime of
370 * the I/O.
371 */
b13c6393 372static int nvme_pci_npages_prp(void)
ac3dd5bd 373{
b13c6393 374 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
6c3c05b0 375 NVME_CTRL_PAGE_SIZE);
ac3dd5bd
JA		 376 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
377}
378
a7a7cbe3
CK		 379/*
380 * Calculates the number of pages needed for the SGL segments. For example a 4k
381 * page can accommodate 256 SGL descriptors.
382 */
b13c6393 383static int nvme_pci_npages_sgl(void)
ac3dd5bd 384{
b13c6393
CK		 385 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
386 PAGE_SIZE);
f4800d6d 387}
ac3dd5bd 388
b13c6393 389static size_t nvme_pci_iod_alloc_size(void)
f4800d6d 390{
b13c6393 391 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
a7a7cbe3 392
b13c6393
CK		 393 return sizeof(__le64 *) * npages +
394 sizeof(struct scatterlist) * NVME_MAX_SEGS;
f4800d6d 395}
ac3dd5bd 396
a4aea562
MB		 397static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
398 unsigned int hctx_idx)
e85248e5 399{
a4aea562 400 struct nvme_dev *dev = data;
147b27e4 401 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 402
42483228
KB		 403 WARN_ON(hctx_idx != 0);
404 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 405
a4aea562
MB		 406 hctx->driver_data = nvmeq;
407 return 0;
e85248e5
MW		 408}
409
a4aea562
MB		 410static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
411 unsigned int hctx_idx)
b60503ba 412{
a4aea562 413 struct nvme_dev *dev = data;
147b27e4 414 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 415
42483228 416 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 417 hctx->driver_data = nvmeq;
418 return 0;
b60503ba
MW		 419}
420
d6296d39
CH		 421static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
422 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 423{
d6296d39 424 struct nvme_dev *dev = set->driver_data;
f4800d6d 425 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 426 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 427 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 428
429 BUG_ON(!nvmeq);
f4800d6d 430 iod->nvmeq = nvmeq;
59e29ce6
SG		 431
432 nvme_req(req)->ctrl = &dev->ctrl;
f4b9e6c9 433 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 434 return 0;
435}
436
3b6592f7
JA		 437static int queue_irq_offset(struct nvme_dev *dev)
438{
439 /* if we have more than 1 vec, admin queue offsets us by 1 */
440 if (dev->num_vecs > 1)
441 return 1;
442
443 return 0;
444}
445
dca51e78
CH		 446static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
447{
448 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 449 int i, qoff, offset;
450
451 offset = queue_irq_offset(dev);
452 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
453 struct blk_mq_queue_map *map = &set->map[i];
454
455 map->nr_queues = dev->io_queues[i];
456 if (!map->nr_queues) {
e20ba6e1 457 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 458 continue;
3b6592f7
JA		 459 }
460
4b04cc6a
JA		 461 /*
462 * The poll queue(s) doesn't have an IRQ (and hence IRQ
463 * affinity), so use the regular blk-mq cpu mapping
464 */
3b6592f7 465 map->queue_offset = qoff;
cb9e0e50 466 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 467 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
468 else
469 blk_mq_map_queues(map);
3b6592f7
JA		 470 qoff += map->nr_queues;
471 offset += map->nr_queues;
472 }
473
474 return 0;
dca51e78
CH		 475}
476
38210800
KB		 477/*
478 * Write sq tail if we are asked to, or if the next command would wrap.
479 */
480static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 481{
38210800
KB		 482 if (!write_sq) {
483 u16 next_tail = nvmeq->sq_tail + 1;
484
485 if (next_tail == nvmeq->q_depth)
486 next_tail = 0;
487 if (next_tail != nvmeq->last_sq_tail)
488 return;
489 }
490
04f3eafd
JA		 491 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
492 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
493 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 494 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 495}
496
b60503ba 497/**
90ea5ca4 498 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 499 * @nvmeq: The queue to use
500 * @cmd: The command to send
04f3eafd 501 * @write_sq: whether to write to the SQ doorbell
b60503ba 502 */
04f3eafd
JA		 503static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
504 bool write_sq)
b60503ba 505{
90ea5ca4 506 spin_lock(&nvmeq->sq_lock);
c1e0cc7e
BH		 507 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
508 cmd, sizeof(*cmd));
90ea5ca4
CH		 509 if (++nvmeq->sq_tail == nvmeq->q_depth)
510 nvmeq->sq_tail = 0;
38210800 511 nvme_write_sq_db(nvmeq, write_sq);
04f3eafd
JA		 512 spin_unlock(&nvmeq->sq_lock);
513}
514
515static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
516{
517 struct nvme_queue *nvmeq = hctx->driver_data;
518
519 spin_lock(&nvmeq->sq_lock);
38210800
KB		 520 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
521 nvme_write_sq_db(nvmeq, true);
90ea5ca4 522 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 523}
524
a7a7cbe3 525static void **nvme_pci_iod_list(struct request *req)
b60503ba 526{
f4800d6d 527 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 528 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 529}
530
955b1b5a
MI		 531static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
532{
533 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 534 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 535 unsigned int avg_seg_size;
536
20469a37 537 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 538
539 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
540 return false;
541 if (!iod->nvmeq->qid)
542 return false;
543 if (!sgl_threshold || avg_seg_size < sgl_threshold)
544 return false;
545 return true;
546}
547
9275c206 548static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 549{
6c3c05b0 550 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 551 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
552 dma_addr_t dma_addr = iod->first_dma;
eca18b23 553 int i;
eca18b23 554
9275c206
CH		 555 for (i = 0; i < iod->npages; i++) {
556 __le64 *prp_list = nvme_pci_iod_list(req)[i];
557 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
558
559 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
560 dma_addr = next_dma_addr;
7fe07d14
CH		 561 }
562
9275c206 563}
dff824b2 564
9275c206
CH		 565static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
566{
567 const int last_sg = SGES_PER_PAGE - 1;
568 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
569 dma_addr_t dma_addr = iod->first_dma;
570 int i;
dff824b2 571
9275c206
CH		 572 for (i = 0; i < iod->npages; i++) {
573 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
574 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
dff824b2 575
9275c206
CH		 576 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
577 dma_addr = next_dma_addr;
578 }
a7a7cbe3 579
9275c206 580}
a7a7cbe3 581
9275c206
CH		 582static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
583{
584 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 585
9275c206
CH		 586 if (is_pci_p2pdma_page(sg_page(iod->sg)))
587 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
588 rq_dma_dir(req));
589 else
590 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
591}
a7a7cbe3 592
9275c206
CH		 593static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
594{
595 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 596
9275c206
CH		 597 if (iod->dma_len) {
598 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
599 rq_dma_dir(req));
600 return;
eca18b23 601 }
ac3dd5bd 602
9275c206
CH		 603 WARN_ON_ONCE(!iod->nents);
604
605 nvme_unmap_sg(dev, req);
606 if (iod->npages == 0)
607 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
608 iod->first_dma);
609 else if (iod->use_sgl)
610 nvme_free_sgls(dev, req);
611 else
612 nvme_free_prps(dev, req);
d43f1ccf 613 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 614}
615
d0877473
KB		 616static void nvme_print_sgl(struct scatterlist *sgl, int nents)
617{
618 int i;
619 struct scatterlist *sg;
620
621 for_each_sg(sgl, sg, nents, i) {
622 dma_addr_t phys = sg_phys(sg);
623 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
624 "dma_address:%pad dma_length:%d\n",
625 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
626 sg_dma_len(sg));
627 }
628}
629
a7a7cbe3
CK		 630static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
631 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 632{
f4800d6d 633 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 634 struct dma_pool *pool;
b131c61d 635 int length = blk_rq_payload_bytes(req);
eca18b23 636 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 637 int dma_len = sg_dma_len(sg);
638 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 639 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 640 __le64 *prp_list;
a7a7cbe3 641 void **list = nvme_pci_iod_list(req);
e025344c 642 dma_addr_t prp_dma;
eca18b23 643 int nprps, i;
ff22b54f 644
6c3c05b0 645 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 646 if (length <= 0) {
647 iod->first_dma = 0;
a7a7cbe3 648 goto done;
5228b328 649 }
ff22b54f 650
6c3c05b0 651 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 652 if (dma_len) {
6c3c05b0 653 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 654 } else {
655 sg = sg_next(sg);
656 dma_addr = sg_dma_address(sg);
657 dma_len = sg_dma_len(sg);
658 }
659
6c3c05b0 660 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 661 iod->first_dma = dma_addr;
a7a7cbe3 662 goto done;
e025344c
SMM		 663 }
664
6c3c05b0 665 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 666 if (nprps <= (256 / 8)) {
667 pool = dev->prp_small_pool;
eca18b23 668 iod->npages = 0;
99802a7a
MW		 669 } else {
670 pool = dev->prp_page_pool;
eca18b23 671 iod->npages = 1;
99802a7a
MW		 672 }
673
69d2b571 674 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 675 if (!prp_list) {
edd10d33 676 iod->first_dma = dma_addr;
eca18b23 677 iod->npages = -1;
86eea289 678 return BLK_STS_RESOURCE;
b77954cb 679 }
eca18b23
MW		 680 list[0] = prp_list;
681 iod->first_dma = prp_dma;
e025344c
SMM		 682 i = 0;
683 for (;;) {
6c3c05b0 684 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 685 __le64 *old_prp_list = prp_list;
69d2b571 686 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 687 if (!prp_list)
fa073216 688 goto free_prps;
eca18b23 689 list[iod->npages++] = prp_list;
7523d834
MW		 690 prp_list[0] = old_prp_list[i - 1];
691 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
692 i = 1;
e025344c
SMM		 693 }
694 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 695 dma_len -= NVME_CTRL_PAGE_SIZE;
696 dma_addr += NVME_CTRL_PAGE_SIZE;
697 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 698 if (length <= 0)
699 break;
700 if (dma_len > 0)
701 continue;
86eea289
KB		 702 if (unlikely(dma_len < 0))
703 goto bad_sgl;
e025344c
SMM		 704 sg = sg_next(sg);
705 dma_addr = sg_dma_address(sg);
706 dma_len = sg_dma_len(sg);
ff22b54f 707 }
a7a7cbe3
CK		 708done:
709 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
710 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 711 return BLK_STS_OK;
fa073216
CH		 712free_prps:
713 nvme_free_prps(dev, req);
714 return BLK_STS_RESOURCE;
715bad_sgl:
d0877473
KB		 716 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
717 "Invalid SGL for payload:%d nents:%d\n",
718 blk_rq_payload_bytes(req), iod->nents);
86eea289 719 return BLK_STS_IOERR;
ff22b54f
MW		 720}
721
a7a7cbe3
CK		 722static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
723 struct scatterlist *sg)
724{
725 sge->addr = cpu_to_le64(sg_dma_address(sg));
726 sge->length = cpu_to_le32(sg_dma_len(sg));
727 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
728}
729
730static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
731 dma_addr_t dma_addr, int entries)
732{
733 sge->addr = cpu_to_le64(dma_addr);
734 if (entries < SGES_PER_PAGE) {
735 sge->length = cpu_to_le32(entries * sizeof(*sge));
736 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
737 } else {
738 sge->length = cpu_to_le32(PAGE_SIZE);
739 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
740 }
741}
742
743static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 744 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 745{
746 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 747 struct dma_pool *pool;
748 struct nvme_sgl_desc *sg_list;
749 struct scatterlist *sg = iod->sg;
a7a7cbe3 750 dma_addr_t sgl_dma;
b0f2853b 751 int i = 0;
a7a7cbe3 752
a7a7cbe3
CK		 753 /* setting the transfer type as SGL */
754 cmd->flags = NVME_CMD_SGL_METABUF;
755
b0f2853b 756 if (entries == 1) {
a7a7cbe3
CK		 757 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
758 return BLK_STS_OK;
759 }
760
761 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
762 pool = dev->prp_small_pool;
763 iod->npages = 0;
764 } else {
765 pool = dev->prp_page_pool;
766 iod->npages = 1;
767 }
768
769 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
770 if (!sg_list) {
771 iod->npages = -1;
772 return BLK_STS_RESOURCE;
773 }
774
775 nvme_pci_iod_list(req)[0] = sg_list;
776 iod->first_dma = sgl_dma;
777
778 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
779
780 do {
781 if (i == SGES_PER_PAGE) {
782 struct nvme_sgl_desc *old_sg_desc = sg_list;
783 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
784
785 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
786 if (!sg_list)
fa073216 787 goto free_sgls;
a7a7cbe3
CK		 788
789 i = 0;
790 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
791 sg_list[i++] = *link;
792 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
793 }
794
795 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 796 sg = sg_next(sg);
b0f2853b 797 } while (--entries > 0);
a7a7cbe3 798
a7a7cbe3 799 return BLK_STS_OK;
fa073216
CH		 800free_sgls:
801 nvme_free_sgls(dev, req);
802 return BLK_STS_RESOURCE;
a7a7cbe3
CK		 803}
804
dff824b2
CH		 805static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
806 struct request *req, struct nvme_rw_command *cmnd,
807 struct bio_vec *bv)
808{
809 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 810 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
811 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 812
813 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
814 if (dma_mapping_error(dev->dev, iod->first_dma))
815 return BLK_STS_RESOURCE;
816 iod->dma_len = bv->bv_len;
817
818 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
819 if (bv->bv_len > first_prp_len)
820 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
359c1f88 821 return BLK_STS_OK;
dff824b2
CH		 822}
823
29791057
CH		 824static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
825 struct request *req, struct nvme_rw_command *cmnd,
826 struct bio_vec *bv)
827{
828 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
829
830 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
831 if (dma_mapping_error(dev->dev, iod->first_dma))
832 return BLK_STS_RESOURCE;
833 iod->dma_len = bv->bv_len;
834
049bf372 835 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 836 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
837 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
838 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 839 return BLK_STS_OK;
29791057
CH		 840}
841
fc17b653 842static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 843 struct nvme_command *cmnd)
d29ec824 844{
f4800d6d 845 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 846 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 847 int nr_mapped;
d29ec824 848
dff824b2
CH		 849 if (blk_rq_nr_phys_segments(req) == 1) {
850 struct bio_vec bv = req_bvec(req);
851
852 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 853 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 854 return nvme_setup_prp_simple(dev, req,
855 &cmnd->rw, &bv);
29791057
CH		 856
857 if (iod->nvmeq->qid &&
858 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
859 return nvme_setup_sgl_simple(dev, req,
860 &cmnd->rw, &bv);
dff824b2
CH		 861 }
862 }
863
864 iod->dma_len = 0;
d43f1ccf
CH		 865 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
866 if (!iod->sg)
867 return BLK_STS_RESOURCE;
f9d03f96 868 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 869 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e 870 if (!iod->nents)
fa073216 871 goto out_free_sg;
d29ec824 872
e0596ab2 873 if (is_pci_p2pdma_page(sg_page(iod->sg)))
2b9f4bb2
LG		 874 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
875 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
e0596ab2
LG		 876 else
877 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 878 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 879 if (!nr_mapped)
fa073216 880 goto out_free_sg;
d29ec824 881
70479b71 882 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 883 if (iod->use_sgl)
b0f2853b 884 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 885 else
886 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 887 if (ret != BLK_STS_OK)
fa073216
CH		 888 goto out_unmap_sg;
889 return BLK_STS_OK;
890
891out_unmap_sg:
892 nvme_unmap_sg(dev, req);
893out_free_sg:
894 mempool_free(iod->sg, dev->iod_mempool);
4aedb705
CH		 895 return ret;
896}
3045c0d0 897
4aedb705
CH		 898static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
899 struct nvme_command *cmnd)
900{
901 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 902
4aedb705
CH		 903 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
904 rq_dma_dir(req), 0);
905 if (dma_mapping_error(dev->dev, iod->meta_dma))
906 return BLK_STS_IOERR;
907 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 908 return BLK_STS_OK;
00df5cb4
MW		 909}
910
d29ec824
CH		 911/*
912 * NOTE: ns is NULL when called on the admin queue.
913 */
fc17b653 914static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 915 const struct blk_mq_queue_data *bd)
edd10d33 916{
a4aea562
MB		 917 struct nvme_ns *ns = hctx->queue->queuedata;
918 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 919 struct nvme_dev *dev = nvmeq->dev;
a4aea562 920 struct request *req = bd->rq;
9b048119 921 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
af7fae85 922 struct nvme_command *cmnd = &iod->cmd;
ebe6d874 923 blk_status_t ret;
e1e5e564 924
9b048119
CH		 925 iod->aborted = 0;
926 iod->npages = -1;
927 iod->nents = 0;
928
d1f06f4a
JA		 929 /*
930 * We should not need to do this, but we're still using this to
931 * ensure we can drain requests on a dying queue.
932 */
4e224106 933 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 934 return BLK_STS_IOERR;
935
f4b9e6c9 936 ret = nvme_setup_cmd(ns, req);
fc17b653 937 if (ret)
f4800d6d 938 return ret;
a4aea562 939
fc17b653 940 if (blk_rq_nr_phys_segments(req)) {
af7fae85 941 ret = nvme_map_data(dev, req, cmnd);
fc17b653 942 if (ret)
9b048119 943 goto out_free_cmd;
fc17b653 944 }
a4aea562 945
4aedb705 946 if (blk_integrity_rq(req)) {
af7fae85 947 ret = nvme_map_metadata(dev, req, cmnd);
4aedb705
CH		 948 if (ret)
949 goto out_unmap_data;
950 }
951
aae239e1 952 blk_mq_start_request(req);
af7fae85 953 nvme_submit_cmd(nvmeq, cmnd, bd->last);
fc17b653 954 return BLK_STS_OK;
4aedb705
CH		 955out_unmap_data:
956 nvme_unmap_data(dev, req);
f9d03f96
CH		 957out_free_cmd:
958 nvme_cleanup_cmd(req);
ba1ca37e 959 return ret;
b60503ba 960}
e1e5e564 961
77f02a7a 962static void nvme_pci_complete_rq(struct request *req)
eee417b0 963{
f4800d6d 964 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 965 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 966
4aedb705
CH		 967 if (blk_integrity_rq(req))
968 dma_unmap_page(dev->dev, iod->meta_dma,
969 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 970 if (blk_rq_nr_phys_segments(req))
4aedb705 971 nvme_unmap_data(dev, req);
77f02a7a 972 nvme_complete_rq(req);
b60503ba
MW		 973}
974
d783e0bd 975/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 976static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 977{
74943d45
KB		 978 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
979
980 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 981}
982
eb281c82 983static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 984{
eb281c82 985 u16 head = nvmeq->cq_head;
adf68f21 986
397c699f
KB		 987 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
988 nvmeq->dbbuf_cq_ei))
989 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 990}
aae239e1 991
cfa27356
CH		 992static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
993{
994 if (!nvmeq->qid)
995 return nvmeq->dev->admin_tagset.tags[0];
996 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
997}
998
5cb525c8 999static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 1000{
74943d45 1001 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1002 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1003 struct request *req;
adf68f21 1004
83a12fb7
SG		 1005 /*
1006 * AEN requests are special as they don't time out and can
1007 * survive any kind of queue freeze and often don't respond to
1008 * aborts. We don't even bother to allocate a struct request
1009 * for them but rather special case them here.
1010 */
62df8016 1011 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1012 nvme_complete_async_event(&nvmeq->dev->ctrl,
1013 cqe->status, &cqe->result);
a0fa9647 1014 return;
83a12fb7 1015 }
b60503ba 1016
62df8016 1017 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1018 if (unlikely(!req)) {
1019 dev_warn(nvmeq->dev->ctrl.device,
1020 "invalid id %d completed on queue %d\n",
62df8016 1021 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1022 return;
1023 }
1024
604c01d5 1025 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
2eb81a33 1026 if (!nvme_try_complete_req(req, cqe->status, cqe->result))
ff029451 1027 nvme_pci_complete_rq(req);
83a12fb7 1028}
b60503ba 1029
5cb525c8
JA		 1030static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1031{
a8de6639
AD		 1032 u16 tmp = nvmeq->cq_head + 1;
1033
1034 if (tmp == nvmeq->q_depth) {
5cb525c8 1035 nvmeq->cq_head = 0;
e2a366a4 1036 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1037 } else {
1038 nvmeq->cq_head = tmp;
b60503ba 1039 }
a0fa9647
JA		 1040}
1041
324b494c 1042static inline int nvme_process_cq(struct nvme_queue *nvmeq)
a0fa9647 1043{
1052b8ac 1044 int found = 0;
b60503ba 1045
1052b8ac 1046 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1047 found++;
b69e2ef2
KB		 1048 /*
1049 * load-load control dependency between phase and the rest of
1050 * the cqe requires a full read memory barrier
1051 */
1052 dma_rmb();
324b494c 1053 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
5cb525c8 1054 nvme_update_cq_head(nvmeq);
920d13a8 1055 }
eb281c82 1056
324b494c 1057 if (found)
920d13a8 1058 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1059 return found;
b60503ba
MW		 1060}
1061
1062static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1063{
58ffacb5 1064 struct nvme_queue *nvmeq = data;
5cb525c8 1065
324b494c 1066 if (nvme_process_cq(nvmeq))
05fae499
CK		 1067 return IRQ_HANDLED;
1068 return IRQ_NONE;
58ffacb5
MW		 1069}
1070
1071static irqreturn_t nvme_irq_check(int irq, void *data)
1072{
1073 struct nvme_queue *nvmeq = data;
4e523547 1074
750dde44 1075 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1076 return IRQ_WAKE_THREAD;
1077 return IRQ_NONE;
58ffacb5
MW		 1078}
1079
0b2a8a9f 1080/*
fa059b85 1081 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1082 * Can be called from any context.
1083 */
fa059b85 1084static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1085{
3a7afd8e 1086 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1087
fa059b85 1088 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1089
fa059b85
KB		 1090 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1091 nvme_process_cq(nvmeq);
1092 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1093}
1094
9743139c 1095static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1096{
1097 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1098 bool found;
1099
1100 if (!nvme_cqe_pending(nvmeq))
1101 return 0;
1102
3a7afd8e 1103 spin_lock(&nvmeq->cq_poll_lock);
324b494c 1104 found = nvme_process_cq(nvmeq);
3a7afd8e 1105 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1106
dabcefab
JA		 1107 return found;
1108}
1109
ad22c355 1110static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1111{
f866fc42 1112 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1113 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1114 struct nvme_command c;
b60503ba 1115
a4aea562
MB		 1116 memset(&c, 0, sizeof(c));
1117 c.common.opcode = nvme_admin_async_event;
ad22c355 1118 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1119 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1120}
1121
b60503ba 1122static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1123{
b60503ba
MW		 1124 struct nvme_command c;
1125
1126 memset(&c, 0, sizeof(c));
1127 c.delete_queue.opcode = opcode;
1128 c.delete_queue.qid = cpu_to_le16(id);
1129
1c63dc66 1130 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1131}
1132
b60503ba 1133static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1134 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1135{
b60503ba 1136 struct nvme_command c;
4b04cc6a
JA		 1137 int flags = NVME_QUEUE_PHYS_CONTIG;
1138
7c349dde 1139 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1140 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1141
d29ec824 1142 /*
16772ae6 1143 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1144 * is attached to the request.
1145 */
b60503ba
MW		 1146 memset(&c, 0, sizeof(c));
1147 c.create_cq.opcode = nvme_admin_create_cq;
1148 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1149 c.create_cq.cqid = cpu_to_le16(qid);
1150 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1151 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1152 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1153
1c63dc66 1154 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1155}
1156
1157static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1158 struct nvme_queue *nvmeq)
1159{
9abd68ef 1160 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1161 struct nvme_command c;
81c1cd98 1162 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1163
9abd68ef
JA		 1164 /*
1165 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1166 * set. Since URGENT priority is zeroes, it makes all queues
1167 * URGENT.
1168 */
1169 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1170 flags |= NVME_SQ_PRIO_MEDIUM;
1171
d29ec824 1172 /*
16772ae6 1173 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1174 * is attached to the request.
1175 */
b60503ba
MW		 1176 memset(&c, 0, sizeof(c));
1177 c.create_sq.opcode = nvme_admin_create_sq;
1178 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1179 c.create_sq.sqid = cpu_to_le16(qid);
1180 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1181 c.create_sq.sq_flags = cpu_to_le16(flags);
1182 c.create_sq.cqid = cpu_to_le16(qid);
1183
1c63dc66 1184 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1185}
1186
1187static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1188{
1189 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1190}
1191
1192static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1193{
1194 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1195}
1196
2a842aca 1197static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1198{
f4800d6d
CH		 1199 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1200 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1201
27fa9bc5
CH		 1202 dev_warn(nvmeq->dev->ctrl.device,
1203 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1204 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1205 blk_mq_free_request(req);
bc5fc7e4
MW		 1206}
1207
b2a0eb1a
KB		 1208static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1209{
b2a0eb1a
KB		 1210 /* If true, indicates loss of adapter communication, possibly by a
1211 * NVMe Subsystem reset.
1212 */
1213 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1214
ad70062c
JW		 1215 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1216 switch (dev->ctrl.state) {
1217 case NVME_CTRL_RESETTING:
ad6a0a52 1218 case NVME_CTRL_CONNECTING:
b2a0eb1a 1219 return false;
ad70062c
JW		 1220 default:
1221 break;
1222 }
b2a0eb1a
KB		 1223
1224 /* We shouldn't reset unless the controller is on fatal error state
1225 * _or_ if we lost the communication with it.
1226 */
1227 if (!(csts & NVME_CSTS_CFS) && !nssro)
1228 return false;
1229
b2a0eb1a
KB		 1230 return true;
1231}
1232
1233static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1234{
1235 /* Read a config register to help see what died. */
1236 u16 pci_status;
1237 int result;
1238
1239 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1240 &pci_status);
1241 if (result == PCIBIOS_SUCCESSFUL)
1242 dev_warn(dev->ctrl.device,
1243 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1244 csts, pci_status);
1245 else
1246 dev_warn(dev->ctrl.device,
1247 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1248 csts, result);
1249}
1250
31c7c7d2 1251static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1252{
f4800d6d
CH		 1253 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1254 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1255 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1256 struct request *abort_req;
a4aea562 1257 struct nvme_command cmd;
b2a0eb1a
KB		 1258 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1259
651438bb
WX		 1260 /* If PCI error recovery process is happening, we cannot reset or
1261 * the recovery mechanism will surely fail.
1262 */
1263 mb();
1264 if (pci_channel_offline(to_pci_dev(dev->dev)))
1265 return BLK_EH_RESET_TIMER;
1266
b2a0eb1a
KB		 1267 /*
1268 * Reset immediately if the controller is failed
1269 */
1270 if (nvme_should_reset(dev, csts)) {
1271 nvme_warn_reset(dev, csts);
1272 nvme_dev_disable(dev, false);
d86c4d8e 1273 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1274 return BLK_EH_DONE;
b2a0eb1a 1275 }
c30341dc 1276
7776db1c
KB		 1277 /*
1278 * Did we miss an interrupt?
1279 */
fa059b85
KB		 1280 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1281 nvme_poll(req->mq_hctx);
1282 else
1283 nvme_poll_irqdisable(nvmeq);
1284
bf392a5d 1285 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1286 dev_warn(dev->ctrl.device,
1287 "I/O %d QID %d timeout, completion polled\n",
1288 req->tag, nvmeq->qid);
db8c48e4 1289 return BLK_EH_DONE;
7776db1c
KB		 1290 }
1291
31c7c7d2 1292 /*
fd634f41
CH		 1293 * Shutdown immediately if controller times out while starting. The
1294 * reset work will see the pci device disabled when it gets the forced
1295 * cancellation error. All outstanding requests are completed on
db8c48e4 1296 * shutdown, so we return BLK_EH_DONE.
fd634f41 1297 */
4244140d
KB		 1298 switch (dev->ctrl.state) {
1299 case NVME_CTRL_CONNECTING:
2036f726 1300 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1301 fallthrough;
2036f726 1302 case NVME_CTRL_DELETING:
b9cac43c 1303 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1304 "I/O %d QID %d timeout, disable controller\n",
1305 req->tag, nvmeq->qid);
27fa9bc5 1306 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1307 nvme_dev_disable(dev, true);
db8c48e4 1308 return BLK_EH_DONE;
39a9dd81
KB		 1309 case NVME_CTRL_RESETTING:
1310 return BLK_EH_RESET_TIMER;
4244140d
KB		 1311 default:
1312 break;
c30341dc
KB		 1313 }
1314
fd634f41 1315 /*
ee0d96d3
BW		 1316 * Shutdown the controller immediately and schedule a reset if the
1317 * command was already aborted once before and still hasn't been
1318 * returned to the driver, or if this is the admin queue.
31c7c7d2 1319 */
f4800d6d 1320 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1321 dev_warn(dev->ctrl.device,
e1569a16
KB		 1322 "I/O %d QID %d timeout, reset controller\n",
1323 req->tag, nvmeq->qid);
7ad92f65 1324 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1325 nvme_dev_disable(dev, false);
d86c4d8e 1326 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1327
db8c48e4 1328 return BLK_EH_DONE;
c30341dc 1329 }
c30341dc 1330
e7a2a87d 1331 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1332 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1333 return BLK_EH_RESET_TIMER;
6bf25d16 1334 }
7bf7d778 1335 iod->aborted = 1;
a4aea562 1336
c30341dc
KB		 1337 memset(&cmd, 0, sizeof(cmd));
1338 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1339 cmd.abort.cid = req->tag;
c30341dc 1340 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1341
1b3c47c1
SG		 1342 dev_warn(nvmeq->dev->ctrl.device,
1343 "I/O %d QID %d timeout, aborting\n",
1344 req->tag, nvmeq->qid);
e7a2a87d
CH		 1345
1346 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
39dfe844 1347 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1348 if (IS_ERR(abort_req)) {
1349 atomic_inc(&dev->ctrl.abort_limit);
1350 return BLK_EH_RESET_TIMER;
1351 }
1352
e7a2a87d 1353 abort_req->end_io_data = NULL;
8eeed0b5 1354 blk_execute_rq_nowait(NULL, abort_req, 0, abort_endio);
c30341dc 1355
31c7c7d2
CH		 1356 /*
1357 * The aborted req will be completed on receiving the abort req.
1358 * We enable the timer again. If hit twice, it'll cause a device reset,
1359 * as the device then is in a faulty state.
1360 */
1361 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1362}
1363
a4aea562
MB		 1364static void nvme_free_queue(struct nvme_queue *nvmeq)
1365{
8a1d09a6 1366 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1367 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1368 if (!nvmeq->sq_cmds)
1369 return;
0f238ff5 1370
63223078 1371 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1372 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1373 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1374 } else {
8a1d09a6 1375 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1376 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1377 }
9e866774
MW		 1378}
1379
a1a5ef99 1380static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1381{
1382 int i;
1383
d858e5f0 1384 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1385 dev->ctrl.queue_count--;
147b27e4 1386 nvme_free_queue(&dev->queues[i]);
121c7ad4 1387 }
22404274
KB		 1388}
1389
4d115420
KB		 1390/**
1391 * nvme_suspend_queue - put queue into suspended state
40581d1a 1392 * @nvmeq: queue to suspend
4d115420
KB		 1393 */
1394static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1395{
4e224106 1396 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1397 return 1;
a09115b2 1398
4e224106 1399 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1400 mb();
a09115b2 1401
4e224106 1402 nvmeq->dev->online_queues--;
1c63dc66 1403 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1404 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1405 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1406 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1407 return 0;
1408}
b60503ba 1409
8fae268b
KB		 1410static void nvme_suspend_io_queues(struct nvme_dev *dev)
1411{
1412 int i;
1413
1414 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1415 nvme_suspend_queue(&dev->queues[i]);
1416}
1417
a5cdb68c 1418static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1419{
147b27e4 1420 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1421
a5cdb68c
KB		 1422 if (shutdown)
1423 nvme_shutdown_ctrl(&dev->ctrl);
1424 else
b5b05048 1425 nvme_disable_ctrl(&dev->ctrl);
07836e65 1426
bf392a5d 1427 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1428}
1429
fa46c6fb
KB		 1430/*
1431 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1432 * that can check this device's completion queues have synced, except
1433 * nvme_poll(). This is the last chance for the driver to see a natural
1434 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1435 */
1436static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1437{
fa46c6fb
KB		 1438 int i;
1439
9210c075
DZ		 1440 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1441 spin_lock(&dev->queues[i].cq_poll_lock);
324b494c 1442 nvme_process_cq(&dev->queues[i]);
9210c075
DZ		 1443 spin_unlock(&dev->queues[i].cq_poll_lock);
1444 }
fa46c6fb
KB		 1445}
1446
8ffaadf7
JD		 1447static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1448 int entry_size)
1449{
1450 int q_depth = dev->q_depth;
5fd4ce1b 1451 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1452 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1453
1454 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1455 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1456
6c3c05b0 1457 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1458 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1459
1460 /*
1461 * Ensure the reduced q_depth is above some threshold where it
1462 * would be better to map queues in system memory with the
1463 * original depth
1464 */
1465 if (q_depth < 64)
1466 return -ENOMEM;
1467 }
1468
1469 return q_depth;
1470}
1471
1472static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1473 int qid)
8ffaadf7 1474{
0f238ff5
LG		 1475 struct pci_dev *pdev = to_pci_dev(dev->dev);
1476
1477 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1478 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1479 if (nvmeq->sq_cmds) {
1480 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1481 nvmeq->sq_cmds);
1482 if (nvmeq->sq_dma_addr) {
1483 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1484 return 0;
1485 }
1486
8a1d09a6 1487 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1488 }
0f238ff5 1489 }
8ffaadf7 1490
8a1d09a6 1491 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1492 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1493 if (!nvmeq->sq_cmds)
1494 return -ENOMEM;
8ffaadf7
JD		 1495 return 0;
1496}
1497
a6ff7262 1498static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1499{
147b27e4 1500 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1501
62314e40
KB		 1502 if (dev->ctrl.queue_count > qid)
1503 return 0;
b60503ba 1504
c1e0cc7e 1505 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1506 nvmeq->q_depth = depth;
1507 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1508 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1509 if (!nvmeq->cqes)
1510 goto free_nvmeq;
b60503ba 1511
8a1d09a6 1512 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1513 goto free_cqdma;
1514
091b6092 1515 nvmeq->dev = dev;
1ab0cd69 1516 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1517 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1518 nvmeq->cq_head = 0;
82123460 1519 nvmeq->cq_phase = 1;
b80d5ccc 1520 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1521 nvmeq->qid = qid;
d858e5f0 1522 dev->ctrl.queue_count++;
36a7e993 1523
147b27e4 1524 return 0;
b60503ba
MW		 1525
1526 free_cqdma:
8a1d09a6
BH		 1527 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1528 nvmeq->cq_dma_addr);
b60503ba 1529 free_nvmeq:
147b27e4 1530 return -ENOMEM;
b60503ba
MW		 1531}
1532
dca51e78 1533static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1534{
0ff199cb
CH		 1535 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1536 int nr = nvmeq->dev->ctrl.instance;
1537
1538 if (use_threaded_interrupts) {
1539 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1540 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1541 } else {
1542 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1543 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1544 }
3001082c
MW		 1545}
1546
22404274 1547static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1548{
22404274 1549 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1550
22404274 1551 nvmeq->sq_tail = 0;
38210800 1552 nvmeq->last_sq_tail = 0;
22404274
KB		 1553 nvmeq->cq_head = 0;
1554 nvmeq->cq_phase = 1;
b80d5ccc 1555 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1556 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1557 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1558 dev->online_queues++;
3a7afd8e 1559 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1560}
1561
4b04cc6a 1562static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1563{
1564 struct nvme_dev *dev = nvmeq->dev;
1565 int result;
7c349dde 1566 u16 vector = 0;
3f85d50b 1567
d1ed6aa1
CH		 1568 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1569
22b55601
KB		 1570 /*
1571 * A queue's vector matches the queue identifier unless the controller
1572 * has only one vector available.
1573 */
4b04cc6a
JA		 1574 if (!polled)
1575 vector = dev->num_vecs == 1 ? 0 : qid;
1576 else
7c349dde 1577 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1578
a8e3e0bb 1579 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1580 if (result)
1581 return result;
b60503ba
MW		 1582
1583 result = adapter_alloc_sq(dev, qid, nvmeq);
1584 if (result < 0)
ded45505 1585 return result;
c80b36cd 1586 if (result)
b60503ba
MW		 1587 goto release_cq;
1588
a8e3e0bb 1589 nvmeq->cq_vector = vector;
161b8be2 1590 nvme_init_queue(nvmeq, qid);
4b04cc6a 1591
7c349dde 1592 if (!polled) {
4b04cc6a
JA		 1593 result = queue_request_irq(nvmeq);
1594 if (result < 0)
1595 goto release_sq;
1596 }
b60503ba 1597
4e224106 1598 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1599 return result;
b60503ba 1600
a8e3e0bb 1601release_sq:
f25a2dfc 1602 dev->online_queues--;
b60503ba 1603 adapter_delete_sq(dev, qid);
a8e3e0bb 1604release_cq:
b60503ba 1605 adapter_delete_cq(dev, qid);
22404274 1606 return result;
b60503ba
MW		 1607}
1608
f363b089 1609static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1610 .queue_rq = nvme_queue_rq,
77f02a7a 1611 .complete = nvme_pci_complete_rq,
a4aea562 1612 .init_hctx = nvme_admin_init_hctx,
0350815a 1613 .init_request = nvme_init_request,
a4aea562
MB		 1614 .timeout = nvme_timeout,
1615};
1616
f363b089 1617static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1618 .queue_rq = nvme_queue_rq,
1619 .complete = nvme_pci_complete_rq,
1620 .commit_rqs = nvme_commit_rqs,
1621 .init_hctx = nvme_init_hctx,
1622 .init_request = nvme_init_request,
1623 .map_queues = nvme_pci_map_queues,
1624 .timeout = nvme_timeout,
1625 .poll = nvme_poll,
dabcefab
JA		 1626};
1627
ea191d2f
KB		 1628static void nvme_dev_remove_admin(struct nvme_dev *dev)
1629{
1c63dc66 1630 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1631 /*
1632 * If the controller was reset during removal, it's possible
1633 * user requests may be waiting on a stopped queue. Start the
1634 * queue to flush these to completion.
1635 */
c81545f9 1636 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1637 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1638 blk_mq_free_tag_set(&dev->admin_tagset);
1639 }
1640}
1641
a4aea562
MB		 1642static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1643{
1c63dc66 1644 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1645 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1646 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1647
38dabe21 1648 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
dc96f938 1649 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
d4ec47f1 1650 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
d43f1ccf 1651 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1652 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1653 dev->admin_tagset.driver_data = dev;
1654
1655 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1656 return -ENOMEM;
34b6c231 1657 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1658
1c63dc66
CH		 1659 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1660 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1661 blk_mq_free_tag_set(&dev->admin_tagset);
1662 return -ENOMEM;
1663 }
1c63dc66 1664 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1665 nvme_dev_remove_admin(dev);
1c63dc66 1666 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1667 return -ENODEV;
1668 }
0fb59cbc 1669 } else
c81545f9 1670 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1671
1672 return 0;
1673}
1674
97f6ef64
XY		 1675static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1676{
1677 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1678}
1679
1680static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1681{
1682 struct pci_dev *pdev = to_pci_dev(dev->dev);
1683
1684 if (size <= dev->bar_mapped_size)
1685 return 0;
1686 if (size > pci_resource_len(pdev, 0))
1687 return -ENOMEM;
1688 if (dev->bar)
1689 iounmap(dev->bar);
1690 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1691 if (!dev->bar) {
1692 dev->bar_mapped_size = 0;
1693 return -ENOMEM;
1694 }
1695 dev->bar_mapped_size = size;
1696 dev->dbs = dev->bar + NVME_REG_DBS;
1697
1698 return 0;
1699}
1700
01ad0990 1701static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1702{
ba47e386 1703 int result;
b60503ba
MW		 1704 u32 aqa;
1705 struct nvme_queue *nvmeq;
1706
97f6ef64
XY		 1707 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1708 if (result < 0)
1709 return result;
1710
8ef2074d 1711 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1712 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1713
7a67cbea
CH		 1714 if (dev->subsystem &&
1715 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1716 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1717
b5b05048 1718 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1719 if (result < 0)
1720 return result;
b60503ba 1721
a6ff7262 1722 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1723 if (result)
1724 return result;
b60503ba 1725
635333e4
MG		 1726 dev->ctrl.numa_node = dev_to_node(dev->dev);
1727
147b27e4 1728 nvmeq = &dev->queues[0];
b60503ba
MW		 1729 aqa = nvmeq->q_depth - 1;
1730 aqa |= aqa << 16;
1731
7a67cbea
CH		 1732 writel(aqa, dev->bar + NVME_REG_AQA);
1733 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1734 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1735
c0f2f45b 1736 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1737 if (result)
d4875622 1738 return result;
a4aea562 1739
2b25d981 1740 nvmeq->cq_vector = 0;
161b8be2 1741 nvme_init_queue(nvmeq, 0);
dca51e78 1742 result = queue_request_irq(nvmeq);
758dd7fd 1743 if (result) {
7c349dde 1744 dev->online_queues--;
d4875622 1745 return result;
758dd7fd 1746 }
025c557a 1747
4e224106 1748 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1749 return result;
1750}
1751
749941f2 1752static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1753{
4b04cc6a 1754 unsigned i, max, rw_queues;
749941f2 1755 int ret = 0;
42f61420 1756
d858e5f0 1757 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1758 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1759 ret = -ENOMEM;
42f61420 1760 break;
749941f2
CH		 1761 }
1762 }
42f61420 1763
d858e5f0 1764 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1765 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1766 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1767 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1768 } else {
1769 rw_queues = max;
1770 }
1771
949928c1 1772 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1773 bool polled = i > rw_queues;
1774
1775 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1776 if (ret)
42f61420 1777 break;
27e8166c 1778 }
749941f2
CH		 1779
1780 /*
1781 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1782 * than the desired amount of queues, and even a controller without
1783 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1784 * be useful to upgrade a buggy firmware for example.
1785 */
1786 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1787}
1788
202021c1
SB		 1789static ssize_t nvme_cmb_show(struct device *dev,
1790 struct device_attribute *attr,
1791 char *buf)
1792{
1793 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1794
c965809c 1795 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1796 ndev->cmbloc, ndev->cmbsz);
1797}
1798static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1799
88de4598 1800static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1801{
88de4598
CH		 1802 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1803
1804 return 1ULL << (12 + 4 * szu);
1805}
1806
1807static u32 nvme_cmb_size(struct nvme_dev *dev)
1808{
1809 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1810}
1811
f65efd6d 1812static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1813{
88de4598 1814 u64 size, offset;
8ffaadf7
JD		 1815 resource_size_t bar_size;
1816 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1817 int bar;
8ffaadf7 1818
9fe5c59f
KB		 1819 if (dev->cmb_size)
1820 return;
1821
20d3bb92
KJ		 1822 if (NVME_CAP_CMBS(dev->ctrl.cap))
1823 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1824
7a67cbea 1825 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1826 if (!dev->cmbsz)
1827 return;
202021c1 1828 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1829
88de4598
CH		 1830 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1831 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1832 bar = NVME_CMB_BIR(dev->cmbloc);
1833 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1834
1835 if (offset > bar_size)
f65efd6d 1836 return;
8ffaadf7 1837
20d3bb92
KJ		 1838 /*
1839 * Tell the controller about the host side address mapping the CMB,
1840 * and enable CMB decoding for the NVMe 1.4+ scheme:
1841 */
1842 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1843 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1844 (pci_bus_address(pdev, bar) + offset),
1845 dev->bar + NVME_REG_CMBMSC);
1846 }
1847
8ffaadf7
JD		 1848 /*
1849 * Controllers may support a CMB size larger than their BAR,
1850 * for example, due to being behind a bridge. Reduce the CMB to
1851 * the reported size of the BAR
1852 */
1853 if (size > bar_size - offset)
1854 size = bar_size - offset;
1855
0f238ff5
LG		 1856 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1857 dev_warn(dev->ctrl.device,
1858 "failed to register the CMB\n");
f65efd6d 1859 return;
0f238ff5
LG		 1860 }
1861
8ffaadf7 1862 dev->cmb_size = size;
0f238ff5
LG		 1863 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1864
1865 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1866 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1867 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1868
1869 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1870 &dev_attr_cmb.attr, NULL))
1871 dev_warn(dev->ctrl.device,
1872 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1873}
1874
1875static inline void nvme_release_cmb(struct nvme_dev *dev)
1876{
0f238ff5 1877 if (dev->cmb_size) {
1c78f773
MG		 1878 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1879 &dev_attr_cmb.attr, NULL);
0f238ff5 1880 dev->cmb_size = 0;
8ffaadf7
JD		 1881 }
1882}
1883
87ad72a5
CH		 1884static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1885{
6c3c05b0 1886 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1887 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1888 struct nvme_command c;
87ad72a5
CH		 1889 int ret;
1890
87ad72a5
CH		 1891 memset(&c, 0, sizeof(c));
1892 c.features.opcode = nvme_admin_set_features;
1893 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1894 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1895 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1896 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1897 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1898 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1899
1900 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1901 if (ret) {
1902 dev_warn(dev->ctrl.device,
1903 "failed to set host mem (err %d, flags %#x).\n",
1904 ret, bits);
1905 }
87ad72a5
CH		 1906 return ret;
1907}
1908
1909static void nvme_free_host_mem(struct nvme_dev *dev)
1910{
1911 int i;
1912
1913 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1914 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 1915 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1916
cc667f6d
LD		 1917 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1918 le64_to_cpu(desc->addr),
1919 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1920 }
1921
1922 kfree(dev->host_mem_desc_bufs);
1923 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1924 dma_free_coherent(dev->dev,
1925 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1926 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1927 dev->host_mem_descs = NULL;
7e5dd57e 1928 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1929}
1930
92dc6895
CH		 1931static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1932 u32 chunk_size)
9d713c2b 1933{
87ad72a5 1934 struct nvme_host_mem_buf_desc *descs;
92dc6895 1935 u32 max_entries, len;
4033f35d 1936 dma_addr_t descs_dma;
2ee0e4ed 1937 int i = 0;
87ad72a5 1938 void **bufs;
6fbcde66 1939 u64 size, tmp;
87ad72a5 1940
87ad72a5
CH		 1941 tmp = (preferred + chunk_size - 1);
1942 do_div(tmp, chunk_size);
1943 max_entries = tmp;
044a9df1
CH		 1944
1945 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1946 max_entries = dev->ctrl.hmmaxd;
1947
750afb08
LC		 1948 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1949 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1950 if (!descs)
1951 goto out;
1952
1953 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1954 if (!bufs)
1955 goto out_free_descs;
1956
244a8fe4 1957 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1958 dma_addr_t dma_addr;
1959
50cdb7c6 1960 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1961 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1962 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1963 if (!bufs[i])
1964 break;
1965
1966 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 1967 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 1968 i++;
1969 }
1970
92dc6895 1971 if (!size)
87ad72a5 1972 goto out_free_bufs;
87ad72a5 1973
87ad72a5
CH		 1974 dev->nr_host_mem_descs = i;
1975 dev->host_mem_size = size;
1976 dev->host_mem_descs = descs;
4033f35d 1977 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1978 dev->host_mem_desc_bufs = bufs;
1979 return 0;
1980
1981out_free_bufs:
1982 while (--i >= 0) {
6c3c05b0 1983 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1984
cc667f6d
LD		 1985 dma_free_attrs(dev->dev, size, bufs[i],
1986 le64_to_cpu(descs[i].addr),
1987 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1988 }
1989
1990 kfree(bufs);
1991out_free_descs:
4033f35d
CH		 1992 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1993 descs_dma);
87ad72a5 1994out:
87ad72a5
CH		 1995 dev->host_mem_descs = NULL;
1996 return -ENOMEM;
1997}
1998
92dc6895
CH		 1999static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2000{
9dc54a0d
CK		 2001 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2002 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2003 u64 chunk_size;
92dc6895
CH		 2004
2005 /* start big and work our way down */
9dc54a0d 2006 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2007 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2008 if (!min || dev->host_mem_size >= min)
2009 return 0;
2010 nvme_free_host_mem(dev);
2011 }
2012 }
2013
2014 return -ENOMEM;
2015}
2016
9620cfba 2017static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2018{
2019 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2020 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2021 u64 min = (u64)dev->ctrl.hmmin * 4096;
2022 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2023 int ret;
87ad72a5
CH		 2024
2025 preferred = min(preferred, max);
2026 if (min > max) {
2027 dev_warn(dev->ctrl.device,
2028 "min host memory (%lld MiB) above limit (%d MiB).\n",
2029 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2030 nvme_free_host_mem(dev);
9620cfba 2031 return 0;
87ad72a5
CH		 2032 }
2033
2034 /*
2035 * If we already have a buffer allocated check if we can reuse it.
2036 */
2037 if (dev->host_mem_descs) {
2038 if (dev->host_mem_size >= min)
2039 enable_bits |= NVME_HOST_MEM_RETURN;
2040 else
2041 nvme_free_host_mem(dev);
2042 }
2043
2044 if (!dev->host_mem_descs) {
92dc6895
CH		 2045 if (nvme_alloc_host_mem(dev, min, preferred)) {
2046 dev_warn(dev->ctrl.device,
2047 "failed to allocate host memory buffer.\n");
9620cfba 2048 return 0; /* controller must work without HMB */
92dc6895
CH		 2049 }
2050
2051 dev_info(dev->ctrl.device,
2052 "allocated %lld MiB host memory buffer.\n",
2053 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2054 }
2055
9620cfba
CH		 2056 ret = nvme_set_host_mem(dev, enable_bits);
2057 if (ret)
87ad72a5 2058 nvme_free_host_mem(dev);
9620cfba 2059 return ret;
9d713c2b
KB		 2060}
2061
612b7286
ML		 2062/*
2063 * nirqs is the number of interrupts available for write and read
2064 * queues. The core already reserved an interrupt for the admin queue.
2065 */
2066static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2067{
612b7286 2068 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2069 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2070
2071 /*
ee0d96d3 2072 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2073 * the default queue is set to 1. The affinity set size is
2074 * also set to one, but the irq core ignores it for this case.
2075 *
2076 * If only one interrupt is available or 'write_queue' == 0, combine
2077 * write and read queues.
2078 *
2079 * If 'write_queues' > 0, ensure it leaves room for at least one read
2080 * queue.
3b6592f7 2081 */
612b7286
ML		 2082 if (!nrirqs) {
2083 nrirqs = 1;
2084 nr_read_queues = 0;
2a5bcfdd 2085 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2086 nr_read_queues = 0;
2a5bcfdd 2087 } else if (nr_write_queues >= nrirqs) {
612b7286 2088 nr_read_queues = 1;
3b6592f7 2089 } else {
2a5bcfdd 2090 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2091 }
612b7286
ML		 2092
2093 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2094 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2095 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2096 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2097 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2098}
2099
6451fe73 2100static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2101{
2102 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2103 struct irq_affinity affd = {
9cfef55b 2104 .pre_vectors = 1,
612b7286
ML		 2105 .calc_sets = nvme_calc_irq_sets,
2106 .priv = dev,
3b6592f7 2107 };
21cc2f3f 2108 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2109
2110 /*
21cc2f3f
JX		 2111 * Poll queues don't need interrupts, but we need at least one I/O queue
2112 * left over for non-polled I/O.
6451fe73 2113 */
21cc2f3f
JX		 2114 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2115 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2116
21cc2f3f
JX		 2117 /*
2118 * Initialize for the single interrupt case, will be updated in
2119 * nvme_calc_irq_sets().
2120 */
612b7286
ML		 2121 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2122 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2123
66341331 2124 /*
21cc2f3f
JX		 2125 * We need interrupts for the admin queue and each non-polled I/O queue,
2126 * but some Apple controllers require all queues to use the first
2127 * vector.
66341331 2128 */
21cc2f3f
JX		 2129 irq_queues = 1;
2130 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2131 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2132 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2133 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2134}
2135
8fae268b
KB		 2136static void nvme_disable_io_queues(struct nvme_dev *dev)
2137{
2138 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2139 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2140}
2141
2a5bcfdd
WZ		 2142static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2143{
e3aef095
NS		 2144 /*
2145 * If tags are shared with admin queue (Apple bug), then
2146 * make sure we only use one IO queue.
2147 */
2148 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2149 return 1;
2a5bcfdd
WZ		 2150 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2151}
2152
8d85fce7 2153static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2154{
147b27e4 2155 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2156 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2157 unsigned int nr_io_queues;
97f6ef64 2158 unsigned long size;
2a5bcfdd 2159 int result;
b60503ba 2160
2a5bcfdd
WZ		 2161 /*
2162 * Sample the module parameters once at reset time so that we have
2163 * stable values to work with.
2164 */
2165 dev->nr_write_queues = write_queues;
2166 dev->nr_poll_queues = poll_queues;
d38e9f04 2167
e3aef095 2168 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2169 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2170 if (result < 0)
1b23484b 2171 return result;
9a0be7ab 2172
f5fa90dc 2173 if (nr_io_queues == 0)
a5229050 2174 return 0;
4e224106
CH		 2175
2176 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2177
0f238ff5 2178 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2179 result = nvme_cmb_qdepth(dev, nr_io_queues,
2180 sizeof(struct nvme_command));
2181 if (result > 0)
2182 dev->q_depth = result;
2183 else
0f238ff5 2184 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2185 }
2186
97f6ef64
XY		 2187 do {
2188 size = db_bar_size(dev, nr_io_queues);
2189 result = nvme_remap_bar(dev, size);
2190 if (!result)
2191 break;
2192 if (!--nr_io_queues)
2193 return -ENOMEM;
2194 } while (1);
2195 adminq->q_db = dev->dbs;
f1938f6e 2196
8fae268b 2197 retry:
9d713c2b 2198 /* Deregister the admin queue's interrupt */
0ff199cb 2199 pci_free_irq(pdev, 0, adminq);
9d713c2b 2200
e32efbfc
JA		 2201 /*
2202 * If we enable msix early due to not intx, disable it again before
2203 * setting up the full range we need.
2204 */
dca51e78 2205 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2206
2207 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2208 if (result <= 0)
dca51e78 2209 return -EIO;
3b6592f7 2210
22b55601 2211 dev->num_vecs = result;
4b04cc6a 2212 result = max(result - 1, 1);
e20ba6e1 2213 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2214
063a8096
MW		 2215 /*
2216 * Should investigate if there's a performance win from allocating
2217 * more queues than interrupt vectors; it might allow the submission
2218 * path to scale better, even if the receive path is limited by the
2219 * number of interrupts.
2220 */
dca51e78 2221 result = queue_request_irq(adminq);
7c349dde 2222 if (result)
d4875622 2223 return result;
4e224106 2224 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB		 2225
2226 result = nvme_create_io_queues(dev);
2227 if (result || dev->online_queues < 2)
2228 return result;
2229
2230 if (dev->online_queues - 1 < dev->max_qid) {
2231 nr_io_queues = dev->online_queues - 1;
2232 nvme_disable_io_queues(dev);
2233 nvme_suspend_io_queues(dev);
2234 goto retry;
2235 }
2236 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2237 dev->io_queues[HCTX_TYPE_DEFAULT],
2238 dev->io_queues[HCTX_TYPE_READ],
2239 dev->io_queues[HCTX_TYPE_POLL]);
2240 return 0;
b60503ba
MW		 2241}
2242
2a842aca 2243static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2244{
db3cbfff 2245 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2246
db3cbfff 2247 blk_mq_free_request(req);
d1ed6aa1 2248 complete(&nvmeq->delete_done);
a5768aa8
KB		 2249}
2250
2a842aca 2251static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2252{
db3cbfff 2253 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2254
d1ed6aa1
CH		 2255 if (error)
2256 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2257
2258 nvme_del_queue_end(req, error);
a5768aa8
KB		 2259}
2260
db3cbfff 2261static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2262{
db3cbfff
KB		 2263 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2264 struct request *req;
2265 struct nvme_command cmd;
bda4e0fb 2266
db3cbfff
KB		 2267 memset(&cmd, 0, sizeof(cmd));
2268 cmd.delete_queue.opcode = opcode;
2269 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2270
39dfe844 2271 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2272 if (IS_ERR(req))
2273 return PTR_ERR(req);
bda4e0fb 2274
db3cbfff
KB		 2275 req->end_io_data = nvmeq;
2276
d1ed6aa1 2277 init_completion(&nvmeq->delete_done);
8eeed0b5 2278 blk_execute_rq_nowait(NULL, req, false,
db3cbfff
KB		 2279 opcode == nvme_admin_delete_cq ?
2280 nvme_del_cq_end : nvme_del_queue_end);
2281 return 0;
bda4e0fb
KB		 2282}
2283
8fae268b 2284static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2285{
5271edd4 2286 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2287 unsigned long timeout;
a5768aa8 2288
db3cbfff 2289 retry:
dc96f938 2290 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2291 while (nr_queues > 0) {
2292 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2293 break;
2294 nr_queues--;
2295 sent++;
db3cbfff 2296 }
d1ed6aa1
CH		 2297 while (sent) {
2298 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2299
2300 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2301 timeout);
2302 if (timeout == 0)
2303 return false;
d1ed6aa1 2304
d1ed6aa1 2305 sent--;
5271edd4
CH		 2306 if (nr_queues)
2307 goto retry;
2308 }
2309 return true;
a5768aa8
KB		 2310}
2311
5d02a5c1 2312static void nvme_dev_add(struct nvme_dev *dev)
b60503ba 2313{
2b1b7e78
JW		 2314 int ret;
2315
5bae7f73 2316 if (!dev->ctrl.tagset) {
376f7ef8 2317 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2318 dev->tagset.nr_hw_queues = dev->online_queues - 1;
8fe34be1 2319 dev->tagset.nr_maps = 2; /* default + read */
ed92ad37
CH		 2320 if (dev->io_queues[HCTX_TYPE_POLL])
2321 dev->tagset.nr_maps++;
ffe7704d 2322 dev->tagset.timeout = NVME_IO_TIMEOUT;
d4ec47f1 2323 dev->tagset.numa_node = dev->ctrl.numa_node;
61f3b896
CK		 2324 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2325 BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2326 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2327 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2328 dev->tagset.driver_data = dev;
b60503ba 2329
d38e9f04
BH		 2330 /*
2331 * Some Apple controllers requires tags to be unique
2332 * across admin and IO queue, so reserve the first 32
2333 * tags of the IO queue.
2334 */
2335 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2336 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2337
2b1b7e78
JW		 2338 ret = blk_mq_alloc_tag_set(&dev->tagset);
2339 if (ret) {
2340 dev_warn(dev->ctrl.device,
2341 "IO queues tagset allocation failed %d\n", ret);
5d02a5c1 2342 return;
2b1b7e78 2343 }
5bae7f73 2344 dev->ctrl.tagset = &dev->tagset;
949928c1
KB		 2345 } else {
2346 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2347
2348 /* Free previously allocated queues that are no longer usable */
2349 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2350 }
949928c1 2351
e8fd41bb 2352 nvme_dbbuf_set(dev);
b60503ba
MW		 2353}
2354
b00a726a 2355static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2356{
b00a726a 2357 int result = -ENOMEM;
e75ec752 2358 struct pci_dev *pdev = to_pci_dev(dev->dev);
4bdf2603 2359 int dma_address_bits = 64;
0877cb0d
KB		 2360
2361 if (pci_enable_device_mem(pdev))
2362 return result;
2363
0877cb0d 2364 pci_set_master(pdev);
0877cb0d 2365
4bdf2603
FS		 2366 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2367 dma_address_bits = 48;
2368 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
052d0efa 2369 goto disable;
0877cb0d 2370
7a67cbea 2371 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2372 result = -ENODEV;
b00a726a 2373 goto disable;
0e53d180 2374 }
e32efbfc
JA		 2375
2376 /*
a5229050
KB		 2377 * Some devices and/or platforms don't advertise or work with INTx
2378 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2379 * adjust this later.
e32efbfc 2380 */
dca51e78
CH		 2381 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2382 if (result < 0)
2383 return result;
e32efbfc 2384
20d0dfe6 2385 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2386
7442ddce 2387 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2388 io_queue_depth);
aa22c8e6 2389 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2390 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2391 dev->dbs = dev->bar + 4096;
1f390c1f 2392
66341331
BH		 2393 /*
2394 * Some Apple controllers require a non-standard SQE size.
2395 * Interestingly they also seem to ignore the CC:IOSQES register
2396 * so we don't bother updating it here.
2397 */
2398 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2399 dev->io_sqes = 7;
2400 else
2401 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2402
2403 /*
2404 * Temporary fix for the Apple controller found in the MacBook8,1 and
2405 * some MacBook7,1 to avoid controller resets and data loss.
2406 */
2407 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2408 dev->q_depth = 2;
9bdcfb10
CH		 2409 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2410 "set queue depth=%u to work around controller resets\n",
1f390c1f 2411 dev->q_depth);
d554b5e1
MP		 2412 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2413 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2414 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2415 dev->q_depth = 64;
2416 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2417 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2418 }
2419
d38e9f04
BH		 2420 /*
2421 * Controllers with the shared tags quirk need the IO queue to be
2422 * big enough so that we get 32 tags for the admin queue
2423 */
2424 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2425 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2426 dev->q_depth = NVME_AQ_DEPTH + 2;
2427 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2428 dev->q_depth);
2429 }
2430
2431
f65efd6d 2432 nvme_map_cmb(dev);
202021c1 2433
a0a3408e
KB		 2434 pci_enable_pcie_error_reporting(pdev);
2435 pci_save_state(pdev);
0877cb0d
KB		 2436 return 0;
2437
2438 disable:
0877cb0d
KB		 2439 pci_disable_device(pdev);
2440 return result;
2441}
2442
2443static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2444{
2445 if (dev->bar)
2446 iounmap(dev->bar);
a1f447b3 2447 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2448}
2449
2450static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2451{
e75ec752
CH		 2452 struct pci_dev *pdev = to_pci_dev(dev->dev);
2453
dca51e78 2454 pci_free_irq_vectors(pdev);
0877cb0d 2455
a0a3408e
KB		 2456 if (pci_is_enabled(pdev)) {
2457 pci_disable_pcie_error_reporting(pdev);
e75ec752 2458 pci_disable_device(pdev);
4d115420 2459 }
4d115420
KB		 2460}
2461
a5cdb68c 2462static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2463{
e43269e6 2464 bool dead = true, freeze = false;
302ad8cc 2465 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2466
77bf25ea 2467 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2468 if (pci_is_enabled(pdev)) {
2469 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2470
ebef7368 2471 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2472 dev->ctrl.state == NVME_CTRL_RESETTING) {
2473 freeze = true;
302ad8cc 2474 nvme_start_freeze(&dev->ctrl);
e43269e6 2475 }
302ad8cc
KB		 2476 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2477 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2478 }
c21377f8 2479
302ad8cc
KB		 2480 /*
2481 * Give the controller a chance to complete all entered requests if
2482 * doing a safe shutdown.
2483 */
e43269e6
KB		 2484 if (!dead && shutdown && freeze)
2485 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2486
2487 nvme_stop_queues(&dev->ctrl);
87ad72a5 2488
64ee0ac0 2489 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2490 nvme_disable_io_queues(dev);
a5cdb68c 2491 nvme_disable_admin_queue(dev, shutdown);
4d115420 2492 }
8fae268b
KB		 2493 nvme_suspend_io_queues(dev);
2494 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2495 nvme_pci_disable(dev);
fa46c6fb 2496 nvme_reap_pending_cqes(dev);
07836e65 2497
e1958e65
ML		 2498 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2499 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
622b8b68
ML		 2500 blk_mq_tagset_wait_completed_request(&dev->tagset);
2501 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
302ad8cc
KB		 2502
2503 /*
2504 * The driver will not be starting up queues again if shutting down so
2505 * must flush all entered requests to their failed completion to avoid
2506 * deadlocking blk-mq hot-cpu notifier.
2507 */
c8e9e9b7 2508 if (shutdown) {
302ad8cc 2509 nvme_start_queues(&dev->ctrl);
c8e9e9b7
KB		 2510 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2511 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2512 }
77bf25ea 2513 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2514}
2515
c1ac9a4b
KB		 2516static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2517{
2518 if (!nvme_wait_reset(&dev->ctrl))
2519 return -EBUSY;
2520 nvme_dev_disable(dev, shutdown);
2521 return 0;
2522}
2523
091b6092
MW		 2524static int nvme_setup_prp_pools(struct nvme_dev *dev)
2525{
e75ec752 2526 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2527 NVME_CTRL_PAGE_SIZE,
2528 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2529 if (!dev->prp_page_pool)
2530 return -ENOMEM;
2531
99802a7a 2532 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2533 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2534 256, 256, 0);
2535 if (!dev->prp_small_pool) {
2536 dma_pool_destroy(dev->prp_page_pool);
2537 return -ENOMEM;
2538 }
091b6092
MW		 2539 return 0;
2540}
2541
2542static void nvme_release_prp_pools(struct nvme_dev *dev)
2543{
2544 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2545 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2546}
2547
770597ec
KB		 2548static void nvme_free_tagset(struct nvme_dev *dev)
2549{
2550 if (dev->tagset.tags)
2551 blk_mq_free_tag_set(&dev->tagset);
2552 dev->ctrl.tagset = NULL;
2553}
2554
1673f1f0 2555static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2556{
1673f1f0 2557 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2558
f9f38e33 2559 nvme_dbbuf_dma_free(dev);
770597ec 2560 nvme_free_tagset(dev);
1c63dc66
CH		 2561 if (dev->ctrl.admin_q)
2562 blk_put_queue(dev->ctrl.admin_q);
e286bcfc 2563 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2564 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2565 put_device(dev->dev);
2566 kfree(dev->queues);
5e82e952
KB		 2567 kfree(dev);
2568}
2569
7c1ce408 2570static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2571{
c1ac9a4b
KB		 2572 /*
2573 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2574 * may be holding this pci_dev's device lock.
2575 */
2576 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2577 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2578 nvme_dev_disable(dev, false);
9f9cafc1 2579 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2580 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2581 nvme_put_ctrl(&dev->ctrl);
2582}
2583
fd634f41 2584static void nvme_reset_work(struct work_struct *work)
5e82e952 2585{
d86c4d8e
CH		 2586 struct nvme_dev *dev =
2587 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2588 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2589 int result;
5e82e952 2590
e71afda4
CK		 2591 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2592 result = -ENODEV;
fd634f41 2593 goto out;
e71afda4 2594 }
5e82e952 2595
fd634f41
CH		 2596 /*
2597 * If we're called to reset a live controller first shut it down before
2598 * moving on.
2599 */
b00a726a 2600 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2601 nvme_dev_disable(dev, false);
d6135c3a 2602 nvme_sync_queues(&dev->ctrl);
5e82e952 2603
5c959d73 2604 mutex_lock(&dev->shutdown_lock);
b00a726a 2605 result = nvme_pci_enable(dev);
f0b50732 2606 if (result)
4726bcf3 2607 goto out_unlock;
f0b50732 2608
01ad0990 2609 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2610 if (result)
4726bcf3 2611 goto out_unlock;
f0b50732 2612
0fb59cbc
KB		 2613 result = nvme_alloc_admin_tags(dev);
2614 if (result)
4726bcf3 2615 goto out_unlock;
b9afca3e 2616
943e942e
JA		 2617 /*
2618 * Limit the max command size to prevent iod->sg allocations going
2619 * over a single page.
2620 */
7637de31
CH		 2621 dev->ctrl.max_hw_sectors = min_t(u32,
2622 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2623 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2624
2625 /*
2626 * Don't limit the IOMMU merged segment size.
2627 */
2628 dma_set_max_seg_size(dev->dev, 0xffffffff);
3d2d861e 2629 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
a48bc520 2630
5c959d73
KB		 2631 mutex_unlock(&dev->shutdown_lock);
2632
2633 /*
2634 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2635 * initializing procedure here.
2636 */
2637 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2638 dev_warn(dev->ctrl.device,
2639 "failed to mark controller CONNECTING\n");
cee6c269 2640 result = -EBUSY;
5c959d73
KB		 2641 goto out;
2642 }
943e942e 2643
95093350
MG		 2644 /*
2645 * We do not support an SGL for metadata (yet), so we are limited to a
2646 * single integrity segment for the separate metadata pointer.
2647 */
2648 dev->ctrl.max_integrity_segments = 1;
2649
f21c4769 2650 result = nvme_init_ctrl_finish(&dev->ctrl);
ce4541f4 2651 if (result)
f58944e2 2652 goto out;
ce4541f4 2653
e286bcfc
SB		 2654 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2655 if (!dev->ctrl.opal_dev)
2656 dev->ctrl.opal_dev =
2657 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2658 else if (was_suspend)
2659 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2660 } else {
2661 free_opal_dev(dev->ctrl.opal_dev);
2662 dev->ctrl.opal_dev = NULL;
4f1244c8 2663 }
a98e58e5 2664
f9f38e33
HK		 2665 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2666 result = nvme_dbbuf_dma_alloc(dev);
2667 if (result)
2668 dev_warn(dev->dev,
2669 "unable to allocate dma for dbbuf\n");
2670 }
2671
9620cfba
CH		 2672 if (dev->ctrl.hmpre) {
2673 result = nvme_setup_host_mem(dev);
2674 if (result < 0)
2675 goto out;
2676 }
87ad72a5 2677
f0b50732 2678 result = nvme_setup_io_queues(dev);
badc34d4 2679 if (result)
f58944e2 2680 goto out;
f0b50732 2681
2659e57b
CH		 2682 /*
2683 * Keep the controller around but remove all namespaces if we don't have
2684 * any working I/O queue.
2685 */
3cf519b5 2686 if (dev->online_queues < 2) {
1b3c47c1 2687 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2688 nvme_kill_queues(&dev->ctrl);
5bae7f73 2689 nvme_remove_namespaces(&dev->ctrl);
770597ec 2690 nvme_free_tagset(dev);
3cf519b5 2691 } else {
25646264 2692 nvme_start_queues(&dev->ctrl);
302ad8cc 2693 nvme_wait_freeze(&dev->ctrl);
5d02a5c1 2694 nvme_dev_add(dev);
302ad8cc 2695 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2696 }
2697
2b1b7e78
JW		 2698 /*
2699 * If only admin queue live, keep it to do further investigation or
2700 * recovery.
2701 */
5d02a5c1 2702 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2703 dev_warn(dev->ctrl.device,
5d02a5c1 2704 "failed to mark controller live state\n");
e71afda4 2705 result = -ENODEV;
bb8d261e
CH		 2706 goto out;
2707 }
92911a55 2708
d09f2b45 2709 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2710 return;
f0b50732 2711
4726bcf3
KB		 2712 out_unlock:
2713 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2714 out:
7c1ce408
CK		 2715 if (result)
2716 dev_warn(dev->ctrl.device,
2717 "Removing after probe failure status: %d\n", result);
2718 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2719}
2720
5c8809e6 2721static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2722{
5c8809e6 2723 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2724 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2725
2726 if (pci_get_drvdata(pdev))
921920ab 2727 device_release_driver(&pdev->dev);
1673f1f0 2728 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2729}
2730
1c63dc66 2731static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2732{
1c63dc66 2733 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2734 return 0;
9ca97374
TH		 2735}
2736
5fd4ce1b 2737static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2738{
5fd4ce1b
CH		 2739 writel(val, to_nvme_dev(ctrl)->bar + off);
2740 return 0;
2741}
4cc06521 2742
7fd8930f
CH		 2743static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2744{
3a8ecc93 2745 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2746 return 0;
4cc06521
KB		 2747}
2748
97c12223
KB		 2749static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2750{
2751 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2752
2db24e4a 2753 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2754}
2755
1c63dc66 2756static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2757 .name = "pcie",
e439bb12 2758 .module = THIS_MODULE,
e0596ab2
LG		 2759 .flags = NVME_F_METADATA_SUPPORTED |
2760 NVME_F_PCI_P2PDMA,
1c63dc66 2761 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2762 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2763 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2764 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2765 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2766 .get_address = nvme_pci_get_address,
1c63dc66 2767};
4cc06521 2768
b00a726a
KB		 2769static int nvme_dev_map(struct nvme_dev *dev)
2770{
b00a726a
KB		 2771 struct pci_dev *pdev = to_pci_dev(dev->dev);
2772
a1f447b3 2773 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2774 return -ENODEV;
2775
97f6ef64 2776 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2777 goto release;
2778
9fa196e7 2779 return 0;
b00a726a 2780 release:
9fa196e7
MG		 2781 pci_release_mem_regions(pdev);
2782 return -ENODEV;
b00a726a
KB		 2783}
2784
8427bbc2 2785static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2786{
2787 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2788 /*
2789 * Several Samsung devices seem to drop off the PCIe bus
2790 * randomly when APST is on and uses the deepest sleep state.
2791 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2792 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2793 * 950 PRO 256GB", but it seems to be restricted to two Dell
2794 * laptops.
2795 */
2796 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2797 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2798 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2799 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2800 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2801 /*
2802 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2803 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2804 * within few minutes after bootup on a Coffee Lake board -
2805 * ASUS PRIME Z370-A
8427bbc2
KHF		 2806 */
2807 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2808 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2809 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2810 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2811 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2812 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2813 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2814 /*
2815 * Forcing to use host managed nvme power settings for
2816 * lowest idle power with quick resume latency on
2817 * Samsung and Toshiba SSDs based on suspend behavior
2818 * on Coffee Lake board for LENOVO C640
2819 */
2820 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2821 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2822 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 2823 }
2824
2825 return 0;
2826}
2827
df4f9bc4
DB		 2828#ifdef CONFIG_ACPI
2829static bool nvme_acpi_storage_d3(struct pci_dev *dev)
2830{
2831 struct acpi_device *adev;
2832 struct pci_dev *root;
2833 acpi_handle handle;
2834 acpi_status status;
2835 u8 val;
2836
2837 /*
2838 * Look for _DSD property specifying that the storage device on the port
2839 * must use D3 to support deep platform power savings during
2840 * suspend-to-idle.
2841 */
2842 root = pcie_find_root_port(dev);
2843 if (!root)
2844 return false;
2845
2846 adev = ACPI_COMPANION(&root->dev);
2847 if (!adev)
2848 return false;
2849
2850 /*
2851 * The property is defined in the PXSX device for South complex ports
2852 * and in the PEGP device for North complex ports.
2853 */
2854 status = acpi_get_handle(adev->handle, "PXSX", &handle);
2855 if (ACPI_FAILURE(status)) {
2856 status = acpi_get_handle(adev->handle, "PEGP", &handle);
2857 if (ACPI_FAILURE(status))
2858 return false;
2859 }
2860
2861 if (acpi_bus_get_device(handle, &adev))
2862 return false;
2863
2864 if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable",
2865 &val))
2866 return false;
2867 return val == 1;
2868}
2869#else
2870static inline bool nvme_acpi_storage_d3(struct pci_dev *dev)
2871{
2872 return false;
2873}
2874#endif /* CONFIG_ACPI */
2875
18119775
KB		 2876static void nvme_async_probe(void *data, async_cookie_t cookie)
2877{
2878 struct nvme_dev *dev = data;
80f513b5 2879
bd46a906 2880 flush_work(&dev->ctrl.reset_work);
18119775 2881 flush_work(&dev->ctrl.scan_work);
80f513b5 2882 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2883}
2884
8d85fce7 2885static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2886{
a4aea562 2887 int node, result = -ENOMEM;
b60503ba 2888 struct nvme_dev *dev;
ff5350a8 2889 unsigned long quirks = id->driver_data;
943e942e 2890 size_t alloc_size;
b60503ba 2891
a4aea562
MB		 2892 node = dev_to_node(&pdev->dev);
2893 if (node == NUMA_NO_NODE)
2fa84351 2894 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2895
2896 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2897 if (!dev)
2898 return -ENOMEM;
147b27e4 2899
2a5bcfdd
WZ		 2900 dev->nr_write_queues = write_queues;
2901 dev->nr_poll_queues = poll_queues;
2902 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2903 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2904 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 2905 if (!dev->queues)
2906 goto free;
2907
e75ec752 2908 dev->dev = get_device(&pdev->dev);
9a6b9458 2909 pci_set_drvdata(pdev, dev);
1c63dc66 2910
b00a726a
KB		 2911 result = nvme_dev_map(dev);
2912 if (result)
b00c9b7a 2913 goto put_pci;
b00a726a 2914
d86c4d8e 2915 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2916 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2917 mutex_init(&dev->shutdown_lock);
b60503ba 2918
091b6092
MW		 2919 result = nvme_setup_prp_pools(dev);
2920 if (result)
b00c9b7a 2921 goto unmap;
4cc06521 2922
8427bbc2 2923 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2924
df4f9bc4
DB		 2925 if (!noacpi && nvme_acpi_storage_d3(pdev)) {
2926 /*
2927 * Some systems use a bios work around to ask for D3 on
2928 * platforms that support kernel managed suspend.
2929 */
2930 dev_info(&pdev->dev,
2931 "platform quirk: setting simple suspend\n");
2932 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2933 }
2934
943e942e
JA		 2935 /*
2936 * Double check that our mempool alloc size will cover the biggest
2937 * command we support.
2938 */
b13c6393 2939 alloc_size = nvme_pci_iod_alloc_size();
943e942e
JA		 2940 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2941
2942 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2943 mempool_kfree,
2944 (void *) alloc_size,
2945 GFP_KERNEL, node);
2946 if (!dev->iod_mempool) {
2947 result = -ENOMEM;
2948 goto release_pools;
2949 }
2950
b6e44b4c
KB		 2951 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2952 quirks);
2953 if (result)
2954 goto release_mempool;
2955
1b3c47c1
SG		 2956 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2957
bd46a906 2958 nvme_reset_ctrl(&dev->ctrl);
18119775 2959 async_schedule(nvme_async_probe, dev);
4caff8fc 2960
b60503ba
MW		 2961 return 0;
2962
b6e44b4c
KB		 2963 release_mempool:
2964 mempool_destroy(dev->iod_mempool);
0877cb0d 2965 release_pools:
091b6092 2966 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2967 unmap:
2968 nvme_dev_unmap(dev);
a96d4f5c 2969 put_pci:
e75ec752 2970 put_device(dev->dev);
b60503ba
MW		 2971 free:
2972 kfree(dev->queues);
b60503ba
MW		 2973 kfree(dev);
2974 return result;
2975}
2976
775755ed 2977static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2978{
a6739479 2979 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2980
2981 /*
2982 * We don't need to check the return value from waiting for the reset
2983 * state as pci_dev device lock is held, making it impossible to race
2984 * with ->remove().
2985 */
2986 nvme_disable_prepare_reset(dev, false);
2987 nvme_sync_queues(&dev->ctrl);
775755ed 2988}
f0d54a54 2989
775755ed
CH		 2990static void nvme_reset_done(struct pci_dev *pdev)
2991{
f263fbb8 2992 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2993
2994 if (!nvme_try_sched_reset(&dev->ctrl))
2995 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 2996}
2997
09ece142
KB		 2998static void nvme_shutdown(struct pci_dev *pdev)
2999{
3000 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 3001
c1ac9a4b 3002 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 3003}
3004
f58944e2
KB		 3005/*
3006 * The driver's remove may be called on a device in a partially initialized
3007 * state. This function must not have any dependencies on the device state in
3008 * order to proceed.
3009 */
8d85fce7 3010static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3011{
3012 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 3013
bb8d261e 3014 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 3015 pci_set_drvdata(pdev, NULL);
0ff9d4e1 3016
6db28eda 3017 if (!pci_device_is_present(pdev)) {
0ff9d4e1 3018 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 3019 nvme_dev_disable(dev, true);
cb4bfda6 3020 nvme_dev_remove_admin(dev);
6db28eda 3021 }
0ff9d4e1 3022
d86c4d8e 3023 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 3024 nvme_stop_ctrl(&dev->ctrl);
3025 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 3026 nvme_dev_disable(dev, true);
9fe5c59f 3027 nvme_release_cmb(dev);
87ad72a5 3028 nvme_free_host_mem(dev);
a4aea562 3029 nvme_dev_remove_admin(dev);
a1a5ef99 3030 nvme_free_queues(dev, 0);
9a6b9458 3031 nvme_release_prp_pools(dev);
b00a726a 3032 nvme_dev_unmap(dev);
726612b6 3033 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3034}
3035
671a6018 3036#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 3037static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3038{
3039 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3040}
3041
3042static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3043{
3044 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3045}
3046
3047static int nvme_resume(struct device *dev)
3048{
3049 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3050 struct nvme_ctrl *ctrl = &ndev->ctrl;
3051
4eaefe8c 3052 if (ndev->last_ps == U32_MAX ||
d916b1be 3053 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
c1ac9a4b 3054 return nvme_try_sched_reset(&ndev->ctrl);
d916b1be
KB		 3055 return 0;
3056}
3057
cd638946
KB		 3058static int nvme_suspend(struct device *dev)
3059{
3060 struct pci_dev *pdev = to_pci_dev(dev);
3061 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3062 struct nvme_ctrl *ctrl = &ndev->ctrl;
3063 int ret = -EBUSY;
3064
4eaefe8c
RW		 3065 ndev->last_ps = U32_MAX;
3066
d916b1be
KB		 3067 /*
3068 * The platform does not remove power for a kernel managed suspend so
3069 * use host managed nvme power settings for lowest idle power if
3070 * possible. This should have quicker resume latency than a full device
3071 * shutdown. But if the firmware is involved after the suspend or the
3072 * device does not support any non-default power states, shut down the
3073 * device fully.
4eaefe8c
RW		 3074 *
3075 * If ASPM is not enabled for the device, shut down the device and allow
3076 * the PCI bus layer to put it into D3 in order to take the PCIe link
3077 * down, so as to allow the platform to achieve its minimum low-power
3078 * state (which may not be possible if the link is up).
b97120b1
CH		 3079 *
3080 * If a host memory buffer is enabled, shut down the device as the NVMe
3081 * specification allows the device to access the host memory buffer in
3082 * host DRAM from all power states, but hosts will fail access to DRAM
3083 * during S3.
d916b1be 3084 */
4eaefe8c 3085 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3086 !pcie_aspm_enabled(pdev) ||
b97120b1 3087 ndev->nr_host_mem_descs ||
c1ac9a4b
KB		 3088 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3089 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3090
3091 nvme_start_freeze(ctrl);
3092 nvme_wait_freeze(ctrl);
3093 nvme_sync_queues(ctrl);
3094
5d02a5c1 3095 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3096 goto unfreeze;
3097
d916b1be
KB		 3098 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3099 if (ret < 0)
3100 goto unfreeze;
3101
7cbb5c6f
ML		 3102 /*
3103 * A saved state prevents pci pm from generically controlling the
3104 * device's power. If we're using protocol specific settings, we don't
3105 * want pci interfering.
3106 */
3107 pci_save_state(pdev);
3108
d916b1be
KB		 3109 ret = nvme_set_power_state(ctrl, ctrl->npss);
3110 if (ret < 0)
3111 goto unfreeze;
3112
3113 if (ret) {
7cbb5c6f
ML		 3114 /* discard the saved state */
3115 pci_load_saved_state(pdev, NULL);
3116
d916b1be
KB		 3117 /*
3118 * Clearing npss forces a controller reset on resume. The
05d3046f 3119 * correct value will be rediscovered then.
d916b1be 3120 */
c1ac9a4b 3121 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3122 ctrl->npss = 0;
d916b1be 3123 }
d916b1be
KB		 3124unfreeze:
3125 nvme_unfreeze(ctrl);
3126 return ret;
3127}
3128
3129static int nvme_simple_suspend(struct device *dev)
3130{
3131 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3132
c1ac9a4b 3133 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3134}
3135
d916b1be 3136static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3137{
3138 struct pci_dev *pdev = to_pci_dev(dev);
3139 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3140
c1ac9a4b 3141 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3142}
3143
21774222 3144static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3145 .suspend = nvme_suspend,
3146 .resume = nvme_resume,
3147 .freeze = nvme_simple_suspend,
3148 .thaw = nvme_simple_resume,
3149 .poweroff = nvme_simple_suspend,
3150 .restore = nvme_simple_resume,
3151};
3152#endif /* CONFIG_PM_SLEEP */
b60503ba 3153
a0a3408e
KB		 3154static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3155 pci_channel_state_t state)
3156{
3157 struct nvme_dev *dev = pci_get_drvdata(pdev);
3158
3159 /*
3160 * A frozen channel requires a reset. When detected, this method will
3161 * shutdown the controller to quiesce. The controller will be restarted
3162 * after the slot reset through driver's slot_reset callback.
3163 */
a0a3408e
KB		 3164 switch (state) {
3165 case pci_channel_io_normal:
3166 return PCI_ERS_RESULT_CAN_RECOVER;
3167 case pci_channel_io_frozen:
d011fb31
KB		 3168 dev_warn(dev->ctrl.device,
3169 "frozen state error detected, reset controller\n");
a5cdb68c 3170 nvme_dev_disable(dev, false);
a0a3408e
KB		 3171 return PCI_ERS_RESULT_NEED_RESET;
3172 case pci_channel_io_perm_failure:
d011fb31
KB		 3173 dev_warn(dev->ctrl.device,
3174 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3175 return PCI_ERS_RESULT_DISCONNECT;
3176 }
3177 return PCI_ERS_RESULT_NEED_RESET;
3178}
3179
3180static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3181{
3182 struct nvme_dev *dev = pci_get_drvdata(pdev);
3183
1b3c47c1 3184 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3185 pci_restore_state(pdev);
d86c4d8e 3186 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3187 return PCI_ERS_RESULT_RECOVERED;
3188}
3189
3190static void nvme_error_resume(struct pci_dev *pdev)
3191{
72cd4cc2
KB		 3192 struct nvme_dev *dev = pci_get_drvdata(pdev);
3193
3194 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3195}
3196
1d352035 3197static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3198 .error_detected = nvme_error_detected,
b60503ba
MW		 3199 .slot_reset = nvme_slot_reset,
3200 .resume = nvme_error_resume,
775755ed
CH		 3201 .reset_prepare = nvme_reset_prepare,
3202 .reset_done = nvme_reset_done,
b60503ba
MW		 3203};
3204
6eb0d698 3205static const struct pci_device_id nvme_id_table[] = {
972b13e2 3206 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3207 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3208 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3209 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3210 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3211 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3212 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3213 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3214 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3215 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3216 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3217 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3218 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3219 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3220 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3221 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3222 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3223 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3224 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3225 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 3226 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3227 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
5bedd3af
CH		 3228 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3229 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
0302ae60 3230 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3231 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3232 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3233 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3234 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3235 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3236 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3237 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3238 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3239 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3240 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3241 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3242 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3243 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3244 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
c9e95c39
CS		 3245 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3246 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
6e6a6828
PT		 3247 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3248 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3249 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
608cc4b1
CH		 3250 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3251 .driver_data = NVME_QUIRK_LIGHTNVM, },
3252 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3253 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 3254 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3255 .driver_data = NVME_QUIRK_LIGHTNVM, },
08b903b5
MN		 3256 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3257 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
f03e42c6
GC		 3258 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3259 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3260 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
5611ec2b
KHF		 3261 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3262 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
02ca079c
KHF		 3263 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3264 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3265 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3266 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3267 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3268 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3269 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3270 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
4bdf2603
FS		 3271 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3272 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3273 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3274 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3275 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3276 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3277 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3278 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3279 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3280 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3281 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3282 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3283 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3284 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3285 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3286 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3287 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04
BH		 3288 NVME_QUIRK_128_BYTES_SQES |
3289 NVME_QUIRK_SHARED_TAGS },
0b85f59d
AS		 3290
3291 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3292 { 0, }
3293};
3294MODULE_DEVICE_TABLE(pci, nvme_id_table);
3295
3296static struct pci_driver nvme_driver = {
3297 .name = "nvme",
3298 .id_table = nvme_id_table,
3299 .probe = nvme_probe,
8d85fce7 3300 .remove = nvme_remove,
09ece142 3301 .shutdown = nvme_shutdown,
d916b1be 3302#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3303 .driver = {
3304 .pm = &nvme_dev_pm_ops,
3305 },
d916b1be 3306#endif
74d986ab 3307 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3308 .err_handler = &nvme_err_handler,
3309};
3310
3311static int __init nvme_init(void)
3312{
81101540
CH		 3313 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3314 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3315 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3316 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
17c33167 3317
9a6327d2 3318 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3319}
3320
3321static void __exit nvme_exit(void)
3322{
3323 pci_unregister_driver(&nvme_driver);
03e0f3a6 3324 flush_workqueue(nvme_wq);
b60503ba
MW		 3325}
3326
3327MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3328MODULE_LICENSE("GPL");
c78b4713 3329MODULE_VERSION("1.0");
b60503ba
MW		 3330module_init(nvme_init);
3331module_exit(nvme_exit);
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