[mirror_ubuntu-jammy-kernel.git] / drivers / nvmem / bcm-ocotp.c

/*
 * Copyright (C) 2016 Broadcom
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/nvmem-provider.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>

/*
 * # of tries for OTP Status. The time to execute a command varies. The slowest
 * commands are writes which also vary based on the # of bits turned on. Writing
 * 0xffffffff takes ~3800 us.
 */
#define OTPC_RETRIES                 5000

/* Sequence to enable OTP program */
#define OTPC_PROG_EN_SEQ             { 0xf, 0x4, 0x8, 0xd }

/* OTPC Commands */
#define OTPC_CMD_READ                0x0
#define OTPC_CMD_OTP_PROG_ENABLE     0x2
#define OTPC_CMD_OTP_PROG_DISABLE    0x3
#define OTPC_CMD_PROGRAM             0x8

/* OTPC Status Bits */
#define OTPC_STAT_CMD_DONE           BIT(1)
#define OTPC_STAT_PROG_OK            BIT(2)

/* OTPC register definition */
#define OTPC_MODE_REG_OFFSET         0x0
#define OTPC_MODE_REG_OTPC_MODE      0
#define OTPC_COMMAND_OFFSET          0x4
#define OTPC_COMMAND_COMMAND_WIDTH   6
#define OTPC_CMD_START_OFFSET        0x8
#define OTPC_CMD_START_START         0
#define OTPC_CPU_STATUS_OFFSET       0xc
#define OTPC_CPUADDR_REG_OFFSET      0x28
#define OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH 16
#define OTPC_CPU_WRITE_REG_OFFSET    0x2c

#define OTPC_CMD_MASK  (BIT(OTPC_COMMAND_COMMAND_WIDTH) - 1)
#define OTPC_ADDR_MASK (BIT(OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH) - 1)


struct otpc_map {
	/* in words. */
	u32 otpc_row_size;
	/* 128 bit row / 4 words support. */
	u16 data_r_offset[4];
	/* 128 bit row / 4 words support. */
	u16 data_w_offset[4];
};

static struct otpc_map otp_map = {
	.otpc_row_size = 1,
	.data_r_offset = {0x10},
	.data_w_offset = {0x2c},
};

static struct otpc_map otp_map_v2 = {
	.otpc_row_size = 2,
	.data_r_offset = {0x10, 0x5c},
	.data_w_offset = {0x2c, 0x64},
};

struct otpc_priv {
	struct device *dev;
	void __iomem *base;
	const struct otpc_map *map;
	struct nvmem_config *config;
};

static inline void set_command(void __iomem *base, u32 command)
{
	writel(command & OTPC_CMD_MASK, base + OTPC_COMMAND_OFFSET);
}

static inline void set_cpu_address(void __iomem *base, u32 addr)
{
	writel(addr & OTPC_ADDR_MASK, base + OTPC_CPUADDR_REG_OFFSET);
}

static inline void set_start_bit(void __iomem *base)
{
	writel(1 << OTPC_CMD_START_START, base + OTPC_CMD_START_OFFSET);
}

static inline void reset_start_bit(void __iomem *base)
{
	writel(0, base + OTPC_CMD_START_OFFSET);
}

static inline void write_cpu_data(void __iomem *base, u32 value)
{
	writel(value, base + OTPC_CPU_WRITE_REG_OFFSET);
}

static int poll_cpu_status(void __iomem *base, u32 value)
{
	u32 status;
	u32 retries;

	for (retries = 0; retries < OTPC_RETRIES; retries++) {
		status = readl(base + OTPC_CPU_STATUS_OFFSET);
		if (status & value)
			break;
		udelay(1);
	}
	if (retries == OTPC_RETRIES)
		return -EAGAIN;

	return 0;
}

static int enable_ocotp_program(void __iomem *base)
{
	static const u32 vals[] = OTPC_PROG_EN_SEQ;
	int i;
	int ret;

	/* Write the magic sequence to enable programming */
	set_command(base, OTPC_CMD_OTP_PROG_ENABLE);
	for (i = 0; i < ARRAY_SIZE(vals); i++) {
		write_cpu_data(base, vals[i]);
		set_start_bit(base);
		ret = poll_cpu_status(base, OTPC_STAT_CMD_DONE);
		reset_start_bit(base);
		if (ret)
			return ret;
	}

	return poll_cpu_status(base, OTPC_STAT_PROG_OK);
}

static int disable_ocotp_program(void __iomem *base)
{
	int ret;

	set_command(base, OTPC_CMD_OTP_PROG_DISABLE);
	set_start_bit(base);
	ret = poll_cpu_status(base, OTPC_STAT_PROG_OK);
	reset_start_bit(base);

	return ret;
}

static int bcm_otpc_read(void *context, unsigned int offset, void *val,
	size_t bytes)
{
	struct otpc_priv *priv = context;
	u32 *buf = val;
	u32 bytes_read;
	u32 address = offset / priv->config->word_size;
	int i, ret;

	for (bytes_read = 0; bytes_read < bytes;) {
		set_command(priv->base, OTPC_CMD_READ);
		set_cpu_address(priv->base, address++);
		set_start_bit(priv->base);
		ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE);
		if (ret) {
			dev_err(priv->dev, "otp read error: 0x%x", ret);
			return -EIO;
		}

		for (i = 0; i < priv->map->otpc_row_size; i++) {
			*buf++ = readl(priv->base +
					priv->map->data_r_offset[i]);
			bytes_read += sizeof(*buf);
		}

		reset_start_bit(priv->base);
	}

	return 0;
}

static int bcm_otpc_write(void *context, unsigned int offset, void *val,
	size_t bytes)
{
	struct otpc_priv *priv = context;
	u32 *buf = val;
	u32 bytes_written;
	u32 address = offset / priv->config->word_size;
	int i, ret;

	if (offset % priv->config->word_size)
		return -EINVAL;

	ret = enable_ocotp_program(priv->base);
	if (ret)
		return -EIO;

	for (bytes_written = 0; bytes_written < bytes;) {
		set_command(priv->base, OTPC_CMD_PROGRAM);
		set_cpu_address(priv->base, address++);
		for (i = 0; i < priv->map->otpc_row_size; i++) {
			writel(*buf, priv->base + priv->map->data_w_offset[i]);
			buf++;
			bytes_written += sizeof(*buf);
		}
		set_start_bit(priv->base);
		ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE);
		reset_start_bit(priv->base);
		if (ret) {
			dev_err(priv->dev, "otp write error: 0x%x", ret);
			return -EIO;
		}
	}

	disable_ocotp_program(priv->base);

	return 0;
}

static struct nvmem_config bcm_otpc_nvmem_config = {
	.name = "bcm-ocotp",
	.read_only = false,
	.word_size = 4,
	.stride = 4,
	.reg_read = bcm_otpc_read,
	.reg_write = bcm_otpc_write,
};

static const struct of_device_id bcm_otpc_dt_ids[] = {
	{ .compatible = "brcm,ocotp", .data = &otp_map },
	{ .compatible = "brcm,ocotp-v2", .data = &otp_map_v2 },
	{ },
};
MODULE_DEVICE_TABLE(of, bcm_otpc_dt_ids);

static const struct acpi_device_id bcm_otpc_acpi_ids[] = {
	{ .id = "BRCM0700", .driver_data = (kernel_ulong_t)&otp_map },
	{ .id = "BRCM0701", .driver_data = (kernel_ulong_t)&otp_map_v2 },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(acpi, bcm_otpc_acpi_ids);

static int bcm_otpc_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct resource *res;
	struct otpc_priv *priv;
	struct nvmem_device *nvmem;
	int err;
	u32 num_words;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->map = device_get_match_data(dev);
	if (!priv->map)
		return -ENODEV;

	/* Get OTP base address register. */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(priv->base)) {
		dev_err(dev, "unable to map I/O memory\n");
		return PTR_ERR(priv->base);
	}

	/* Enable CPU access to OTPC. */
	writel(readl(priv->base + OTPC_MODE_REG_OFFSET) |
		BIT(OTPC_MODE_REG_OTPC_MODE),
		priv->base + OTPC_MODE_REG_OFFSET);
	reset_start_bit(priv->base);

	/* Read size of memory in words. */
	err = device_property_read_u32(dev, "brcm,ocotp-size", &num_words);
	if (err) {
		dev_err(dev, "size parameter not specified\n");
		return -EINVAL;
	} else if (num_words == 0) {
		dev_err(dev, "size must be > 0\n");
		return -EINVAL;
	}

	bcm_otpc_nvmem_config.size = 4 * num_words;
	bcm_otpc_nvmem_config.dev = dev;
	bcm_otpc_nvmem_config.priv = priv;

	if (priv->map == &otp_map_v2) {
		bcm_otpc_nvmem_config.word_size = 8;
		bcm_otpc_nvmem_config.stride = 8;
	}

	priv->config = &bcm_otpc_nvmem_config;

	nvmem = devm_nvmem_register(dev, &bcm_otpc_nvmem_config);
	if (IS_ERR(nvmem)) {
		dev_err(dev, "error registering nvmem config\n");
		return PTR_ERR(nvmem);
	}

	return 0;
}

static struct platform_driver bcm_otpc_driver = {
	.probe	= bcm_otpc_probe,
	.driver = {
		.name	= "brcm-otpc",
		.of_match_table = bcm_otpc_dt_ids,
		.acpi_match_table = ACPI_PTR(bcm_otpc_acpi_ids),
	},
};
module_platform_driver(bcm_otpc_driver);

MODULE_DESCRIPTION("Broadcom OTPC driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9d59c6e8 JR	1	/*
	2	* Copyright (C) 2016 Broadcom
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License as
	6	* published by the Free Software Foundation version 2.
	7	*
	8	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	9	* kind, whether express or implied; without even the implied warranty
	10	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
16941555	14	#include <linux/acpi.h>
9d59c6e8 JR	15	#include <linux/delay.h>
	16	#include <linux/device.h>
	17	#include <linux/io.h>
	18	#include <linux/module.h>
	19	#include <linux/nvmem-provider.h>
	20	#include <linux/of.h>
16941555	21	#include <linux/of_device.h>
9d59c6e8 JR	22	#include <linux/platform_device.h>
	23
	24	/*
	25	* # of tries for OTP Status. The time to execute a command varies. The slowest
	26	* commands are writes which also vary based on the # of bits turned on. Writing
	27	* 0xffffffff takes ~3800 us.
	28	*/
	29	#define OTPC_RETRIES 5000
	30
	31	/* Sequence to enable OTP program */
	32	#define OTPC_PROG_EN_SEQ { 0xf, 0x4, 0x8, 0xd }
	33
	34	/* OTPC Commands */
	35	#define OTPC_CMD_READ 0x0
	36	#define OTPC_CMD_OTP_PROG_ENABLE 0x2
	37	#define OTPC_CMD_OTP_PROG_DISABLE 0x3
e827756d	38	#define OTPC_CMD_PROGRAM 0x8
9d59c6e8 JR	39
	40	/* OTPC Status Bits */
	41	#define OTPC_STAT_CMD_DONE BIT(1)
	42	#define OTPC_STAT_PROG_OK BIT(2)
	43
	44	/* OTPC register definition */
	45	#define OTPC_MODE_REG_OFFSET 0x0
	46	#define OTPC_MODE_REG_OTPC_MODE 0
	47	#define OTPC_COMMAND_OFFSET 0x4
	48	#define OTPC_COMMAND_COMMAND_WIDTH 6
	49	#define OTPC_CMD_START_OFFSET 0x8
	50	#define OTPC_CMD_START_START 0
	51	#define OTPC_CPU_STATUS_OFFSET 0xc
	52	#define OTPC_CPUADDR_REG_OFFSET 0x28
	53	#define OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH 16
	54	#define OTPC_CPU_WRITE_REG_OFFSET 0x2c
	55
	56	#define OTPC_CMD_MASK (BIT(OTPC_COMMAND_COMMAND_WIDTH) - 1)
	57	#define OTPC_ADDR_MASK (BIT(OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH) - 1)
	58
	59
	60	struct otpc_map {
	61	/* in words. */
	62	u32 otpc_row_size;
	63	/* 128 bit row / 4 words support. */
	64	u16 data_r_offset[4];
	65	/* 128 bit row / 4 words support. */
	66	u16 data_w_offset[4];
	67	};
	68
	69	static struct otpc_map otp_map = {
	70	.otpc_row_size = 1,
	71	.data_r_offset = {0x10},
	72	.data_w_offset = {0x2c},
	73	};
	74
	75	static struct otpc_map otp_map_v2 = {
	76	.otpc_row_size = 2,
	77	.data_r_offset = {0x10, 0x5c},
	78	.data_w_offset = {0x2c, 0x64},
	79	};
	80
	81	struct otpc_priv {
16941555 SM	82	struct device *dev;
	83	void __iomem *base;
	84	const struct otpc_map *map;
9d59c6e8 JR	85	struct nvmem_config *config;
	86	};
	87
	88	static inline void set_command(void __iomem *base, u32 command)
	89	{
	90	writel(command & OTPC_CMD_MASK, base + OTPC_COMMAND_OFFSET);
	91	}
	92
	93	static inline void set_cpu_address(void __iomem *base, u32 addr)
	94	{
	95	writel(addr & OTPC_ADDR_MASK, base + OTPC_CPUADDR_REG_OFFSET);
	96	}
	97
	98	static inline void set_start_bit(void __iomem *base)
	99	{
	100	writel(1 << OTPC_CMD_START_START, base + OTPC_CMD_START_OFFSET);
	101	}
	102
	103	static inline void reset_start_bit(void __iomem *base)
	104	{
	105	writel(0, base + OTPC_CMD_START_OFFSET);
	106	}
	107
	108	static inline void write_cpu_data(void __iomem *base, u32 value)
	109	{
	110	writel(value, base + OTPC_CPU_WRITE_REG_OFFSET);
	111	}
	112
	113	static int poll_cpu_status(void __iomem *base, u32 value)
	114	{
	115	u32 status;
	116	u32 retries;
	117
	118	for (retries = 0; retries < OTPC_RETRIES; retries++) {
	119	status = readl(base + OTPC_CPU_STATUS_OFFSET);
	120	if (status & value)
	121	break;
	122	udelay(1);
	123	}
	124	if (retries == OTPC_RETRIES)
	125	return -EAGAIN;
	126
	127	return 0;
	128	}
	129
	130	static int enable_ocotp_program(void __iomem *base)
	131	{
	132	static const u32 vals[] = OTPC_PROG_EN_SEQ;
	133	int i;
	134	int ret;
	135
	136	/* Write the magic sequence to enable programming */
	137	set_command(base, OTPC_CMD_OTP_PROG_ENABLE);
	138	for (i = 0; i < ARRAY_SIZE(vals); i++) {
	139	write_cpu_data(base, vals[i]);
	140	set_start_bit(base);
	141	ret = poll_cpu_status(base, OTPC_STAT_CMD_DONE);
	142	reset_start_bit(base);
	143	if (ret)
	144	return ret;
	145	}
	146
	147	return poll_cpu_status(base, OTPC_STAT_PROG_OK);
	148	}
149
150	static int disable_ocotp_program(void __iomem *base)
151	{
152	int ret;
153
154	set_command(base, OTPC_CMD_OTP_PROG_DISABLE);
155	set_start_bit(base);
156	ret = poll_cpu_status(base, OTPC_STAT_PROG_OK);
157	reset_start_bit(base);
158
159	return ret;
160	}
161
162	static int bcm_otpc_read(void context, unsigned int offset, void val,
163	size_t bytes)
164	{
165	struct otpc_priv *priv = context;
166	u32 *buf = val;
167	u32 bytes_read;
168	u32 address = offset / priv->config->word_size;
169	int i, ret;
170
171	for (bytes_read = 0; bytes_read < bytes;) {
172	set_command(priv->base, OTPC_CMD_READ);
173	set_cpu_address(priv->base, address++);
174	set_start_bit(priv->base);
175	ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE);
176	if (ret) {
177	dev_err(priv->dev, "otp read error: 0x%x", ret);
178	return -EIO;
179	}
180
181	for (i = 0; i < priv->map->otpc_row_size; i++) {
182	*buf++ = readl(priv->base +
183	priv->map->data_r_offset[i]);
184	bytes_read += sizeof(*buf);
185	}
186
187	reset_start_bit(priv->base);
188	}
189
190	return 0;
191	}
192
193	static int bcm_otpc_write(void context, unsigned int offset, void val,
194	size_t bytes)
195	{
196	struct otpc_priv *priv = context;
197	u32 *buf = val;
198	u32 bytes_written;
199	u32 address = offset / priv->config->word_size;
200	int i, ret;
201
202	if (offset % priv->config->word_size)
203	return -EINVAL;
204
205	ret = enable_ocotp_program(priv->base);
206	if (ret)
207	return -EIO;
208
209	for (bytes_written = 0; bytes_written < bytes;) {
210	set_command(priv->base, OTPC_CMD_PROGRAM);
211	set_cpu_address(priv->base, address++);
212	for (i = 0; i < priv->map->otpc_row_size; i++) {
e827756d	213	writel(*buf, priv->base + priv->map->data_w_offset[i]);
9d59c6e8 JR	214	buf++;
	215	bytes_written += sizeof(*buf);
	216	}
	217	set_start_bit(priv->base);
	218	ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE);
	219	reset_start_bit(priv->base);
	220	if (ret) {
	221	dev_err(priv->dev, "otp write error: 0x%x", ret);
	222	return -EIO;
	223	}
	224	}
	225
	226	disable_ocotp_program(priv->base);
	227
	228	return 0;
	229	}
	230
	231	static struct nvmem_config bcm_otpc_nvmem_config = {
	232	.name = "bcm-ocotp",
	233	.read_only = false,
	234	.word_size = 4,
	235	.stride = 4,
9d59c6e8 JR	236	.reg_read = bcm_otpc_read,
	237	.reg_write = bcm_otpc_write,
	238	};
	239
	240	static const struct of_device_id bcm_otpc_dt_ids[] = {
16941555 SM	241	{ .compatible = "brcm,ocotp", .data = &otp_map },
16941555 SM	242	{ .compatible = "brcm,ocotp-v2", .data = &otp_map_v2 },
9d59c6e8 JR	243	{ },
	244	};
	245	MODULE_DEVICE_TABLE(of, bcm_otpc_dt_ids);
	246
16941555 SM	247	static const struct acpi_device_id bcm_otpc_acpi_ids[] = {
	248	{ .id = "BRCM0700", .driver_data = (kernel_ulong_t)&otp_map },
	249	{ .id = "BRCM0701", .driver_data = (kernel_ulong_t)&otp_map_v2 },
	250	{ /* sentinel */ }
	251	};
	252	MODULE_DEVICE_TABLE(acpi, bcm_otpc_acpi_ids);
	253
9d59c6e8 JR	254	static int bcm_otpc_probe(struct platform_device *pdev)
	255	{
	256	struct device *dev = &pdev->dev;
9d59c6e8 JR	257	struct resource *res;
	258	struct otpc_priv *priv;
	259	struct nvmem_device *nvmem;
	260	int err;
	261	u32 num_words;
	262
	263	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	264	if (!priv)
	265	return -ENOMEM;
	266
16941555 SM	267	priv->map = device_get_match_data(dev);
	268	if (!priv->map)
	269	return -ENODEV;
9d59c6e8 JR	270
	271	/* Get OTP base address register. */
	272	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	273	priv->base = devm_ioremap_resource(dev, res);
	274	if (IS_ERR(priv->base)) {
	275	dev_err(dev, "unable to map I/O memory\n");
	276	return PTR_ERR(priv->base);
	277	}
	278
	279	/* Enable CPU access to OTPC. */
	280	writel(readl(priv->base + OTPC_MODE_REG_OFFSET) \|
	281	BIT(OTPC_MODE_REG_OTPC_MODE),
	282	priv->base + OTPC_MODE_REG_OFFSET);
	283	reset_start_bit(priv->base);
	284
	285	/* Read size of memory in words. */
16941555	286	err = device_property_read_u32(dev, "brcm,ocotp-size", &num_words);
9d59c6e8 JR	287	if (err) {
	288	dev_err(dev, "size parameter not specified\n");
	289	return -EINVAL;
	290	} else if (num_words == 0) {
	291	dev_err(dev, "size must be > 0\n");
	292	return -EINVAL;
	293	}
	294
	295	bcm_otpc_nvmem_config.size = 4 * num_words;
	296	bcm_otpc_nvmem_config.dev = dev;
	297	bcm_otpc_nvmem_config.priv = priv;
	298
16941555	299	if (priv->map == &otp_map_v2) {
9d59c6e8 JR	300	bcm_otpc_nvmem_config.word_size = 8;
	301	bcm_otpc_nvmem_config.stride = 8;
	302	}
	303
	304	priv->config = &bcm_otpc_nvmem_config;
	305
b2236dbd	306	nvmem = devm_nvmem_register(dev, &bcm_otpc_nvmem_config);
9d59c6e8 JR	307	if (IS_ERR(nvmem)) {
	308	dev_err(dev, "error registering nvmem config\n");
	309	return PTR_ERR(nvmem);
	310	}
	311
9d59c6e8 JR	312	return 0;
	313	}
	314
9d59c6e8 JR	315	static struct platform_driver bcm_otpc_driver = {
9d59c6e8 JR	316	.probe = bcm_otpc_probe,
9d59c6e8 JR	317	.driver = {
	318	.name = "brcm-otpc",
	319	.of_match_table = bcm_otpc_dt_ids,
16941555	320	.acpi_match_table = ACPI_PTR(bcm_otpc_acpi_ids),
9d59c6e8 JR	321	},
	322	};
	323	module_platform_driver(bcm_otpc_driver);
	324
	325	MODULE_DESCRIPTION("Broadcom OTPC driver");
	326	MODULE_LICENSE("GPL v2");