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acee2e8d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
3edba6b4 PZ |
2 | /* |
3 | * i.MX6 OCOTP fusebox driver | |
4 | * | |
5 | * Copyright (c) 2015 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de> | |
6 | * | |
7 | * Based on the barebox ocotp driver, | |
8 | * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>, | |
9 | * Orex Computed Radiography | |
10 | * | |
0642bac7 RL |
11 | * Write support based on the fsl_otp driver, |
12 | * Copyright (C) 2010-2013 Freescale Semiconductor, Inc | |
3edba6b4 PZ |
13 | */ |
14 | ||
deb31970 | 15 | #include <linux/clk.h> |
3edba6b4 PZ |
16 | #include <linux/device.h> |
17 | #include <linux/io.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/nvmem-provider.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/of_device.h> | |
22 | #include <linux/platform_device.h> | |
3edba6b4 | 23 | #include <linux/slab.h> |
0642bac7 | 24 | #include <linux/delay.h> |
3edba6b4 | 25 | |
9b66587e RL |
26 | #define IMX_OCOTP_OFFSET_B0W0 0x400 /* Offset from base address of the |
27 | * OTP Bank0 Word0 | |
28 | */ | |
29 | #define IMX_OCOTP_OFFSET_PER_WORD 0x10 /* Offset between the start addr | |
30 | * of two consecutive OTP words. | |
31 | */ | |
0642bac7 | 32 | |
9b66587e | 33 | #define IMX_OCOTP_ADDR_CTRL 0x0000 |
0642bac7 | 34 | #define IMX_OCOTP_ADDR_CTRL_SET 0x0004 |
9b66587e | 35 | #define IMX_OCOTP_ADDR_CTRL_CLR 0x0008 |
0642bac7 | 36 | #define IMX_OCOTP_ADDR_TIMING 0x0010 |
ffd9115f BD |
37 | #define IMX_OCOTP_ADDR_DATA0 0x0020 |
38 | #define IMX_OCOTP_ADDR_DATA1 0x0030 | |
39 | #define IMX_OCOTP_ADDR_DATA2 0x0040 | |
40 | #define IMX_OCOTP_ADDR_DATA3 0x0050 | |
9b66587e | 41 | |
c03bb448 | 42 | #define IMX_OCOTP_BM_CTRL_ADDR 0x000000FF |
0642bac7 | 43 | #define IMX_OCOTP_BM_CTRL_BUSY 0x00000100 |
9b66587e | 44 | #define IMX_OCOTP_BM_CTRL_ERROR 0x00000200 |
0642bac7 | 45 | #define IMX_OCOTP_BM_CTRL_REL_SHADOWS 0x00000400 |
9b66587e | 46 | |
159dbaf5 BD |
47 | #define TIMING_STROBE_PROG_US 10 /* Min time to blow a fuse */ |
48 | #define TIMING_STROBE_READ_NS 37 /* Min time before read */ | |
49 | #define TIMING_RELAX_NS 17 | |
828ae7a4 BD |
50 | #define DEF_FSOURCE 1001 /* > 1000 ns */ |
51 | #define DEF_STROBE_PROG 10000 /* IPG clocks */ | |
0642bac7 | 52 | #define IMX_OCOTP_WR_UNLOCK 0x3E770000 |
9b66587e RL |
53 | #define IMX_OCOTP_READ_LOCKED_VAL 0xBADABADA |
54 | ||
0642bac7 RL |
55 | static DEFINE_MUTEX(ocotp_mutex); |
56 | ||
3edba6b4 PZ |
57 | struct ocotp_priv { |
58 | struct device *dev; | |
deb31970 | 59 | struct clk *clk; |
3edba6b4 | 60 | void __iomem *base; |
e20d2b29 | 61 | const struct ocotp_params *params; |
0642bac7 | 62 | struct nvmem_config *config; |
3edba6b4 PZ |
63 | }; |
64 | ||
828ae7a4 BD |
65 | struct ocotp_params { |
66 | unsigned int nregs; | |
67 | unsigned int bank_address_words; | |
68 | void (*set_timing)(struct ocotp_priv *priv); | |
69 | }; | |
70 | ||
0642bac7 RL |
71 | static int imx_ocotp_wait_for_busy(void __iomem *base, u32 flags) |
72 | { | |
73 | int count; | |
74 | u32 c, mask; | |
75 | ||
76 | mask = IMX_OCOTP_BM_CTRL_BUSY | IMX_OCOTP_BM_CTRL_ERROR | flags; | |
77 | ||
78 | for (count = 10000; count >= 0; count--) { | |
79 | c = readl(base + IMX_OCOTP_ADDR_CTRL); | |
80 | if (!(c & mask)) | |
81 | break; | |
82 | cpu_relax(); | |
83 | } | |
84 | ||
85 | if (count < 0) { | |
86 | /* HW_OCOTP_CTRL[ERROR] will be set under the following | |
87 | * conditions: | |
88 | * - A write is performed to a shadow register during a shadow | |
89 | * reload (essentially, while HW_OCOTP_CTRL[RELOAD_SHADOWS] is | |
90 | * set. In addition, the contents of the shadow register shall | |
91 | * not be updated. | |
92 | * - A write is performed to a shadow register which has been | |
93 | * locked. | |
94 | * - A read is performed to from a shadow register which has | |
95 | * been read locked. | |
96 | * - A program is performed to a fuse word which has been locked | |
97 | * - A read is performed to from a fuse word which has been read | |
98 | * locked. | |
99 | */ | |
100 | if (c & IMX_OCOTP_BM_CTRL_ERROR) | |
101 | return -EPERM; | |
102 | return -ETIMEDOUT; | |
103 | } | |
104 | ||
105 | return 0; | |
106 | } | |
107 | ||
9b66587e RL |
108 | static void imx_ocotp_clr_err_if_set(void __iomem *base) |
109 | { | |
110 | u32 c; | |
111 | ||
112 | c = readl(base + IMX_OCOTP_ADDR_CTRL); | |
113 | if (!(c & IMX_OCOTP_BM_CTRL_ERROR)) | |
114 | return; | |
115 | ||
116 | writel(IMX_OCOTP_BM_CTRL_ERROR, base + IMX_OCOTP_ADDR_CTRL_CLR); | |
117 | } | |
118 | ||
33e5e29c SK |
119 | static int imx_ocotp_read(void *context, unsigned int offset, |
120 | void *val, size_t bytes) | |
3edba6b4 PZ |
121 | { |
122 | struct ocotp_priv *priv = context; | |
3edba6b4 | 123 | unsigned int count; |
33e5e29c | 124 | u32 *buf = val; |
deb31970 | 125 | int i, ret; |
3edba6b4 PZ |
126 | u32 index; |
127 | ||
128 | index = offset >> 2; | |
33e5e29c | 129 | count = bytes >> 2; |
3edba6b4 | 130 | |
e20d2b29 BD |
131 | if (count > (priv->params->nregs - index)) |
132 | count = priv->params->nregs - index; | |
3edba6b4 | 133 | |
0642bac7 RL |
134 | mutex_lock(&ocotp_mutex); |
135 | ||
deb31970 PF |
136 | ret = clk_prepare_enable(priv->clk); |
137 | if (ret < 0) { | |
0642bac7 | 138 | mutex_unlock(&ocotp_mutex); |
deb31970 PF |
139 | dev_err(priv->dev, "failed to prepare/enable ocotp clk\n"); |
140 | return ret; | |
141 | } | |
3edba6b4 | 142 | |
0642bac7 RL |
143 | ret = imx_ocotp_wait_for_busy(priv->base, 0); |
144 | if (ret < 0) { | |
145 | dev_err(priv->dev, "timeout during read setup\n"); | |
146 | goto read_end; | |
147 | } | |
148 | ||
9b66587e RL |
149 | for (i = index; i < (index + count); i++) { |
150 | *buf++ = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 + | |
151 | i * IMX_OCOTP_OFFSET_PER_WORD); | |
deb31970 | 152 | |
9b66587e RL |
153 | /* 47.3.1.2 |
154 | * For "read locked" registers 0xBADABADA will be returned and | |
155 | * HW_OCOTP_CTRL[ERROR] will be set. It must be cleared by | |
156 | * software before any new write, read or reload access can be | |
157 | * issued | |
158 | */ | |
159 | if (*(buf - 1) == IMX_OCOTP_READ_LOCKED_VAL) | |
160 | imx_ocotp_clr_err_if_set(priv->base); | |
161 | } | |
0642bac7 | 162 | ret = 0; |
9b66587e | 163 | |
0642bac7 | 164 | read_end: |
9b66587e | 165 | clk_disable_unprepare(priv->clk); |
0642bac7 RL |
166 | mutex_unlock(&ocotp_mutex); |
167 | return ret; | |
168 | } | |
169 | ||
b50cb68f BD |
170 | static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv) |
171 | { | |
172 | unsigned long clk_rate = 0; | |
173 | unsigned long strobe_read, relax, strobe_prog; | |
174 | u32 timing = 0; | |
175 | ||
176 | /* 47.3.1.3.1 | |
177 | * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX] | |
178 | * fields with timing values to match the current frequency of the | |
179 | * ipg_clk. OTP writes will work at maximum bus frequencies as long | |
180 | * as the HW_OCOTP_TIMING parameters are set correctly. | |
159dbaf5 BD |
181 | * |
182 | * Note: there are minimum timings required to ensure an OTP fuse burns | |
183 | * correctly that are independent of the ipg_clk. Those values are not | |
184 | * formally documented anywhere however, working from the minimum | |
185 | * timings given in u-boot we can say: | |
186 | * | |
187 | * - Minimum STROBE_PROG time is 10 microseconds. Intuitively 10 | |
188 | * microseconds feels about right as representative of a minimum time | |
189 | * to physically burn out a fuse. | |
190 | * | |
191 | * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before | |
192 | * performing another read is 37 nanoseconds | |
193 | * | |
194 | * - Minimum RELAX timing is 17 nanoseconds. This final RELAX minimum | |
195 | * timing is not entirely clear the documentation says "This | |
196 | * count value specifies the time to add to all default timing | |
197 | * parameters other than the Tpgm and Trd. It is given in number | |
198 | * of ipg_clk periods." where Tpgm and Trd refer to STROBE_PROG | |
199 | * and STROBE_READ respectively. What the other timing parameters | |
200 | * are though, is not specified. Experience shows a zero RELAX | |
201 | * value will mess up a re-load of the shadow registers post OTP | |
202 | * burn. | |
b50cb68f BD |
203 | */ |
204 | clk_rate = clk_get_rate(priv->clk); | |
205 | ||
159dbaf5 BD |
206 | relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1; |
207 | strobe_read = DIV_ROUND_UP(clk_rate * TIMING_STROBE_READ_NS, | |
208 | 1000000000); | |
209 | strobe_read += 2 * (relax + 1) - 1; | |
210 | strobe_prog = DIV_ROUND_CLOSEST(clk_rate * TIMING_STROBE_PROG_US, | |
211 | 1000000); | |
212 | strobe_prog += 2 * (relax + 1) - 1; | |
b50cb68f | 213 | |
0493c479 BD |
214 | timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000; |
215 | timing |= strobe_prog & 0x00000FFF; | |
b50cb68f BD |
216 | timing |= (relax << 12) & 0x0000F000; |
217 | timing |= (strobe_read << 16) & 0x003F0000; | |
218 | ||
219 | writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); | |
220 | } | |
221 | ||
828ae7a4 BD |
222 | static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv) |
223 | { | |
224 | unsigned long clk_rate = 0; | |
225 | u64 fsource, strobe_prog; | |
226 | u32 timing = 0; | |
227 | ||
228 | /* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1 | |
229 | * 6.4.3.3 | |
230 | */ | |
231 | clk_rate = clk_get_rate(priv->clk); | |
232 | fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE, | |
233 | NSEC_PER_SEC) + 1; | |
234 | strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG, | |
235 | NSEC_PER_SEC) + 1; | |
236 | ||
237 | timing = strobe_prog & 0x00000FFF; | |
238 | timing |= (fsource << 12) & 0x000FF000; | |
239 | ||
240 | writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); | |
241 | } | |
242 | ||
0642bac7 RL |
243 | static int imx_ocotp_write(void *context, unsigned int offset, void *val, |
244 | size_t bytes) | |
245 | { | |
246 | struct ocotp_priv *priv = context; | |
247 | u32 *buf = val; | |
248 | int ret; | |
249 | ||
0642bac7 RL |
250 | u32 ctrl; |
251 | u8 waddr; | |
ffd9115f | 252 | u8 word = 0; |
0642bac7 RL |
253 | |
254 | /* allow only writing one complete OTP word at a time */ | |
255 | if ((bytes != priv->config->word_size) || | |
256 | (offset % priv->config->word_size)) | |
257 | return -EINVAL; | |
258 | ||
259 | mutex_lock(&ocotp_mutex); | |
260 | ||
261 | ret = clk_prepare_enable(priv->clk); | |
262 | if (ret < 0) { | |
263 | mutex_unlock(&ocotp_mutex); | |
264 | dev_err(priv->dev, "failed to prepare/enable ocotp clk\n"); | |
265 | return ret; | |
266 | } | |
267 | ||
b50cb68f | 268 | /* Setup the write timing values */ |
828ae7a4 | 269 | priv->params->set_timing(priv); |
0642bac7 RL |
270 | |
271 | /* 47.3.1.3.2 | |
272 | * Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear. | |
273 | * Overlapped accesses are not supported by the controller. Any pending | |
274 | * write or reload must be completed before a write access can be | |
275 | * requested. | |
276 | */ | |
277 | ret = imx_ocotp_wait_for_busy(priv->base, 0); | |
278 | if (ret < 0) { | |
279 | dev_err(priv->dev, "timeout during timing setup\n"); | |
280 | goto write_end; | |
281 | } | |
282 | ||
283 | /* 47.3.1.3.3 | |
284 | * Write the requested address to HW_OCOTP_CTRL[ADDR] and program the | |
285 | * unlock code into HW_OCOTP_CTRL[WR_UNLOCK]. This must be programmed | |
286 | * for each write access. The lock code is documented in the register | |
287 | * description. Both the unlock code and address can be written in the | |
288 | * same operation. | |
289 | */ | |
ffd9115f BD |
290 | if (priv->params->bank_address_words != 0) { |
291 | /* | |
292 | * In banked/i.MX7 mode the OTP register bank goes into waddr | |
293 | * see i.MX 7Solo Applications Processor Reference Manual, Rev. | |
294 | * 0.1 section 6.4.3.1 | |
295 | */ | |
296 | offset = offset / priv->config->word_size; | |
297 | waddr = offset / priv->params->bank_address_words; | |
298 | word = offset & (priv->params->bank_address_words - 1); | |
299 | } else { | |
300 | /* | |
301 | * Non-banked i.MX6 mode. | |
302 | * OTP write/read address specifies one of 128 word address | |
303 | * locations | |
304 | */ | |
305 | waddr = offset / 4; | |
306 | } | |
0642bac7 RL |
307 | |
308 | ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL); | |
309 | ctrl &= ~IMX_OCOTP_BM_CTRL_ADDR; | |
310 | ctrl |= waddr & IMX_OCOTP_BM_CTRL_ADDR; | |
311 | ctrl |= IMX_OCOTP_WR_UNLOCK; | |
312 | ||
313 | writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL); | |
314 | ||
315 | /* 47.3.1.3.4 | |
316 | * Write the data to the HW_OCOTP_DATA register. This will automatically | |
317 | * set HW_OCOTP_CTRL[BUSY] and clear HW_OCOTP_CTRL[WR_UNLOCK]. To | |
318 | * protect programming same OTP bit twice, before program OCOTP will | |
319 | * automatically read fuse value in OTP and use read value to mask | |
320 | * program data. The controller will use masked program data to program | |
321 | * a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit | |
322 | * fields with 1's will result in that OTP bit being programmed. Bit | |
323 | * fields with 0's will be ignored. At the same time that the write is | |
324 | * accepted, the controller makes an internal copy of | |
325 | * HW_OCOTP_CTRL[ADDR] which cannot be updated until the next write | |
326 | * sequence is initiated. This copy guarantees that erroneous writes to | |
327 | * HW_OCOTP_CTRL[ADDR] will not affect an active write operation. It | |
328 | * should also be noted that during the programming HW_OCOTP_DATA will | |
329 | * shift right (with zero fill). This shifting is required to program | |
330 | * the OTP serially. During the write operation, HW_OCOTP_DATA cannot be | |
331 | * modified. | |
ffd9115f BD |
332 | * Note: on i.MX7 there are four data fields to write for banked write |
333 | * with the fuse blowing operation only taking place after data0 | |
334 | * has been written. This is why data0 must always be the last | |
335 | * register written. | |
0642bac7 | 336 | */ |
ffd9115f BD |
337 | if (priv->params->bank_address_words != 0) { |
338 | /* Banked/i.MX7 mode */ | |
339 | switch (word) { | |
340 | case 0: | |
341 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); | |
342 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); | |
343 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); | |
344 | writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0); | |
345 | break; | |
346 | case 1: | |
347 | writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1); | |
348 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); | |
349 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); | |
350 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); | |
351 | break; | |
352 | case 2: | |
353 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); | |
354 | writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2); | |
355 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); | |
356 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); | |
357 | break; | |
358 | case 3: | |
359 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); | |
360 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); | |
361 | writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3); | |
362 | writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); | |
363 | break; | |
364 | } | |
365 | } else { | |
366 | /* Non-banked i.MX6 mode */ | |
367 | writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0); | |
368 | } | |
0642bac7 RL |
369 | |
370 | /* 47.4.1.4.5 | |
371 | * Once complete, the controller will clear BUSY. A write request to a | |
372 | * protected or locked region will result in no OTP access and no | |
373 | * setting of HW_OCOTP_CTRL[BUSY]. In addition HW_OCOTP_CTRL[ERROR] will | |
374 | * be set. It must be cleared by software before any new write access | |
375 | * can be issued. | |
376 | */ | |
377 | ret = imx_ocotp_wait_for_busy(priv->base, 0); | |
378 | if (ret < 0) { | |
379 | if (ret == -EPERM) { | |
380 | dev_err(priv->dev, "failed write to locked region"); | |
381 | imx_ocotp_clr_err_if_set(priv->base); | |
382 | } else { | |
383 | dev_err(priv->dev, "timeout during data write\n"); | |
384 | } | |
385 | goto write_end; | |
386 | } | |
387 | ||
388 | /* 47.3.1.4 | |
389 | * Write Postamble: Due to internal electrical characteristics of the | |
390 | * OTP during writes, all OTP operations following a write must be | |
391 | * separated by 2 us after the clearing of HW_OCOTP_CTRL_BUSY following | |
392 | * the write. | |
393 | */ | |
394 | udelay(2); | |
395 | ||
396 | /* reload all shadow registers */ | |
397 | writel(IMX_OCOTP_BM_CTRL_REL_SHADOWS, | |
398 | priv->base + IMX_OCOTP_ADDR_CTRL_SET); | |
399 | ret = imx_ocotp_wait_for_busy(priv->base, | |
400 | IMX_OCOTP_BM_CTRL_REL_SHADOWS); | |
401 | if (ret < 0) { | |
402 | dev_err(priv->dev, "timeout during shadow register reload\n"); | |
403 | goto write_end; | |
404 | } | |
405 | ||
406 | write_end: | |
407 | clk_disable_unprepare(priv->clk); | |
408 | mutex_unlock(&ocotp_mutex); | |
409 | if (ret < 0) | |
410 | return ret; | |
411 | return bytes; | |
3edba6b4 PZ |
412 | } |
413 | ||
3edba6b4 PZ |
414 | static struct nvmem_config imx_ocotp_nvmem_config = { |
415 | .name = "imx-ocotp", | |
0642bac7 | 416 | .read_only = false, |
33e5e29c SK |
417 | .word_size = 4, |
418 | .stride = 4, | |
33e5e29c | 419 | .reg_read = imx_ocotp_read, |
0642bac7 | 420 | .reg_write = imx_ocotp_write, |
3edba6b4 PZ |
421 | }; |
422 | ||
e20d2b29 BD |
423 | static const struct ocotp_params imx6q_params = { |
424 | .nregs = 128, | |
ffd9115f | 425 | .bank_address_words = 0, |
828ae7a4 | 426 | .set_timing = imx_ocotp_set_imx6_timing, |
e20d2b29 BD |
427 | }; |
428 | ||
429 | static const struct ocotp_params imx6sl_params = { | |
430 | .nregs = 64, | |
ffd9115f | 431 | .bank_address_words = 0, |
828ae7a4 | 432 | .set_timing = imx_ocotp_set_imx6_timing, |
e20d2b29 BD |
433 | }; |
434 | ||
6da27821 AH |
435 | static const struct ocotp_params imx6sll_params = { |
436 | .nregs = 128, | |
437 | .bank_address_words = 0, | |
438 | .set_timing = imx_ocotp_set_imx6_timing, | |
439 | }; | |
440 | ||
e20d2b29 BD |
441 | static const struct ocotp_params imx6sx_params = { |
442 | .nregs = 128, | |
ffd9115f | 443 | .bank_address_words = 0, |
828ae7a4 | 444 | .set_timing = imx_ocotp_set_imx6_timing, |
e20d2b29 BD |
445 | }; |
446 | ||
447 | static const struct ocotp_params imx6ul_params = { | |
448 | .nregs = 128, | |
ffd9115f | 449 | .bank_address_words = 0, |
828ae7a4 | 450 | .set_timing = imx_ocotp_set_imx6_timing, |
e20d2b29 BD |
451 | }; |
452 | ||
ffbc34bf SW |
453 | static const struct ocotp_params imx6ull_params = { |
454 | .nregs = 64, | |
455 | .bank_address_words = 0, | |
456 | .set_timing = imx_ocotp_set_imx6_timing, | |
457 | }; | |
458 | ||
e20d2b29 BD |
459 | static const struct ocotp_params imx7d_params = { |
460 | .nregs = 64, | |
ffd9115f | 461 | .bank_address_words = 4, |
828ae7a4 | 462 | .set_timing = imx_ocotp_set_imx7_timing, |
e20d2b29 BD |
463 | }; |
464 | ||
c8b63ddc AH |
465 | static const struct ocotp_params imx7ulp_params = { |
466 | .nregs = 256, | |
467 | .bank_address_words = 0, | |
468 | }; | |
469 | ||
38e7b6ef LS |
470 | static const struct ocotp_params imx8mq_params = { |
471 | .nregs = 256, | |
5a1c1724 LC |
472 | .bank_address_words = 0, |
473 | .set_timing = imx_ocotp_set_imx6_timing, | |
38e7b6ef LS |
474 | }; |
475 | ||
4112c853 BD |
476 | static const struct ocotp_params imx8mm_params = { |
477 | .nregs = 256, | |
478 | .bank_address_words = 0, | |
479 | .set_timing = imx_ocotp_set_imx6_timing, | |
480 | }; | |
481 | ||
3edba6b4 | 482 | static const struct of_device_id imx_ocotp_dt_ids[] = { |
e20d2b29 BD |
483 | { .compatible = "fsl,imx6q-ocotp", .data = &imx6q_params }, |
484 | { .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params }, | |
485 | { .compatible = "fsl,imx6sx-ocotp", .data = &imx6sx_params }, | |
486 | { .compatible = "fsl,imx6ul-ocotp", .data = &imx6ul_params }, | |
ffbc34bf | 487 | { .compatible = "fsl,imx6ull-ocotp", .data = &imx6ull_params }, |
e20d2b29 | 488 | { .compatible = "fsl,imx7d-ocotp", .data = &imx7d_params }, |
6da27821 | 489 | { .compatible = "fsl,imx6sll-ocotp", .data = &imx6sll_params }, |
c8b63ddc | 490 | { .compatible = "fsl,imx7ulp-ocotp", .data = &imx7ulp_params }, |
38e7b6ef | 491 | { .compatible = "fsl,imx8mq-ocotp", .data = &imx8mq_params }, |
4112c853 | 492 | { .compatible = "fsl,imx8mm-ocotp", .data = &imx8mm_params }, |
3edba6b4 PZ |
493 | { }, |
494 | }; | |
495 | MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids); | |
496 | ||
497 | static int imx_ocotp_probe(struct platform_device *pdev) | |
498 | { | |
3edba6b4 | 499 | struct device *dev = &pdev->dev; |
3edba6b4 PZ |
500 | struct ocotp_priv *priv; |
501 | struct nvmem_device *nvmem; | |
502 | ||
503 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
504 | if (!priv) | |
505 | return -ENOMEM; | |
506 | ||
4cefb74a RL |
507 | priv->dev = dev; |
508 | ||
3b26cd88 | 509 | priv->base = devm_platform_ioremap_resource(pdev, 0); |
3edba6b4 PZ |
510 | if (IS_ERR(priv->base)) |
511 | return PTR_ERR(priv->base); | |
512 | ||
4cefb74a | 513 | priv->clk = devm_clk_get(dev, NULL); |
deb31970 PF |
514 | if (IS_ERR(priv->clk)) |
515 | return PTR_ERR(priv->clk); | |
516 | ||
e20d2b29 BD |
517 | priv->params = of_device_get_match_data(&pdev->dev); |
518 | imx_ocotp_nvmem_config.size = 4 * priv->params->nregs; | |
3edba6b4 | 519 | imx_ocotp_nvmem_config.dev = dev; |
33e5e29c | 520 | imx_ocotp_nvmem_config.priv = priv; |
0642bac7 | 521 | priv->config = &imx_ocotp_nvmem_config; |
a830274f | 522 | nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config); |
0642bac7 | 523 | |
3edba6b4 | 524 | |
a830274f | 525 | return PTR_ERR_OR_ZERO(nvmem); |
3edba6b4 PZ |
526 | } |
527 | ||
528 | static struct platform_driver imx_ocotp_driver = { | |
529 | .probe = imx_ocotp_probe, | |
3edba6b4 PZ |
530 | .driver = { |
531 | .name = "imx_ocotp", | |
532 | .of_match_table = imx_ocotp_dt_ids, | |
533 | }, | |
534 | }; | |
535 | module_platform_driver(imx_ocotp_driver); | |
536 | ||
537 | MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>"); | |
aef9a4de | 538 | MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver"); |
3edba6b4 | 539 | MODULE_LICENSE("GPL v2"); |