[mirror_ubuntu-bionic-kernel.git] / drivers / nvmem / imx-ocotp.c

/*
 * i.MX6 OCOTP fusebox driver
 *
 * Copyright (c) 2015 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
 *
 * Based on the barebox ocotp driver,
 * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>,
 *	Orex Computed Radiography
 *
 * Write support based on the fsl_otp driver,
 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2
 * as published by the Free Software Foundation.
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/nvmem-provider.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/delay.h>

#define IMX_OCOTP_OFFSET_B0W0		0x400 /* Offset from base address of the
					       * OTP Bank0 Word0
					       */
#define IMX_OCOTP_OFFSET_PER_WORD	0x10  /* Offset between the start addr
					       * of two consecutive OTP words.
					       */

#define IMX_OCOTP_ADDR_CTRL		0x0000
#define IMX_OCOTP_ADDR_CTRL_SET		0x0004
#define IMX_OCOTP_ADDR_CTRL_CLR		0x0008
#define IMX_OCOTP_ADDR_TIMING		0x0010
#define IMX_OCOTP_ADDR_DATA0		0x0020
#define IMX_OCOTP_ADDR_DATA1		0x0030
#define IMX_OCOTP_ADDR_DATA2		0x0040
#define IMX_OCOTP_ADDR_DATA3		0x0050

#define IMX_OCOTP_BM_CTRL_ADDR		0x0000007F
#define IMX_OCOTP_BM_CTRL_BUSY		0x00000100
#define IMX_OCOTP_BM_CTRL_ERROR		0x00000200
#define IMX_OCOTP_BM_CTRL_REL_SHADOWS	0x00000400

#define DEF_RELAX			20	/* > 16.5ns */
#define DEF_FSOURCE			1001	/* > 1000 ns */
#define DEF_STROBE_PROG			10000	/* IPG clocks */
#define IMX_OCOTP_WR_UNLOCK		0x3E770000
#define IMX_OCOTP_READ_LOCKED_VAL	0xBADABADA

static DEFINE_MUTEX(ocotp_mutex);

struct ocotp_priv {
	struct device *dev;
	struct clk *clk;
	void __iomem *base;
	const struct ocotp_params *params;
	struct nvmem_config *config;
};

struct ocotp_params {
	unsigned int nregs;
	unsigned int bank_address_words;
	void (*set_timing)(struct ocotp_priv *priv);
};

static int imx_ocotp_wait_for_busy(void __iomem *base, u32 flags)
{
	int count;
	u32 c, mask;

	mask = IMX_OCOTP_BM_CTRL_BUSY | IMX_OCOTP_BM_CTRL_ERROR | flags;

	for (count = 10000; count >= 0; count--) {
		c = readl(base + IMX_OCOTP_ADDR_CTRL);
		if (!(c & mask))
			break;
		cpu_relax();
	}

	if (count < 0) {
		/* HW_OCOTP_CTRL[ERROR] will be set under the following
		 * conditions:
		 * - A write is performed to a shadow register during a shadow
		 *   reload (essentially, while HW_OCOTP_CTRL[RELOAD_SHADOWS] is
		 *   set. In addition, the contents of the shadow register shall
		 *   not be updated.
		 * - A write is performed to a shadow register which has been
		 *   locked.
		 * - A read is performed to from a shadow register which has
		 *   been read locked.
		 * - A program is performed to a fuse word which has been locked
		 * - A read is performed to from a fuse word which has been read
		 *   locked.
		 */
		if (c & IMX_OCOTP_BM_CTRL_ERROR)
			return -EPERM;
		return -ETIMEDOUT;
	}

	return 0;
}

static void imx_ocotp_clr_err_if_set(void __iomem *base)
{
	u32 c;

	c = readl(base + IMX_OCOTP_ADDR_CTRL);
	if (!(c & IMX_OCOTP_BM_CTRL_ERROR))
		return;

	writel(IMX_OCOTP_BM_CTRL_ERROR, base + IMX_OCOTP_ADDR_CTRL_CLR);
}

static int imx_ocotp_read(void *context, unsigned int offset,
			  void *val, size_t bytes)
{
	struct ocotp_priv *priv = context;
	unsigned int count;
	u32 *buf = val;
	int i, ret;
	u32 index;

	index = offset >> 2;
	count = bytes >> 2;

	if (count > (priv->params->nregs - index))
		count = priv->params->nregs - index;

	mutex_lock(&ocotp_mutex);

	ret = clk_prepare_enable(priv->clk);
	if (ret < 0) {
		mutex_unlock(&ocotp_mutex);
		dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
		return ret;
	}

	ret = imx_ocotp_wait_for_busy(priv->base, 0);
	if (ret < 0) {
		dev_err(priv->dev, "timeout during read setup\n");
		goto read_end;
	}

	for (i = index; i < (index + count); i++) {
		*buf++ = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 +
			       i * IMX_OCOTP_OFFSET_PER_WORD);

		/* 47.3.1.2
		 * For "read locked" registers 0xBADABADA will be returned and
		 * HW_OCOTP_CTRL[ERROR] will be set. It must be cleared by
		 * software before any new write, read or reload access can be
		 * issued
		 */
		if (*(buf - 1) == IMX_OCOTP_READ_LOCKED_VAL)
			imx_ocotp_clr_err_if_set(priv->base);
	}
	ret = 0;

read_end:
	clk_disable_unprepare(priv->clk);
	mutex_unlock(&ocotp_mutex);
	return ret;
}

static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv)
{
	unsigned long clk_rate = 0;
	unsigned long strobe_read, relax, strobe_prog;
	u32 timing = 0;

	/* 47.3.1.3.1
	 * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX]
	 * fields with timing values to match the current frequency of the
	 * ipg_clk. OTP writes will work at maximum bus frequencies as long
	 * as the HW_OCOTP_TIMING parameters are set correctly.
	 */
	clk_rate = clk_get_rate(priv->clk);

	relax = clk_rate / (1000000000 / DEF_RELAX) - 1;
	strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1;
	strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1;

	timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000;
	timing |= strobe_prog & 0x00000FFF;
	timing |= (relax       << 12) & 0x0000F000;
	timing |= (strobe_read << 16) & 0x003F0000;

	writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
}

static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv)
{
	unsigned long clk_rate = 0;
	u64 fsource, strobe_prog;
	u32 timing = 0;

	/* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1
	 * 6.4.3.3
	 */
	clk_rate = clk_get_rate(priv->clk);
	fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE,
				   NSEC_PER_SEC) + 1;
	strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG,
					    NSEC_PER_SEC) + 1;

	timing = strobe_prog & 0x00000FFF;
	timing |= (fsource << 12) & 0x000FF000;

	writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
}

static int imx_ocotp_write(void *context, unsigned int offset, void *val,
			   size_t bytes)
{
	struct ocotp_priv *priv = context;
	u32 *buf = val;
	int ret;

	u32 ctrl;
	u8 waddr;
	u8 word = 0;

	/* allow only writing one complete OTP word at a time */
	if ((bytes != priv->config->word_size) ||
	    (offset % priv->config->word_size))
		return -EINVAL;

	mutex_lock(&ocotp_mutex);

	ret = clk_prepare_enable(priv->clk);
	if (ret < 0) {
		mutex_unlock(&ocotp_mutex);
		dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
		return ret;
	}

	/* Setup the write timing values */
	priv->params->set_timing(priv);

	/* 47.3.1.3.2
	 * Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear.
	 * Overlapped accesses are not supported by the controller. Any pending
	 * write or reload must be completed before a write access can be
	 * requested.
	 */
	ret = imx_ocotp_wait_for_busy(priv->base, 0);
	if (ret < 0) {
		dev_err(priv->dev, "timeout during timing setup\n");
		goto write_end;
	}

	/* 47.3.1.3.3
	 * Write the requested address to HW_OCOTP_CTRL[ADDR] and program the
	 * unlock code into HW_OCOTP_CTRL[WR_UNLOCK]. This must be programmed
	 * for each write access. The lock code is documented in the register
	 * description. Both the unlock code and address can be written in the
	 * same operation.
	 */
	if (priv->params->bank_address_words != 0) {
		/*
		 * In banked/i.MX7 mode the OTP register bank goes into waddr
		 * see i.MX 7Solo Applications Processor Reference Manual, Rev.
		 * 0.1 section 6.4.3.1
		 */
		offset = offset / priv->config->word_size;
		waddr = offset / priv->params->bank_address_words;
		word  = offset & (priv->params->bank_address_words - 1);
	} else {
		/*
		 * Non-banked i.MX6 mode.
		 * OTP write/read address specifies one of 128 word address
		 * locations
		 */
		waddr = offset / 4;
	}

	ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL);
	ctrl &= ~IMX_OCOTP_BM_CTRL_ADDR;
	ctrl |= waddr & IMX_OCOTP_BM_CTRL_ADDR;
	ctrl |= IMX_OCOTP_WR_UNLOCK;

	writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL);

	/* 47.3.1.3.4
	 * Write the data to the HW_OCOTP_DATA register. This will automatically
	 * set HW_OCOTP_CTRL[BUSY] and clear HW_OCOTP_CTRL[WR_UNLOCK]. To
	 * protect programming same OTP bit twice, before program OCOTP will
	 * automatically read fuse value in OTP and use read value to mask
	 * program data. The controller will use masked program data to program
	 * a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit
	 * fields with 1's will result in that OTP bit being programmed. Bit
	 * fields with 0's will be ignored. At the same time that the write is
	 * accepted, the controller makes an internal copy of
	 * HW_OCOTP_CTRL[ADDR] which cannot be updated until the next write
	 * sequence is initiated. This copy guarantees that erroneous writes to
	 * HW_OCOTP_CTRL[ADDR] will not affect an active write operation. It
	 * should also be noted that during the programming HW_OCOTP_DATA will
	 * shift right (with zero fill). This shifting is required to program
	 * the OTP serially. During the write operation, HW_OCOTP_DATA cannot be
	 * modified.
	 * Note: on i.MX7 there are four data fields to write for banked write
	 *       with the fuse blowing operation only taking place after data0
	 *	 has been written. This is why data0 must always be the last
	 *	 register written.
	 */
	if (priv->params->bank_address_words != 0) {
		/* Banked/i.MX7 mode */
		switch (word) {
		case 0:
			writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
			writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
			writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
			writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
			break;
		case 1:
			writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1);
			writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
			writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
			writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
			break;
		case 2:
			writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
			writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2);
			writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
			writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
			break;
		case 3:
			writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
			writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
			writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3);
			writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
			break;
		}
	} else {
		/* Non-banked i.MX6 mode */
		writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
	}

	/* 47.4.1.4.5
	 * Once complete, the controller will clear BUSY. A write request to a
	 * protected or locked region will result in no OTP access and no
	 * setting of HW_OCOTP_CTRL[BUSY]. In addition HW_OCOTP_CTRL[ERROR] will
	 * be set. It must be cleared by software before any new write access
	 * can be issued.
	 */
	ret = imx_ocotp_wait_for_busy(priv->base, 0);
	if (ret < 0) {
		if (ret == -EPERM) {
			dev_err(priv->dev, "failed write to locked region");
			imx_ocotp_clr_err_if_set(priv->base);
		} else {
			dev_err(priv->dev, "timeout during data write\n");
		}
		goto write_end;
	}

	/* 47.3.1.4
	 * Write Postamble: Due to internal electrical characteristics of the
	 * OTP during writes, all OTP operations following a write must be
	 * separated by 2 us after the clearing of HW_OCOTP_CTRL_BUSY following
	 * the write.
	 */
	udelay(2);

	/* reload all shadow registers */
	writel(IMX_OCOTP_BM_CTRL_REL_SHADOWS,
	       priv->base + IMX_OCOTP_ADDR_CTRL_SET);
	ret = imx_ocotp_wait_for_busy(priv->base,
				      IMX_OCOTP_BM_CTRL_REL_SHADOWS);
	if (ret < 0) {
		dev_err(priv->dev, "timeout during shadow register reload\n");
		goto write_end;
	}

write_end:
	clk_disable_unprepare(priv->clk);
	mutex_unlock(&ocotp_mutex);
	if (ret < 0)
		return ret;
	return bytes;
}

static struct nvmem_config imx_ocotp_nvmem_config = {
	.name = "imx-ocotp",
	.read_only = false,
	.word_size = 4,
	.stride = 4,
	.reg_read = imx_ocotp_read,
	.reg_write = imx_ocotp_write,
};

static const struct ocotp_params imx6q_params = {
	.nregs = 128,
	.bank_address_words = 0,
	.set_timing = imx_ocotp_set_imx6_timing,
};

static const struct ocotp_params imx6sl_params = {
	.nregs = 64,
	.bank_address_words = 0,
	.set_timing = imx_ocotp_set_imx6_timing,
};

static const struct ocotp_params imx6sx_params = {
	.nregs = 128,
	.bank_address_words = 0,
	.set_timing = imx_ocotp_set_imx6_timing,
};

static const struct ocotp_params imx6ul_params = {
	.nregs = 128,
	.bank_address_words = 0,
	.set_timing = imx_ocotp_set_imx6_timing,
};

static const struct ocotp_params imx7d_params = {
	.nregs = 64,
	.bank_address_words = 4,
	.set_timing = imx_ocotp_set_imx7_timing,
};

static const struct of_device_id imx_ocotp_dt_ids[] = {
	{ .compatible = "fsl,imx6q-ocotp",  .data = &imx6q_params },
	{ .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params },
	{ .compatible = "fsl,imx6sx-ocotp", .data = &imx6sx_params },
	{ .compatible = "fsl,imx6ul-ocotp", .data = &imx6ul_params },
	{ .compatible = "fsl,imx7d-ocotp",  .data = &imx7d_params },
	{ },
};
MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);

static int imx_ocotp_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id;
	struct device *dev = &pdev->dev;
	struct resource *res;
	struct ocotp_priv *priv;
	struct nvmem_device *nvmem;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->dev = dev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(priv->base))
		return PTR_ERR(priv->base);

	priv->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(priv->clk))
		return PTR_ERR(priv->clk);

	clk_prepare_enable(priv->clk);
	imx_ocotp_clr_err_if_set(priv->base);
	clk_disable_unprepare(priv->clk);

	of_id = of_match_device(imx_ocotp_dt_ids, dev);
	priv->params = of_device_get_match_data(&pdev->dev);
	imx_ocotp_nvmem_config.size = 4 * priv->params->nregs;
	imx_ocotp_nvmem_config.dev = dev;
	imx_ocotp_nvmem_config.priv = priv;
	priv->config = &imx_ocotp_nvmem_config;
	nvmem = nvmem_register(&imx_ocotp_nvmem_config);

	if (IS_ERR(nvmem))
		return PTR_ERR(nvmem);

	platform_set_drvdata(pdev, nvmem);

	return 0;
}

static int imx_ocotp_remove(struct platform_device *pdev)
{
	struct nvmem_device *nvmem = platform_get_drvdata(pdev);

	return nvmem_unregister(nvmem);
}

static struct platform_driver imx_ocotp_driver = {
	.probe	= imx_ocotp_probe,
	.remove	= imx_ocotp_remove,
	.driver = {
		.name	= "imx_ocotp",
		.of_match_table = imx_ocotp_dt_ids,
	},
};
module_platform_driver(imx_ocotp_driver);

MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
3edba6b4 PZ	1	/*
	2	* i.MX6 OCOTP fusebox driver
	3	*
	4	* Copyright (c) 2015 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
	5	*
	6	* Based on the barebox ocotp driver,
	7	* Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>,
	8	* Orex Computed Radiography
	9	*
0642bac7 RL	10	* Write support based on the fsl_otp driver,
	11	* Copyright (C) 2010-2013 Freescale Semiconductor, Inc
	12	*
3edba6b4 PZ	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License version 2
	15	* as published by the Free Software Foundation.
	16	*
	17	* http://www.opensource.org/licenses/gpl-license.html
	18	* http://www.gnu.org/copyleft/gpl.html
	19	*/
	20
deb31970	21	#include <linux/clk.h>
3edba6b4 PZ	22	#include <linux/device.h>
	23	#include <linux/io.h>
	24	#include <linux/module.h>
	25	#include <linux/nvmem-provider.h>
	26	#include <linux/of.h>
	27	#include <linux/of_device.h>
	28	#include <linux/platform_device.h>
3edba6b4	29	#include <linux/slab.h>
0642bac7	30	#include <linux/delay.h>
3edba6b4	31
9b66587e RL	32	#define IMX_OCOTP_OFFSET_B0W0 0x400 /* Offset from base address of the
	33	* OTP Bank0 Word0
	34	*/
	35	#define IMX_OCOTP_OFFSET_PER_WORD 0x10 /* Offset between the start addr
	36	* of two consecutive OTP words.
	37	*/
0642bac7	38
9b66587e	39	#define IMX_OCOTP_ADDR_CTRL 0x0000
0642bac7	40	#define IMX_OCOTP_ADDR_CTRL_SET 0x0004
9b66587e	41	#define IMX_OCOTP_ADDR_CTRL_CLR 0x0008
0642bac7	42	#define IMX_OCOTP_ADDR_TIMING 0x0010
ffd9115f BD	43	#define IMX_OCOTP_ADDR_DATA0 0x0020
	44	#define IMX_OCOTP_ADDR_DATA1 0x0030
	45	#define IMX_OCOTP_ADDR_DATA2 0x0040
	46	#define IMX_OCOTP_ADDR_DATA3 0x0050
9b66587e	47
0642bac7 RL	48	#define IMX_OCOTP_BM_CTRL_ADDR 0x0000007F
0642bac7 RL	49	#define IMX_OCOTP_BM_CTRL_BUSY 0x00000100
9b66587e	50	#define IMX_OCOTP_BM_CTRL_ERROR 0x00000200
0642bac7	51	#define IMX_OCOTP_BM_CTRL_REL_SHADOWS 0x00000400
9b66587e	52
828ae7a4 BD	53	#define DEF_RELAX 20 /* > 16.5ns */
	54	#define DEF_FSOURCE 1001 /* > 1000 ns */
	55	#define DEF_STROBE_PROG 10000 /* IPG clocks */
0642bac7	56	#define IMX_OCOTP_WR_UNLOCK 0x3E770000
9b66587e RL	57	#define IMX_OCOTP_READ_LOCKED_VAL 0xBADABADA
9b66587e RL	58
0642bac7 RL	59	static DEFINE_MUTEX(ocotp_mutex);
0642bac7 RL	60
3edba6b4 PZ	61	struct ocotp_priv {
3edba6b4 PZ	62	struct device *dev;
deb31970	63	struct clk *clk;
3edba6b4	64	void __iomem *base;
e20d2b29	65	const struct ocotp_params *params;
0642bac7	66	struct nvmem_config *config;
3edba6b4 PZ	67	};
3edba6b4 PZ	68
828ae7a4 BD	69	struct ocotp_params {
	70	unsigned int nregs;
	71	unsigned int bank_address_words;
	72	void (set_timing)(struct ocotp_priv priv);
	73	};
	74
0642bac7 RL	75	static int imx_ocotp_wait_for_busy(void __iomem *base, u32 flags)
	76	{
	77	int count;
	78	u32 c, mask;
	79
	80	mask = IMX_OCOTP_BM_CTRL_BUSY \| IMX_OCOTP_BM_CTRL_ERROR \| flags;
	81
	82	for (count = 10000; count >= 0; count--) {
	83	c = readl(base + IMX_OCOTP_ADDR_CTRL);
	84	if (!(c & mask))
	85	break;
	86	cpu_relax();
	87	}
	88
	89	if (count < 0) {
	90	/* HW_OCOTP_CTRL[ERROR] will be set under the following
	91	* conditions:
	92	* - A write is performed to a shadow register during a shadow
	93	* reload (essentially, while HW_OCOTP_CTRL[RELOAD_SHADOWS] is
	94	* set. In addition, the contents of the shadow register shall
	95	* not be updated.
	96	* - A write is performed to a shadow register which has been
	97	* locked.
	98	* - A read is performed to from a shadow register which has
	99	* been read locked.
	100	* - A program is performed to a fuse word which has been locked
	101	* - A read is performed to from a fuse word which has been read
	102	* locked.
	103	*/
	104	if (c & IMX_OCOTP_BM_CTRL_ERROR)
	105	return -EPERM;
	106	return -ETIMEDOUT;
	107	}
	108
	109	return 0;
	110	}
	111
9b66587e RL	112	static void imx_ocotp_clr_err_if_set(void __iomem *base)
	113	{
	114	u32 c;
	115
	116	c = readl(base + IMX_OCOTP_ADDR_CTRL);
	117	if (!(c & IMX_OCOTP_BM_CTRL_ERROR))
	118	return;
	119
	120	writel(IMX_OCOTP_BM_CTRL_ERROR, base + IMX_OCOTP_ADDR_CTRL_CLR);
	121	}
	122
33e5e29c SK	123	static int imx_ocotp_read(void *context, unsigned int offset,
33e5e29c SK	124	void *val, size_t bytes)
3edba6b4 PZ	125	{
3edba6b4 PZ	126	struct ocotp_priv *priv = context;
3edba6b4	127	unsigned int count;
33e5e29c	128	u32 *buf = val;
deb31970	129	int i, ret;
3edba6b4 PZ	130	u32 index;
	131
	132	index = offset >> 2;
33e5e29c	133	count = bytes >> 2;
3edba6b4	134
e20d2b29 BD	135	if (count > (priv->params->nregs - index))
e20d2b29 BD	136	count = priv->params->nregs - index;
3edba6b4	137
0642bac7 RL	138	mutex_lock(&ocotp_mutex);
0642bac7 RL	139
deb31970 PF	140	ret = clk_prepare_enable(priv->clk);
deb31970 PF	141	if (ret < 0) {
0642bac7	142	mutex_unlock(&ocotp_mutex);
deb31970 PF	143	dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
	144	return ret;
	145	}
3edba6b4	146
0642bac7 RL	147	ret = imx_ocotp_wait_for_busy(priv->base, 0);
	148	if (ret < 0) {
	149	dev_err(priv->dev, "timeout during read setup\n");
	150	goto read_end;
	151	}
	152
9b66587e RL	153	for (i = index; i < (index + count); i++) {
	154	*buf++ = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 +
	155	i * IMX_OCOTP_OFFSET_PER_WORD);
deb31970	156
9b66587e RL	157	/* 47.3.1.2
	158	* For "read locked" registers 0xBADABADA will be returned and
	159	* HW_OCOTP_CTRL[ERROR] will be set. It must be cleared by
	160	* software before any new write, read or reload access can be
	161	* issued
	162	*/
	163	if (*(buf - 1) == IMX_OCOTP_READ_LOCKED_VAL)
	164	imx_ocotp_clr_err_if_set(priv->base);
	165	}
0642bac7	166	ret = 0;
9b66587e	167
0642bac7	168	read_end:
9b66587e	169	clk_disable_unprepare(priv->clk);
0642bac7 RL	170	mutex_unlock(&ocotp_mutex);
	171	return ret;
	172	}
	173
b50cb68f BD	174	static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv)
	175	{
	176	unsigned long clk_rate = 0;
	177	unsigned long strobe_read, relax, strobe_prog;
	178	u32 timing = 0;
	179
	180	/* 47.3.1.3.1
	181	* Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX]
	182	* fields with timing values to match the current frequency of the
	183	* ipg_clk. OTP writes will work at maximum bus frequencies as long
	184	* as the HW_OCOTP_TIMING parameters are set correctly.
	185	*/
	186	clk_rate = clk_get_rate(priv->clk);
	187
	188	relax = clk_rate / (1000000000 / DEF_RELAX) - 1;
	189	strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1;
	190	strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1;
	191
f23a1f22 BD	192	timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000;
f23a1f22 BD	193	timing \|= strobe_prog & 0x00000FFF;
b50cb68f BD	194	timing \|= (relax << 12) & 0x0000F000;
	195	timing \|= (strobe_read << 16) & 0x003F0000;
	196
	197	writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
	198	}
	199
828ae7a4 BD	200	static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv)
	201	{
	202	unsigned long clk_rate = 0;
	203	u64 fsource, strobe_prog;
	204	u32 timing = 0;
	205
	206	/* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1
	207	* 6.4.3.3
	208	*/
	209	clk_rate = clk_get_rate(priv->clk);
	210	fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE,
	211	NSEC_PER_SEC) + 1;
	212	strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG,
	213	NSEC_PER_SEC) + 1;
	214
	215	timing = strobe_prog & 0x00000FFF;
	216	timing \|= (fsource << 12) & 0x000FF000;
	217
	218	writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
	219	}
	220
0642bac7 RL	221	static int imx_ocotp_write(void context, unsigned int offset, void val,
	222	size_t bytes)
	223	{
	224	struct ocotp_priv *priv = context;
	225	u32 *buf = val;
	226	int ret;
	227
0642bac7 RL	228	u32 ctrl;
0642bac7 RL	229	u8 waddr;
ffd9115f	230	u8 word = 0;
0642bac7 RL	231
	232	/* allow only writing one complete OTP word at a time */
	233	if ((bytes != priv->config->word_size) \|\|
	234	(offset % priv->config->word_size))
	235	return -EINVAL;
	236
	237	mutex_lock(&ocotp_mutex);
	238
	239	ret = clk_prepare_enable(priv->clk);
	240	if (ret < 0) {
	241	mutex_unlock(&ocotp_mutex);
	242	dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
	243	return ret;
	244	}
	245
b50cb68f	246	/* Setup the write timing values */
828ae7a4	247	priv->params->set_timing(priv);
0642bac7 RL	248
	249	/* 47.3.1.3.2
	250	* Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear.
	251	* Overlapped accesses are not supported by the controller. Any pending
	252	* write or reload must be completed before a write access can be
	253	* requested.
	254	*/
	255	ret = imx_ocotp_wait_for_busy(priv->base, 0);
	256	if (ret < 0) {
	257	dev_err(priv->dev, "timeout during timing setup\n");
	258	goto write_end;
	259	}
	260
	261	/* 47.3.1.3.3
	262	* Write the requested address to HW_OCOTP_CTRL[ADDR] and program the
	263	* unlock code into HW_OCOTP_CTRL[WR_UNLOCK]. This must be programmed
	264	* for each write access. The lock code is documented in the register
	265	* description. Both the unlock code and address can be written in the
	266	* same operation.
	267	*/
ffd9115f BD	268	if (priv->params->bank_address_words != 0) {
	269	/*
	270	* In banked/i.MX7 mode the OTP register bank goes into waddr
	271	* see i.MX 7Solo Applications Processor Reference Manual, Rev.
	272	* 0.1 section 6.4.3.1
	273	*/
	274	offset = offset / priv->config->word_size;
	275	waddr = offset / priv->params->bank_address_words;
	276	word = offset & (priv->params->bank_address_words - 1);
	277	} else {
	278	/*
	279	* Non-banked i.MX6 mode.
	280	* OTP write/read address specifies one of 128 word address
	281	* locations
	282	*/
	283	waddr = offset / 4;
	284	}
0642bac7 RL	285
	286	ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL);
	287	ctrl &= ~IMX_OCOTP_BM_CTRL_ADDR;
	288	ctrl \|= waddr & IMX_OCOTP_BM_CTRL_ADDR;
	289	ctrl \|= IMX_OCOTP_WR_UNLOCK;
	290
	291	writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL);
	292
	293	/* 47.3.1.3.4
	294	* Write the data to the HW_OCOTP_DATA register. This will automatically
	295	* set HW_OCOTP_CTRL[BUSY] and clear HW_OCOTP_CTRL[WR_UNLOCK]. To
	296	* protect programming same OTP bit twice, before program OCOTP will
	297	* automatically read fuse value in OTP and use read value to mask
	298	* program data. The controller will use masked program data to program
	299	* a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit
	300	* fields with 1's will result in that OTP bit being programmed. Bit
	301	* fields with 0's will be ignored. At the same time that the write is
	302	* accepted, the controller makes an internal copy of
	303	* HW_OCOTP_CTRL[ADDR] which cannot be updated until the next write
	304	* sequence is initiated. This copy guarantees that erroneous writes to
	305	* HW_OCOTP_CTRL[ADDR] will not affect an active write operation. It
	306	* should also be noted that during the programming HW_OCOTP_DATA will
	307	* shift right (with zero fill). This shifting is required to program
	308	* the OTP serially. During the write operation, HW_OCOTP_DATA cannot be
	309	* modified.
ffd9115f BD	310	* Note: on i.MX7 there are four data fields to write for banked write
	311	* with the fuse blowing operation only taking place after data0
	312	* has been written. This is why data0 must always be the last
	313	* register written.
0642bac7	314	*/
ffd9115f BD	315	if (priv->params->bank_address_words != 0) {
	316	/* Banked/i.MX7 mode */
	317	switch (word) {
	318	case 0:
	319	writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
	320	writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
	321	writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
	322	writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
	323	break;
	324	case 1:
	325	writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1);
	326	writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
	327	writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
	328	writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
	329	break;
	330	case 2:
	331	writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
	332	writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2);
	333	writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
	334	writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
	335	break;
	336	case 3:
	337	writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
	338	writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
	339	writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3);
	340	writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
	341	break;
	342	}
	343	} else {
	344	/* Non-banked i.MX6 mode */
	345	writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
	346	}
0642bac7 RL	347
	348	/* 47.4.1.4.5
	349	* Once complete, the controller will clear BUSY. A write request to a
	350	* protected or locked region will result in no OTP access and no
	351	* setting of HW_OCOTP_CTRL[BUSY]. In addition HW_OCOTP_CTRL[ERROR] will
	352	* be set. It must be cleared by software before any new write access
	353	* can be issued.
	354	*/
	355	ret = imx_ocotp_wait_for_busy(priv->base, 0);
	356	if (ret < 0) {
	357	if (ret == -EPERM) {
	358	dev_err(priv->dev, "failed write to locked region");
	359	imx_ocotp_clr_err_if_set(priv->base);
	360	} else {
	361	dev_err(priv->dev, "timeout during data write\n");
	362	}
	363	goto write_end;
	364	}
	365
	366	/* 47.3.1.4
	367	* Write Postamble: Due to internal electrical characteristics of the
	368	* OTP during writes, all OTP operations following a write must be
	369	* separated by 2 us after the clearing of HW_OCOTP_CTRL_BUSY following
	370	* the write.
	371	*/
	372	udelay(2);
	373
	374	/* reload all shadow registers */
	375	writel(IMX_OCOTP_BM_CTRL_REL_SHADOWS,
	376	priv->base + IMX_OCOTP_ADDR_CTRL_SET);
	377	ret = imx_ocotp_wait_for_busy(priv->base,
	378	IMX_OCOTP_BM_CTRL_REL_SHADOWS);
	379	if (ret < 0) {
	380	dev_err(priv->dev, "timeout during shadow register reload\n");
	381	goto write_end;
	382	}
	383
	384	write_end:
	385	clk_disable_unprepare(priv->clk);
	386	mutex_unlock(&ocotp_mutex);
	387	if (ret < 0)
	388	return ret;
	389	return bytes;
3edba6b4 PZ	390	}
3edba6b4 PZ	391
3edba6b4 PZ	392	static struct nvmem_config imx_ocotp_nvmem_config = {
3edba6b4 PZ	393	.name = "imx-ocotp",
0642bac7	394	.read_only = false,
33e5e29c SK	395	.word_size = 4,
33e5e29c SK	396	.stride = 4,
33e5e29c	397	.reg_read = imx_ocotp_read,
0642bac7	398	.reg_write = imx_ocotp_write,
3edba6b4 PZ	399	};
3edba6b4 PZ	400
e20d2b29 BD	401	static const struct ocotp_params imx6q_params = {
e20d2b29 BD	402	.nregs = 128,
ffd9115f	403	.bank_address_words = 0,
828ae7a4	404	.set_timing = imx_ocotp_set_imx6_timing,
e20d2b29 BD	405	};
	406
	407	static const struct ocotp_params imx6sl_params = {
	408	.nregs = 64,
ffd9115f	409	.bank_address_words = 0,
828ae7a4	410	.set_timing = imx_ocotp_set_imx6_timing,
e20d2b29 BD	411	};
	412
	413	static const struct ocotp_params imx6sx_params = {
	414	.nregs = 128,
ffd9115f	415	.bank_address_words = 0,
828ae7a4	416	.set_timing = imx_ocotp_set_imx6_timing,
e20d2b29 BD	417	};
	418
	419	static const struct ocotp_params imx6ul_params = {
	420	.nregs = 128,
ffd9115f	421	.bank_address_words = 0,
828ae7a4	422	.set_timing = imx_ocotp_set_imx6_timing,
e20d2b29 BD	423	};
	424
	425	static const struct ocotp_params imx7d_params = {
	426	.nregs = 64,
ffd9115f	427	.bank_address_words = 4,
828ae7a4	428	.set_timing = imx_ocotp_set_imx7_timing,
e20d2b29 BD	429	};
e20d2b29 BD	430
3edba6b4	431	static const struct of_device_id imx_ocotp_dt_ids[] = {
e20d2b29 BD	432	{ .compatible = "fsl,imx6q-ocotp", .data = &imx6q_params },
	433	{ .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params },
	434	{ .compatible = "fsl,imx6sx-ocotp", .data = &imx6sx_params },
	435	{ .compatible = "fsl,imx6ul-ocotp", .data = &imx6ul_params },
	436	{ .compatible = "fsl,imx7d-ocotp", .data = &imx7d_params },
3edba6b4 PZ	437	{ },
	438	};
	439	MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);
	440
	441	static int imx_ocotp_probe(struct platform_device *pdev)
	442	{
	443	const struct of_device_id *of_id;
	444	struct device *dev = &pdev->dev;
	445	struct resource *res;
3edba6b4 PZ	446	struct ocotp_priv *priv;
	447	struct nvmem_device *nvmem;
	448
	449	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	450	if (!priv)
	451	return -ENOMEM;
	452
4cefb74a RL	453	priv->dev = dev;
4cefb74a RL	454
3edba6b4 PZ	455	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	456	priv->base = devm_ioremap_resource(dev, res);
	457	if (IS_ERR(priv->base))
	458	return PTR_ERR(priv->base);
	459
4cefb74a	460	priv->clk = devm_clk_get(dev, NULL);
deb31970 PF	461	if (IS_ERR(priv->clk))
	462	return PTR_ERR(priv->clk);
	463
638d8251 LS	464	clk_prepare_enable(priv->clk);
	465	imx_ocotp_clr_err_if_set(priv->base);
	466	clk_disable_unprepare(priv->clk);
	467
3edba6b4	468	of_id = of_match_device(imx_ocotp_dt_ids, dev);
e20d2b29 BD	469	priv->params = of_device_get_match_data(&pdev->dev);
e20d2b29 BD	470	imx_ocotp_nvmem_config.size = 4 * priv->params->nregs;
3edba6b4	471	imx_ocotp_nvmem_config.dev = dev;
33e5e29c	472	imx_ocotp_nvmem_config.priv = priv;
0642bac7	473	priv->config = &imx_ocotp_nvmem_config;
3edba6b4	474	nvmem = nvmem_register(&imx_ocotp_nvmem_config);
0642bac7	475
3edba6b4 PZ	476	if (IS_ERR(nvmem))
	477	return PTR_ERR(nvmem);
	478
	479	platform_set_drvdata(pdev, nvmem);
	480
	481	return 0;
	482	}
	483
	484	static int imx_ocotp_remove(struct platform_device *pdev)
	485	{
	486	struct nvmem_device *nvmem = platform_get_drvdata(pdev);
	487
	488	return nvmem_unregister(nvmem);
	489	}
	490
	491	static struct platform_driver imx_ocotp_driver = {
	492	.probe = imx_ocotp_probe,
	493	.remove = imx_ocotp_remove,
	494	.driver = {
	495	.name = "imx_ocotp",
	496	.of_match_table = imx_ocotp_dt_ids,
	497	},
	498	};
	499	module_platform_driver(imx_ocotp_driver);
	500
	501	MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
aef9a4de	502	MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver");
3edba6b4	503	MODULE_LICENSE("GPL v2");