[mirror_ubuntu-bionic-kernel.git] / drivers / nvmem / lpc18xx_eeprom.c

/*
 * NXP LPC18xx/LPC43xx EEPROM memory NVMEM driver
 *
 * Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/nvmem-provider.h>
#include <linux/platform_device.h>
#include <linux/reset.h>

/* Registers */
#define LPC18XX_EEPROM_AUTOPROG			0x00c
#define LPC18XX_EEPROM_AUTOPROG_WORD		0x1

#define LPC18XX_EEPROM_CLKDIV			0x014

#define LPC18XX_EEPROM_PWRDWN			0x018
#define LPC18XX_EEPROM_PWRDWN_NO		0x0
#define LPC18XX_EEPROM_PWRDWN_YES		0x1

#define LPC18XX_EEPROM_INTSTAT			0xfe0
#define LPC18XX_EEPROM_INTSTAT_END_OF_PROG	BIT(2)

#define LPC18XX_EEPROM_INTSTATCLR		0xfe8
#define LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST	BIT(2)

/* Fixed page size (bytes) */
#define LPC18XX_EEPROM_PAGE_SIZE		0x80

/* EEPROM device requires a ~1500 kHz clock (min 800 kHz, max 1600 kHz) */
#define LPC18XX_EEPROM_CLOCK_HZ			1500000

/* EEPROM requires 3 ms of erase/program time between each writing */
#define LPC18XX_EEPROM_PROGRAM_TIME		3

struct lpc18xx_eeprom_dev {
	struct clk *clk;
	void __iomem *reg_base;
	void __iomem *mem_base;
	struct nvmem_device *nvmem;
	unsigned reg_bytes;
	unsigned val_bytes;
	int size;
};

static inline void lpc18xx_eeprom_writel(struct lpc18xx_eeprom_dev *eeprom,
					 u32 reg, u32 val)
{
	writel(val, eeprom->reg_base + reg);
}

static inline u32 lpc18xx_eeprom_readl(struct lpc18xx_eeprom_dev *eeprom,
				       u32 reg)
{
	return readl(eeprom->reg_base + reg);
}

static int lpc18xx_eeprom_busywait_until_prog(struct lpc18xx_eeprom_dev *eeprom)
{
	unsigned long end;
	u32 val;

	/* Wait until EEPROM program operation has finished */
	end = jiffies + msecs_to_jiffies(LPC18XX_EEPROM_PROGRAM_TIME * 10);

	while (time_is_after_jiffies(end)) {
		val = lpc18xx_eeprom_readl(eeprom, LPC18XX_EEPROM_INTSTAT);

		if (val & LPC18XX_EEPROM_INTSTAT_END_OF_PROG) {
			lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_INTSTATCLR,
					LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST);
			return 0;
		}

		usleep_range(LPC18XX_EEPROM_PROGRAM_TIME * USEC_PER_MSEC,
			     (LPC18XX_EEPROM_PROGRAM_TIME + 1) * USEC_PER_MSEC);
	}

	return -ETIMEDOUT;
}

static int lpc18xx_eeprom_gather_write(void *context, unsigned int reg,
				       void *val, size_t bytes)
{
	struct lpc18xx_eeprom_dev *eeprom = context;
	unsigned int offset = reg;
	int ret;

	/*
	 * The last page contains the EEPROM initialization data and is not
	 * writable.
	 */
	if ((reg > eeprom->size - LPC18XX_EEPROM_PAGE_SIZE) ||
			(reg + bytes > eeprom->size - LPC18XX_EEPROM_PAGE_SIZE))
		return -EINVAL;


	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
			      LPC18XX_EEPROM_PWRDWN_NO);

	/* Wait 100 us while the EEPROM wakes up */
	usleep_range(100, 200);

	while (bytes) {
		writel(*(u32 *)val, eeprom->mem_base + offset);
		ret = lpc18xx_eeprom_busywait_until_prog(eeprom);
		if (ret < 0)
			return ret;

		bytes -= eeprom->val_bytes;
		val += eeprom->val_bytes;
		offset += eeprom->val_bytes;
	}

	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
			      LPC18XX_EEPROM_PWRDWN_YES);

	return 0;
}

static int lpc18xx_eeprom_read(void *context, unsigned int offset,
			       void *val, size_t bytes)
{
	struct lpc18xx_eeprom_dev *eeprom = context;

	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
			      LPC18XX_EEPROM_PWRDWN_NO);

	/* Wait 100 us while the EEPROM wakes up */
	usleep_range(100, 200);

	while (bytes) {
		*(u32 *)val = readl(eeprom->mem_base + offset);
		bytes -= eeprom->val_bytes;
		val += eeprom->val_bytes;
		offset += eeprom->val_bytes;
	}

	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
			      LPC18XX_EEPROM_PWRDWN_YES);

	return 0;
}


static struct nvmem_config lpc18xx_nvmem_config = {
	.name = "lpc18xx-eeprom",
	.stride = 4,
	.word_size = 4,
	.reg_read = lpc18xx_eeprom_read,
	.reg_write = lpc18xx_eeprom_gather_write,
};

static int lpc18xx_eeprom_probe(struct platform_device *pdev)
{
	struct lpc18xx_eeprom_dev *eeprom;
	struct device *dev = &pdev->dev;
	struct reset_control *rst;
	unsigned long clk_rate;
	struct resource *res;
	int ret;

	eeprom = devm_kzalloc(dev, sizeof(*eeprom), GFP_KERNEL);
	if (!eeprom)
		return -ENOMEM;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
	eeprom->reg_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(eeprom->reg_base))
		return PTR_ERR(eeprom->reg_base);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
	eeprom->mem_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(eeprom->mem_base))
		return PTR_ERR(eeprom->mem_base);

	eeprom->clk = devm_clk_get(&pdev->dev, "eeprom");
	if (IS_ERR(eeprom->clk)) {
		dev_err(&pdev->dev, "failed to get eeprom clock\n");
		return PTR_ERR(eeprom->clk);
	}

	ret = clk_prepare_enable(eeprom->clk);
	if (ret < 0) {
		dev_err(dev, "failed to prepare/enable eeprom clk: %d\n", ret);
		return ret;
	}

	rst = devm_reset_control_get_exclusive(dev, NULL);
	if (IS_ERR(rst)) {
		dev_err(dev, "failed to get reset: %ld\n", PTR_ERR(rst));
		ret = PTR_ERR(rst);
		goto err_clk;
	}

	ret = reset_control_assert(rst);
	if (ret < 0) {
		dev_err(dev, "failed to assert reset: %d\n", ret);
		goto err_clk;
	}

	eeprom->val_bytes = 4;
	eeprom->reg_bytes = 4;

	/*
	 * Clock rate is generated by dividing the system bus clock by the
	 * division factor, contained in the divider register (minus 1 encoded).
	 */
	clk_rate = clk_get_rate(eeprom->clk);
	clk_rate = DIV_ROUND_UP(clk_rate, LPC18XX_EEPROM_CLOCK_HZ) - 1;
	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_CLKDIV, clk_rate);

	/*
	 * Writing a single word to the page will start the erase/program cycle
	 * automatically
	 */
	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_AUTOPROG,
			      LPC18XX_EEPROM_AUTOPROG_WORD);

	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
			      LPC18XX_EEPROM_PWRDWN_YES);

	eeprom->size = resource_size(res);
	lpc18xx_nvmem_config.size = resource_size(res);
	lpc18xx_nvmem_config.dev = dev;
	lpc18xx_nvmem_config.priv = eeprom;

	eeprom->nvmem = nvmem_register(&lpc18xx_nvmem_config);
	if (IS_ERR(eeprom->nvmem)) {
		ret = PTR_ERR(eeprom->nvmem);
		goto err_clk;
	}

	platform_set_drvdata(pdev, eeprom);

	return 0;

err_clk:
	clk_disable_unprepare(eeprom->clk);

	return ret;
}

static int lpc18xx_eeprom_remove(struct platform_device *pdev)
{
	struct lpc18xx_eeprom_dev *eeprom = platform_get_drvdata(pdev);
	int ret;

	ret = nvmem_unregister(eeprom->nvmem);
	if (ret < 0)
		return ret;

	clk_disable_unprepare(eeprom->clk);

	return 0;
}

static const struct of_device_id lpc18xx_eeprom_of_match[] = {
	{ .compatible = "nxp,lpc1857-eeprom" },
	{ },
};
MODULE_DEVICE_TABLE(of, lpc18xx_eeprom_of_match);

static struct platform_driver lpc18xx_eeprom_driver = {
	.probe = lpc18xx_eeprom_probe,
	.remove = lpc18xx_eeprom_remove,
	.driver = {
		.name = "lpc18xx-eeprom",
		.of_match_table = lpc18xx_eeprom_of_match,
	},
};

module_platform_driver(lpc18xx_eeprom_driver);

MODULE_AUTHOR("Ariel D'Alessandro <ariel@vanguardiasur.com.ar>");
MODULE_DESCRIPTION("NXP LPC18xx EEPROM memory Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
f02f8aee AA	1	/*
	2	* NXP LPC18xx/LPC43xx EEPROM memory NVMEM driver
	3	*
	4	* Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published by
	8	* the Free Software Foundation.
	9	*/
	10
	11	#include <linux/clk.h>
	12	#include <linux/device.h>
	13	#include <linux/delay.h>
	14	#include <linux/err.h>
	15	#include <linux/io.h>
	16	#include <linux/module.h>
	17	#include <linux/nvmem-provider.h>
	18	#include <linux/platform_device.h>
f02f8aee AA	19	#include <linux/reset.h>
	20
	21	/* Registers */
	22	#define LPC18XX_EEPROM_AUTOPROG 0x00c
	23	#define LPC18XX_EEPROM_AUTOPROG_WORD 0x1
	24
	25	#define LPC18XX_EEPROM_CLKDIV 0x014
	26
	27	#define LPC18XX_EEPROM_PWRDWN 0x018
	28	#define LPC18XX_EEPROM_PWRDWN_NO 0x0
	29	#define LPC18XX_EEPROM_PWRDWN_YES 0x1
	30
	31	#define LPC18XX_EEPROM_INTSTAT 0xfe0
	32	#define LPC18XX_EEPROM_INTSTAT_END_OF_PROG BIT(2)
	33
	34	#define LPC18XX_EEPROM_INTSTATCLR 0xfe8
	35	#define LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST BIT(2)
	36
	37	/* Fixed page size (bytes) */
	38	#define LPC18XX_EEPROM_PAGE_SIZE 0x80
	39
	40	/* EEPROM device requires a ~1500 kHz clock (min 800 kHz, max 1600 kHz) */
	41	#define LPC18XX_EEPROM_CLOCK_HZ 1500000
	42
	43	/* EEPROM requires 3 ms of erase/program time between each writing */
	44	#define LPC18XX_EEPROM_PROGRAM_TIME 3
	45
	46	struct lpc18xx_eeprom_dev {
	47	struct clk *clk;
	48	void __iomem *reg_base;
	49	void __iomem *mem_base;
	50	struct nvmem_device *nvmem;
	51	unsigned reg_bytes;
	52	unsigned val_bytes;
2e8d0733	53	int size;
f02f8aee AA	54	};
	55
	56	static inline void lpc18xx_eeprom_writel(struct lpc18xx_eeprom_dev *eeprom,
	57	u32 reg, u32 val)
	58	{
	59	writel(val, eeprom->reg_base + reg);
	60	}
	61
	62	static inline u32 lpc18xx_eeprom_readl(struct lpc18xx_eeprom_dev *eeprom,
	63	u32 reg)
	64	{
	65	return readl(eeprom->reg_base + reg);
	66	}
	67
	68	static int lpc18xx_eeprom_busywait_until_prog(struct lpc18xx_eeprom_dev *eeprom)
	69	{
	70	unsigned long end;
	71	u32 val;
	72
	73	/* Wait until EEPROM program operation has finished */
	74	end = jiffies + msecs_to_jiffies(LPC18XX_EEPROM_PROGRAM_TIME * 10);
	75
	76	while (time_is_after_jiffies(end)) {
	77	val = lpc18xx_eeprom_readl(eeprom, LPC18XX_EEPROM_INTSTAT);
	78
	79	if (val & LPC18XX_EEPROM_INTSTAT_END_OF_PROG) {
	80	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_INTSTATCLR,
	81	LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST);
	82	return 0;
	83	}
	84
	85	usleep_range(LPC18XX_EEPROM_PROGRAM_TIME * USEC_PER_MSEC,
	86	(LPC18XX_EEPROM_PROGRAM_TIME + 1) * USEC_PER_MSEC);
	87	}
	88
	89	return -ETIMEDOUT;
	90	}
	91
2e8d0733 SK	92	static int lpc18xx_eeprom_gather_write(void *context, unsigned int reg,
2e8d0733 SK	93	void *val, size_t bytes)
f02f8aee AA	94	{
f02f8aee AA	95	struct lpc18xx_eeprom_dev *eeprom = context;
2e8d0733	96	unsigned int offset = reg;
f02f8aee AA	97	int ret;
f02f8aee AA	98
2e8d0733 SK	99	/*
	100	* The last page contains the EEPROM initialization data and is not
	101	* writable.
	102	*/
	103	if ((reg > eeprom->size - LPC18XX_EEPROM_PAGE_SIZE) \|\|
	104	(reg + bytes > eeprom->size - LPC18XX_EEPROM_PAGE_SIZE))
f02f8aee AA	105	return -EINVAL;
f02f8aee AA	106
2e8d0733	107
f02f8aee AA	108	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
	109	LPC18XX_EEPROM_PWRDWN_NO);
	110
	111	/* Wait 100 us while the EEPROM wakes up */
	112	usleep_range(100, 200);
	113
2e8d0733	114	while (bytes) {
f02f8aee AA	115	writel((u32 )val, eeprom->mem_base + offset);
	116	ret = lpc18xx_eeprom_busywait_until_prog(eeprom);
	117	if (ret < 0)
	118	return ret;
	119
2e8d0733	120	bytes -= eeprom->val_bytes;
f02f8aee AA	121	val += eeprom->val_bytes;
	122	offset += eeprom->val_bytes;
	123	}
	124
	125	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
	126	LPC18XX_EEPROM_PWRDWN_YES);
	127
	128	return 0;
	129	}
	130
2e8d0733 SK	131	static int lpc18xx_eeprom_read(void *context, unsigned int offset,
2e8d0733 SK	132	void *val, size_t bytes)
f02f8aee AA	133	{
f02f8aee AA	134	struct lpc18xx_eeprom_dev *eeprom = context;
f02f8aee AA	135
	136	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
	137	LPC18XX_EEPROM_PWRDWN_NO);
	138
	139	/* Wait 100 us while the EEPROM wakes up */
	140	usleep_range(100, 200);
	141
2e8d0733	142	while (bytes) {
f02f8aee	143	(u32 )val = readl(eeprom->mem_base + offset);
2e8d0733	144	bytes -= eeprom->val_bytes;
f02f8aee AA	145	val += eeprom->val_bytes;
	146	offset += eeprom->val_bytes;
	147	}
	148
	149	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
	150	LPC18XX_EEPROM_PWRDWN_YES);
	151
	152	return 0;
	153	}
	154
f02f8aee AA	155
	156	static struct nvmem_config lpc18xx_nvmem_config = {
	157	.name = "lpc18xx-eeprom",
2e8d0733 SK	158	.stride = 4,
	159	.word_size = 4,
	160	.reg_read = lpc18xx_eeprom_read,
	161	.reg_write = lpc18xx_eeprom_gather_write,
f02f8aee AA	162	};
	163
	164	static int lpc18xx_eeprom_probe(struct platform_device *pdev)
	165	{
	166	struct lpc18xx_eeprom_dev *eeprom;
	167	struct device *dev = &pdev->dev;
	168	struct reset_control *rst;
	169	unsigned long clk_rate;
f02f8aee AA	170	struct resource *res;
	171	int ret;
	172
	173	eeprom = devm_kzalloc(dev, sizeof(*eeprom), GFP_KERNEL);
	174	if (!eeprom)
	175	return -ENOMEM;
	176
	177	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
	178	eeprom->reg_base = devm_ioremap_resource(dev, res);
	179	if (IS_ERR(eeprom->reg_base))
	180	return PTR_ERR(eeprom->reg_base);
	181
	182	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
	183	eeprom->mem_base = devm_ioremap_resource(dev, res);
	184	if (IS_ERR(eeprom->mem_base))
	185	return PTR_ERR(eeprom->mem_base);
	186
	187	eeprom->clk = devm_clk_get(&pdev->dev, "eeprom");
	188	if (IS_ERR(eeprom->clk)) {
	189	dev_err(&pdev->dev, "failed to get eeprom clock\n");
	190	return PTR_ERR(eeprom->clk);
	191	}
	192
	193	ret = clk_prepare_enable(eeprom->clk);
	194	if (ret < 0) {
	195	dev_err(dev, "failed to prepare/enable eeprom clk: %d\n", ret);
	196	return ret;
	197	}
	198
aed0c46e	199	rst = devm_reset_control_get_exclusive(dev, NULL);
f02f8aee AA	200	if (IS_ERR(rst)) {
	201	dev_err(dev, "failed to get reset: %ld\n", PTR_ERR(rst));
	202	ret = PTR_ERR(rst);
	203	goto err_clk;
	204	}
	205
	206	ret = reset_control_assert(rst);
	207	if (ret < 0) {
	208	dev_err(dev, "failed to assert reset: %d\n", ret);
	209	goto err_clk;
	210	}
	211
2e8d0733 SK	212	eeprom->val_bytes = 4;
2e8d0733 SK	213	eeprom->reg_bytes = 4;
f02f8aee AA	214
	215	/*
	216	* Clock rate is generated by dividing the system bus clock by the
	217	* division factor, contained in the divider register (minus 1 encoded).
	218	*/
	219	clk_rate = clk_get_rate(eeprom->clk);
	220	clk_rate = DIV_ROUND_UP(clk_rate, LPC18XX_EEPROM_CLOCK_HZ) - 1;
	221	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_CLKDIV, clk_rate);
	222
	223	/*
	224	* Writing a single word to the page will start the erase/program cycle
	225	* automatically
	226	*/
	227	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_AUTOPROG,
	228	LPC18XX_EEPROM_AUTOPROG_WORD);
	229
	230	lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
	231	LPC18XX_EEPROM_PWRDWN_YES);
	232
2e8d0733 SK	233	eeprom->size = resource_size(res);
2e8d0733 SK	234	lpc18xx_nvmem_config.size = resource_size(res);
f02f8aee	235	lpc18xx_nvmem_config.dev = dev;
2e8d0733	236	lpc18xx_nvmem_config.priv = eeprom;
f02f8aee AA	237
	238	eeprom->nvmem = nvmem_register(&lpc18xx_nvmem_config);
	239	if (IS_ERR(eeprom->nvmem)) {
	240	ret = PTR_ERR(eeprom->nvmem);
	241	goto err_clk;
	242	}
	243
	244	platform_set_drvdata(pdev, eeprom);
	245
	246	return 0;
	247
	248	err_clk:
	249	clk_disable_unprepare(eeprom->clk);
	250
	251	return ret;
	252	}
	253
	254	static int lpc18xx_eeprom_remove(struct platform_device *pdev)
	255	{
	256	struct lpc18xx_eeprom_dev *eeprom = platform_get_drvdata(pdev);
	257	int ret;
	258
	259	ret = nvmem_unregister(eeprom->nvmem);
	260	if (ret < 0)
	261	return ret;
	262
	263	clk_disable_unprepare(eeprom->clk);
	264
	265	return 0;
	266	}
	267
	268	static const struct of_device_id lpc18xx_eeprom_of_match[] = {
	269	{ .compatible = "nxp,lpc1857-eeprom" },
	270	{ },
	271	};
	272	MODULE_DEVICE_TABLE(of, lpc18xx_eeprom_of_match);
	273
	274	static struct platform_driver lpc18xx_eeprom_driver = {
	275	.probe = lpc18xx_eeprom_probe,
	276	.remove = lpc18xx_eeprom_remove,
	277	.driver = {
	278	.name = "lpc18xx-eeprom",
	279	.of_match_table = lpc18xx_eeprom_of_match,
	280	},
	281	};
	282
	283	module_platform_driver(lpc18xx_eeprom_driver);
	284
	285	MODULE_AUTHOR("Ariel D'Alessandro <ariel@vanguardiasur.com.ar>");
	286	MODULE_DESCRIPTION("NXP LPC18xx EEPROM memory Driver");
	287	MODULE_LICENSE("GPL v2");