[mirror_ubuntu-jammy-kernel.git] / drivers / nvmem / meson-mx-efuse.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Amlogic Meson6, Meson8 and Meson8b eFuse Driver
 *
 * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
 */

#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/nvmem-provider.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/sizes.h>
#include <linux/slab.h>

#define MESON_MX_EFUSE_CNTL1					0x04
#define MESON_MX_EFUSE_CNTL1_PD_ENABLE				BIT(27)
#define MESON_MX_EFUSE_CNTL1_AUTO_RD_BUSY			BIT(26)
#define MESON_MX_EFUSE_CNTL1_AUTO_RD_START			BIT(25)
#define MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE			BIT(24)
#define MESON_MX_EFUSE_CNTL1_BYTE_WR_DATA			GENMASK(23, 16)
#define MESON_MX_EFUSE_CNTL1_AUTO_WR_BUSY			BIT(14)
#define MESON_MX_EFUSE_CNTL1_AUTO_WR_START			BIT(13)
#define MESON_MX_EFUSE_CNTL1_AUTO_WR_ENABLE			BIT(12)
#define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET			BIT(11)
#define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK			GENMASK(10, 0)

#define MESON_MX_EFUSE_CNTL2					0x08

#define MESON_MX_EFUSE_CNTL4					0x10
#define MESON_MX_EFUSE_CNTL4_ENCRYPT_ENABLE			BIT(10)

struct meson_mx_efuse_platform_data {
	const char *name;
	unsigned int word_size;
};

struct meson_mx_efuse {
	void __iomem *base;
	struct clk *core_clk;
	struct nvmem_device *nvmem;
	struct nvmem_config config;
};

static void meson_mx_efuse_mask_bits(struct meson_mx_efuse *efuse, u32 reg,
				     u32 mask, u32 set)
{
	u32 data;

	data = readl(efuse->base + reg);
	data &= ~mask;
	data |= (set & mask);

	writel(data, efuse->base + reg);
}

static int meson_mx_efuse_hw_enable(struct meson_mx_efuse *efuse)
{
	int err;

	err = clk_prepare_enable(efuse->core_clk);
	if (err)
		return err;

	/* power up the efuse */
	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
				 MESON_MX_EFUSE_CNTL1_PD_ENABLE, 0);

	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL4,
				 MESON_MX_EFUSE_CNTL4_ENCRYPT_ENABLE, 0);

	return 0;
}

static void meson_mx_efuse_hw_disable(struct meson_mx_efuse *efuse)
{
	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
				 MESON_MX_EFUSE_CNTL1_PD_ENABLE,
				 MESON_MX_EFUSE_CNTL1_PD_ENABLE);

	clk_disable_unprepare(efuse->core_clk);
}

static int meson_mx_efuse_read_addr(struct meson_mx_efuse *efuse,
				    unsigned int addr, u32 *value)
{
	int err;
	u32 regval;

	/* write the address to read */
	regval = FIELD_PREP(MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK, addr);
	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
				 MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK, regval);

	/* inform the hardware that we changed the address */
	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
				 MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET,
				 MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET);
	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
				 MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET, 0);

	/* start the read process */
	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
				 MESON_MX_EFUSE_CNTL1_AUTO_RD_START,
				 MESON_MX_EFUSE_CNTL1_AUTO_RD_START);
	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
				 MESON_MX_EFUSE_CNTL1_AUTO_RD_START, 0);

	/*
	 * perform a dummy read to ensure that the HW has the RD_BUSY bit set
	 * when polling for the status below.
	 */
	readl(efuse->base + MESON_MX_EFUSE_CNTL1);

	err = readl_poll_timeout_atomic(efuse->base + MESON_MX_EFUSE_CNTL1,
			regval,
			(!(regval & MESON_MX_EFUSE_CNTL1_AUTO_RD_BUSY)),
			1, 1000);
	if (err) {
		dev_err(efuse->config.dev,
			"Timeout while reading efuse address %u\n", addr);
		return err;
	}

	*value = readl(efuse->base + MESON_MX_EFUSE_CNTL2);

	return 0;
}

static int meson_mx_efuse_read(void *context, unsigned int offset,
			       void *buf, size_t bytes)
{
	struct meson_mx_efuse *efuse = context;
	u32 tmp;
	int err, i, addr;

	err = meson_mx_efuse_hw_enable(efuse);
	if (err)
		return err;

	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
				 MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE,
				 MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE);

	for (i = 0; i < bytes; i += efuse->config.word_size) {
		addr = (offset + i) / efuse->config.word_size;

		err = meson_mx_efuse_read_addr(efuse, addr, &tmp);
		if (err)
			break;

		memcpy(buf + i, &tmp,
		       min_t(size_t, bytes - i, efuse->config.word_size));
	}

	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
				 MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE, 0);

	meson_mx_efuse_hw_disable(efuse);

	return err;
}

static const struct meson_mx_efuse_platform_data meson6_efuse_data = {
	.name = "meson6-efuse",
	.word_size = 1,
};

static const struct meson_mx_efuse_platform_data meson8_efuse_data = {
	.name = "meson8-efuse",
	.word_size = 4,
};

static const struct meson_mx_efuse_platform_data meson8b_efuse_data = {
	.name = "meson8b-efuse",
	.word_size = 4,
};

static const struct of_device_id meson_mx_efuse_match[] = {
	{ .compatible = "amlogic,meson6-efuse", .data = &meson6_efuse_data },
	{ .compatible = "amlogic,meson8-efuse", .data = &meson8_efuse_data },
	{ .compatible = "amlogic,meson8b-efuse", .data = &meson8b_efuse_data },
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, meson_mx_efuse_match);

static int meson_mx_efuse_probe(struct platform_device *pdev)
{
	const struct meson_mx_efuse_platform_data *drvdata;
	struct meson_mx_efuse *efuse;
	struct resource *res;

	drvdata = of_device_get_match_data(&pdev->dev);
	if (!drvdata)
		return -EINVAL;

	efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL);
	if (!efuse)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	efuse->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(efuse->base))
		return PTR_ERR(efuse->base);

	efuse->config.name = devm_kstrdup(&pdev->dev, drvdata->name,
					  GFP_KERNEL);
	efuse->config.owner = THIS_MODULE;
	efuse->config.dev = &pdev->dev;
	efuse->config.priv = efuse;
	efuse->config.stride = drvdata->word_size;
	efuse->config.word_size = drvdata->word_size;
	efuse->config.size = SZ_512;
	efuse->config.read_only = true;
	efuse->config.reg_read = meson_mx_efuse_read;

	efuse->core_clk = devm_clk_get(&pdev->dev, "core");
	if (IS_ERR(efuse->core_clk)) {
		dev_err(&pdev->dev, "Failed to get core clock\n");
		return PTR_ERR(efuse->core_clk);
	}

	efuse->nvmem = devm_nvmem_register(&pdev->dev, &efuse->config);

	return PTR_ERR_OR_ZERO(efuse->nvmem);
}

static struct platform_driver meson_mx_efuse_driver = {
	.probe = meson_mx_efuse_probe,
	.driver = {
		.name = "meson-mx-efuse",
		.of_match_table = meson_mx_efuse_match,
	},
};

module_platform_driver(meson_mx_efuse_driver);

MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
MODULE_DESCRIPTION("Amlogic Meson MX eFuse NVMEM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
5b497af4	1	// SPDX-License-Identifier: GPL-2.0-only
8caef1fa MB	2	/*
	3	* Amlogic Meson6, Meson8 and Meson8b eFuse Driver
	4	*
	5	* Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
8caef1fa MB	6	*/
	7
	8	#include <linux/bitfield.h>
	9	#include <linux/bitops.h>
	10	#include <linux/clk.h>
	11	#include <linux/delay.h>
	12	#include <linux/io.h>
	13	#include <linux/iopoll.h>
	14	#include <linux/module.h>
	15	#include <linux/nvmem-provider.h>
	16	#include <linux/of.h>
	17	#include <linux/of_device.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/sizes.h>
	20	#include <linux/slab.h>
	21
	22	#define MESON_MX_EFUSE_CNTL1 0x04
	23	#define MESON_MX_EFUSE_CNTL1_PD_ENABLE BIT(27)
	24	#define MESON_MX_EFUSE_CNTL1_AUTO_RD_BUSY BIT(26)
	25	#define MESON_MX_EFUSE_CNTL1_AUTO_RD_START BIT(25)
	26	#define MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE BIT(24)
	27	#define MESON_MX_EFUSE_CNTL1_BYTE_WR_DATA GENMASK(23, 16)
	28	#define MESON_MX_EFUSE_CNTL1_AUTO_WR_BUSY BIT(14)
	29	#define MESON_MX_EFUSE_CNTL1_AUTO_WR_START BIT(13)
	30	#define MESON_MX_EFUSE_CNTL1_AUTO_WR_ENABLE BIT(12)
	31	#define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET BIT(11)
	32	#define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK GENMASK(10, 0)
	33
	34	#define MESON_MX_EFUSE_CNTL2 0x08
	35
	36	#define MESON_MX_EFUSE_CNTL4 0x10
	37	#define MESON_MX_EFUSE_CNTL4_ENCRYPT_ENABLE BIT(10)
	38
	39	struct meson_mx_efuse_platform_data {
	40	const char *name;
	41	unsigned int word_size;
	42	};
	43
	44	struct meson_mx_efuse {
	45	void __iomem *base;
	46	struct clk *core_clk;
	47	struct nvmem_device *nvmem;
	48	struct nvmem_config config;
	49	};
	50
	51	static void meson_mx_efuse_mask_bits(struct meson_mx_efuse *efuse, u32 reg,
	52	u32 mask, u32 set)
	53	{
	54	u32 data;
	55
	56	data = readl(efuse->base + reg);
	57	data &= ~mask;
	58	data \|= (set & mask);
	59
	60	writel(data, efuse->base + reg);
	61	}
	62
	63	static int meson_mx_efuse_hw_enable(struct meson_mx_efuse *efuse)
	64	{
	65	int err;
	66
	67	err = clk_prepare_enable(efuse->core_clk);
	68	if (err)
	69	return err;
70
71	/* power up the efuse */
72	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
73	MESON_MX_EFUSE_CNTL1_PD_ENABLE, 0);
74
75	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL4,
76	MESON_MX_EFUSE_CNTL4_ENCRYPT_ENABLE, 0);
77
78	return 0;
79	}
80
81	static void meson_mx_efuse_hw_disable(struct meson_mx_efuse *efuse)
82	{
83	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
84	MESON_MX_EFUSE_CNTL1_PD_ENABLE,
85	MESON_MX_EFUSE_CNTL1_PD_ENABLE);
86
87	clk_disable_unprepare(efuse->core_clk);
88	}
89
90	static int meson_mx_efuse_read_addr(struct meson_mx_efuse *efuse,
91	unsigned int addr, u32 *value)
92	{
93	int err;
94	u32 regval;
95
96	/* write the address to read */
97	regval = FIELD_PREP(MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK, addr);
98	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
99	MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK, regval);
100
101	/* inform the hardware that we changed the address */
102	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
103	MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET,
104	MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET);
105	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
106	MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET, 0);
107
108	/* start the read process */
109	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
110	MESON_MX_EFUSE_CNTL1_AUTO_RD_START,
111	MESON_MX_EFUSE_CNTL1_AUTO_RD_START);
112	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
113	MESON_MX_EFUSE_CNTL1_AUTO_RD_START, 0);
114
115	/*
116	* perform a dummy read to ensure that the HW has the RD_BUSY bit set
117	* when polling for the status below.
118	*/
119	readl(efuse->base + MESON_MX_EFUSE_CNTL1);
120
121	err = readl_poll_timeout_atomic(efuse->base + MESON_MX_EFUSE_CNTL1,
122	regval,
123	(!(regval & MESON_MX_EFUSE_CNTL1_AUTO_RD_BUSY)),
124	1, 1000);
125	if (err) {
126	dev_err(efuse->config.dev,
127	"Timeout while reading efuse address %u\n", addr);
128	return err;
129	}
130
131	*value = readl(efuse->base + MESON_MX_EFUSE_CNTL2);
132
133	return 0;
134	}
135
136	static int meson_mx_efuse_read(void *context, unsigned int offset,
137	void *buf, size_t bytes)
138	{
139	struct meson_mx_efuse *efuse = context;
140	u32 tmp;
141	int err, i, addr;
142
143	err = meson_mx_efuse_hw_enable(efuse);
144	if (err)
145	return err;
146
147	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
148	MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE,
149	MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE);
150
8a42d3fc MB	151	for (i = 0; i < bytes; i += efuse->config.word_size) {
8a42d3fc MB	152	addr = (offset + i) / efuse->config.word_size;
8caef1fa MB	153
	154	err = meson_mx_efuse_read_addr(efuse, addr, &tmp);
	155	if (err)
	156	break;
	157
cb6b0a39 MB	158	memcpy(buf + i, &tmp,
cb6b0a39 MB	159	min_t(size_t, bytes - i, efuse->config.word_size));
8caef1fa MB	160	}
	161
	162	meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
	163	MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE, 0);
	164
	165	meson_mx_efuse_hw_disable(efuse);
	166
	167	return err;
	168	}
	169
	170	static const struct meson_mx_efuse_platform_data meson6_efuse_data = {
	171	.name = "meson6-efuse",
	172	.word_size = 1,
	173	};
	174
	175	static const struct meson_mx_efuse_platform_data meson8_efuse_data = {
	176	.name = "meson8-efuse",
	177	.word_size = 4,
	178	};
	179
	180	static const struct meson_mx_efuse_platform_data meson8b_efuse_data = {
	181	.name = "meson8b-efuse",
	182	.word_size = 4,
	183	};
	184
	185	static const struct of_device_id meson_mx_efuse_match[] = {
	186	{ .compatible = "amlogic,meson6-efuse", .data = &meson6_efuse_data },
	187	{ .compatible = "amlogic,meson8-efuse", .data = &meson8_efuse_data },
	188	{ .compatible = "amlogic,meson8b-efuse", .data = &meson8b_efuse_data },
	189	{ /* sentinel */ },
	190	};
	191	MODULE_DEVICE_TABLE(of, meson_mx_efuse_match);
	192
	193	static int meson_mx_efuse_probe(struct platform_device *pdev)
	194	{
	195	const struct meson_mx_efuse_platform_data *drvdata;
	196	struct meson_mx_efuse *efuse;
	197	struct resource *res;
	198
	199	drvdata = of_device_get_match_data(&pdev->dev);
	200	if (!drvdata)
	201	return -EINVAL;
	202
	203	efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL);
	204	if (!efuse)
	205	return -ENOMEM;
	206
	207	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	208	efuse->base = devm_ioremap_resource(&pdev->dev, res);
	209	if (IS_ERR(efuse->base))
	210	return PTR_ERR(efuse->base);
	211
	212	efuse->config.name = devm_kstrdup(&pdev->dev, drvdata->name,
	213	GFP_KERNEL);
	214	efuse->config.owner = THIS_MODULE;
	215	efuse->config.dev = &pdev->dev;
	216	efuse->config.priv = efuse;
	217	efuse->config.stride = drvdata->word_size;
	218	efuse->config.word_size = drvdata->word_size;
	219	efuse->config.size = SZ_512;
	220	efuse->config.read_only = true;
	221	efuse->config.reg_read = meson_mx_efuse_read;
	222
	223	efuse->core_clk = devm_clk_get(&pdev->dev, "core");
224	if (IS_ERR(efuse->core_clk)) {
225	dev_err(&pdev->dev, "Failed to get core clock\n");
226	return PTR_ERR(efuse->core_clk);
227	}
228
7afbde9e	229	efuse->nvmem = devm_nvmem_register(&pdev->dev, &efuse->config);
8caef1fa	230
7afbde9e	231	return PTR_ERR_OR_ZERO(efuse->nvmem);
8caef1fa MB	232	}
	233
	234	static struct platform_driver meson_mx_efuse_driver = {
	235	.probe = meson_mx_efuse_probe,
8caef1fa MB	236	.driver = {
	237	.name = "meson-mx-efuse",
	238	.of_match_table = meson_mx_efuse_match,
	239	},
	240	};
	241
	242	module_platform_driver(meson_mx_efuse_driver);
	243
	244	MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
	245	MODULE_DESCRIPTION("Amlogic Meson MX eFuse NVMEM driver");
	246	MODULE_LICENSE("GPL v2");